1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routine for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point * 37 * routines. * 38 * This file also contains routines that takes care of initialization * 39 * uninit routine and interrupt routine * 40 * * 41 * * 42 * Environment: * 43 * Kernel Mode - * 44 * * 45 * ********************************************************************** 46 */ 47 48 #include <sys/dlpi.h> 49 #include <sys/mac.h> 50 #include "e1000g_sw.h" 51 #include "e1000g_debug.h" 52 53 #define E1000_RX_INTPT_TIME 128 54 #define E1000_RX_PKT_CNT 8 55 56 static char ident[] = "Intel PRO/1000 Ethernet 5.1.7"; 57 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 58 static char e1000g_version[] = "Driver Ver. 5.1.7"; 59 60 /* 61 * Proto types for DDI entry points 62 */ 63 static int e1000gattach(dev_info_t *, ddi_attach_cmd_t); 64 static int e1000gdetach(dev_info_t *, ddi_detach_cmd_t); 65 66 /* 67 * init and intr routines prototype 68 */ 69 static int e1000g_resume(dev_info_t *devinfo); 70 static int e1000g_suspend(dev_info_t *devinfo); 71 static uint_t e1000g_intr_pciexpress(caddr_t); 72 static uint_t e1000g_intr(caddr_t); 73 static void e1000g_intr_work(struct e1000g *, uint32_t); 74 #pragma inline(e1000g_intr_work) 75 static int e1000g_init(struct e1000g *); 76 static int e1000g_start(struct e1000g *); 77 static void e1000g_stop(struct e1000g *); 78 static int e1000g_m_start(void *); 79 static void e1000g_m_stop(void *); 80 static int e1000g_m_promisc(void *, boolean_t); 81 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 82 static int e1000g_m_unicst(void *, const uint8_t *); 83 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 84 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 85 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 86 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 87 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 88 static void e1000g_m_blank(void *, time_t, uint32_t); 89 static void e1000g_m_resources(void *); 90 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 91 static void e1000g_init_locks(struct e1000g *Adapter); 92 static void e1000g_destroy_locks(struct e1000g *Adapter); 93 static int e1000g_set_driver_params(struct e1000g *Adapter); 94 static int e1000g_register_mac(struct e1000g *Adapter); 95 static boolean_t e1000g_rx_drain(struct e1000g *Adapter); 96 static boolean_t e1000g_tx_drain(struct e1000g *Adapter); 97 static void e1000g_init_unicst(struct e1000g *Adapter); 98 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 99 100 /* 101 * Local routines 102 */ 103 static void e1000g_tx_drop(struct e1000g *Adapter); 104 static void e1000g_link_timer(void *); 105 static void e1000g_LocalTimer(void *); 106 static boolean_t e1000g_link_check(struct e1000g *); 107 static boolean_t e1000g_stall_check(struct e1000g *); 108 static void e1000g_smartspeed(struct e1000g *); 109 static void e1000g_getparam(struct e1000g *Adapter); 110 static int e1000g_getprop(struct e1000g *, char *, int, int, int); 111 static void e1000g_error(dev_info_t *dip, char *fmt, char *a1, 112 char *a2, char *a3, char *a4, char *a5, char *a6); 113 static void enable_timeout(struct e1000g *Adapter); 114 static void disable_timeout(struct e1000g *Adapter); 115 static void start_timeout(struct e1000g *Adapter); 116 static void restart_timeout(struct e1000g *Adapter); 117 static void stop_timeout(struct e1000g *Adapter); 118 static void e1000g_force_speed_duplex(struct e1000g *Adapter); 119 static void e1000g_get_max_frame_size(struct e1000g *Adapter); 120 static boolean_t is_valid_mac_addr(uint8_t *mac_addr); 121 static void e1000g_unattach(dev_info_t *, struct e1000g *); 122 static void e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 123 static void e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 124 static void e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 125 static void e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 126 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *e1000gp, 127 struct iocblk *iocp, mblk_t *mp); 128 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *Adapter, 129 struct iocblk *iocp, mblk_t *mp); 130 static boolean_t e1000g_set_loopback_mode(struct e1000g *Adapter, 131 uint32_t mode); 132 static void e1000g_set_internal_loopback(struct e1000g *Adapter); 133 static void e1000g_set_external_loopback_1000(struct e1000g *Adapter); 134 static void e1000g_set_external_loopback_100(struct e1000g *Adapter); 135 static void e1000g_set_external_loopback_10(struct e1000g *Adapter); 136 static int e1000g_add_intrs(struct e1000g *Adapter); 137 static int e1000g_intr_add(struct e1000g *Adapter, int intr_type); 138 static int e1000g_rem_intrs(struct e1000g *Adapter); 139 static int e1000g_enable_intrs(struct e1000g *Adapter); 140 static int e1000g_disable_intrs(struct e1000g *Adapter); 141 static boolean_t e1000g_link_up(struct e1000g *Adapter); 142 #ifdef __sparc 143 static boolean_t e1000g_find_mac_address(struct e1000g *Adapter); 144 #endif 145 146 static struct cb_ops cb_ws_ops = { 147 nulldev, /* cb_open */ 148 nulldev, /* cb_close */ 149 nodev, /* cb_strategy */ 150 nodev, /* cb_print */ 151 nodev, /* cb_dump */ 152 nodev, /* cb_read */ 153 nodev, /* cb_write */ 154 nodev, /* cb_ioctl */ 155 nodev, /* cb_devmap */ 156 nodev, /* cb_mmap */ 157 nodev, /* cb_segmap */ 158 nochpoll, /* cb_chpoll */ 159 ddi_prop_op, /* cb_prop_op */ 160 NULL, /* cb_stream */ 161 D_MP | D_HOTPLUG, /* cb_flag */ 162 CB_REV, /* cb_rev */ 163 nodev, /* cb_aread */ 164 nodev /* cb_awrite */ 165 }; 166 167 static struct dev_ops ws_ops = { 168 DEVO_REV, /* devo_rev */ 169 0, /* devo_refcnt */ 170 NULL, /* devo_getinfo */ 171 nulldev, /* devo_identify */ 172 nulldev, /* devo_probe */ 173 e1000gattach, /* devo_attach */ 174 e1000gdetach, /* devo_detach */ 175 nodev, /* devo_reset */ 176 &cb_ws_ops, /* devo_cb_ops */ 177 NULL, /* devo_bus_ops */ 178 ddi_power /* devo_power */ 179 }; 180 181 static struct modldrv modldrv = { 182 &mod_driverops, /* Type of module. This one is a driver */ 183 ident, /* Discription string */ 184 &ws_ops, /* driver ops */ 185 }; 186 187 static struct modlinkage modlinkage = { 188 MODREV_1, &modldrv, NULL 189 }; 190 191 /* 192 * DMA access attributes <Little Endian Card> 193 */ 194 static ddi_device_acc_attr_t accattr1 = { 195 DDI_DEVICE_ATTR_V0, 196 DDI_STRUCTURE_LE_ACC, 197 DDI_STRICTORDER_ACC, 198 }; 199 200 #define E1000G_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 201 202 static mac_callbacks_t e1000g_m_callbacks = { 203 E1000G_M_CALLBACK_FLAGS, 204 e1000g_m_stat, 205 e1000g_m_start, 206 e1000g_m_stop, 207 e1000g_m_promisc, 208 e1000g_m_multicst, 209 e1000g_m_unicst, 210 e1000g_m_tx, 211 e1000g_m_resources, 212 e1000g_m_ioctl, 213 e1000g_m_getcapab 214 }; 215 216 /* 217 * Global variables 218 */ 219 boolean_t force_detach_enabled = B_FALSE; 220 uint32_t e1000g_mblks_pending = 0; 221 /* 222 * The rwlock is defined to protect the whole processing of rx recycling 223 * and the rx packets release in detach processing to make them mutually 224 * exclusive. 225 * The rx recycling processes different rx packets in different threads, 226 * so it will be protected with RW_READER and it won't block any other rx 227 * recycling threads. 228 * While the detach processing will be protected with RW_WRITER to make 229 * it mutually exclusive with the rx recycling. 230 */ 231 krwlock_t e1000g_rx_detach_lock; 232 /* 233 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 234 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 235 * If there are many e1000g instances, the system may run out of DVMA 236 * resources during the initialization of the instances, then the flag will 237 * be changed to "USE_DMA". Because different e1000g instances are initialized 238 * in parallel, we need to use this lock to protect the flag. 239 */ 240 krwlock_t e1000g_dma_type_lock; 241 242 243 /* 244 * Loadable module configuration entry points for the driver 245 */ 246 247 /* 248 * ********************************************************************** 249 * Name: _init * 250 * * 251 * Description: * 252 * Initializes a loadable module. It is called before * 253 * any other routine in a loadable module. * 254 * All global locks are intialised here and it returns the retun * 255 * value from mod_install() * 256 * This is mandotary function for the driver * 257 * Parameter Passed: * 258 * None * 259 * Return Value: * 260 * 0 on success * 261 * Functions called * 262 * mod_install() (system call) * 263 * * 264 * ********************************************************************** 265 */ 266 int 267 _init(void) 268 { 269 int status; 270 271 mac_init_ops(&ws_ops, WSNAME); 272 status = mod_install(&modlinkage); 273 if (status != DDI_SUCCESS) 274 mac_fini_ops(&ws_ops); 275 else { 276 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 277 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 278 } 279 280 return (status); 281 } 282 283 /* 284 * ********************************************************************** 285 * Name: _fini * 286 * * 287 * Description: * 288 * Prepares a loadable module for unloading. It is * 289 * called when the system wants to unload a module. * 290 * This is mandotary function for the driver * 291 * Parameter Passed: * 292 * None * 293 * Return Value: * 294 * 0 on success * 295 * Functions called * 296 * mod_remove() (system call) * 297 * * 298 * * 299 * * 300 * ********************************************************************** 301 */ 302 int 303 _fini(void) 304 { 305 int status; 306 307 rw_enter(&e1000g_rx_detach_lock, RW_READER); 308 if (e1000g_mblks_pending != 0) { 309 rw_exit(&e1000g_rx_detach_lock); 310 return (EBUSY); 311 } 312 rw_exit(&e1000g_rx_detach_lock); 313 314 status = mod_remove(&modlinkage); 315 if (status == DDI_SUCCESS) { 316 mac_fini_ops(&ws_ops); 317 rw_destroy(&e1000g_rx_detach_lock); 318 rw_destroy(&e1000g_dma_type_lock); 319 } 320 321 return (status); 322 } 323 324 /* 325 * ********************************************************************** 326 * Name: _info * 327 * * 328 * Description: * 329 * Returns information about a loadable module. * 330 * This is mandotary function for the driver * 331 * Parameter Passed: * 332 * module info structure * 333 * Return Value: * 334 * 0 on success * 335 * Functions called * 336 * mod_info() (system call) * 337 * * 338 * * 339 * ********************************************************************** 340 */ 341 int 342 _info(struct modinfo *modinfop) 343 { 344 return (mod_info(&modlinkage, modinfop)); 345 } 346 347 /* 348 * Interface exists: make available by filling in network interface 349 * record. System will initialize the interface when it is ready 350 * to accept packets. 351 */ 352 353 /* 354 * ********************************************************************** 355 * Name: e1000gattach * 356 * * 357 * Description: * 358 * This function is the device-specific initialization * 359 * entry point. This entry point is required and must be writ- * 360 * ten. The DDI_ATTACH command must be provided in the attach * 361 * entry point. When attach() is called with cmd set to DDI_ATTACH, * 362 * all normal kernel services (such as kmem_alloc(9F)) are * 363 * available for use by the driver. Device interrupts are not * 364 * blocked when attaching a device to the system. * 365 * * 366 * The attach() function will be called once for each instance * 367 * of the device on the system with cmd set to DDI_ATTACH. * 368 * Until attach() succeeds, the only driver entry points which * 369 * may be called are open(9E) and getinfo(9E). * 370 * * 371 * * 372 * * 373 * Parameter Passed: * 374 * * 375 * Return Value: * 376 * * 377 * Functions called * 378 * * 379 * * 380 * ********************************************************************** 381 */ 382 static int 383 e1000gattach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 384 { 385 struct e1000g *Adapter; 386 struct e1000_hw *hw; 387 ddi_acc_handle_t handle; 388 off_t mem_size; 389 int instance; 390 391 switch (cmd) { 392 default: 393 e1000g_log(NULL, CE_WARN, 394 "Unsupported command send to e1000gattach... "); 395 return (DDI_FAILURE); 396 397 case DDI_RESUME: 398 return (e1000g_resume(devinfo)); 399 400 case DDI_ATTACH: 401 break; 402 } 403 404 /* 405 * get device instance number 406 */ 407 instance = ddi_get_instance(devinfo); 408 409 /* 410 * Allocate soft data structure 411 */ 412 Adapter = 413 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 414 415 Adapter->dip = devinfo; 416 Adapter->AdapterInstance = instance; 417 Adapter->tx_ring->adapter = Adapter; 418 Adapter->rx_ring->adapter = Adapter; 419 420 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 421 422 hw = &Adapter->Shared; 423 424 /* 425 * Map in the device registers. 426 * 427 * first get the size of device register to be mapped. The 428 * second parameter is the register we are interested. I our 429 * wiseman 0 is for config registers and 1 is for memory mapped 430 * registers Mem size should have memory mapped region size 431 */ 432 ddi_dev_regsize(devinfo, 1, /* register of interest */ 433 (off_t *)&mem_size); 434 435 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 436 (caddr_t *)&hw->hw_addr, 437 0, mem_size, &accattr1, &Adapter->E1000_handle)) 438 != DDI_SUCCESS) { 439 e1000g_log(Adapter, CE_WARN, "ddi_regs_map_setup failed"); 440 goto attach_fail; 441 } 442 Adapter->attach_progress |= ATTACH_PROGRESS_REGSMAPPED; 443 444 Adapter->osdep.E1000_handle = Adapter->E1000_handle; 445 hw->back = &Adapter->osdep; 446 447 /* 448 * PCI Configure 449 */ 450 if (pci_config_setup(devinfo, &handle) != DDI_SUCCESS) { 451 e1000g_log(Adapter, CE_WARN, 452 "PCI configuration could not be read."); 453 goto attach_fail; 454 } 455 456 Adapter->handle = handle; 457 Adapter->osdep.handle = handle; 458 459 hw->vendor_id = 460 pci_config_get16(handle, PCI_CONF_VENID); 461 hw->device_id = 462 pci_config_get16(handle, PCI_CONF_DEVID); 463 hw->revision_id = 464 pci_config_get8(handle, PCI_CONF_REVID); 465 hw->subsystem_id = 466 pci_config_get16(handle, PCI_CONF_SUBSYSID); 467 hw->subsystem_vendor_id = 468 pci_config_get16(handle, PCI_CONF_SUBVENID); 469 470 Adapter->attach_progress |= ATTACH_PROGRESS_PCICONFIG; 471 472 /* 473 * Initialize driver parameters 474 */ 475 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 476 goto attach_fail; 477 } 478 Adapter->attach_progress |= ATTACH_PROGRESS_PROP; 479 480 /* 481 * Initialize interrupts 482 */ 483 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 484 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 485 goto attach_fail; 486 } 487 Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; 488 Adapter->attach_progress |= ATTACH_PROGRESS_INTRADDED; 489 490 /* 491 * Initialize mutex's for this device. 492 * Do this before enabling the interrupt handler and 493 * register the softint to avoid the condition where 494 * interrupt handler can try using uninitialized mutex 495 */ 496 e1000g_init_locks(Adapter); 497 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 498 499 if (ddi_intr_add_softint(devinfo, 500 &Adapter->tx_softint_handle, Adapter->tx_softint_pri, 501 e1000g_tx_freemsg, (caddr_t)Adapter) != DDI_SUCCESS) { 502 e1000g_log(Adapter, CE_WARN, "Add soft intr failed"); 503 goto attach_fail; 504 } 505 Adapter->attach_progress |= ATTACH_PROGRESS_SOFTINTR; 506 507 /* 508 * Initialize Driver Counters 509 */ 510 if (InitStatsCounters(Adapter) != DDI_SUCCESS) { 511 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 512 goto attach_fail; 513 } 514 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 515 516 /* 517 * Allocate dma resources for descriptors and buffers 518 */ 519 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 520 e1000g_log(Adapter, CE_WARN, "Alloc dma resources failed"); 521 goto attach_fail; 522 } 523 Adapter->attach_progress |= ATTACH_PROGRESS_ALLOC; 524 525 /* 526 * Initialize chip hardware and software structures 527 */ 528 if (e1000g_init(Adapter) != DDI_SUCCESS) { 529 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 530 goto attach_fail; 531 } 532 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 533 534 /* 535 * Initialize NDD parameters 536 */ 537 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 538 e1000g_log(Adapter, CE_WARN, "Init NDD failed"); 539 goto attach_fail; 540 } 541 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 542 543 /* 544 * Register the driver to the MAC 545 */ 546 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 547 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 548 goto attach_fail; 549 } 550 Adapter->attach_progress |= ATTACH_PROGRESS_MACREGISTERED; 551 552 /* 553 * Now that mutex locks are initialized, and the chip is also 554 * initialized, enable interrupts. 555 */ 556 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 557 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 558 goto attach_fail; 559 } 560 Adapter->attach_progress |= ATTACH_PROGRESS_INTRENABLED; 561 562 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 563 564 return (DDI_SUCCESS); 565 566 attach_fail: 567 e1000g_unattach(devinfo, Adapter); 568 return (DDI_FAILURE); 569 } 570 571 static int 572 e1000g_register_mac(struct e1000g *Adapter) 573 { 574 struct e1000_hw *hw = &Adapter->Shared; 575 mac_register_t *mac; 576 int err; 577 578 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 579 return (DDI_FAILURE); 580 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 581 mac->m_driver = Adapter; 582 mac->m_dip = Adapter->dip; 583 mac->m_src_addr = hw->mac_addr; 584 mac->m_callbacks = &e1000g_m_callbacks; 585 mac->m_min_sdu = 0; 586 mac->m_max_sdu = 587 (hw->max_frame_size > FRAME_SIZE_UPTO_8K) ? 588 hw->max_frame_size - 256 : 589 (hw->max_frame_size != ETHERMAX) ? 590 hw->max_frame_size - 24 : ETHERMTU; 591 err = mac_register(mac, &Adapter->mh); 592 mac_free(mac); 593 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 594 } 595 596 static int 597 e1000g_set_driver_params(struct e1000g *Adapter) 598 { 599 dev_info_t *devinfo; 600 ddi_acc_handle_t handle; 601 struct e1000_hw *hw; 602 uint32_t mem_bar, io_bar; 603 #ifdef __sparc 604 ulong_t iommu_pagesize; 605 #endif 606 607 devinfo = Adapter->dip; 608 handle = Adapter->handle; 609 hw = &Adapter->Shared; 610 611 /* Set Mac Type */ 612 if (e1000_set_mac_type(hw) != 0) { 613 e1000g_log(Adapter, CE_WARN, 614 "Could not identify hardware"); 615 return (DDI_FAILURE); 616 } 617 618 /* ich8 needs to map flash memory */ 619 if (hw->mac_type == e1000_ich8lan) { 620 /* get flash size */ 621 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 622 &Adapter->osdep.ich_flash_size) != DDI_SUCCESS) { 623 e1000g_log(Adapter, CE_WARN, 624 "ddi_dev_regsize for ich8 flash failed"); 625 return (DDI_FAILURE); 626 } 627 628 /* map flash in */ 629 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 630 &Adapter->osdep.ich_flash_base, 0, 631 Adapter->osdep.ich_flash_size, 632 &accattr1, 633 &Adapter->osdep.ich_flash_handle) != DDI_SUCCESS) { 634 e1000g_log(Adapter, CE_WARN, 635 "ddi_regs_map_setup for for ich8 flash failed"); 636 return (DDI_FAILURE); 637 } 638 } 639 640 /* get mem_base addr */ 641 mem_bar = pci_config_get32(handle, PCI_CONF_BASE0); 642 Adapter->bar64 = mem_bar & PCI_BASE_TYPE_ALL; 643 644 /* get io_base addr */ 645 if (hw->mac_type >= e1000_82544) { 646 if (Adapter->bar64) { 647 /* IO BAR is different for 64 bit BAR mode */ 648 io_bar = pci_config_get32(handle, PCI_CONF_BASE4); 649 } else { 650 /* normal 32-bit BAR mode */ 651 io_bar = pci_config_get32(handle, PCI_CONF_BASE2); 652 } 653 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 654 } else { 655 /* no I/O access for adapters prior to 82544 */ 656 hw->io_base = 0x0; 657 } 658 659 e1000_read_pci_cfg(hw, 660 PCI_COMMAND_REGISTER, &(hw->pci_cmd_word)); 661 662 /* Set the wait_autoneg_complete flag to B_FALSE */ 663 hw->wait_autoneg_complete = B_FALSE; 664 665 /* Adaptive IFS related changes */ 666 hw->adaptive_ifs = B_TRUE; 667 668 /* set phy init script revision */ 669 if ((hw->mac_type == e1000_82547) || 670 (hw->mac_type == e1000_82541) || 671 (hw->mac_type == e1000_82547_rev_2) || 672 (hw->mac_type == e1000_82541_rev_2)) 673 hw->phy_init_script = 1; 674 675 /* Enable the TTL workaround for TnT: DCR 49 */ 676 hw->ttl_wa_activation = 1; 677 678 if (hw->mac_type == e1000_82571) 679 hw->laa_is_present = B_TRUE; 680 681 /* Get conf file properties */ 682 e1000g_getparam(Adapter); 683 684 hw->forced_speed_duplex = e1000_100_full; 685 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 686 e1000g_force_speed_duplex(Adapter); 687 688 e1000g_get_max_frame_size(Adapter); 689 hw->min_frame_size = 690 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 691 692 #ifdef __sparc 693 /* Get the system page size */ 694 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 695 iommu_pagesize = dvma_pagesize(devinfo); 696 if (iommu_pagesize != 0) { 697 if (Adapter->sys_page_sz == iommu_pagesize) { 698 if (iommu_pagesize > 0x4000) 699 Adapter->sys_page_sz = 0x4000; 700 } else { 701 if (Adapter->sys_page_sz > iommu_pagesize) 702 Adapter->sys_page_sz = iommu_pagesize; 703 } 704 } 705 Adapter->dvma_page_num = hw->max_frame_size / 706 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 707 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 708 #endif 709 710 /* Set Rx/Tx buffer size */ 711 switch (hw->max_frame_size) { 712 case ETHERMAX: 713 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 714 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 715 break; 716 case FRAME_SIZE_UPTO_4K: 717 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_4K; 718 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_4K; 719 break; 720 case FRAME_SIZE_UPTO_8K: 721 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_8K; 722 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_8K; 723 break; 724 case FRAME_SIZE_UPTO_10K: 725 case FRAME_SIZE_UPTO_16K: 726 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_16K; 727 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_16K; 728 break; 729 default: 730 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 731 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 732 break; 733 } 734 Adapter->RxBufferSize += E1000G_IPALIGNPRESERVEROOM; 735 736 /* 737 * For Wiseman adapters we have an requirement of having receive 738 * buffers aligned at 256 byte boundary. Since Livengood does not 739 * require this and forcing it for all hardwares will have 740 * performance implications, I am making it applicable only for 741 * Wiseman and for Jumbo frames enabled mode as rest of the time, 742 * it is okay to have normal frames...but it does involve a 743 * potential risk where we may loose data if buffer is not 744 * aligned...so all wiseman boards to have 256 byte aligned 745 * buffers 746 */ 747 if (hw->mac_type < e1000_82543) 748 Adapter->RcvBufferAlignment = RECEIVE_BUFFER_ALIGN_SIZE; 749 else 750 /* 751 * For livengood, there is no such Rcv buf alignment 752 * requirement 753 */ 754 Adapter->RcvBufferAlignment = 1; 755 756 /* DmaFairness */ 757 if (hw->mac_type <= e1000_82543) 758 hw->dma_fairness = DEFAULTRXPCIPRIORITYVAL; 759 else 760 hw->dma_fairness = 0; 761 762 /* MasterLatencyTimer */ 763 Adapter->MasterLatencyTimer = DEFAULTMASTERLATENCYTIMERVAL; 764 765 /* MWIEnable */ 766 Adapter->MWIEnable = DEFAULTMWIENABLEVAL; 767 768 /* profile jumbo traffic */ 769 Adapter->ProfileJumboTraffic = DEFAULTPROFILEJUMBOTRAFFIC; 770 771 e1000_set_media_type(hw); 772 /* copper options */ 773 if (hw->media_type == e1000_media_type_copper) { 774 hw->mdix = 0; /* AUTO_ALL_MODES */ 775 hw->disable_polarity_correction = B_FALSE; 776 hw->master_slave = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 777 } 778 779 Adapter->link_state = LINK_STATE_UNKNOWN; 780 781 return (DDI_SUCCESS); 782 } 783 784 /* 785 * ********************************************************************** 786 * Name: e1000gdettach * 787 * * 788 * Description: * 789 * The detach() function is the complement of the attach routine. * 790 * If cmd is set to DDI_DETACH, detach() is used to remove the * 791 * state associated with a given instance of a device node * 792 * prior to the removal of that instance from the system. * 793 * * 794 * The detach() function will be called once for each instance * 795 * of the device for which there has been a successful attach() * 796 * once there are no longer any opens on the device. * 797 * * 798 * Interrupts routine are disabled, All memory allocated by this * 799 * driver are freed. * 800 * * 801 * Parameter Passed: * 802 * devinfo structure, cmd * 803 * * 804 * Return Value: * 805 * DDI_SUCCESS on success * 806 * * 807 * Functions called * 808 * * 809 * * 810 * ********************************************************************** 811 */ 812 static int 813 e1000gdetach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 814 { 815 struct e1000g *Adapter; 816 817 switch (cmd) { 818 default: 819 return (DDI_FAILURE); 820 821 case DDI_SUSPEND: 822 return (e1000g_suspend(devinfo)); 823 824 case DDI_DETACH: 825 break; 826 } 827 828 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 829 if (Adapter == NULL) 830 return (DDI_FAILURE); 831 832 if (Adapter->started) 833 e1000g_stop(Adapter); 834 835 if (!e1000g_rx_drain(Adapter)) { 836 if (!force_detach_enabled) 837 return (DDI_FAILURE); 838 } 839 840 if (e1000g_disable_intrs(Adapter) != DDI_SUCCESS) { 841 e1000g_log(Adapter, CE_WARN, 842 "Disable DDI interrupts failed"); 843 return (DDI_FAILURE); 844 } 845 Adapter->attach_progress &= ~ATTACH_PROGRESS_INTRENABLED; 846 847 if (mac_unregister(Adapter->mh) != 0) { 848 e1000g_log(Adapter, CE_WARN, 849 "Unregister MAC failed"); 850 return (DDI_FAILURE); 851 } 852 Adapter->attach_progress &= ~ATTACH_PROGRESS_MACREGISTERED; 853 854 e1000g_unattach(devinfo, Adapter); 855 856 return (DDI_SUCCESS); 857 } 858 859 static void 860 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 861 { 862 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRENABLED) { 863 (void) e1000g_disable_intrs(Adapter); 864 } 865 866 if (Adapter->attach_progress & ATTACH_PROGRESS_MACREGISTERED) { 867 (void) mac_unregister(Adapter->mh); 868 } 869 870 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 871 e1000g_nd_cleanup(Adapter); 872 } 873 874 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRADDED) { 875 (void) e1000g_rem_intrs(Adapter); 876 } 877 878 if (Adapter->attach_progress & ATTACH_PROGRESS_SOFTINTR) { 879 (void) ddi_intr_remove_softint(Adapter->tx_softint_handle); 880 } 881 882 if (Adapter->attach_progress & ATTACH_PROGRESS_PROP) { 883 (void) ddi_prop_remove_all(devinfo); 884 } 885 886 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 887 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 888 } 889 890 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 891 e1000_reset_hw(&Adapter->Shared); 892 } 893 894 if (Adapter->attach_progress & ATTACH_PROGRESS_REGSMAPPED) { 895 ddi_regs_map_free(&Adapter->E1000_handle); 896 } 897 898 if (Adapter->attach_progress & ATTACH_PROGRESS_PCICONFIG) { 899 pci_config_teardown(&Adapter->handle); 900 } 901 902 if (Adapter->attach_progress & ATTACH_PROGRESS_ALLOC) { 903 e1000g_release_dma_resources(Adapter); 904 } 905 906 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 907 e1000g_destroy_locks(Adapter); 908 } 909 910 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 911 912 /* 913 * Another hotplug spec requirement, 914 * run ddi_set_driver_private(devinfo, null); 915 */ 916 ddi_set_driver_private(devinfo, NULL); 917 } 918 919 static void 920 e1000g_init_locks(struct e1000g *Adapter) 921 { 922 e1000g_tx_ring_t *tx_ring; 923 e1000g_rx_ring_t *rx_ring; 924 925 rw_init(&Adapter->chip_lock, NULL, 926 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 927 mutex_init(&Adapter->e1000g_linklock, NULL, 928 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 929 mutex_init(&Adapter->e1000g_timeout_lock, NULL, 930 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 931 mutex_init(&Adapter->TbiCntrMutex, NULL, 932 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 933 934 mutex_init(&Adapter->tx_msg_chain->lock, NULL, 935 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->tx_softint_pri)); 936 937 tx_ring = Adapter->tx_ring; 938 939 mutex_init(&tx_ring->tx_lock, NULL, 940 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 941 mutex_init(&tx_ring->usedlist_lock, NULL, 942 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 943 mutex_init(&tx_ring->freelist_lock, NULL, 944 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 945 946 rx_ring = Adapter->rx_ring; 947 948 mutex_init(&rx_ring->rx_lock, NULL, 949 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 950 mutex_init(&rx_ring->freelist_lock, NULL, 951 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 952 } 953 954 static void 955 e1000g_destroy_locks(struct e1000g *Adapter) 956 { 957 e1000g_tx_ring_t *tx_ring; 958 e1000g_rx_ring_t *rx_ring; 959 960 tx_ring = Adapter->tx_ring; 961 mutex_destroy(&tx_ring->tx_lock); 962 mutex_destroy(&tx_ring->usedlist_lock); 963 mutex_destroy(&tx_ring->freelist_lock); 964 965 rx_ring = Adapter->rx_ring; 966 mutex_destroy(&rx_ring->rx_lock); 967 mutex_destroy(&rx_ring->freelist_lock); 968 969 mutex_destroy(&Adapter->tx_msg_chain->lock); 970 mutex_destroy(&Adapter->e1000g_linklock); 971 mutex_destroy(&Adapter->TbiCntrMutex); 972 mutex_destroy(&Adapter->e1000g_timeout_lock); 973 rw_destroy(&Adapter->chip_lock); 974 } 975 976 static int 977 e1000g_resume(dev_info_t *devinfo) 978 { 979 struct e1000g *Adapter; 980 981 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 982 if (Adapter == NULL) 983 return (DDI_FAILURE); 984 985 if (e1000g_start(Adapter)) 986 return (DDI_FAILURE); 987 988 return (DDI_SUCCESS); 989 } 990 991 static int 992 e1000g_suspend(dev_info_t *devinfo) 993 { 994 struct e1000g *Adapter; 995 996 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 997 if (Adapter == NULL) 998 return (DDI_FAILURE); 999 1000 e1000g_stop(Adapter); 1001 1002 return (DDI_SUCCESS); 1003 } 1004 1005 static int 1006 e1000g_init(struct e1000g *Adapter) 1007 { 1008 uint32_t pba; 1009 uint32_t ctrl; 1010 struct e1000_hw *hw; 1011 clock_t link_timeout; 1012 1013 hw = &Adapter->Shared; 1014 1015 rw_enter(&Adapter->chip_lock, RW_WRITER); 1016 1017 /* Preserve manageability features */ 1018 e1000_check_phy_reset_block(hw); 1019 1020 /* 1021 * reset to put the hardware in a known state 1022 * before we try to do anything with the eeprom 1023 */ 1024 (void) e1000_reset_hw(hw); 1025 1026 (void) e1000_init_eeprom_params(hw); 1027 1028 if (e1000_validate_eeprom_checksum(hw) < 0) { 1029 /* 1030 * Some PCI-E parts fail the first check due to 1031 * the link being in sleep state. Call it again, 1032 * if it fails a second time its a real issue. 1033 */ 1034 if (e1000_validate_eeprom_checksum(hw) < 0) { 1035 e1000g_log(Adapter, CE_WARN, 1036 "Invalid EEPROM checksum. Please contact " 1037 "the vendor to update the EEPROM."); 1038 goto init_fail; 1039 } 1040 } 1041 1042 #ifdef __sparc 1043 /* 1044 * Firstly, we try to get the local ethernet address from OBP. If 1045 * fail, we get from EEPROM of NIC card. 1046 */ 1047 if (!e1000g_find_mac_address(Adapter)) { 1048 if (e1000_read_mac_addr(hw) < 0) { 1049 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1050 goto init_fail; 1051 } 1052 } 1053 #else 1054 /* Get the local ethernet address. */ 1055 if (e1000_read_mac_addr(hw) < 0) { 1056 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1057 goto init_fail; 1058 } 1059 #endif 1060 1061 /* check for valid mac address */ 1062 if (!is_valid_mac_addr(hw->mac_addr)) { 1063 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1064 goto init_fail; 1065 } 1066 1067 e1000_get_bus_info(hw); 1068 1069 /* Master Latency Timer implementation */ 1070 if (Adapter->MasterLatencyTimer) { 1071 pci_config_put8(Adapter->handle, PCI_CONF_LATENCY_TIMER, 1072 Adapter->MasterLatencyTimer); 1073 } 1074 1075 if (hw->mac_type < e1000_82547) { 1076 /* 1077 * Total FIFO is 64K 1078 */ 1079 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1080 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1081 else 1082 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1083 } else if (hw->mac_type >= e1000_82571 && 1084 hw->mac_type <= e1000_82572) { 1085 /* 1086 * Total FIFO is 48K 1087 */ 1088 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1089 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1090 else 1091 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1092 } else if (hw->mac_type == e1000_ich8lan) { 1093 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1094 } else { 1095 /* 1096 * Total FIFO is 40K 1097 */ 1098 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1099 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1100 else 1101 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1102 } 1103 E1000_WRITE_REG(hw, PBA, pba); 1104 1105 /* 1106 * These parameters set thresholds for the adapter's generation(Tx) 1107 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1108 * settings. Flow control is enabled or disabled in the configuration 1109 * file. 1110 * High-water mark is set down from the top of the rx fifo (not 1111 * sensitive to max_frame_size) and low-water is set just below 1112 * high-water mark. 1113 */ 1114 hw->fc_high_water = 1115 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1116 E1000_FC_HIGH_DIFF; 1117 hw->fc_low_water = 1118 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1119 E1000_FC_LOW_DIFF; 1120 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 1121 hw->fc_send_xon = B_TRUE; 1122 1123 /* 1124 * Reset the adapter hardware the second time. 1125 */ 1126 (void) e1000_reset_hw(hw); 1127 1128 /* disable wakeup control by default */ 1129 if (hw->mac_type >= e1000_82544) 1130 E1000_WRITE_REG(hw, WUC, 0); 1131 1132 /* MWI setup */ 1133 if (Adapter->MWIEnable) { 1134 hw->pci_cmd_word |= CMD_MEM_WRT_INVALIDATE; 1135 e1000_pci_set_mwi(hw); 1136 } else 1137 e1000_pci_clear_mwi(hw); 1138 1139 /* 1140 * Configure/Initialize hardware 1141 */ 1142 if (e1000_init_hw(hw) < 0) { 1143 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1144 goto init_fail; 1145 } 1146 1147 /* Disable Smart Power Down */ 1148 phy_spd_state(hw, B_FALSE); 1149 1150 /* 1151 * Initialize unicast addresses. 1152 */ 1153 e1000g_init_unicst(Adapter); 1154 1155 /* 1156 * Setup and initialize the transmit structures. 1157 */ 1158 SetupTransmitStructures(Adapter); 1159 DelayInMilliseconds(5); 1160 1161 /* 1162 * Setup and initialize the mctable structures. After this routine 1163 * completes Multicast table will be set 1164 */ 1165 SetupMulticastTable(Adapter); 1166 DelayInMilliseconds(5); 1167 1168 /* 1169 * Setup and initialize the receive structures. After this routine 1170 * completes we can receive packets off of the wire. 1171 */ 1172 SetupReceiveStructures(Adapter); 1173 DelayInMilliseconds(5); 1174 1175 /* 1176 * Implement Adaptive IFS 1177 */ 1178 e1000_reset_adaptive(hw); 1179 1180 /* Setup Interrupt Throttling Register */ 1181 E1000_WRITE_REG(hw, ITR, Adapter->intr_throttling_rate); 1182 1183 /* Start the timer for link setup */ 1184 if (hw->autoneg) 1185 link_timeout = PHY_AUTO_NEG_TIME * drv_usectohz(100000); 1186 else 1187 link_timeout = PHY_FORCE_TIME * drv_usectohz(100000); 1188 1189 mutex_enter(&Adapter->e1000g_linklock); 1190 if (hw->wait_autoneg_complete) { 1191 Adapter->link_complete = B_TRUE; 1192 } else { 1193 Adapter->link_complete = B_FALSE; 1194 Adapter->link_tid = timeout(e1000g_link_timer, 1195 (void *)Adapter, link_timeout); 1196 } 1197 mutex_exit(&Adapter->e1000g_linklock); 1198 1199 /* Enable PCI-Ex master */ 1200 if (hw->bus_type == e1000_bus_type_pci_express) { 1201 e1000_enable_pciex_master(hw); 1202 } 1203 1204 Adapter->init_count++; 1205 1206 rw_exit(&Adapter->chip_lock); 1207 1208 return (DDI_SUCCESS); 1209 1210 init_fail: 1211 rw_exit(&Adapter->chip_lock); 1212 return (DDI_FAILURE); 1213 } 1214 1215 /* 1216 * Check if the link is up 1217 */ 1218 static boolean_t 1219 e1000g_link_up(struct e1000g *Adapter) 1220 { 1221 struct e1000_hw *hw; 1222 boolean_t link_up; 1223 1224 hw = &Adapter->Shared; 1225 1226 /* Ensure this is set to get accurate copper link status */ 1227 hw->get_link_status = B_TRUE; 1228 1229 e1000_check_for_link(hw); 1230 1231 if ((E1000_READ_REG(hw, STATUS) & E1000_STATUS_LU) || 1232 ((!hw->get_link_status) && (hw->mac_type == e1000_82543)) || 1233 ((hw->media_type == e1000_media_type_internal_serdes) && 1234 (!hw->serdes_link_down))) { 1235 link_up = B_TRUE; 1236 } else { 1237 link_up = B_FALSE; 1238 } 1239 1240 return (link_up); 1241 } 1242 1243 static void 1244 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1245 { 1246 struct iocblk *iocp; 1247 struct e1000g *e1000gp; 1248 enum ioc_reply status; 1249 int err; 1250 1251 iocp = (struct iocblk *)mp->b_rptr; 1252 iocp->ioc_error = 0; 1253 e1000gp = (struct e1000g *)arg; 1254 1255 ASSERT(e1000gp); 1256 if (e1000gp == NULL) { 1257 miocnak(q, mp, 0, EINVAL); 1258 return; 1259 } 1260 1261 switch (iocp->ioc_cmd) { 1262 1263 case LB_GET_INFO_SIZE: 1264 case LB_GET_INFO: 1265 case LB_GET_MODE: 1266 case LB_SET_MODE: 1267 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1268 break; 1269 1270 case ND_GET: 1271 case ND_SET: 1272 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1273 break; 1274 1275 case E1000G_IOC_REG_PEEK: 1276 case E1000G_IOC_REG_POKE: 1277 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1278 break; 1279 case E1000G_IOC_CHIP_RESET: 1280 e1000gp->reset_count++; 1281 if (e1000g_reset(e1000gp)) 1282 status = IOC_ACK; 1283 else 1284 status = IOC_INVAL; 1285 break; 1286 default: 1287 status = IOC_INVAL; 1288 break; 1289 } 1290 1291 /* 1292 * Decide how to reply 1293 */ 1294 switch (status) { 1295 default: 1296 case IOC_INVAL: 1297 /* 1298 * Error, reply with a NAK and EINVAL or the specified error 1299 */ 1300 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1301 EINVAL : iocp->ioc_error); 1302 break; 1303 1304 case IOC_DONE: 1305 /* 1306 * OK, reply already sent 1307 */ 1308 break; 1309 1310 case IOC_ACK: 1311 /* 1312 * OK, reply with an ACK 1313 */ 1314 miocack(q, mp, 0, 0); 1315 break; 1316 1317 case IOC_REPLY: 1318 /* 1319 * OK, send prepared reply as ACK or NAK 1320 */ 1321 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1322 M_IOCACK : M_IOCNAK; 1323 qreply(q, mp); 1324 break; 1325 } 1326 } 1327 1328 static void e1000g_m_blank(void *arg, time_t ticks, uint32_t count) 1329 { 1330 struct e1000g *Adapter; 1331 1332 Adapter = (struct e1000g *)arg; 1333 1334 /* 1335 * Adjust ITR (Interrupt Throttling Register) to coalesce 1336 * interrupts. This formula and its coefficient come from 1337 * our experiments. 1338 */ 1339 if (Adapter->intr_adaptive) { 1340 Adapter->intr_throttling_rate = count << 5; 1341 E1000_WRITE_REG(&Adapter->Shared, ITR, 1342 Adapter->intr_throttling_rate); 1343 } 1344 } 1345 1346 static void 1347 e1000g_m_resources(void *arg) 1348 { 1349 struct e1000g *adapter = (struct e1000g *)arg; 1350 mac_rx_fifo_t mrf; 1351 1352 mrf.mrf_type = MAC_RX_FIFO; 1353 mrf.mrf_blank = e1000g_m_blank; 1354 mrf.mrf_arg = (void *)adapter; 1355 mrf.mrf_normal_blank_time = E1000_RX_INTPT_TIME; 1356 mrf.mrf_normal_pkt_count = E1000_RX_PKT_CNT; 1357 1358 adapter->mrh = mac_resource_add(adapter->mh, (mac_resource_t *)&mrf); 1359 } 1360 1361 static int 1362 e1000g_m_start(void *arg) 1363 { 1364 struct e1000g *Adapter = (struct e1000g *)arg; 1365 1366 return (e1000g_start(Adapter)); 1367 } 1368 1369 static int 1370 e1000g_start(struct e1000g *Adapter) 1371 { 1372 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1373 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1374 e1000g_log(Adapter, CE_WARN, 1375 "Adapter initialization failed"); 1376 return (ENOTACTIVE); 1377 } 1378 } 1379 1380 enable_timeout(Adapter); 1381 1382 rw_enter(&Adapter->chip_lock, RW_WRITER); 1383 1384 e1000g_EnableInterrupt(Adapter); 1385 if (Adapter->tx_intr_enable) 1386 e1000g_EnableTxInterrupt(Adapter); 1387 1388 Adapter->started = B_TRUE; 1389 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1390 1391 rw_exit(&Adapter->chip_lock); 1392 1393 return (0); 1394 } 1395 1396 static void 1397 e1000g_m_stop(void *arg) 1398 { 1399 struct e1000g *Adapter = (struct e1000g *)arg; 1400 1401 e1000g_stop(Adapter); 1402 } 1403 1404 static void 1405 e1000g_stop(struct e1000g *Adapter) 1406 { 1407 timeout_id_t tid; 1408 e1000g_tx_ring_t *tx_ring; 1409 boolean_t link_changed; 1410 1411 tx_ring = Adapter->tx_ring; 1412 1413 /* Set stop flags */ 1414 rw_enter(&Adapter->chip_lock, RW_WRITER); 1415 1416 Adapter->started = B_FALSE; 1417 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1418 1419 rw_exit(&Adapter->chip_lock); 1420 1421 /* Drain tx sessions */ 1422 (void) e1000g_tx_drain(Adapter); 1423 1424 /* Disable timers */ 1425 disable_timeout(Adapter); 1426 1427 /* Disable the tx timer for 82547 chipset */ 1428 mutex_enter(&tx_ring->tx_lock); 1429 tx_ring->timer_enable_82547 = B_FALSE; 1430 tid = tx_ring->timer_id_82547; 1431 tx_ring->timer_id_82547 = 0; 1432 mutex_exit(&tx_ring->tx_lock); 1433 1434 if (tid != 0) 1435 (void) untimeout(tid); 1436 1437 /* Disable the link timer */ 1438 mutex_enter(&Adapter->e1000g_linklock); 1439 tid = Adapter->link_tid; 1440 Adapter->link_tid = 0; 1441 mutex_exit(&Adapter->e1000g_linklock); 1442 1443 if (tid != 0) 1444 (void) untimeout(tid); 1445 1446 /* Stop the chip and release pending resources */ 1447 rw_enter(&Adapter->chip_lock, RW_WRITER); 1448 1449 e1000g_DisableAllInterrupts(Adapter); 1450 1451 e1000_reset_hw(&Adapter->Shared); 1452 1453 /* Release resources still held by the TX descriptors */ 1454 e1000g_tx_drop(Adapter); 1455 1456 /* Clean the pending rx jumbo packet fragment */ 1457 if (Adapter->rx_mblk != NULL) { 1458 freemsg(Adapter->rx_mblk); 1459 Adapter->rx_mblk = NULL; 1460 Adapter->rx_mblk_tail = NULL; 1461 Adapter->rx_packet_len = 0; 1462 } 1463 1464 rw_exit(&Adapter->chip_lock); 1465 } 1466 1467 static void 1468 e1000g_tx_drop(struct e1000g *Adapter) 1469 { 1470 e1000g_tx_ring_t *tx_ring; 1471 e1000g_msg_chain_t *msg_chain; 1472 PTX_SW_PACKET packet; 1473 mblk_t *mp; 1474 mblk_t *nmp; 1475 uint32_t packet_count; 1476 1477 tx_ring = Adapter->tx_ring; 1478 1479 /* 1480 * Here we don't need to protect the lists using 1481 * the usedlist_lock and freelist_lock, for they 1482 * have been protected by the chip_lock. 1483 */ 1484 mp = NULL; 1485 nmp = NULL; 1486 packet_count = 0; 1487 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list); 1488 while (packet != NULL) { 1489 if (packet->mp != NULL) { 1490 /* Assemble the message chain */ 1491 if (mp == NULL) { 1492 mp = packet->mp; 1493 nmp = packet->mp; 1494 } else { 1495 nmp->b_next = packet->mp; 1496 nmp = packet->mp; 1497 } 1498 /* Disconnect the message from the sw packet */ 1499 packet->mp = NULL; 1500 } 1501 1502 FreeTxSwPacket(packet); 1503 packet_count++; 1504 1505 packet = (PTX_SW_PACKET) 1506 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1507 } 1508 1509 if (mp != NULL) { 1510 msg_chain = Adapter->tx_msg_chain; 1511 mutex_enter(&msg_chain->lock); 1512 if (msg_chain->head == NULL) { 1513 msg_chain->head = mp; 1514 msg_chain->tail = nmp; 1515 } else { 1516 msg_chain->tail->b_next = mp; 1517 msg_chain->tail = nmp; 1518 } 1519 mutex_exit(&msg_chain->lock); 1520 } 1521 1522 ddi_intr_trigger_softint(Adapter->tx_softint_handle, NULL); 1523 1524 if (packet_count > 0) { 1525 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1526 QUEUE_INIT_LIST(&tx_ring->used_list); 1527 1528 /* Setup TX descriptor pointers */ 1529 tx_ring->tbd_next = tx_ring->tbd_first; 1530 tx_ring->tbd_oldest = tx_ring->tbd_first; 1531 1532 /* Setup our HW Tx Head & Tail descriptor pointers */ 1533 E1000_WRITE_REG(&Adapter->Shared, TDH, 0); 1534 E1000_WRITE_REG(&Adapter->Shared, TDT, 0); 1535 } 1536 } 1537 1538 static boolean_t 1539 e1000g_tx_drain(struct e1000g *Adapter) 1540 { 1541 int i; 1542 boolean_t done; 1543 e1000g_tx_ring_t *tx_ring; 1544 1545 tx_ring = Adapter->tx_ring; 1546 1547 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1548 for (i = 0; i < WSDRAINTIME; i++) { 1549 mutex_enter(&tx_ring->usedlist_lock); 1550 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1551 mutex_exit(&tx_ring->usedlist_lock); 1552 1553 if (done) 1554 break; 1555 1556 msec_delay(1); 1557 } 1558 1559 return (done); 1560 } 1561 1562 static boolean_t 1563 e1000g_rx_drain(struct e1000g *Adapter) 1564 { 1565 boolean_t done; 1566 1567 mutex_enter(&Adapter->rx_ring->freelist_lock); 1568 done = (Adapter->rx_avail_freepkt == Adapter->NumRxFreeList); 1569 mutex_exit(&Adapter->rx_ring->freelist_lock); 1570 1571 return (done); 1572 } 1573 1574 boolean_t 1575 e1000g_reset(struct e1000g *Adapter) 1576 { 1577 e1000g_stop(Adapter); 1578 1579 if (e1000g_start(Adapter)) { 1580 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1581 return (B_FALSE); 1582 } 1583 1584 return (B_TRUE); 1585 } 1586 1587 /* 1588 * ********************************************************************** 1589 * Name: e1000g_intr_pciexpress * 1590 * * 1591 * Description: * 1592 * This interrupt service routine is for PCI-Express adapters. * 1593 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED * 1594 * bit is set. * 1595 * * 1596 * Parameter Passed: * 1597 * * 1598 * Return Value: * 1599 * * 1600 * Functions called: * 1601 * e1000g_intr_work * 1602 * * 1603 * ********************************************************************** 1604 */ 1605 static uint_t 1606 e1000g_intr_pciexpress(caddr_t arg) 1607 { 1608 struct e1000g *Adapter; 1609 uint32_t ICRContents; 1610 1611 Adapter = (struct e1000g *)arg; 1612 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1613 1614 if (ICRContents & E1000_ICR_INT_ASSERTED) { 1615 /* 1616 * E1000_ICR_INT_ASSERTED bit was set: 1617 * Read(Clear) the ICR, claim this interrupt, 1618 * look for work to do. 1619 */ 1620 e1000g_intr_work(Adapter, ICRContents); 1621 return (DDI_INTR_CLAIMED); 1622 } else { 1623 /* 1624 * E1000_ICR_INT_ASSERTED bit was not set: 1625 * Don't claim this interrupt, return immediately. 1626 */ 1627 return (DDI_INTR_UNCLAIMED); 1628 } 1629 } 1630 1631 /* 1632 * ********************************************************************** 1633 * Name: e1000g_intr * 1634 * * 1635 * Description: * 1636 * This interrupt service routine is for PCI/PCI-X adapters. * 1637 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED * 1638 * bit is set or not. * 1639 * * 1640 * Parameter Passed: * 1641 * * 1642 * Return Value: * 1643 * * 1644 * Functions called: * 1645 * e1000g_intr_work * 1646 * * 1647 * ********************************************************************** 1648 */ 1649 static uint_t 1650 e1000g_intr(caddr_t arg) 1651 { 1652 struct e1000g *Adapter; 1653 uint32_t ICRContents; 1654 1655 Adapter = (struct e1000g *)arg; 1656 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1657 1658 if (ICRContents) { 1659 /* 1660 * Any bit was set in ICR: 1661 * Read(Clear) the ICR, claim this interrupt, 1662 * look for work to do. 1663 */ 1664 e1000g_intr_work(Adapter, ICRContents); 1665 return (DDI_INTR_CLAIMED); 1666 } else { 1667 /* 1668 * No bit was set in ICR: 1669 * Don't claim this interrupt, return immediately. 1670 */ 1671 return (DDI_INTR_UNCLAIMED); 1672 } 1673 } 1674 1675 /* 1676 * ********************************************************************** 1677 * Name: e1000g_intr_work * 1678 * * 1679 * Description: * 1680 * Called from interrupt service routines. * 1681 * Read(clear) the ICR contents and call appropriate interrupt * 1682 * processing routines. * 1683 * * 1684 * Parameter Passed: * 1685 * * 1686 * Return Value: * 1687 * * 1688 * Functions called: * 1689 * e1000g_receive * 1690 * e1000g_link_check * 1691 * e1000g_recycle * 1692 * * 1693 * ********************************************************************** 1694 */ 1695 static void 1696 e1000g_intr_work(struct e1000g *Adapter, uint32_t ICRContents) 1697 { 1698 if (ICRContents & E1000_ICR_RXT0) { 1699 mblk_t *mp; 1700 1701 rw_enter(&Adapter->chip_lock, RW_READER); 1702 /* 1703 * Here we need to check the "started" flag to ensure the 1704 * receive routine will not execute when the adapter is 1705 * stopped or being reset. 1706 */ 1707 if (Adapter->started) { 1708 mutex_enter(&Adapter->rx_ring->rx_lock); 1709 mp = e1000g_receive(Adapter); 1710 mutex_exit(&Adapter->rx_ring->rx_lock); 1711 1712 rw_exit(&Adapter->chip_lock); 1713 1714 if (mp != NULL) 1715 mac_rx(Adapter->mh, Adapter->mrh, mp); 1716 } else { 1717 rw_exit(&Adapter->chip_lock); 1718 } 1719 } 1720 1721 /* 1722 * The Receive Sequence errors RXSEQ and the link status change LSC 1723 * are checked to detect that the cable has been pulled out. For 1724 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1725 * are an indication that cable is not connected. 1726 */ 1727 if ((ICRContents & E1000_ICR_RXSEQ) || 1728 (ICRContents & E1000_ICR_LSC) || 1729 (ICRContents & E1000_ICR_GPI_EN1)) { 1730 boolean_t link_changed; 1731 timeout_id_t tid = 0; 1732 1733 /* 1734 * Encountered RX Sequence Error!!! Link maybe forced and 1735 * the cable may have just been disconnected so we will 1736 * read the LOS to see. 1737 */ 1738 if (ICRContents & E1000_ICR_RXSEQ) 1739 Adapter->rx_seq_intr++; 1740 1741 stop_timeout(Adapter); 1742 1743 mutex_enter(&Adapter->e1000g_linklock); 1744 /* e1000g_link_check takes care of link status change */ 1745 link_changed = e1000g_link_check(Adapter); 1746 /* 1747 * If the link timer has not timed out, we'll not notify 1748 * the upper layer with any link state until the link 1749 * is up. 1750 */ 1751 if (link_changed && !Adapter->link_complete) { 1752 if (Adapter->link_state == LINK_STATE_UP) { 1753 Adapter->link_complete = B_TRUE; 1754 tid = Adapter->link_tid; 1755 Adapter->link_tid = 0; 1756 } else { 1757 link_changed = B_FALSE; 1758 } 1759 } 1760 mutex_exit(&Adapter->e1000g_linklock); 1761 1762 if (link_changed) { 1763 if (tid != 0) 1764 (void) untimeout(tid); 1765 1766 mac_link_update(Adapter->mh, Adapter->link_state); 1767 } 1768 1769 start_timeout(Adapter); 1770 } 1771 1772 if (ICRContents & E1000G_ICR_TX_INTR) { 1773 if (!Adapter->tx_intr_enable) 1774 e1000g_DisableTxInterrupt(Adapter); 1775 /* Schedule the re-transmit */ 1776 if (Adapter->resched_needed) { 1777 Adapter->tx_reschedule++; 1778 Adapter->resched_needed = B_FALSE; 1779 mac_tx_update(Adapter->mh); 1780 } 1781 if (Adapter->tx_intr_enable) { 1782 /* Recycle the tx descriptors */ 1783 rw_enter(&Adapter->chip_lock, RW_READER); 1784 Adapter->tx_recycle_intr++; 1785 e1000g_recycle(Adapter->tx_ring); 1786 rw_exit(&Adapter->chip_lock); 1787 /* Free the recycled messages */ 1788 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 1789 NULL); 1790 } 1791 } 1792 } 1793 1794 static void 1795 e1000g_init_unicst(struct e1000g *Adapter) 1796 { 1797 struct e1000_hw *hw; 1798 int slot; 1799 1800 hw = &Adapter->Shared; 1801 1802 if (Adapter->init_count == 0) { 1803 /* Initialize the multiple unicast addresses */ 1804 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1805 1806 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1807 Adapter->unicst_total--; 1808 1809 Adapter->unicst_avail = Adapter->unicst_total - 1; 1810 1811 /* Store the default mac address */ 1812 e1000_rar_set(hw, hw->mac_addr, 0); 1813 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1814 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1815 1816 bcopy(hw->mac_addr, Adapter->unicst_addr[0].mac.addr, 1817 ETHERADDRL); 1818 Adapter->unicst_addr[0].mac.set = 1; 1819 1820 for (slot = 1; slot < Adapter->unicst_total; slot++) 1821 Adapter->unicst_addr[slot].mac.set = 0; 1822 } else { 1823 /* Recover the default mac address */ 1824 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac_addr, 1825 ETHERADDRL); 1826 1827 /* Store the default mac address */ 1828 e1000_rar_set(hw, hw->mac_addr, 0); 1829 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1830 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1831 1832 /* Re-configure the RAR registers */ 1833 for (slot = 1; slot < Adapter->unicst_total; slot++) 1834 e1000_rar_set(hw, 1835 Adapter->unicst_addr[slot].mac.addr, slot); 1836 } 1837 } 1838 1839 static int 1840 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 1841 { 1842 struct e1000g *Adapter; 1843 1844 Adapter = (struct e1000g *)arg; 1845 1846 /* Store the default MAC address */ 1847 bcopy(mac_addr, Adapter->Shared.mac_addr, ETHERADDRL); 1848 1849 /* Set MAC address in address slot 0, which is the default address */ 1850 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 1851 } 1852 1853 static int 1854 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 1855 mac_addr_slot_t slot) 1856 { 1857 struct e1000_hw *hw; 1858 1859 hw = &Adapter->Shared; 1860 1861 /* 1862 * Error if the address specified is a multicast or broadcast 1863 * address. 1864 */ 1865 if (((mac_addr[0] & 01) == 1) || 1866 (bcmp(mac_addr, ðerbroadcastaddr, ETHERADDRL) == 0)) 1867 return (EINVAL); 1868 1869 rw_enter(&Adapter->chip_lock, RW_WRITER); 1870 1871 /* 1872 * The first revision of Wiseman silicon (rev 2.0) has an errata 1873 * that requires the receiver to be in reset when any of the 1874 * receive address registers (RAR regs) are accessed. The first 1875 * rev of Wiseman silicon also requires MWI to be disabled when 1876 * a global reset or a receive reset is issued. So before we 1877 * initialize the RARs, we check the rev of the Wiseman controller 1878 * and work around any necessary HW errata. 1879 */ 1880 if (hw->mac_type == e1000_82542_rev2_0) { 1881 e1000_pci_clear_mwi(hw); 1882 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1883 DelayInMilliseconds(5); 1884 } 1885 1886 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 1887 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 1888 1889 if (slot == 0) { 1890 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1891 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1892 } 1893 1894 /* 1895 * If we are using Wiseman rev 2.0 silicon, we will have previously 1896 * put the receive in reset, and disabled MWI, to work around some 1897 * HW errata. Now we should take the receiver out of reset, and 1898 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 1899 */ 1900 if (hw->mac_type == e1000_82542_rev2_0) { 1901 E1000_WRITE_REG(hw, RCTL, 0); 1902 DelayInMilliseconds(1); 1903 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1904 e1000_pci_set_mwi(hw); 1905 SetupReceiveStructures(Adapter); 1906 } 1907 1908 rw_exit(&Adapter->chip_lock); 1909 1910 return (0); 1911 } 1912 1913 /* 1914 * e1000g_m_unicst_add() - will find an unused address slot, set the 1915 * address value to the one specified, reserve that slot and enable 1916 * the NIC to start filtering on the new MAC address. 1917 * Returns 0 on success. 1918 */ 1919 static int 1920 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 1921 { 1922 struct e1000g *Adapter = (struct e1000g *)arg; 1923 mac_addr_slot_t slot; 1924 int err; 1925 1926 if (mac_unicst_verify(Adapter->mh, 1927 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 1928 return (EINVAL); 1929 1930 rw_enter(&Adapter->chip_lock, RW_WRITER); 1931 if (Adapter->unicst_avail == 0) { 1932 /* no slots available */ 1933 rw_exit(&Adapter->chip_lock); 1934 return (ENOSPC); 1935 } 1936 1937 /* 1938 * Primary/default address is in slot 0. The next addresses 1939 * are the multiple MAC addresses. So multiple MAC address 0 1940 * is in slot 1, 1 in slot 2, and so on. So the first multiple 1941 * MAC address resides in slot 1. 1942 */ 1943 for (slot = 1; slot < Adapter->unicst_total; slot++) { 1944 if (Adapter->unicst_addr[slot].mac.set == 0) { 1945 Adapter->unicst_addr[slot].mac.set = 1; 1946 break; 1947 } 1948 } 1949 1950 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 1951 1952 Adapter->unicst_avail--; 1953 rw_exit(&Adapter->chip_lock); 1954 1955 maddr->mma_slot = slot; 1956 1957 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 1958 rw_enter(&Adapter->chip_lock, RW_WRITER); 1959 Adapter->unicst_addr[slot].mac.set = 0; 1960 Adapter->unicst_avail++; 1961 rw_exit(&Adapter->chip_lock); 1962 } 1963 1964 return (err); 1965 } 1966 1967 /* 1968 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 1969 * call to e1000g_m_unicst_add(). The slot number that was returned in 1970 * e1000g_m_unicst_add() is passed in the call to remove the address. 1971 * Returns 0 on success. 1972 */ 1973 static int 1974 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 1975 { 1976 struct e1000g *Adapter = (struct e1000g *)arg; 1977 int err; 1978 1979 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 1980 return (EINVAL); 1981 1982 rw_enter(&Adapter->chip_lock, RW_WRITER); 1983 if (Adapter->unicst_addr[slot].mac.set == 1) { 1984 Adapter->unicst_addr[slot].mac.set = 0; 1985 Adapter->unicst_avail++; 1986 rw_exit(&Adapter->chip_lock); 1987 1988 /* Copy the default address to the passed slot */ 1989 if (err = e1000g_unicst_set(Adapter, 1990 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 1991 rw_enter(&Adapter->chip_lock, RW_WRITER); 1992 Adapter->unicst_addr[slot].mac.set = 1; 1993 Adapter->unicst_avail--; 1994 rw_exit(&Adapter->chip_lock); 1995 } 1996 return (err); 1997 } 1998 rw_exit(&Adapter->chip_lock); 1999 2000 return (EINVAL); 2001 } 2002 2003 /* 2004 * e1000g_m_unicst_modify() - modifies the value of an address that 2005 * has been added by e1000g_m_unicst_add(). The new address, address 2006 * length and the slot number that was returned in the call to add 2007 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2008 * set to 0. Returns 0 on success. 2009 */ 2010 static int 2011 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2012 { 2013 struct e1000g *Adapter = (struct e1000g *)arg; 2014 mac_addr_slot_t slot; 2015 2016 if (mac_unicst_verify(Adapter->mh, 2017 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2018 return (EINVAL); 2019 2020 slot = maddr->mma_slot; 2021 2022 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2023 return (EINVAL); 2024 2025 rw_enter(&Adapter->chip_lock, RW_WRITER); 2026 if (Adapter->unicst_addr[slot].mac.set == 1) { 2027 rw_exit(&Adapter->chip_lock); 2028 2029 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2030 } 2031 rw_exit(&Adapter->chip_lock); 2032 2033 return (EINVAL); 2034 } 2035 2036 /* 2037 * e1000g_m_unicst_get() - will get the MAC address and all other 2038 * information related to the address slot passed in mac_multi_addr_t. 2039 * mma_flags should be set to 0 in the call. 2040 * On return, mma_flags can take the following values: 2041 * 1) MMAC_SLOT_UNUSED 2042 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2043 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2044 * 4) MMAC_SLOT_USED 2045 */ 2046 static int 2047 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2048 { 2049 struct e1000g *Adapter = (struct e1000g *)arg; 2050 mac_addr_slot_t slot; 2051 2052 slot = maddr->mma_slot; 2053 2054 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2055 return (EINVAL); 2056 2057 rw_enter(&Adapter->chip_lock, RW_WRITER); 2058 if (Adapter->unicst_addr[slot].mac.set == 1) { 2059 bcopy(Adapter->unicst_addr[slot].mac.addr, 2060 maddr->mma_addr, ETHERADDRL); 2061 maddr->mma_flags = MMAC_SLOT_USED; 2062 } else { 2063 maddr->mma_flags = MMAC_SLOT_UNUSED; 2064 } 2065 rw_exit(&Adapter->chip_lock); 2066 2067 return (0); 2068 } 2069 2070 static int 2071 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2072 { 2073 unsigned i; 2074 int res = 0; 2075 2076 rw_enter(&Adapter->chip_lock, RW_WRITER); 2077 2078 if ((multiaddr[0] & 01) == 0) { 2079 res = EINVAL; 2080 goto done; 2081 } 2082 2083 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2084 res = ENOENT; 2085 goto done; 2086 } 2087 2088 bcopy(multiaddr, 2089 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2090 Adapter->mcast_count++; 2091 2092 /* 2093 * Update the MC table in the hardware 2094 */ 2095 e1000g_DisableInterrupt(Adapter); 2096 2097 SetupMulticastTable(Adapter); 2098 2099 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2100 SetupReceiveStructures(Adapter); 2101 2102 e1000g_EnableInterrupt(Adapter); 2103 2104 done: 2105 rw_exit(&Adapter->chip_lock); 2106 return (res); 2107 } 2108 2109 static int 2110 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2111 { 2112 unsigned i; 2113 2114 rw_enter(&Adapter->chip_lock, RW_WRITER); 2115 2116 for (i = 0; i < Adapter->mcast_count; i++) { 2117 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2118 ETHERADDRL) == 0) { 2119 for (i++; i < Adapter->mcast_count; i++) { 2120 Adapter->mcast_table[i - 1] = 2121 Adapter->mcast_table[i]; 2122 } 2123 Adapter->mcast_count--; 2124 break; 2125 } 2126 } 2127 2128 /* 2129 * Update the MC table in the hardware 2130 */ 2131 e1000g_DisableInterrupt(Adapter); 2132 2133 SetupMulticastTable(Adapter); 2134 2135 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2136 SetupReceiveStructures(Adapter); 2137 2138 e1000g_EnableInterrupt(Adapter); 2139 2140 done: 2141 rw_exit(&Adapter->chip_lock); 2142 return (0); 2143 } 2144 2145 int 2146 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2147 { 2148 struct e1000g *Adapter = (struct e1000g *)arg; 2149 2150 return ((add) ? multicst_add(Adapter, addr) 2151 : multicst_remove(Adapter, addr)); 2152 } 2153 2154 int 2155 e1000g_m_promisc(void *arg, boolean_t on) 2156 { 2157 struct e1000g *Adapter = (struct e1000g *)arg; 2158 ULONG RctlRegValue; 2159 2160 rw_enter(&Adapter->chip_lock, RW_WRITER); 2161 2162 RctlRegValue = E1000_READ_REG(&Adapter->Shared, RCTL); 2163 2164 if (on) 2165 RctlRegValue |= 2166 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2167 else 2168 RctlRegValue &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2169 2170 E1000_WRITE_REG(&Adapter->Shared, RCTL, RctlRegValue); 2171 2172 Adapter->e1000g_promisc = on; 2173 2174 rw_exit(&Adapter->chip_lock); 2175 2176 return (0); 2177 } 2178 2179 static boolean_t 2180 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2181 { 2182 struct e1000g *Adapter = (struct e1000g *)arg; 2183 2184 switch (cap) { 2185 case MAC_CAPAB_HCKSUM: { 2186 uint32_t *txflags = cap_data; 2187 2188 /* 2189 * In Jumbo mode, enabling hardware checksum will cause 2190 * port hang. 2191 */ 2192 if (Adapter->Shared.max_frame_size > ETHERMAX) 2193 return (B_FALSE); 2194 2195 /* 2196 * Checksum on/off selection via global parameters. 2197 * 2198 * If the chip is flagged as not capable of (correctly) 2199 * handling FULL checksumming, we don't enable it on either 2200 * Rx or Tx side. Otherwise, we take this chip's settings 2201 * from the patchable global defaults. 2202 * 2203 * We advertise our capabilities only if TX offload is 2204 * enabled. On receive, the stack will accept checksummed 2205 * packets anyway, even if we haven't said we can deliver 2206 * them. 2207 */ 2208 switch (Adapter->Shared.mac_type) { 2209 /* 2210 * Switch on hardware checksum offload of 2211 * chip 82540, 82545, 82546 2212 */ 2213 case e1000_82540: 2214 case e1000_82544: /* pci8086,1008 */ 2215 case e1000_82545: 2216 case e1000_82545_rev_3: /* pci8086,1026 */ 2217 case e1000_82571: 2218 case e1000_82572: 2219 case e1000_82573: 2220 case e1000_80003es2lan: 2221 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2222 break; 2223 2224 case e1000_82546: /* 82546EB. devID: 1010, 101d */ 2225 case e1000_82546_rev_3: /* 82546GB. devID: 1079, 107a */ 2226 #if !defined(__sparc) && !defined(__amd64) 2227 /* Workaround for Galaxy on 32bit */ 2228 return (B_FALSE); 2229 #else 2230 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2231 break; 2232 #endif 2233 2234 /* 2235 * We don't have the following PRO 1000 chip types at 2236 * hand and haven't tested their hardware checksum 2237 * offload capability. We had better switch them off. 2238 * e1000_undefined = 0, 2239 * e1000_82542_rev2_0, 2240 * e1000_82542_rev2_1, 2241 * e1000_82543, 2242 * e1000_82541, 2243 * e1000_82541_rev_2, 2244 * e1000_82547, 2245 * e1000_82547_rev_2, 2246 * e1000_num_macs 2247 */ 2248 default: 2249 return (B_FALSE); 2250 } 2251 2252 break; 2253 } 2254 case MAC_CAPAB_POLL: 2255 /* 2256 * There's nothing for us to fill in, simply returning 2257 * B_TRUE stating that we support polling is sufficient. 2258 */ 2259 break; 2260 2261 case MAC_CAPAB_MULTIADDRESS: { 2262 multiaddress_capab_t *mmacp = cap_data; 2263 2264 /* 2265 * The number of MAC addresses made available by 2266 * this capability is one less than the total as 2267 * the primary address in slot 0 is counted in 2268 * the total. 2269 */ 2270 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2271 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2272 /* No multiple factory addresses, set mma_flag to 0 */ 2273 mmacp->maddr_flag = 0; 2274 mmacp->maddr_handle = Adapter; 2275 mmacp->maddr_add = e1000g_m_unicst_add; 2276 mmacp->maddr_remove = e1000g_m_unicst_remove; 2277 mmacp->maddr_modify = e1000g_m_unicst_modify; 2278 mmacp->maddr_get = e1000g_m_unicst_get; 2279 mmacp->maddr_reserve = NULL; 2280 break; 2281 } 2282 default: 2283 return (B_FALSE); 2284 } 2285 return (B_TRUE); 2286 } 2287 2288 /* 2289 * ********************************************************************** 2290 * Name: e1000g_getparam * 2291 * * 2292 * Description: This routine gets user-configured values out of the * 2293 * configuration file e1000g.conf. * 2294 * For each configurable value, there is a minimum, a maximum, and a * 2295 * default. * 2296 * If user does not configure a value, use the default. * 2297 * If user configures below the minimum, use the minumum. * 2298 * If user configures above the maximum, use the maxumum. * 2299 * * 2300 * Arguments: * 2301 * Adapter - A pointer to our adapter structure * 2302 * * 2303 * Returns: None * 2304 * ********************************************************************** 2305 */ 2306 static void 2307 e1000g_getparam(struct e1000g *Adapter) 2308 { 2309 /* 2310 * get each configurable property from e1000g.conf 2311 */ 2312 2313 /* 2314 * NumTxDescriptors 2315 */ 2316 Adapter->NumTxDescriptors = 2317 e1000g_getprop(Adapter, "NumTxDescriptors", 2318 MINNUMTXDESCRIPTOR, MAXNUMTXDESCRIPTOR, 2319 DEFAULTNUMTXDESCRIPTOR); 2320 2321 /* 2322 * NumRxDescriptors 2323 */ 2324 Adapter->NumRxDescriptors = 2325 e1000g_getprop(Adapter, "NumRxDescriptors", 2326 MINNUMRXDESCRIPTOR, MAXNUMRXDESCRIPTOR, 2327 DEFAULTNUMRXDESCRIPTOR); 2328 2329 /* 2330 * NumRxFreeList 2331 */ 2332 Adapter->NumRxFreeList = 2333 e1000g_getprop(Adapter, "NumRxFreeList", 2334 MINNUMRXFREELIST, MAXNUMRXFREELIST, 2335 DEFAULTNUMRXFREELIST); 2336 2337 /* 2338 * NumTxPacketList 2339 */ 2340 Adapter->NumTxSwPacket = 2341 e1000g_getprop(Adapter, "NumTxPacketList", 2342 MINNUMTXSWPACKET, MAXNUMTXSWPACKET, 2343 DEFAULTNUMTXSWPACKET); 2344 2345 /* 2346 * FlowControl 2347 */ 2348 Adapter->Shared.fc_send_xon = B_TRUE; 2349 Adapter->Shared.fc = 2350 e1000g_getprop(Adapter, "FlowControl", 2351 E1000_FC_NONE, 4, DEFAULTFLOWCONTROLVAL); 2352 /* 4 is the setting that says "let the eeprom decide" */ 2353 if (Adapter->Shared.fc == 4) 2354 Adapter->Shared.fc = E1000_FC_DEFAULT; 2355 2356 /* 2357 * MaxNumReceivePackets 2358 */ 2359 Adapter->MaxNumReceivePackets = 2360 e1000g_getprop(Adapter, "MaxNumReceivePackets", 2361 MINNUMRCVPKTONINTR, MAXNUMRCVPKTONINTR, 2362 DEFAULTMAXNUMRCVPKTONINTR); 2363 2364 /* 2365 * TxInterruptDelay 2366 */ 2367 Adapter->TxInterruptDelay = 2368 e1000g_getprop(Adapter, "TxInterruptDelay", 2369 MINTXINTERRUPTDELAYVAL, MAXTXINTERRUPTDELAYVAL, 2370 DEFAULTTXINTERRUPTDELAYVAL); 2371 2372 /* 2373 * PHY master slave setting 2374 */ 2375 Adapter->Shared.master_slave = 2376 e1000g_getprop(Adapter, "SetMasterSlave", 2377 e1000_ms_hw_default, e1000_ms_auto, 2378 e1000_ms_hw_default); 2379 2380 /* 2381 * Parameter which controls TBI mode workaround, which is only 2382 * needed on certain switches such as Cisco 6500/Foundry 2383 */ 2384 Adapter->Shared.tbi_compatibility_en = 2385 e1000g_getprop(Adapter, "TbiCompatibilityEnable", 2386 0, 1, DEFAULTTBICOMPATIBILITYENABLE); 2387 2388 /* 2389 * MSI Enable 2390 */ 2391 Adapter->msi_enabled = 2392 e1000g_getprop(Adapter, "MSIEnable", 2393 0, 1, DEFAULTMSIENABLE); 2394 2395 /* 2396 * Interrupt Throttling Rate 2397 */ 2398 Adapter->intr_throttling_rate = 2399 e1000g_getprop(Adapter, "intr_throttling_rate", 2400 MININTERRUPTTHROTTLINGVAL, MAXINTERRUPTTHROTTLINGVAL, 2401 DEFAULTINTERRUPTTHROTTLINGVAL); 2402 2403 /* 2404 * Adaptive Interrupt Blanking Enable/Disable 2405 * It is enabled by default 2406 */ 2407 Adapter->intr_adaptive = 2408 (e1000g_getprop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2409 B_TRUE : B_FALSE; 2410 } 2411 2412 /* 2413 * ********************************************************************** 2414 * Name: e1000g_getprop * 2415 * * 2416 * Description: get a user-configure property value out of the * 2417 * configuration file e1000g.conf. * 2418 * Caller provides name of the property, a default value, a * 2419 * minimum value, and a maximum value. * 2420 * * 2421 * Returns: configured value of the property, with default, minimum and * 2422 * maximum properly applied. * 2423 * ********************************************************************** 2424 */ 2425 static int 2426 e1000g_getprop(struct e1000g *Adapter, /* point to per-adapter structure */ 2427 char *propname, /* name of the property */ 2428 int minval, /* minimum acceptable value */ 2429 int maxval, /* maximim acceptable value */ 2430 int defval) /* default value */ 2431 { 2432 int propval; /* value returned for requested property */ 2433 int *props; /* point to array of properties returned */ 2434 uint_t nprops; /* number of property value returned */ 2435 2436 /* 2437 * get the array of properties from the config file 2438 */ 2439 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2440 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2441 /* got some properties, test if we got enough */ 2442 if (Adapter->AdapterInstance < nprops) { 2443 propval = props[Adapter->AdapterInstance]; 2444 } else { 2445 /* not enough properties configured */ 2446 propval = defval; 2447 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2448 "Not Enough %s values found in e1000g.conf" 2449 " - set to %d\n", 2450 propname, propval); 2451 } 2452 2453 /* free memory allocated for properties */ 2454 ddi_prop_free(props); 2455 2456 } else { 2457 propval = defval; 2458 } 2459 2460 /* 2461 * enforce limits 2462 */ 2463 if (propval > maxval) { 2464 propval = maxval; 2465 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2466 "Too High %s value in e1000g.conf - set to %d\n", 2467 propname, propval); 2468 } 2469 2470 if (propval < minval) { 2471 propval = minval; 2472 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2473 "Too Low %s value in e1000g.conf - set to %d\n", 2474 propname, propval); 2475 } 2476 2477 return (propval); 2478 } 2479 2480 static boolean_t 2481 e1000g_link_check(struct e1000g *Adapter) 2482 { 2483 uint16_t speed, duplex, phydata; 2484 boolean_t link_changed = B_FALSE; 2485 struct e1000_hw *hw; 2486 uint32_t reg_tarc; 2487 2488 hw = &Adapter->Shared; 2489 2490 if (e1000g_link_up(Adapter)) { 2491 /* 2492 * The Link is up, check whether it was marked as down earlier 2493 */ 2494 if (Adapter->link_state != LINK_STATE_UP) { 2495 e1000_get_speed_and_duplex(hw, &speed, &duplex); 2496 Adapter->link_speed = speed; 2497 Adapter->link_duplex = duplex; 2498 Adapter->link_state = LINK_STATE_UP; 2499 link_changed = B_TRUE; 2500 2501 Adapter->tx_link_down_timeout = 0; 2502 2503 if ((hw->mac_type == e1000_82571) || 2504 (hw->mac_type == e1000_82572)) { 2505 reg_tarc = E1000_READ_REG(hw, TARC0); 2506 if (speed == SPEED_1000) 2507 reg_tarc |= (1 << 21); 2508 else 2509 reg_tarc &= ~(1 << 21); 2510 E1000_WRITE_REG(hw, TARC0, reg_tarc); 2511 } 2512 2513 e1000g_log(Adapter, CE_NOTE, 2514 "Adapter %dMbps %s %s link is up.", speed, 2515 ((duplex == FULL_DUPLEX) ? 2516 "full duplex" : "half duplex"), 2517 ((hw->media_type == e1000_media_type_copper) ? 2518 "copper" : "fiber")); 2519 } 2520 Adapter->smartspeed = 0; 2521 } else { 2522 if (Adapter->link_state != LINK_STATE_DOWN) { 2523 Adapter->link_speed = 0; 2524 Adapter->link_duplex = 0; 2525 Adapter->link_state = LINK_STATE_DOWN; 2526 link_changed = B_TRUE; 2527 2528 e1000g_log(Adapter, CE_NOTE, 2529 "Adapter %s link is down.", 2530 ((hw->media_type == e1000_media_type_copper) ? 2531 "copper" : "fiber")); 2532 2533 /* 2534 * SmartSpeed workaround for Tabor/TanaX, When the 2535 * driver loses link disable auto master/slave 2536 * resolution. 2537 */ 2538 if (hw->phy_type == e1000_phy_igp) { 2539 e1000_read_phy_reg(hw, 2540 PHY_1000T_CTRL, &phydata); 2541 phydata |= CR_1000T_MS_ENABLE; 2542 e1000_write_phy_reg(hw, 2543 PHY_1000T_CTRL, phydata); 2544 } 2545 /* 2546 * Workaround for esb2. Data stuck in fifo on a link 2547 * down event. Reset the adapter to recover it. 2548 */ 2549 if (hw->mac_type == e1000_80003es2lan) { 2550 (void) e1000g_reset(Adapter); 2551 } 2552 } else { 2553 e1000g_smartspeed(Adapter); 2554 } 2555 2556 if (Adapter->started) { 2557 if (Adapter->tx_link_down_timeout < 2558 MAX_TX_LINK_DOWN_TIMEOUT) { 2559 Adapter->tx_link_down_timeout++; 2560 } else if (Adapter->tx_link_down_timeout == 2561 MAX_TX_LINK_DOWN_TIMEOUT) { 2562 rw_enter(&Adapter->chip_lock, RW_WRITER); 2563 e1000g_tx_drop(Adapter); 2564 rw_exit(&Adapter->chip_lock); 2565 Adapter->tx_link_down_timeout++; 2566 } 2567 } 2568 } 2569 2570 return (link_changed); 2571 } 2572 2573 static void 2574 e1000g_LocalTimer(void *ws) 2575 { 2576 struct e1000g *Adapter = (struct e1000g *)ws; 2577 struct e1000_hw *hw; 2578 e1000g_ether_addr_t ether_addr; 2579 boolean_t link_changed; 2580 2581 hw = &Adapter->Shared; 2582 2583 (void) e1000g_tx_freemsg((caddr_t)Adapter, NULL); 2584 2585 if (e1000g_stall_check(Adapter)) { 2586 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 2587 "Tx stall detected. Activate automatic recovery.\n"); 2588 Adapter->StallWatchdog = 0; 2589 Adapter->tx_recycle_fail = 0; 2590 Adapter->reset_count++; 2591 (void) e1000g_reset(Adapter); 2592 } 2593 2594 link_changed = B_FALSE; 2595 mutex_enter(&Adapter->e1000g_linklock); 2596 if (Adapter->link_complete) 2597 link_changed = e1000g_link_check(Adapter); 2598 mutex_exit(&Adapter->e1000g_linklock); 2599 2600 if (link_changed) 2601 mac_link_update(Adapter->mh, Adapter->link_state); 2602 2603 /* 2604 * With 82571 controllers, any locally administered address will 2605 * be overwritten when there is a reset on the other port. 2606 * Detect this circumstance and correct it. 2607 */ 2608 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) { 2609 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, RA, 0); 2610 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, RA, 1); 2611 2612 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2613 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2614 2615 if ((ether_addr.mac.addr[5] != hw->mac_addr[0]) || 2616 (ether_addr.mac.addr[4] != hw->mac_addr[1]) || 2617 (ether_addr.mac.addr[3] != hw->mac_addr[2]) || 2618 (ether_addr.mac.addr[2] != hw->mac_addr[3]) || 2619 (ether_addr.mac.addr[1] != hw->mac_addr[4]) || 2620 (ether_addr.mac.addr[0] != hw->mac_addr[5])) { 2621 e1000_rar_set(hw, hw->mac_addr, 0); 2622 } 2623 } 2624 2625 /* 2626 * RP: ttl_workaround : DCR 49 2627 */ 2628 e1000_igp_ttl_workaround(hw); 2629 2630 /* 2631 * Check for Adaptive IFS settings If there are lots of collisions 2632 * change the value in steps... 2633 * These properties should only be set for 10/100 2634 */ 2635 if ((hw->media_type == e1000_media_type_copper) && 2636 ((Adapter->link_speed == SPEED_100) || 2637 (Adapter->link_speed == SPEED_10))) { 2638 e1000_update_adaptive(hw); 2639 } 2640 /* 2641 * Set Timer Interrupts 2642 */ 2643 E1000_WRITE_REG(hw, ICS, E1000_IMS_RXT0); 2644 2645 restart_timeout(Adapter); 2646 } 2647 2648 /* 2649 * The function e1000g_link_timer() is called when the timer for link setup 2650 * is expired, which indicates the completion of the link setup. The link 2651 * state will not be updated until the link setup is completed. And the 2652 * link state will not be sent to the upper layer through mac_link_update() 2653 * in this function. It will be updated in the local timer routine or the 2654 * interrupt service routine after the interface is started (plumbed). 2655 */ 2656 static void 2657 e1000g_link_timer(void *arg) 2658 { 2659 struct e1000g *Adapter = (struct e1000g *)arg; 2660 2661 mutex_enter(&Adapter->e1000g_linklock); 2662 Adapter->link_complete = B_TRUE; 2663 Adapter->link_tid = 0; 2664 mutex_exit(&Adapter->e1000g_linklock); 2665 } 2666 2667 /* 2668 * ********************************************************************** 2669 * Name: e1000g_force_speed_duplex * 2670 * * 2671 * Description: * 2672 * This function forces speed and duplex for 10/100 Mbps speeds * 2673 * and also for 1000 Mbps speeds, it advertises half or full duplex * 2674 * * 2675 * Parameter Passed: * 2676 * struct e1000g* (information of adpater) * 2677 * * 2678 * Return Value: * 2679 * * 2680 * Functions called: * 2681 * ********************************************************************** 2682 */ 2683 static void 2684 e1000g_force_speed_duplex(struct e1000g *Adapter) 2685 { 2686 int forced; 2687 2688 /* 2689 * get value out of config file 2690 */ 2691 forced = e1000g_getprop(Adapter, "ForceSpeedDuplex", 2692 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2693 2694 switch (forced) { 2695 case GDIAG_10_HALF: 2696 /* 2697 * Disable Auto Negotiation 2698 */ 2699 Adapter->Shared.autoneg = B_FALSE; 2700 Adapter->Shared.forced_speed_duplex = e1000_10_half; 2701 break; 2702 case GDIAG_10_FULL: 2703 /* 2704 * Disable Auto Negotiation 2705 */ 2706 Adapter->Shared.autoneg = B_FALSE; 2707 Adapter->Shared.forced_speed_duplex = e1000_10_full; 2708 break; 2709 case GDIAG_100_HALF: 2710 /* 2711 * Disable Auto Negotiation 2712 */ 2713 Adapter->Shared.autoneg = B_FALSE; 2714 Adapter->Shared.forced_speed_duplex = e1000_100_half; 2715 break; 2716 case GDIAG_100_FULL: 2717 /* 2718 * Disable Auto Negotiation 2719 */ 2720 Adapter->Shared.autoneg = B_FALSE; 2721 Adapter->Shared.forced_speed_duplex = e1000_100_full; 2722 break; 2723 case GDIAG_1000_FULL: 2724 /* 2725 * The gigabit spec requires autonegotiation. Therefore, 2726 * when the user wants to force the speed to 1000Mbps, we 2727 * enable AutoNeg, but only allow the harware to advertise 2728 * 1000Mbps. This is different from 10/100 operation, where 2729 * we are allowed to link without any negotiation. 2730 */ 2731 Adapter->Shared.autoneg = B_TRUE; 2732 Adapter->Shared.autoneg_advertised = ADVERTISE_1000_FULL; 2733 break; 2734 default: /* obey the setting of AutoNegAdvertised */ 2735 Adapter->Shared.autoneg = B_TRUE; 2736 Adapter->Shared.autoneg_advertised = 2737 (uint16_t)e1000g_getprop(Adapter, "AutoNegAdvertised", 2738 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 2739 AUTONEG_ADVERTISE_SPEED_DEFAULT); 2740 break; 2741 } /* switch */ 2742 } 2743 2744 /* 2745 * ********************************************************************** 2746 * Name: e1000g_get_max_frame_size * 2747 * * 2748 * Description: * 2749 * This function reads MaxFrameSize from e1000g.conf and sets it for * 2750 * adapter. * 2751 * * 2752 * Parameter Passed: * 2753 * struct e1000g* (information of adpater) * 2754 * * 2755 * Return Value: * 2756 * * 2757 * Functions called: * 2758 * ********************************************************************** 2759 */ 2760 static void 2761 e1000g_get_max_frame_size(struct e1000g *Adapter) 2762 { 2763 int max_frame; 2764 2765 /* 2766 * get value out of config file 2767 */ 2768 max_frame = e1000g_getprop(Adapter, "MaxFrameSize", 0, 3, 0); 2769 2770 switch (max_frame) { 2771 case 0: 2772 Adapter->Shared.max_frame_size = ETHERMAX; 2773 break; 2774 case 1: 2775 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_4K; 2776 break; 2777 case 2: 2778 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_8K; 2779 break; 2780 case 3: 2781 if (Adapter->Shared.mac_type < e1000_82571) 2782 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_16K; 2783 else 2784 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_10K; 2785 break; 2786 default: 2787 Adapter->Shared.max_frame_size = ETHERMAX; 2788 break; 2789 } /* switch */ 2790 2791 /* ich8 does not do jumbo frames */ 2792 if (Adapter->Shared.mac_type == e1000_ich8lan) { 2793 Adapter->Shared.max_frame_size = ETHERMAX; 2794 } 2795 } 2796 2797 static void 2798 arm_timer(struct e1000g *Adapter) 2799 { 2800 Adapter->WatchDogTimer_id = 2801 timeout(e1000g_LocalTimer, 2802 (void *)Adapter, 1 * drv_usectohz(1000000)); 2803 } 2804 2805 static void 2806 enable_timeout(struct e1000g *Adapter) 2807 { 2808 mutex_enter(&Adapter->e1000g_timeout_lock); 2809 2810 if (!Adapter->timeout_enabled) { 2811 Adapter->timeout_enabled = B_TRUE; 2812 Adapter->timeout_started = B_TRUE; 2813 2814 arm_timer(Adapter); 2815 } 2816 2817 mutex_exit(&Adapter->e1000g_timeout_lock); 2818 } 2819 2820 static void 2821 disable_timeout(struct e1000g *Adapter) 2822 { 2823 timeout_id_t tid; 2824 2825 mutex_enter(&Adapter->e1000g_timeout_lock); 2826 2827 Adapter->timeout_enabled = B_FALSE; 2828 Adapter->timeout_started = B_FALSE; 2829 2830 tid = Adapter->WatchDogTimer_id; 2831 Adapter->WatchDogTimer_id = 0; 2832 2833 mutex_exit(&Adapter->e1000g_timeout_lock); 2834 2835 if (tid != 0) 2836 (void) untimeout(tid); 2837 } 2838 2839 static void 2840 start_timeout(struct e1000g *Adapter) 2841 { 2842 mutex_enter(&Adapter->e1000g_timeout_lock); 2843 2844 if (Adapter->timeout_enabled) { 2845 if (!Adapter->timeout_started) { 2846 Adapter->timeout_started = B_TRUE; 2847 arm_timer(Adapter); 2848 } 2849 } 2850 2851 mutex_exit(&Adapter->e1000g_timeout_lock); 2852 } 2853 2854 static void 2855 restart_timeout(struct e1000g *Adapter) 2856 { 2857 mutex_enter(&Adapter->e1000g_timeout_lock); 2858 2859 if (Adapter->timeout_started) 2860 arm_timer(Adapter); 2861 2862 mutex_exit(&Adapter->e1000g_timeout_lock); 2863 } 2864 2865 static void 2866 stop_timeout(struct e1000g *Adapter) 2867 { 2868 timeout_id_t tid; 2869 2870 mutex_enter(&Adapter->e1000g_timeout_lock); 2871 2872 Adapter->timeout_started = B_FALSE; 2873 2874 tid = Adapter->WatchDogTimer_id; 2875 Adapter->WatchDogTimer_id = 0; 2876 2877 mutex_exit(&Adapter->e1000g_timeout_lock); 2878 2879 if (tid != 0) 2880 (void) untimeout(tid); 2881 } 2882 2883 void 2884 e1000g_DisableInterrupt(struct e1000g *Adapter) 2885 { 2886 E1000_WRITE_REG(&Adapter->Shared, IMC, 2887 0xffffffff & ~E1000_IMC_RXSEQ); 2888 } 2889 2890 void 2891 e1000g_EnableInterrupt(struct e1000g *Adapter) 2892 { 2893 E1000_WRITE_REG(&Adapter->Shared, IMS, 2894 IMS_ENABLE_MASK & ~E1000_IMS_TXDW & ~E1000_IMS_TXQE); 2895 } 2896 2897 void 2898 e1000g_DisableAllInterrupts(struct e1000g *Adapter) 2899 { 2900 E1000_WRITE_REG(&Adapter->Shared, IMC, 0xffffffff) 2901 } 2902 2903 void 2904 e1000g_EnableTxInterrupt(struct e1000g *Adapter) 2905 { 2906 E1000_WRITE_REG(&Adapter->Shared, IMS, E1000G_IMS_TX_INTR); 2907 } 2908 2909 void 2910 e1000g_DisableTxInterrupt(struct e1000g *Adapter) 2911 { 2912 E1000_WRITE_REG(&Adapter->Shared, IMC, E1000G_IMC_TX_INTR); 2913 } 2914 2915 void 2916 e1000_pci_set_mwi(struct e1000_hw *hw) 2917 { 2918 uint16_t val = hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE; 2919 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2920 } 2921 2922 void 2923 e1000_pci_clear_mwi(struct e1000_hw *hw) 2924 { 2925 uint16_t val = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; 2926 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2927 } 2928 2929 void 2930 e1000_write_pci_cfg(struct e1000_hw *adapter, 2931 uint32_t reg, uint16_t *value) 2932 { 2933 pci_config_put16(((struct e1000g_osdep *)(adapter->back))->handle, 2934 reg, *value); 2935 } 2936 2937 void 2938 e1000_read_pci_cfg(struct e1000_hw *adapter, 2939 uint32_t reg, uint16_t *value) 2940 { 2941 *value = 2942 pci_config_get16(((struct e1000g_osdep *)(adapter->back))-> 2943 handle, reg); 2944 } 2945 2946 #ifndef __sparc 2947 void 2948 e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 2949 { 2950 outl(port, value); 2951 } 2952 2953 uint32_t 2954 e1000_io_read(struct e1000_hw *hw, unsigned long port) 2955 { 2956 return (inl(port)); 2957 } 2958 #endif 2959 2960 static void 2961 e1000g_smartspeed(struct e1000g *adapter) 2962 { 2963 uint16_t phy_status; 2964 uint16_t phy_ctrl; 2965 2966 /* 2967 * If we're not T-or-T, or we're not autoneg'ing, or we're not 2968 * advertising 1000Full, we don't even use the workaround 2969 */ 2970 if ((adapter->Shared.phy_type != e1000_phy_igp) || 2971 !adapter->Shared.autoneg || 2972 !(adapter->Shared.autoneg_advertised & ADVERTISE_1000_FULL)) 2973 return; 2974 2975 /* 2976 * True if this is the first call of this function or after every 2977 * 30 seconds of not having link 2978 */ 2979 if (adapter->smartspeed == 0) { 2980 /* 2981 * If Master/Slave config fault is asserted twice, we 2982 * assume back-to-back 2983 */ 2984 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 2985 &phy_status); 2986 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 2987 return; 2988 2989 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 2990 &phy_status); 2991 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 2992 return; 2993 /* 2994 * We're assuming back-2-back because our status register 2995 * insists! there's a fault in the master/slave 2996 * relationship that was "negotiated" 2997 */ 2998 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 2999 &phy_ctrl); 3000 /* 3001 * Is the phy configured for manual configuration of 3002 * master/slave? 3003 */ 3004 if (phy_ctrl & CR_1000T_MS_ENABLE) { 3005 /* 3006 * Yes. Then disable manual configuration (enable 3007 * auto configuration) of master/slave 3008 */ 3009 phy_ctrl &= ~CR_1000T_MS_ENABLE; 3010 e1000_write_phy_reg(&adapter->Shared, 3011 PHY_1000T_CTRL, phy_ctrl); 3012 /* 3013 * Effectively starting the clock 3014 */ 3015 adapter->smartspeed++; 3016 /* 3017 * Restart autonegotiation 3018 */ 3019 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 3020 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 3021 &phy_ctrl)) { 3022 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 3023 MII_CR_RESTART_AUTO_NEG); 3024 e1000_write_phy_reg(&adapter->Shared, 3025 PHY_CTRL, phy_ctrl); 3026 } 3027 } 3028 return; 3029 /* 3030 * Has 6 seconds transpired still without link? Remember, 3031 * you should reset the smartspeed counter once you obtain 3032 * link 3033 */ 3034 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 3035 /* 3036 * Yes. Remember, we did at the start determine that 3037 * there's a master/slave configuration fault, so we're 3038 * still assuming there's someone on the other end, but we 3039 * just haven't yet been able to talk to it. We then 3040 * re-enable auto configuration of master/slave to see if 3041 * we're running 2/3 pair cables. 3042 */ 3043 /* 3044 * If still no link, perhaps using 2/3 pair cable 3045 */ 3046 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3047 &phy_ctrl); 3048 phy_ctrl |= CR_1000T_MS_ENABLE; 3049 e1000_write_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 3050 phy_ctrl); 3051 /* 3052 * Restart autoneg with phy enabled for manual 3053 * configuration of master/slave 3054 */ 3055 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 3056 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 3057 &phy_ctrl)) { 3058 phy_ctrl |= 3059 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 3060 e1000_write_phy_reg(&adapter->Shared, PHY_CTRL, 3061 phy_ctrl); 3062 } 3063 /* 3064 * Hopefully, there are no more faults and we've obtained 3065 * link as a result. 3066 */ 3067 } 3068 /* 3069 * Restart process after E1000_SMARTSPEED_MAX iterations (30 3070 * seconds) 3071 */ 3072 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 3073 adapter->smartspeed = 0; 3074 } 3075 3076 static boolean_t 3077 is_valid_mac_addr(uint8_t *mac_addr) 3078 { 3079 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3080 const uint8_t addr_test2[6] = 3081 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3082 3083 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3084 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3085 return (B_FALSE); 3086 3087 return (B_TRUE); 3088 } 3089 3090 /* 3091 * ********************************************************************** 3092 * Name: * 3093 * e1000g_stall_check * 3094 * * 3095 * Description: * 3096 * This function checks if the adapter is stalled. (In transmit) * 3097 * * 3098 * It is called each time the timeout is invoked. * 3099 * If the transmit descriptor reclaim continuously fails, * 3100 * the watchdog value will increment by 1. If the watchdog * 3101 * value exceeds the threshold, the adapter is assumed to * 3102 * have stalled and need to be reset. * 3103 * * 3104 * Arguments: * 3105 * Adapter - A pointer to our context sensitive "Adapter" * 3106 * structure. * 3107 * * 3108 * Returns: * 3109 * B_TRUE - The dapter is assumed to have stalled. * 3110 * B_FALSE * 3111 * * 3112 * ********************************************************************** 3113 */ 3114 static boolean_t 3115 e1000g_stall_check(struct e1000g *Adapter) 3116 { 3117 if (Adapter->link_state != LINK_STATE_UP) 3118 return (B_FALSE); 3119 3120 if (Adapter->tx_recycle_fail > 0) 3121 Adapter->StallWatchdog++; 3122 else 3123 Adapter->StallWatchdog = 0; 3124 3125 if (Adapter->StallWatchdog < E1000G_STALL_WATCHDOG_COUNT) 3126 return (B_FALSE); 3127 3128 return (B_TRUE); 3129 } 3130 3131 3132 static enum ioc_reply 3133 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3134 { 3135 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3136 e1000g_peekpoke_t *ppd; 3137 uint64_t mem_va; 3138 uint64_t maxoff; 3139 boolean_t peek; 3140 3141 switch (iocp->ioc_cmd) { 3142 3143 case E1000G_IOC_REG_PEEK: 3144 peek = B_TRUE; 3145 break; 3146 3147 case E1000G_IOC_REG_POKE: 3148 peek = B_FALSE; 3149 break; 3150 3151 deault: 3152 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3153 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3154 iocp->ioc_cmd); 3155 return (IOC_INVAL); 3156 } 3157 3158 /* 3159 * Validate format of ioctl 3160 */ 3161 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3162 return (IOC_INVAL); 3163 if (mp->b_cont == NULL) 3164 return (IOC_INVAL); 3165 3166 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3167 3168 /* 3169 * Validate request parameters 3170 */ 3171 switch (ppd->pp_acc_space) { 3172 3173 default: 3174 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3175 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3176 ppd->pp_acc_space); 3177 return (IOC_INVAL); 3178 3179 case E1000G_PP_SPACE_REG: 3180 /* 3181 * Memory-mapped I/O space 3182 */ 3183 ASSERT(ppd->pp_acc_size == 4); 3184 if (ppd->pp_acc_size != 4) 3185 return (IOC_INVAL); 3186 3187 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3188 return (IOC_INVAL); 3189 3190 mem_va = 0; 3191 maxoff = 0x10000; 3192 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3193 break; 3194 3195 case E1000G_PP_SPACE_E1000G: 3196 /* 3197 * E1000g data structure! 3198 */ 3199 mem_va = (uintptr_t)e1000gp; 3200 maxoff = sizeof (struct e1000g); 3201 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3202 break; 3203 3204 } 3205 3206 if (ppd->pp_acc_offset >= maxoff) 3207 return (IOC_INVAL); 3208 3209 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3210 return (IOC_INVAL); 3211 3212 /* 3213 * All OK - go! 3214 */ 3215 ppd->pp_acc_offset += mem_va; 3216 (*ppfn)(e1000gp, ppd); 3217 return (peek ? IOC_REPLY : IOC_ACK); 3218 } 3219 3220 static void 3221 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3222 { 3223 ddi_acc_handle_t handle; 3224 uint32_t *regaddr; 3225 3226 handle = 3227 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle, 3228 regaddr = 3229 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3230 3231 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3232 } 3233 3234 static void 3235 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3236 { 3237 ddi_acc_handle_t handle; 3238 uint32_t *regaddr; 3239 uint32_t value; 3240 3241 handle = 3242 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle, 3243 regaddr = 3244 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3245 value = (uint32_t)ppd->pp_acc_data; 3246 3247 ddi_put32(handle, regaddr, value); 3248 } 3249 3250 static void 3251 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3252 { 3253 uint64_t value; 3254 void *vaddr; 3255 3256 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3257 3258 switch (ppd->pp_acc_size) { 3259 case 1: 3260 value = *(uint8_t *)vaddr; 3261 break; 3262 3263 case 2: 3264 value = *(uint16_t *)vaddr; 3265 break; 3266 3267 case 4: 3268 value = *(uint32_t *)vaddr; 3269 break; 3270 3271 case 8: 3272 value = *(uint64_t *)vaddr; 3273 break; 3274 } 3275 3276 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3277 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3278 (void *)e1000gp, (void *)ppd, value, vaddr); 3279 3280 ppd->pp_acc_data = value; 3281 } 3282 3283 static void 3284 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3285 { 3286 uint64_t value; 3287 void *vaddr; 3288 3289 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3290 value = ppd->pp_acc_data; 3291 3292 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3293 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3294 (void *)e1000gp, (void *)ppd, value, vaddr); 3295 3296 switch (ppd->pp_acc_size) { 3297 case 1: 3298 *(uint8_t *)vaddr = (uint8_t)value; 3299 break; 3300 3301 case 2: 3302 *(uint16_t *)vaddr = (uint16_t)value; 3303 break; 3304 3305 case 4: 3306 *(uint32_t *)vaddr = (uint32_t)value; 3307 break; 3308 3309 case 8: 3310 *(uint64_t *)vaddr = (uint64_t)value; 3311 break; 3312 } 3313 } 3314 3315 /* 3316 * Loopback Support 3317 */ 3318 static lb_property_t lb_normal = 3319 { normal, "normal", E1000G_LB_NONE }; 3320 static lb_property_t lb_external1000 = 3321 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3322 static lb_property_t lb_external100 = 3323 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3324 static lb_property_t lb_external10 = 3325 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3326 static lb_property_t lb_phy = 3327 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3328 3329 static enum ioc_reply 3330 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3331 { 3332 lb_info_sz_t *lbsp; 3333 lb_property_t *lbpp; 3334 struct e1000_hw *hw; 3335 uint32_t *lbmp; 3336 uint32_t size; 3337 uint32_t value; 3338 uint16_t phy_status; 3339 uint16_t phy_ext_status; 3340 3341 hw = &Adapter->Shared; 3342 3343 if (mp->b_cont == NULL) 3344 return (IOC_INVAL); 3345 3346 switch (iocp->ioc_cmd) { 3347 default: 3348 return (IOC_INVAL); 3349 3350 case LB_GET_INFO_SIZE: 3351 size = sizeof (lb_info_sz_t); 3352 if (iocp->ioc_count != size) 3353 return (IOC_INVAL); 3354 3355 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3356 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3357 3358 value = sizeof (lb_normal); 3359 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3360 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3361 (hw->media_type == e1000_media_type_fiber) || 3362 (hw->media_type == e1000_media_type_internal_serdes)) { 3363 value += sizeof (lb_phy); 3364 switch (hw->mac_type) { 3365 case e1000_82571: 3366 case e1000_82572: 3367 value += sizeof (lb_external1000); 3368 break; 3369 } 3370 } 3371 if ((phy_status & MII_SR_100X_FD_CAPS) || 3372 (phy_status & MII_SR_100T2_FD_CAPS)) 3373 value += sizeof (lb_external100); 3374 if (phy_status & MII_SR_10T_FD_CAPS) 3375 value += sizeof (lb_external10); 3376 3377 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3378 *lbsp = value; 3379 break; 3380 3381 case LB_GET_INFO: 3382 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3383 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3384 3385 value = sizeof (lb_normal); 3386 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3387 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3388 (hw->media_type == e1000_media_type_fiber) || 3389 (hw->media_type == e1000_media_type_internal_serdes)) { 3390 value += sizeof (lb_phy); 3391 switch (hw->mac_type) { 3392 case e1000_82571: 3393 case e1000_82572: 3394 value += sizeof (lb_external1000); 3395 break; 3396 } 3397 } 3398 if ((phy_status & MII_SR_100X_FD_CAPS) || 3399 (phy_status & MII_SR_100T2_FD_CAPS)) 3400 value += sizeof (lb_external100); 3401 if (phy_status & MII_SR_10T_FD_CAPS) 3402 value += sizeof (lb_external10); 3403 3404 size = value; 3405 if (iocp->ioc_count != size) 3406 return (IOC_INVAL); 3407 3408 value = 0; 3409 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3410 lbpp[value++] = lb_normal; 3411 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3412 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3413 (hw->media_type == e1000_media_type_fiber) || 3414 (hw->media_type == e1000_media_type_internal_serdes)) { 3415 lbpp[value++] = lb_phy; 3416 switch (hw->mac_type) { 3417 case e1000_82571: 3418 case e1000_82572: 3419 lbpp[value++] = lb_external1000; 3420 break; 3421 } 3422 } 3423 if ((phy_status & MII_SR_100X_FD_CAPS) || 3424 (phy_status & MII_SR_100T2_FD_CAPS)) 3425 lbpp[value++] = lb_external100; 3426 if (phy_status & MII_SR_10T_FD_CAPS) 3427 lbpp[value++] = lb_external10; 3428 break; 3429 3430 case LB_GET_MODE: 3431 size = sizeof (uint32_t); 3432 if (iocp->ioc_count != size) 3433 return (IOC_INVAL); 3434 3435 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3436 *lbmp = Adapter->loopback_mode; 3437 break; 3438 3439 case LB_SET_MODE: 3440 size = 0; 3441 if (iocp->ioc_count != sizeof (uint32_t)) 3442 return (IOC_INVAL); 3443 3444 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3445 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3446 return (IOC_INVAL); 3447 break; 3448 } 3449 3450 iocp->ioc_count = size; 3451 iocp->ioc_error = 0; 3452 3453 return (IOC_REPLY); 3454 } 3455 3456 static boolean_t 3457 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3458 { 3459 struct e1000_hw *hw; 3460 #ifndef __sparc 3461 uint32_t reg_rctl; 3462 #endif 3463 int i, times; 3464 3465 if (mode == Adapter->loopback_mode) 3466 return (B_TRUE); 3467 3468 hw = &Adapter->Shared; 3469 times = 0; 3470 3471 again: 3472 switch (mode) { 3473 default: 3474 return (B_FALSE); 3475 3476 case E1000G_LB_NONE: 3477 /* Get original speed and duplex settings */ 3478 e1000g_force_speed_duplex(Adapter); 3479 /* Reset the chip */ 3480 hw->wait_autoneg_complete = B_TRUE; 3481 (void) e1000g_reset(Adapter); 3482 hw->wait_autoneg_complete = B_FALSE; 3483 break; 3484 3485 case E1000G_LB_EXTERNAL_1000: 3486 e1000g_set_external_loopback_1000(Adapter); 3487 break; 3488 3489 case E1000G_LB_EXTERNAL_100: 3490 e1000g_set_external_loopback_100(Adapter); 3491 break; 3492 3493 case E1000G_LB_EXTERNAL_10: 3494 e1000g_set_external_loopback_10(Adapter); 3495 break; 3496 3497 case E1000G_LB_INTERNAL_PHY: 3498 e1000g_set_internal_loopback(Adapter); 3499 break; 3500 } 3501 3502 times++; 3503 3504 switch (mode) { 3505 case E1000G_LB_EXTERNAL_1000: 3506 case E1000G_LB_EXTERNAL_100: 3507 case E1000G_LB_EXTERNAL_10: 3508 case E1000G_LB_INTERNAL_PHY: 3509 #ifndef __sparc 3510 /* Enable the CRC stripping for loopback */ 3511 reg_rctl = E1000_READ_REG(hw, RCTL); 3512 reg_rctl |= E1000_RCTL_SECRC; 3513 E1000_WRITE_REG(hw, RCTL, reg_rctl); 3514 #endif 3515 /* Wait for link up */ 3516 for (i = (PHY_FORCE_TIME * 2); i > 0; i--) 3517 msec_delay(100); 3518 3519 if (!e1000g_link_up(Adapter)) { 3520 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3521 "Failed to get the link up"); 3522 if (times < 2) { 3523 /* Reset the link */ 3524 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3525 "Reset the link ..."); 3526 (void) e1000g_reset(Adapter); 3527 goto again; 3528 } 3529 } 3530 break; 3531 } 3532 3533 Adapter->loopback_mode = mode; 3534 3535 return (B_TRUE); 3536 } 3537 3538 /* 3539 * The following loopback settings are from Intel's technical 3540 * document - "How To Loopback". All the register settings and 3541 * time delay values are directly inherited from the document 3542 * without more explanations available. 3543 */ 3544 static void 3545 e1000g_set_internal_loopback(struct e1000g *Adapter) 3546 { 3547 struct e1000_hw *hw; 3548 uint32_t ctrl; 3549 uint32_t status; 3550 uint16_t phy_ctrl; 3551 3552 hw = &Adapter->Shared; 3553 3554 /* Disable Smart Power Down */ 3555 phy_spd_state(hw, B_FALSE); 3556 3557 e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl); 3558 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3559 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3560 3561 switch (hw->mac_type) { 3562 case e1000_82540: 3563 case e1000_82545: 3564 case e1000_82545_rev_3: 3565 case e1000_82546: 3566 case e1000_82546_rev_3: 3567 case e1000_82573: 3568 /* Auto-MDI/MDIX off */ 3569 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3570 /* Reset PHY to update Auto-MDI/MDIX */ 3571 e1000_write_phy_reg(hw, PHY_CTRL, 3572 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3573 /* Reset PHY to auto-neg off and force 1000 */ 3574 e1000_write_phy_reg(hw, PHY_CTRL, 3575 phy_ctrl | MII_CR_RESET); 3576 break; 3577 } 3578 3579 /* Set loopback */ 3580 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl | MII_CR_LOOPBACK); 3581 3582 msec_delay(250); 3583 3584 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3585 ctrl = E1000_READ_REG(hw, CTRL); 3586 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3587 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3588 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3589 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3590 E1000_CTRL_FD); /* Force Duplex to FULL */ 3591 3592 switch (hw->mac_type) { 3593 case e1000_82540: 3594 case e1000_82545: 3595 case e1000_82545_rev_3: 3596 case e1000_82546: 3597 case e1000_82546_rev_3: 3598 /* 3599 * For some serdes we'll need to commit the writes now 3600 * so that the status is updated on link 3601 */ 3602 if (hw->media_type == e1000_media_type_internal_serdes) { 3603 E1000_WRITE_REG(hw, CTRL, ctrl); 3604 msec_delay(100); 3605 ctrl = E1000_READ_REG(hw, CTRL); 3606 } 3607 3608 if (hw->media_type == e1000_media_type_copper) { 3609 /* Invert Loss of Signal */ 3610 ctrl |= E1000_CTRL_ILOS; 3611 } else { 3612 /* Set ILOS on fiber nic if half duplex is detected */ 3613 status = E1000_READ_REG(hw, STATUS); 3614 if ((status & E1000_STATUS_FD) == 0) 3615 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3616 } 3617 break; 3618 3619 case e1000_82571: 3620 case e1000_82572: 3621 if (hw->media_type != e1000_media_type_copper) { 3622 /* Set ILOS on fiber nic if half duplex is detected */ 3623 status = E1000_READ_REG(hw, STATUS); 3624 if ((status & E1000_STATUS_FD) == 0) 3625 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3626 } 3627 break; 3628 3629 case e1000_82573: 3630 ctrl |= E1000_CTRL_ILOS; 3631 break; 3632 } 3633 3634 E1000_WRITE_REG(hw, CTRL, ctrl); 3635 3636 /* 3637 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3638 * For background, see comments above e1000g_set_internal_loopback(). 3639 */ 3640 switch (hw->mac_type) { 3641 case e1000_82540: 3642 case e1000_82545: 3643 case e1000_82545_rev_3: 3644 case e1000_82546: 3645 case e1000_82546_rev_3: 3646 case e1000_82573: 3647 e1000_write_phy_reg(hw, 29, 0x001F); 3648 e1000_write_phy_reg(hw, 30, 0x8FFC); 3649 e1000_write_phy_reg(hw, 29, 0x001A); 3650 e1000_write_phy_reg(hw, 30, 0x8FF0); 3651 break; 3652 } 3653 } 3654 3655 static void 3656 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3657 { 3658 struct e1000_hw *hw; 3659 uint32_t rctl; 3660 uint32_t ctrl_ext; 3661 uint32_t ctrl; 3662 uint32_t status; 3663 uint32_t txcw; 3664 3665 hw = &Adapter->Shared; 3666 3667 /* Disable Smart Power Down */ 3668 phy_spd_state(hw, B_FALSE); 3669 3670 switch (hw->media_type) { 3671 case e1000_media_type_copper: 3672 /* Force link up (Must be done before the PHY writes) */ 3673 ctrl = E1000_READ_REG(hw, CTRL); 3674 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3675 E1000_WRITE_REG(hw, CTRL, ctrl); 3676 3677 rctl = E1000_READ_REG(hw, RCTL); 3678 rctl |= (E1000_RCTL_EN | 3679 E1000_RCTL_SBP | 3680 E1000_RCTL_UPE | 3681 E1000_RCTL_MPE | 3682 E1000_RCTL_LPE | 3683 E1000_RCTL_BAM); /* 0x803E */ 3684 E1000_WRITE_REG(hw, RCTL, rctl); 3685 3686 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3687 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3688 E1000_CTRL_EXT_SDP6_DATA | 3689 E1000_CTRL_EXT_SDP7_DATA | 3690 E1000_CTRL_EXT_SDP4_DIR | 3691 E1000_CTRL_EXT_SDP6_DIR | 3692 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3693 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3694 3695 /* 3696 * This sequence tunes the PHY's SDP and no customer 3697 * settable values. For background, see comments above 3698 * e1000g_set_internal_loopback(). 3699 */ 3700 e1000_write_phy_reg(hw, 0x0, 0x140); 3701 msec_delay(10); 3702 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3703 e1000_write_phy_reg(hw, 0x12, 0xC10); 3704 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3705 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3706 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3707 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3708 3709 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3710 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3711 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3712 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3713 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3714 3715 msec_delay(50); 3716 break; 3717 case e1000_media_type_fiber: 3718 case e1000_media_type_internal_serdes: 3719 status = E1000_READ_REG(hw, STATUS); 3720 if (((status & E1000_STATUS_LU) == 0) || 3721 (hw->media_type == e1000_media_type_internal_serdes)) { 3722 ctrl = E1000_READ_REG(hw, CTRL); 3723 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3724 E1000_WRITE_REG(hw, CTRL, ctrl); 3725 } 3726 3727 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3728 txcw = E1000_READ_REG(hw, TXCW); 3729 txcw &= ~((uint32_t)1 << 31); 3730 E1000_WRITE_REG(hw, TXCW, txcw); 3731 3732 /* 3733 * Write 0x410 to Serdes Control register 3734 * to enable Serdes analog loopback 3735 */ 3736 E1000_WRITE_REG(hw, SCTL, 0x0410); 3737 msec_delay(10); 3738 break; 3739 default: 3740 break; 3741 } 3742 } 3743 3744 static void 3745 e1000g_set_external_loopback_100(struct e1000g *Adapter) 3746 { 3747 struct e1000_hw *hw; 3748 uint32_t ctrl; 3749 uint16_t phy_ctrl; 3750 3751 hw = &Adapter->Shared; 3752 3753 /* Disable Smart Power Down */ 3754 phy_spd_state(hw, B_FALSE); 3755 3756 phy_ctrl = (MII_CR_FULL_DUPLEX | 3757 MII_CR_SPEED_100); 3758 3759 /* Force 100/FD, reset PHY */ 3760 e1000_write_phy_reg(hw, PHY_CTRL, 3761 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 3762 msec_delay(10); 3763 3764 /* Force 100/FD */ 3765 e1000_write_phy_reg(hw, PHY_CTRL, 3766 phy_ctrl); /* 0x2100 */ 3767 msec_delay(10); 3768 3769 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3770 ctrl = E1000_READ_REG(hw, CTRL); 3771 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3772 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3773 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3774 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3775 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 3776 E1000_CTRL_FD); /* Force Duplex to FULL */ 3777 3778 E1000_WRITE_REG(hw, CTRL, ctrl); 3779 } 3780 3781 static void 3782 e1000g_set_external_loopback_10(struct e1000g *Adapter) 3783 { 3784 struct e1000_hw *hw; 3785 uint32_t ctrl; 3786 uint16_t phy_ctrl; 3787 3788 hw = &Adapter->Shared; 3789 3790 /* Disable Smart Power Down */ 3791 phy_spd_state(hw, B_FALSE); 3792 3793 phy_ctrl = (MII_CR_FULL_DUPLEX | 3794 MII_CR_SPEED_10); 3795 3796 /* Force 10/FD, reset PHY */ 3797 e1000_write_phy_reg(hw, PHY_CTRL, 3798 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 3799 msec_delay(10); 3800 3801 /* Force 10/FD */ 3802 e1000_write_phy_reg(hw, PHY_CTRL, 3803 phy_ctrl); /* 0x0100 */ 3804 msec_delay(10); 3805 3806 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3807 ctrl = E1000_READ_REG(hw, CTRL); 3808 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3809 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3810 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3811 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3812 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 3813 E1000_CTRL_FD); /* Force Duplex to FULL */ 3814 3815 E1000_WRITE_REG(hw, CTRL, ctrl); 3816 } 3817 3818 #ifdef __sparc 3819 static boolean_t 3820 e1000g_find_mac_address(struct e1000g *Adapter) 3821 { 3822 uchar_t *bytes; 3823 struct ether_addr sysaddr; 3824 uint_t nelts; 3825 int err; 3826 boolean_t found = B_FALSE; 3827 3828 /* 3829 * The "vendor's factory-set address" may already have 3830 * been extracted from the chip, but if the property 3831 * "local-mac-address" is set we use that instead. 3832 * 3833 * We check whether it looks like an array of 6 3834 * bytes (which it should, if OBP set it). If we can't 3835 * make sense of it this way, we'll ignore it. 3836 */ 3837 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3838 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3839 if (err == DDI_PROP_SUCCESS) { 3840 if (nelts == ETHERADDRL) { 3841 while (nelts--) 3842 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3843 found = B_TRUE; 3844 } 3845 ddi_prop_free(bytes); 3846 } 3847 3848 /* 3849 * Look up the OBP property "local-mac-address?". If the user has set 3850 * 'local-mac-address? = false', use "the system address" instead. 3851 */ 3852 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 3853 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3854 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3855 if (localetheraddr(NULL, &sysaddr) != 0) { 3856 bcopy(&sysaddr, Adapter->Shared.mac_addr, 3857 ETHERADDRL); 3858 found = B_TRUE; 3859 } 3860 } 3861 ddi_prop_free(bytes); 3862 } 3863 3864 /* 3865 * Finally(!), if there's a valid "mac-address" property (created 3866 * if we netbooted from this interface), we must use this instead 3867 * of any of the above to ensure that the NFS/install server doesn't 3868 * get confused by the address changing as Solaris takes over! 3869 */ 3870 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3871 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3872 if (err == DDI_PROP_SUCCESS) { 3873 if (nelts == ETHERADDRL) { 3874 while (nelts--) 3875 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3876 found = B_TRUE; 3877 } 3878 ddi_prop_free(bytes); 3879 } 3880 3881 if (found) { 3882 bcopy(Adapter->Shared.mac_addr, Adapter->Shared.perm_mac_addr, 3883 ETHERADDRL); 3884 } 3885 3886 return (found); 3887 } 3888 #endif 3889 3890 static int 3891 e1000g_add_intrs(struct e1000g *Adapter) 3892 { 3893 dev_info_t *devinfo; 3894 int intr_types; 3895 int rc; 3896 3897 devinfo = Adapter->dip; 3898 3899 /* Get supported interrupt types */ 3900 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3901 3902 if (rc != DDI_SUCCESS) { 3903 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3904 "Get supported interrupt types failed: %d\n", rc); 3905 return (DDI_FAILURE); 3906 } 3907 3908 /* 3909 * Based on Intel Technical Advisory document (TA-160), there are some 3910 * cases where some older Intel PCI-X NICs may "advertise" to the OS 3911 * that it supports MSI, but in fact has problems. 3912 * So we should only enable MSI for PCI-E NICs and disable MSI for old 3913 * PCI/PCI-X NICs. 3914 */ 3915 if (Adapter->Shared.mac_type < e1000_82571) 3916 Adapter->msi_enabled = B_FALSE; 3917 3918 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 3919 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 3920 3921 if (rc != DDI_SUCCESS) { 3922 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3923 "Add MSI failed, trying Legacy interrupts\n"); 3924 } else { 3925 Adapter->intr_type = DDI_INTR_TYPE_MSI; 3926 } 3927 } 3928 3929 if ((Adapter->intr_type == 0) && 3930 (intr_types & DDI_INTR_TYPE_FIXED)) { 3931 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 3932 3933 if (rc != DDI_SUCCESS) { 3934 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3935 "Add Legacy interrupts failed\n"); 3936 return (DDI_FAILURE); 3937 } 3938 3939 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 3940 } 3941 3942 if (Adapter->intr_type == 0) { 3943 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3944 "No interrupts registered\n"); 3945 return (DDI_FAILURE); 3946 } 3947 3948 return (DDI_SUCCESS); 3949 } 3950 3951 /* 3952 * e1000g_intr_add() handles MSI/Legacy interrupts 3953 */ 3954 static int 3955 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 3956 { 3957 dev_info_t *devinfo; 3958 int count, avail, actual; 3959 int x, y, rc, inum = 0; 3960 int flag; 3961 ddi_intr_handler_t *intr_handler; 3962 3963 devinfo = Adapter->dip; 3964 3965 /* get number of interrupts */ 3966 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 3967 if ((rc != DDI_SUCCESS) || (count == 0)) { 3968 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3969 "Get interrupt number failed. Return: %d, count: %d\n", 3970 rc, count); 3971 return (DDI_FAILURE); 3972 } 3973 3974 /* get number of available interrupts */ 3975 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 3976 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3977 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3978 "Get interrupt available number failed. " 3979 "Return: %d, available: %d\n", rc, avail); 3980 return (DDI_FAILURE); 3981 } 3982 3983 if (avail < count) { 3984 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3985 "Interrupts count: %d, available: %d\n", 3986 count, avail); 3987 } 3988 3989 /* Allocate an array of interrupt handles */ 3990 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 3991 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 3992 3993 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 3994 flag = DDI_INTR_ALLOC_NORMAL; 3995 3996 /* call ddi_intr_alloc() */ 3997 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 3998 count, &actual, flag); 3999 4000 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4001 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4002 "Allocate interrupts failed: %d\n", rc); 4003 4004 kmem_free(Adapter->htable, Adapter->intr_size); 4005 return (DDI_FAILURE); 4006 } 4007 4008 if (actual < count) { 4009 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 4010 "Interrupts requested: %d, received: %d\n", 4011 count, actual); 4012 } 4013 4014 Adapter->intr_cnt = actual; 4015 4016 /* Get priority for first msi, assume remaining are all the same */ 4017 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 4018 4019 if (rc != DDI_SUCCESS) { 4020 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4021 "Get interrupt priority failed: %d\n", rc); 4022 4023 /* Free already allocated intr */ 4024 for (y = 0; y < actual; y++) 4025 (void) ddi_intr_free(Adapter->htable[y]); 4026 4027 kmem_free(Adapter->htable, Adapter->intr_size); 4028 return (DDI_FAILURE); 4029 } 4030 4031 /* 4032 * In Legacy Interrupt mode, for PCI-Express adapters, we should 4033 * use the interrupt service routine e1000g_intr_pciexpress() 4034 * to avoid interrupt stealing when sharing interrupt with other 4035 * devices. 4036 */ 4037 if (Adapter->Shared.mac_type < e1000_82571) 4038 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 4039 else 4040 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 4041 4042 /* Call ddi_intr_add_handler() */ 4043 for (x = 0; x < actual; x++) { 4044 rc = ddi_intr_add_handler(Adapter->htable[x], 4045 intr_handler, (caddr_t)Adapter, NULL); 4046 4047 if (rc != DDI_SUCCESS) { 4048 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4049 "Add interrupt handler failed: %d\n", rc); 4050 4051 /* Remove already added handler */ 4052 for (y = 0; y < x; y++) 4053 (void) ddi_intr_remove_handler( 4054 Adapter->htable[y]); 4055 4056 /* Free already allocated intr */ 4057 for (y = 0; y < actual; y++) 4058 (void) ddi_intr_free(Adapter->htable[y]); 4059 4060 kmem_free(Adapter->htable, Adapter->intr_size); 4061 return (DDI_FAILURE); 4062 } 4063 } 4064 4065 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 4066 4067 if (rc != DDI_SUCCESS) { 4068 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4069 "Get interrupt cap failed: %d\n", rc); 4070 4071 /* Free already allocated intr */ 4072 for (y = 0; y < actual; y++) { 4073 (void) ddi_intr_remove_handler(Adapter->htable[y]); 4074 (void) ddi_intr_free(Adapter->htable[y]); 4075 } 4076 4077 kmem_free(Adapter->htable, Adapter->intr_size); 4078 return (DDI_FAILURE); 4079 } 4080 4081 return (DDI_SUCCESS); 4082 } 4083 4084 static int 4085 e1000g_rem_intrs(struct e1000g *Adapter) 4086 { 4087 int x; 4088 int rc; 4089 4090 for (x = 0; x < Adapter->intr_cnt; x++) { 4091 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4092 if (rc != DDI_SUCCESS) { 4093 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4094 "Remove intr handler failed: %d\n", rc); 4095 return (DDI_FAILURE); 4096 } 4097 4098 rc = ddi_intr_free(Adapter->htable[x]); 4099 if (rc != DDI_SUCCESS) { 4100 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4101 "Free intr failed: %d\n", rc); 4102 return (DDI_FAILURE); 4103 } 4104 } 4105 4106 kmem_free(Adapter->htable, Adapter->intr_size); 4107 4108 return (DDI_SUCCESS); 4109 } 4110 4111 static int 4112 e1000g_enable_intrs(struct e1000g *Adapter) 4113 { 4114 int x; 4115 int rc; 4116 4117 /* Enable interrupts */ 4118 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4119 /* Call ddi_intr_block_enable() for MSI */ 4120 rc = ddi_intr_block_enable(Adapter->htable, 4121 Adapter->intr_cnt); 4122 if (rc != DDI_SUCCESS) { 4123 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4124 "Enable block intr failed: %d\n", rc); 4125 return (DDI_FAILURE); 4126 } 4127 } else { 4128 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4129 for (x = 0; x < Adapter->intr_cnt; x++) { 4130 rc = ddi_intr_enable(Adapter->htable[x]); 4131 if (rc != DDI_SUCCESS) { 4132 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4133 "Enable intr failed: %d\n", rc); 4134 return (DDI_FAILURE); 4135 } 4136 } 4137 } 4138 4139 return (DDI_SUCCESS); 4140 } 4141 4142 static int 4143 e1000g_disable_intrs(struct e1000g *Adapter) 4144 { 4145 int x; 4146 int rc; 4147 4148 /* Disable all interrupts */ 4149 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4150 rc = ddi_intr_block_disable(Adapter->htable, 4151 Adapter->intr_cnt); 4152 if (rc != DDI_SUCCESS) { 4153 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4154 "Disable block intr failed: %d\n", rc); 4155 return (DDI_FAILURE); 4156 } 4157 } else { 4158 for (x = 0; x < Adapter->intr_cnt; x++) { 4159 rc = ddi_intr_disable(Adapter->htable[x]); 4160 if (rc != DDI_SUCCESS) { 4161 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4162 "Disable intr failed: %d\n", rc); 4163 return (DDI_FAILURE); 4164 } 4165 } 4166 } 4167 4168 return (DDI_SUCCESS); 4169 } 4170 4171 /* 4172 * phy_spd_state - set smart-power-down (SPD) state 4173 * 4174 * This only acts on the 82541/47 family and the 82571/72 family. 4175 * For any others, return without doing anything. 4176 */ 4177 void 4178 phy_spd_state(struct e1000_hw *hw, boolean_t enable) 4179 { 4180 int32_t offset; /* offset to register */ 4181 uint16_t spd_bit; /* bit to be set */ 4182 uint16_t reg; /* register contents */ 4183 4184 switch (hw->mac_type) { 4185 case e1000_82541: 4186 case e1000_82547: 4187 case e1000_82541_rev_2: 4188 case e1000_82547_rev_2: 4189 offset = IGP01E1000_GMII_FIFO; 4190 spd_bit = IGP01E1000_GMII_SPD; 4191 break; 4192 case e1000_82571: 4193 case e1000_82572: 4194 offset = IGP02E1000_PHY_POWER_MGMT; 4195 spd_bit = IGP02E1000_PM_SPD; 4196 break; 4197 default: 4198 return; /* no action */ 4199 } 4200 4201 e1000_read_phy_reg(hw, offset, ®); 4202 4203 if (enable) 4204 reg |= spd_bit; /* enable: set the spd bit */ 4205 else 4206 reg &= ~spd_bit; /* disable: clear the spd bit */ 4207 4208 e1000_write_phy_reg(hw, offset, reg); 4209 } 4210 4211 /* 4212 * The real intent of this routine is to return the value from pci-e 4213 * config space at offset reg into the capability space. 4214 * ICH devices are "PCI Express"-ish. They have a configuration space, 4215 * but do not contain PCI Express Capability registers, so this returns 4216 * the equivalent of "not supported" 4217 */ 4218 int32_t 4219 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4220 { 4221 *value = pci_config_get16(((struct e1000g_osdep *)hw->back)->handle, 4222 PCI_EX_CONF_CAP + reg); 4223 4224 return (0); 4225 } 4226 4227 /* 4228 * Enables PCI-Express master access. 4229 * 4230 * hw: Struct containing variables accessed by shared code 4231 * 4232 * returns: - none. 4233 */ 4234 void 4235 e1000_enable_pciex_master(struct e1000_hw *hw) 4236 { 4237 uint32_t ctrl; 4238 4239 if (hw->bus_type != e1000_bus_type_pci_express) 4240 return; 4241 4242 ctrl = E1000_READ_REG(hw, CTRL); 4243 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 4244 E1000_WRITE_REG(hw, CTRL, ctrl); 4245 } 4246