1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.14"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 98 /* 99 * Local routines 100 */ 101 static boolean_t e1000g_reset_adapter(struct e1000g *); 102 static void e1000g_tx_clean(struct e1000g *); 103 static void e1000g_rx_clean(struct e1000g *); 104 static void e1000g_link_timer(void *); 105 static void e1000g_local_timer(void *); 106 static boolean_t e1000g_link_check(struct e1000g *); 107 static boolean_t e1000g_stall_check(struct e1000g *); 108 static void e1000g_smartspeed(struct e1000g *); 109 static void e1000g_get_conf(struct e1000g *); 110 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 111 static void enable_watchdog_timer(struct e1000g *); 112 static void disable_watchdog_timer(struct e1000g *); 113 static void start_watchdog_timer(struct e1000g *); 114 static void restart_watchdog_timer(struct e1000g *); 115 static void stop_watchdog_timer(struct e1000g *); 116 static void stop_link_timer(struct e1000g *); 117 static void stop_82547_timer(e1000g_tx_ring_t *); 118 static void e1000g_force_speed_duplex(struct e1000g *); 119 static void e1000g_get_max_frame_size(struct e1000g *); 120 static boolean_t is_valid_mac_addr(uint8_t *); 121 static void e1000g_unattach(dev_info_t *, struct e1000g *); 122 #ifdef E1000G_DEBUG 123 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 124 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 125 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 126 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 127 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 128 struct iocblk *, mblk_t *); 129 #endif 130 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 131 struct iocblk *, mblk_t *); 132 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 133 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 134 static void e1000g_set_internal_loopback(struct e1000g *); 135 static void e1000g_set_external_loopback_1000(struct e1000g *); 136 static void e1000g_set_external_loopback_100(struct e1000g *); 137 static void e1000g_set_external_loopback_10(struct e1000g *); 138 static int e1000g_add_intrs(struct e1000g *); 139 static int e1000g_intr_add(struct e1000g *, int); 140 static int e1000g_rem_intrs(struct e1000g *); 141 static int e1000g_enable_intrs(struct e1000g *); 142 static int e1000g_disable_intrs(struct e1000g *); 143 static boolean_t e1000g_link_up(struct e1000g *); 144 #ifdef __sparc 145 static boolean_t e1000g_find_mac_address(struct e1000g *); 146 #endif 147 static void e1000g_get_phy_state(struct e1000g *); 148 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 149 const void *impl_data); 150 static void e1000g_fm_init(struct e1000g *Adapter); 151 static void e1000g_fm_fini(struct e1000g *Adapter); 152 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 153 static void e1000g_param_sync(struct e1000g *); 154 static void e1000g_get_driver_control(struct e1000_hw *); 155 static void e1000g_release_driver_control(struct e1000_hw *); 156 static void e1000g_restore_promisc(struct e1000g *Adapter); 157 158 mac_priv_prop_t e1000g_priv_props[] = { 159 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 160 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 161 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 162 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 163 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 164 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 165 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 166 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 167 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 168 {"_intr_adaptive", MAC_PROP_PERM_RW}, 169 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 170 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 171 }; 172 #define E1000G_MAX_PRIV_PROPS \ 173 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 174 175 176 static struct cb_ops cb_ws_ops = { 177 nulldev, /* cb_open */ 178 nulldev, /* cb_close */ 179 nodev, /* cb_strategy */ 180 nodev, /* cb_print */ 181 nodev, /* cb_dump */ 182 nodev, /* cb_read */ 183 nodev, /* cb_write */ 184 nodev, /* cb_ioctl */ 185 nodev, /* cb_devmap */ 186 nodev, /* cb_mmap */ 187 nodev, /* cb_segmap */ 188 nochpoll, /* cb_chpoll */ 189 ddi_prop_op, /* cb_prop_op */ 190 NULL, /* cb_stream */ 191 D_MP | D_HOTPLUG, /* cb_flag */ 192 CB_REV, /* cb_rev */ 193 nodev, /* cb_aread */ 194 nodev /* cb_awrite */ 195 }; 196 197 static struct dev_ops ws_ops = { 198 DEVO_REV, /* devo_rev */ 199 0, /* devo_refcnt */ 200 NULL, /* devo_getinfo */ 201 nulldev, /* devo_identify */ 202 nulldev, /* devo_probe */ 203 e1000g_attach, /* devo_attach */ 204 e1000g_detach, /* devo_detach */ 205 nodev, /* devo_reset */ 206 &cb_ws_ops, /* devo_cb_ops */ 207 NULL, /* devo_bus_ops */ 208 ddi_power, /* devo_power */ 209 e1000g_quiesce /* devo_quiesce */ 210 }; 211 212 static struct modldrv modldrv = { 213 &mod_driverops, /* Type of module. This one is a driver */ 214 ident, /* Discription string */ 215 &ws_ops, /* driver ops */ 216 }; 217 218 static struct modlinkage modlinkage = { 219 MODREV_1, &modldrv, NULL 220 }; 221 222 /* Access attributes for register mapping */ 223 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 224 DDI_DEVICE_ATTR_V0, 225 DDI_STRUCTURE_LE_ACC, 226 DDI_STRICTORDER_ACC, 227 DDI_FLAGERR_ACC 228 }; 229 230 #define E1000G_M_CALLBACK_FLAGS \ 231 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 232 233 static mac_callbacks_t e1000g_m_callbacks = { 234 E1000G_M_CALLBACK_FLAGS, 235 e1000g_m_stat, 236 e1000g_m_start, 237 e1000g_m_stop, 238 e1000g_m_promisc, 239 e1000g_m_multicst, 240 NULL, 241 e1000g_m_tx, 242 e1000g_m_ioctl, 243 e1000g_m_getcapab, 244 NULL, 245 NULL, 246 e1000g_m_setprop, 247 e1000g_m_getprop 248 }; 249 250 /* 251 * Global variables 252 */ 253 uint32_t e1000g_mblks_pending = 0; 254 /* 255 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 256 * Here we maintain a private dev_info list if e1000g_force_detach is 257 * enabled. If we force the driver to detach while there are still some 258 * rx buffers retained in the upper layer, we have to keep a copy of the 259 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 260 * structure will be freed after the driver is detached. However when we 261 * finally free those rx buffers released by the upper layer, we need to 262 * refer to the dev_info to free the dma buffers. So we save a copy of 263 * the dev_info for this purpose. On x86 platform, we assume this copy 264 * of dev_info is always valid, but on SPARC platform, it could be invalid 265 * after the system board level DR operation. For this reason, the global 266 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 267 */ 268 #ifdef __sparc 269 boolean_t e1000g_force_detach = B_FALSE; 270 #else 271 boolean_t e1000g_force_detach = B_TRUE; 272 #endif 273 private_devi_list_t *e1000g_private_devi_list = NULL; 274 275 /* 276 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 277 * the private dev_info list, and to serialize the processing of rx buffer 278 * freeing and rx buffer recycling. 279 */ 280 kmutex_t e1000g_rx_detach_lock; 281 /* 282 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 283 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 284 * If there are many e1000g instances, the system may run out of DVMA 285 * resources during the initialization of the instances, then the flag will 286 * be changed to "USE_DMA". Because different e1000g instances are initialized 287 * in parallel, we need to use this lock to protect the flag. 288 */ 289 krwlock_t e1000g_dma_type_lock; 290 291 /* 292 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 293 * Based on the information from Intel, the 82546 chipset has some hardware 294 * problem. When one port is being reset and the other port is trying to 295 * access the eeprom, it could cause system hang or panic. To workaround this 296 * hardware problem, we use a global mutex to prevent such operations from 297 * happening simultaneously on different instances. This workaround is applied 298 * to all the devices supported by this driver. 299 */ 300 kmutex_t e1000g_nvm_lock; 301 302 /* 303 * Loadable module configuration entry points for the driver 304 */ 305 306 /* 307 * _init - module initialization 308 */ 309 int 310 _init(void) 311 { 312 int status; 313 314 mac_init_ops(&ws_ops, WSNAME); 315 status = mod_install(&modlinkage); 316 if (status != DDI_SUCCESS) 317 mac_fini_ops(&ws_ops); 318 else { 319 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 320 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 321 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 322 } 323 324 return (status); 325 } 326 327 /* 328 * _fini - module finalization 329 */ 330 int 331 _fini(void) 332 { 333 int status; 334 335 if (e1000g_mblks_pending != 0) 336 return (EBUSY); 337 338 status = mod_remove(&modlinkage); 339 if (status == DDI_SUCCESS) { 340 mac_fini_ops(&ws_ops); 341 342 if (e1000g_force_detach) { 343 private_devi_list_t *devi_node; 344 345 mutex_enter(&e1000g_rx_detach_lock); 346 while (e1000g_private_devi_list != NULL) { 347 devi_node = e1000g_private_devi_list; 348 e1000g_private_devi_list = 349 e1000g_private_devi_list->next; 350 351 kmem_free(devi_node->priv_dip, 352 sizeof (struct dev_info)); 353 kmem_free(devi_node, 354 sizeof (private_devi_list_t)); 355 } 356 mutex_exit(&e1000g_rx_detach_lock); 357 } 358 359 mutex_destroy(&e1000g_rx_detach_lock); 360 rw_destroy(&e1000g_dma_type_lock); 361 mutex_destroy(&e1000g_nvm_lock); 362 } 363 364 return (status); 365 } 366 367 /* 368 * _info - module information 369 */ 370 int 371 _info(struct modinfo *modinfop) 372 { 373 return (mod_info(&modlinkage, modinfop)); 374 } 375 376 /* 377 * e1000g_attach - driver attach 378 * 379 * This function is the device-specific initialization entry 380 * point. This entry point is required and must be written. 381 * The DDI_ATTACH command must be provided in the attach entry 382 * point. When attach() is called with cmd set to DDI_ATTACH, 383 * all normal kernel services (such as kmem_alloc(9F)) are 384 * available for use by the driver. 385 * 386 * The attach() function will be called once for each instance 387 * of the device on the system with cmd set to DDI_ATTACH. 388 * Until attach() succeeds, the only driver entry points which 389 * may be called are open(9E) and getinfo(9E). 390 */ 391 static int 392 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 393 { 394 struct e1000g *Adapter; 395 struct e1000_hw *hw; 396 struct e1000g_osdep *osdep; 397 int instance; 398 399 switch (cmd) { 400 default: 401 e1000g_log(NULL, CE_WARN, 402 "Unsupported command send to e1000g_attach... "); 403 return (DDI_FAILURE); 404 405 case DDI_RESUME: 406 return (e1000g_resume(devinfo)); 407 408 case DDI_ATTACH: 409 break; 410 } 411 412 /* 413 * get device instance number 414 */ 415 instance = ddi_get_instance(devinfo); 416 417 /* 418 * Allocate soft data structure 419 */ 420 Adapter = 421 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 422 423 Adapter->dip = devinfo; 424 Adapter->instance = instance; 425 Adapter->tx_ring->adapter = Adapter; 426 Adapter->rx_ring->adapter = Adapter; 427 428 hw = &Adapter->shared; 429 osdep = &Adapter->osdep; 430 hw->back = osdep; 431 osdep->adapter = Adapter; 432 433 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 434 435 /* 436 * Initialize for fma support 437 */ 438 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 439 0, 0x0f, 440 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 441 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 442 e1000g_fm_init(Adapter); 443 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 444 445 /* 446 * PCI Configure 447 */ 448 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 449 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 450 goto attach_fail; 451 } 452 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 453 454 /* 455 * Setup hardware 456 */ 457 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 458 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 459 goto attach_fail; 460 } 461 462 /* 463 * Map in the device registers. 464 */ 465 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 466 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 467 goto attach_fail; 468 } 469 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 470 471 /* 472 * Initialize driver parameters 473 */ 474 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 475 goto attach_fail; 476 } 477 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 478 479 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 480 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 481 goto attach_fail; 482 } 483 484 /* 485 * Initialize interrupts 486 */ 487 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 488 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 489 goto attach_fail; 490 } 491 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 492 493 /* 494 * Initialize mutex's for this device. 495 * Do this before enabling the interrupt handler and 496 * register the softint to avoid the condition where 497 * interrupt handler can try using uninitialized mutex 498 */ 499 e1000g_init_locks(Adapter); 500 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 501 502 /* 503 * Initialize Driver Counters 504 */ 505 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 506 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 507 goto attach_fail; 508 } 509 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 510 511 /* 512 * Initialize chip hardware and software structures 513 */ 514 rw_enter(&Adapter->chip_lock, RW_WRITER); 515 if (e1000g_init(Adapter) != DDI_SUCCESS) { 516 rw_exit(&Adapter->chip_lock); 517 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 518 goto attach_fail; 519 } 520 rw_exit(&Adapter->chip_lock); 521 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 522 523 /* 524 * Register the driver to the MAC 525 */ 526 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 527 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 528 goto attach_fail; 529 } 530 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 531 532 /* 533 * Now that mutex locks are initialized, and the chip is also 534 * initialized, enable interrupts. 535 */ 536 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 537 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 538 goto attach_fail; 539 } 540 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 541 542 /* 543 * If e1000g_force_detach is enabled, in global private dip list, 544 * we will create a new entry, which maintains the priv_dip for DR 545 * supports after driver detached. 546 */ 547 if (e1000g_force_detach) { 548 private_devi_list_t *devi_node; 549 550 Adapter->priv_dip = 551 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 552 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 553 sizeof (struct dev_info)); 554 555 devi_node = 556 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 557 558 mutex_enter(&e1000g_rx_detach_lock); 559 devi_node->priv_dip = Adapter->priv_dip; 560 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 561 devi_node->pending_rx_count = 0; 562 563 Adapter->priv_devi_node = devi_node; 564 565 if (e1000g_private_devi_list == NULL) { 566 devi_node->prev = NULL; 567 devi_node->next = NULL; 568 e1000g_private_devi_list = devi_node; 569 } else { 570 devi_node->prev = NULL; 571 devi_node->next = e1000g_private_devi_list; 572 e1000g_private_devi_list->prev = devi_node; 573 e1000g_private_devi_list = devi_node; 574 } 575 mutex_exit(&e1000g_rx_detach_lock); 576 } 577 578 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 579 Adapter->e1000g_state = E1000G_INITIALIZED; 580 581 return (DDI_SUCCESS); 582 583 attach_fail: 584 e1000g_unattach(devinfo, Adapter); 585 return (DDI_FAILURE); 586 } 587 588 static int 589 e1000g_register_mac(struct e1000g *Adapter) 590 { 591 struct e1000_hw *hw = &Adapter->shared; 592 mac_register_t *mac; 593 int err; 594 595 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 596 return (DDI_FAILURE); 597 598 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 599 mac->m_driver = Adapter; 600 mac->m_dip = Adapter->dip; 601 mac->m_src_addr = hw->mac.addr; 602 mac->m_callbacks = &e1000g_m_callbacks; 603 mac->m_min_sdu = 0; 604 mac->m_max_sdu = Adapter->default_mtu; 605 mac->m_margin = VLAN_TAGSZ; 606 mac->m_priv_props = e1000g_priv_props; 607 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 608 mac->m_v12n = MAC_VIRT_LEVEL1; 609 610 err = mac_register(mac, &Adapter->mh); 611 mac_free(mac); 612 613 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 614 } 615 616 static int 617 e1000g_identify_hardware(struct e1000g *Adapter) 618 { 619 struct e1000_hw *hw = &Adapter->shared; 620 struct e1000g_osdep *osdep = &Adapter->osdep; 621 622 /* Get the device id */ 623 hw->vendor_id = 624 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 625 hw->device_id = 626 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 627 hw->revision_id = 628 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 629 hw->subsystem_device_id = 630 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 631 hw->subsystem_vendor_id = 632 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 633 634 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 635 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 636 "MAC type could not be set properly."); 637 return (DDI_FAILURE); 638 } 639 640 return (DDI_SUCCESS); 641 } 642 643 static int 644 e1000g_regs_map(struct e1000g *Adapter) 645 { 646 dev_info_t *devinfo = Adapter->dip; 647 struct e1000_hw *hw = &Adapter->shared; 648 struct e1000g_osdep *osdep = &Adapter->osdep; 649 off_t mem_size; 650 651 /* Get size of adapter register memory */ 652 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 653 DDI_SUCCESS) { 654 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 655 "ddi_dev_regsize for registers failed"); 656 return (DDI_FAILURE); 657 } 658 659 /* Map adapter register memory */ 660 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 661 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 662 &osdep->reg_handle)) != DDI_SUCCESS) { 663 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 664 "ddi_regs_map_setup for registers failed"); 665 goto regs_map_fail; 666 } 667 668 /* ICH needs to map flash memory */ 669 if (hw->mac.type == e1000_ich8lan || 670 hw->mac.type == e1000_ich9lan || 671 hw->mac.type == e1000_ich10lan) { 672 /* get flash size */ 673 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 674 &mem_size) != DDI_SUCCESS) { 675 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 676 "ddi_dev_regsize for ICH flash failed"); 677 goto regs_map_fail; 678 } 679 680 /* map flash in */ 681 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 682 (caddr_t *)&hw->flash_address, 0, 683 mem_size, &e1000g_regs_acc_attr, 684 &osdep->ich_flash_handle) != DDI_SUCCESS) { 685 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 686 "ddi_regs_map_setup for ICH flash failed"); 687 goto regs_map_fail; 688 } 689 } 690 691 return (DDI_SUCCESS); 692 693 regs_map_fail: 694 if (osdep->reg_handle != NULL) 695 ddi_regs_map_free(&osdep->reg_handle); 696 697 return (DDI_FAILURE); 698 } 699 700 static int 701 e1000g_set_driver_params(struct e1000g *Adapter) 702 { 703 struct e1000_hw *hw; 704 uint32_t mem_bar, io_bar, bar64; 705 706 hw = &Adapter->shared; 707 708 /* Set MAC type and initialize hardware functions */ 709 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 710 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 711 "Could not setup hardware functions"); 712 return (DDI_FAILURE); 713 } 714 715 /* Get bus information */ 716 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 717 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 718 "Could not get bus information"); 719 return (DDI_FAILURE); 720 } 721 722 /* get mem_base addr */ 723 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 724 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 725 726 /* get io_base addr */ 727 if (hw->mac.type >= e1000_82544) { 728 if (bar64) { 729 /* IO BAR is different for 64 bit BAR mode */ 730 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 731 PCI_CONF_BASE4); 732 } else { 733 /* normal 32-bit BAR mode */ 734 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 735 PCI_CONF_BASE2); 736 } 737 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 738 } else { 739 /* no I/O access for adapters prior to 82544 */ 740 hw->io_base = 0x0; 741 } 742 743 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 744 745 hw->mac.autoneg_failed = B_TRUE; 746 747 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 748 hw->phy.autoneg_wait_to_complete = B_FALSE; 749 750 /* Adaptive IFS related changes */ 751 hw->mac.adaptive_ifs = B_TRUE; 752 753 /* Enable phy init script for IGP phy of 82541/82547 */ 754 if ((hw->mac.type == e1000_82547) || 755 (hw->mac.type == e1000_82541) || 756 (hw->mac.type == e1000_82547_rev_2) || 757 (hw->mac.type == e1000_82541_rev_2)) 758 e1000_init_script_state_82541(hw, B_TRUE); 759 760 /* Enable the TTL workaround for 82541/82547 */ 761 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 762 763 #ifdef __sparc 764 Adapter->strip_crc = B_TRUE; 765 #else 766 Adapter->strip_crc = B_FALSE; 767 #endif 768 769 /* Get conf file properties */ 770 e1000g_get_conf(Adapter); 771 772 /* Get speed/duplex settings in conf file */ 773 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 774 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 775 e1000g_force_speed_duplex(Adapter); 776 777 /* Get Jumbo Frames settings in conf file */ 778 e1000g_get_max_frame_size(Adapter); 779 780 /* Set Rx/Tx buffer size */ 781 e1000g_set_bufsize(Adapter); 782 783 /* Master Latency Timer */ 784 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 785 786 /* copper options */ 787 if (hw->phy.media_type == e1000_media_type_copper) { 788 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 789 hw->phy.disable_polarity_correction = B_FALSE; 790 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 791 } 792 793 /* The initial link state should be "unknown" */ 794 Adapter->link_state = LINK_STATE_UNKNOWN; 795 796 /* Initialize rx parameters */ 797 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 798 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 799 800 /* Initialize tx parameters */ 801 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 802 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 803 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 804 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 805 806 /* Initialize rx parameters */ 807 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 808 809 return (DDI_SUCCESS); 810 } 811 812 static void 813 e1000g_set_bufsize(struct e1000g *Adapter) 814 { 815 struct e1000_mac_info *mac = &Adapter->shared.mac; 816 uint64_t rx_size; 817 uint64_t tx_size; 818 819 dev_info_t *devinfo = Adapter->dip; 820 #ifdef __sparc 821 ulong_t iommu_pagesize; 822 #endif 823 /* Get the system page size */ 824 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 825 826 #ifdef __sparc 827 iommu_pagesize = dvma_pagesize(devinfo); 828 if (iommu_pagesize != 0) { 829 if (Adapter->sys_page_sz == iommu_pagesize) { 830 if (iommu_pagesize > 0x4000) 831 Adapter->sys_page_sz = 0x4000; 832 } else { 833 if (Adapter->sys_page_sz > iommu_pagesize) 834 Adapter->sys_page_sz = iommu_pagesize; 835 } 836 } 837 if (Adapter->lso_enable) { 838 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 839 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 840 } else { 841 Adapter->dvma_page_num = Adapter->max_frame_size / 842 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 843 } 844 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 845 #endif 846 847 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 848 849 if (Adapter->mem_workaround_82546 && 850 ((mac->type == e1000_82545) || 851 (mac->type == e1000_82546) || 852 (mac->type == e1000_82546_rev_3))) { 853 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 854 } else { 855 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 856 if ((rx_size > FRAME_SIZE_UPTO_2K) && 857 (rx_size <= FRAME_SIZE_UPTO_4K)) 858 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 859 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 860 (rx_size <= FRAME_SIZE_UPTO_8K)) 861 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 862 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 863 (rx_size <= FRAME_SIZE_UPTO_16K)) 864 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 865 else 866 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 867 } 868 869 tx_size = Adapter->max_frame_size; 870 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 871 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 872 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 873 (tx_size <= FRAME_SIZE_UPTO_8K)) 874 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 875 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 876 (tx_size <= FRAME_SIZE_UPTO_16K)) 877 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 878 else 879 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 880 881 /* 882 * For Wiseman adapters we have an requirement of having receive 883 * buffers aligned at 256 byte boundary. Since Livengood does not 884 * require this and forcing it for all hardwares will have 885 * performance implications, I am making it applicable only for 886 * Wiseman and for Jumbo frames enabled mode as rest of the time, 887 * it is okay to have normal frames...but it does involve a 888 * potential risk where we may loose data if buffer is not 889 * aligned...so all wiseman boards to have 256 byte aligned 890 * buffers 891 */ 892 if (mac->type < e1000_82543) 893 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 894 else 895 Adapter->rx_buf_align = 1; 896 } 897 898 /* 899 * e1000g_detach - driver detach 900 * 901 * The detach() function is the complement of the attach routine. 902 * If cmd is set to DDI_DETACH, detach() is used to remove the 903 * state associated with a given instance of a device node 904 * prior to the removal of that instance from the system. 905 * 906 * The detach() function will be called once for each instance 907 * of the device for which there has been a successful attach() 908 * once there are no longer any opens on the device. 909 * 910 * Interrupts routine are disabled, All memory allocated by this 911 * driver are freed. 912 */ 913 static int 914 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 915 { 916 struct e1000g *Adapter; 917 boolean_t rx_drain; 918 919 switch (cmd) { 920 default: 921 return (DDI_FAILURE); 922 923 case DDI_SUSPEND: 924 return (e1000g_suspend(devinfo)); 925 926 case DDI_DETACH: 927 break; 928 } 929 930 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 931 if (Adapter == NULL) 932 return (DDI_FAILURE); 933 934 rx_drain = e1000g_rx_drain(Adapter); 935 if (!rx_drain && !e1000g_force_detach) 936 return (DDI_FAILURE); 937 938 if (mac_unregister(Adapter->mh) != 0) { 939 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 940 return (DDI_FAILURE); 941 } 942 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 943 944 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 945 946 if (!e1000g_force_detach && !rx_drain) 947 return (DDI_FAILURE); 948 949 e1000g_unattach(devinfo, Adapter); 950 951 return (DDI_SUCCESS); 952 } 953 954 /* 955 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 956 */ 957 void 958 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 959 { 960 ASSERT(e1000g_private_devi_list != NULL); 961 ASSERT(devi_node != NULL); 962 963 if (devi_node->prev != NULL) 964 devi_node->prev->next = devi_node->next; 965 if (devi_node->next != NULL) 966 devi_node->next->prev = devi_node->prev; 967 if (devi_node == e1000g_private_devi_list) 968 e1000g_private_devi_list = devi_node->next; 969 970 kmem_free(devi_node->priv_dip, 971 sizeof (struct dev_info)); 972 kmem_free(devi_node, 973 sizeof (private_devi_list_t)); 974 } 975 976 static void 977 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 978 { 979 private_devi_list_t *devi_node; 980 int result; 981 982 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 983 (void) e1000g_disable_intrs(Adapter); 984 } 985 986 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 987 (void) mac_unregister(Adapter->mh); 988 } 989 990 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 991 (void) e1000g_rem_intrs(Adapter); 992 } 993 994 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 995 (void) ddi_prop_remove_all(devinfo); 996 } 997 998 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 999 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1000 } 1001 1002 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1003 stop_link_timer(Adapter); 1004 1005 mutex_enter(&e1000g_nvm_lock); 1006 result = e1000_reset_hw(&Adapter->shared); 1007 mutex_exit(&e1000g_nvm_lock); 1008 1009 if (result != E1000_SUCCESS) { 1010 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1011 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1012 } 1013 } 1014 1015 e1000g_release_multicast(Adapter); 1016 1017 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1018 if (Adapter->osdep.reg_handle != NULL) 1019 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1020 if (Adapter->osdep.ich_flash_handle != NULL) 1021 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1022 } 1023 1024 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1025 if (Adapter->osdep.cfg_handle != NULL) 1026 pci_config_teardown(&Adapter->osdep.cfg_handle); 1027 } 1028 1029 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1030 e1000g_destroy_locks(Adapter); 1031 } 1032 1033 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1034 e1000g_fm_fini(Adapter); 1035 } 1036 1037 mutex_enter(&e1000g_rx_detach_lock); 1038 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1039 devi_node = Adapter->priv_devi_node; 1040 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1041 1042 if (devi_node->pending_rx_count == 0) { 1043 e1000g_free_priv_devi_node(devi_node); 1044 } 1045 } 1046 mutex_exit(&e1000g_rx_detach_lock); 1047 1048 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1049 1050 /* 1051 * Another hotplug spec requirement, 1052 * run ddi_set_driver_private(devinfo, null); 1053 */ 1054 ddi_set_driver_private(devinfo, NULL); 1055 } 1056 1057 static void 1058 e1000g_init_locks(struct e1000g *Adapter) 1059 { 1060 e1000g_tx_ring_t *tx_ring; 1061 e1000g_rx_ring_t *rx_ring; 1062 1063 rw_init(&Adapter->chip_lock, NULL, 1064 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1065 mutex_init(&Adapter->link_lock, NULL, 1066 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1067 mutex_init(&Adapter->watchdog_lock, NULL, 1068 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1069 1070 tx_ring = Adapter->tx_ring; 1071 1072 mutex_init(&tx_ring->tx_lock, NULL, 1073 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1074 mutex_init(&tx_ring->usedlist_lock, NULL, 1075 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1076 mutex_init(&tx_ring->freelist_lock, NULL, 1077 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1078 1079 rx_ring = Adapter->rx_ring; 1080 1081 mutex_init(&rx_ring->rx_lock, NULL, 1082 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1083 } 1084 1085 static void 1086 e1000g_destroy_locks(struct e1000g *Adapter) 1087 { 1088 e1000g_tx_ring_t *tx_ring; 1089 e1000g_rx_ring_t *rx_ring; 1090 1091 tx_ring = Adapter->tx_ring; 1092 mutex_destroy(&tx_ring->tx_lock); 1093 mutex_destroy(&tx_ring->usedlist_lock); 1094 mutex_destroy(&tx_ring->freelist_lock); 1095 1096 rx_ring = Adapter->rx_ring; 1097 mutex_destroy(&rx_ring->rx_lock); 1098 1099 mutex_destroy(&Adapter->link_lock); 1100 mutex_destroy(&Adapter->watchdog_lock); 1101 rw_destroy(&Adapter->chip_lock); 1102 } 1103 1104 static int 1105 e1000g_resume(dev_info_t *devinfo) 1106 { 1107 struct e1000g *Adapter; 1108 1109 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1110 if (Adapter == NULL) 1111 e1000g_log(Adapter, CE_PANIC, 1112 "Instance pointer is null\n"); 1113 1114 if (Adapter->dip != devinfo) 1115 e1000g_log(Adapter, CE_PANIC, 1116 "Devinfo is not the same as saved devinfo\n"); 1117 1118 rw_enter(&Adapter->chip_lock, RW_WRITER); 1119 1120 if (Adapter->e1000g_state & E1000G_STARTED) { 1121 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1122 rw_exit(&Adapter->chip_lock); 1123 /* 1124 * We note the failure, but return success, as the 1125 * system is still usable without this controller. 1126 */ 1127 e1000g_log(Adapter, CE_WARN, 1128 "e1000g_resume: failed to restart controller\n"); 1129 return (DDI_SUCCESS); 1130 } 1131 /* Enable and start the watchdog timer */ 1132 enable_watchdog_timer(Adapter); 1133 } 1134 1135 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1136 1137 rw_exit(&Adapter->chip_lock); 1138 1139 return (DDI_SUCCESS); 1140 } 1141 1142 static int 1143 e1000g_suspend(dev_info_t *devinfo) 1144 { 1145 struct e1000g *Adapter; 1146 1147 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1148 if (Adapter == NULL) 1149 return (DDI_FAILURE); 1150 1151 rw_enter(&Adapter->chip_lock, RW_WRITER); 1152 1153 Adapter->e1000g_state |= E1000G_SUSPENDED; 1154 1155 /* if the port isn't plumbed, we can simply return */ 1156 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1157 rw_exit(&Adapter->chip_lock); 1158 return (DDI_SUCCESS); 1159 } 1160 1161 e1000g_stop(Adapter, B_FALSE); 1162 1163 rw_exit(&Adapter->chip_lock); 1164 1165 /* Disable and stop all the timers */ 1166 disable_watchdog_timer(Adapter); 1167 stop_link_timer(Adapter); 1168 stop_82547_timer(Adapter->tx_ring); 1169 1170 return (DDI_SUCCESS); 1171 } 1172 1173 static int 1174 e1000g_init(struct e1000g *Adapter) 1175 { 1176 uint32_t pba; 1177 uint32_t high_water; 1178 struct e1000_hw *hw; 1179 clock_t link_timeout; 1180 int result; 1181 1182 hw = &Adapter->shared; 1183 1184 /* 1185 * reset to put the hardware in a known state 1186 * before we try to do anything with the eeprom 1187 */ 1188 mutex_enter(&e1000g_nvm_lock); 1189 result = e1000_reset_hw(hw); 1190 mutex_exit(&e1000g_nvm_lock); 1191 1192 if (result != E1000_SUCCESS) { 1193 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1194 goto init_fail; 1195 } 1196 1197 mutex_enter(&e1000g_nvm_lock); 1198 result = e1000_validate_nvm_checksum(hw); 1199 if (result < E1000_SUCCESS) { 1200 /* 1201 * Some PCI-E parts fail the first check due to 1202 * the link being in sleep state. Call it again, 1203 * if it fails a second time its a real issue. 1204 */ 1205 result = e1000_validate_nvm_checksum(hw); 1206 } 1207 mutex_exit(&e1000g_nvm_lock); 1208 1209 if (result < E1000_SUCCESS) { 1210 e1000g_log(Adapter, CE_WARN, 1211 "Invalid NVM checksum. Please contact " 1212 "the vendor to update the NVM."); 1213 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1214 goto init_fail; 1215 } 1216 1217 result = 0; 1218 #ifdef __sparc 1219 /* 1220 * First, we try to get the local ethernet address from OBP. If 1221 * failed, then we get it from the EEPROM of NIC card. 1222 */ 1223 result = e1000g_find_mac_address(Adapter); 1224 #endif 1225 /* Get the local ethernet address. */ 1226 if (!result) { 1227 mutex_enter(&e1000g_nvm_lock); 1228 result = e1000_read_mac_addr(hw); 1229 mutex_exit(&e1000g_nvm_lock); 1230 } 1231 1232 if (result < E1000_SUCCESS) { 1233 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1234 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1235 goto init_fail; 1236 } 1237 1238 /* check for valid mac address */ 1239 if (!is_valid_mac_addr(hw->mac.addr)) { 1240 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1241 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1242 goto init_fail; 1243 } 1244 1245 /* Set LAA state for 82571 chipset */ 1246 e1000_set_laa_state_82571(hw, B_TRUE); 1247 1248 /* Master Latency Timer implementation */ 1249 if (Adapter->master_latency_timer) { 1250 pci_config_put8(Adapter->osdep.cfg_handle, 1251 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1252 } 1253 1254 if (hw->mac.type < e1000_82547) { 1255 /* 1256 * Total FIFO is 64K 1257 */ 1258 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1259 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1260 else 1261 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1262 } else if ((hw->mac.type == e1000_82571) || 1263 (hw->mac.type == e1000_82572) || 1264 (hw->mac.type == e1000_80003es2lan)) { 1265 /* 1266 * Total FIFO is 48K 1267 */ 1268 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1269 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1270 else 1271 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1272 } else if (hw->mac.type == e1000_82573) { 1273 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1274 } else if (hw->mac.type == e1000_82574) { 1275 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1276 pba = E1000_READ_REG(hw, E1000_PBA); 1277 } else if (hw->mac.type == e1000_ich8lan) { 1278 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1279 } else if (hw->mac.type == e1000_ich9lan) { 1280 pba = E1000_PBA_10K; 1281 } else if (hw->mac.type == e1000_ich10lan) { 1282 pba = E1000_PBA_10K; 1283 } else { 1284 /* 1285 * Total FIFO is 40K 1286 */ 1287 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1288 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1289 else 1290 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1291 } 1292 E1000_WRITE_REG(hw, E1000_PBA, pba); 1293 1294 /* 1295 * These parameters set thresholds for the adapter's generation(Tx) 1296 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1297 * settings. Flow control is enabled or disabled in the configuration 1298 * file. 1299 * High-water mark is set down from the top of the rx fifo (not 1300 * sensitive to max_frame_size) and low-water is set just below 1301 * high-water mark. 1302 * The high water mark must be low enough to fit one full frame above 1303 * it in the rx FIFO. Should be the lower of: 1304 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1305 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1306 * Rx FIFO size minus one full frame. 1307 */ 1308 high_water = min(((pba << 10) * 9 / 10), 1309 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1310 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1311 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1312 ((pba << 10) - Adapter->max_frame_size))); 1313 1314 hw->fc.high_water = high_water & 0xFFF8; 1315 hw->fc.low_water = hw->fc.high_water - 8; 1316 1317 if (hw->mac.type == e1000_80003es2lan) 1318 hw->fc.pause_time = 0xFFFF; 1319 else 1320 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1321 hw->fc.send_xon = B_TRUE; 1322 1323 /* 1324 * Reset the adapter hardware the second time. 1325 */ 1326 mutex_enter(&e1000g_nvm_lock); 1327 result = e1000_reset_hw(hw); 1328 mutex_exit(&e1000g_nvm_lock); 1329 1330 if (result != E1000_SUCCESS) { 1331 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1332 goto init_fail; 1333 } 1334 1335 /* disable wakeup control by default */ 1336 if (hw->mac.type >= e1000_82544) 1337 E1000_WRITE_REG(hw, E1000_WUC, 0); 1338 1339 /* 1340 * MWI should be disabled on 82546. 1341 */ 1342 if (hw->mac.type == e1000_82546) 1343 e1000_pci_clear_mwi(hw); 1344 else 1345 e1000_pci_set_mwi(hw); 1346 1347 /* 1348 * Configure/Initialize hardware 1349 */ 1350 mutex_enter(&e1000g_nvm_lock); 1351 result = e1000_init_hw(hw); 1352 mutex_exit(&e1000g_nvm_lock); 1353 1354 if (result < E1000_SUCCESS) { 1355 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1356 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1357 goto init_fail; 1358 } 1359 1360 /* 1361 * Restore LED settings to the default from EEPROM 1362 * to meet the standard for Sun platforms. 1363 */ 1364 (void) e1000_cleanup_led(hw); 1365 1366 /* Disable Smart Power Down */ 1367 phy_spd_state(hw, B_FALSE); 1368 1369 /* Make sure driver has control */ 1370 e1000g_get_driver_control(hw); 1371 1372 /* 1373 * Initialize unicast addresses. 1374 */ 1375 e1000g_init_unicst(Adapter); 1376 1377 /* 1378 * Setup and initialize the mctable structures. After this routine 1379 * completes Multicast table will be set 1380 */ 1381 e1000g_setup_multicast(Adapter); 1382 msec_delay(5); 1383 1384 /* 1385 * Implement Adaptive IFS 1386 */ 1387 e1000_reset_adaptive(hw); 1388 1389 /* Setup Interrupt Throttling Register */ 1390 if (hw->mac.type >= e1000_82540) { 1391 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1392 } else 1393 Adapter->intr_adaptive = B_FALSE; 1394 1395 /* Start the timer for link setup */ 1396 if (hw->mac.autoneg) 1397 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1398 else 1399 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1400 1401 mutex_enter(&Adapter->link_lock); 1402 if (hw->phy.autoneg_wait_to_complete) { 1403 Adapter->link_complete = B_TRUE; 1404 } else { 1405 Adapter->link_complete = B_FALSE; 1406 Adapter->link_tid = timeout(e1000g_link_timer, 1407 (void *)Adapter, link_timeout); 1408 } 1409 mutex_exit(&Adapter->link_lock); 1410 1411 /* Enable PCI-Ex master */ 1412 if (hw->bus.type == e1000_bus_type_pci_express) { 1413 e1000_enable_pciex_master(hw); 1414 } 1415 1416 /* Save the state of the phy */ 1417 e1000g_get_phy_state(Adapter); 1418 1419 e1000g_param_sync(Adapter); 1420 1421 Adapter->init_count++; 1422 1423 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1424 goto init_fail; 1425 } 1426 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1427 goto init_fail; 1428 } 1429 1430 Adapter->poll_mode = e1000g_poll_mode; 1431 1432 return (DDI_SUCCESS); 1433 1434 init_fail: 1435 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1436 return (DDI_FAILURE); 1437 } 1438 1439 static int 1440 e1000g_alloc_rx_data(struct e1000g *Adapter) 1441 { 1442 e1000g_rx_ring_t *rx_ring; 1443 e1000g_rx_data_t *rx_data; 1444 1445 rx_ring = Adapter->rx_ring; 1446 1447 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1448 1449 if (rx_data == NULL) 1450 return (DDI_FAILURE); 1451 1452 rx_data->priv_devi_node = Adapter->priv_devi_node; 1453 rx_data->rx_ring = rx_ring; 1454 1455 mutex_init(&rx_data->freelist_lock, NULL, 1456 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1457 mutex_init(&rx_data->recycle_lock, NULL, 1458 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1459 1460 rx_ring->rx_data = rx_data; 1461 1462 return (DDI_SUCCESS); 1463 } 1464 1465 void 1466 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1467 { 1468 rx_sw_packet_t *packet, *next_packet; 1469 1470 if (rx_data == NULL) 1471 return; 1472 1473 packet = rx_data->packet_area; 1474 while (packet != NULL) { 1475 next_packet = packet->next; 1476 e1000g_free_rx_sw_packet(packet, B_TRUE); 1477 packet = next_packet; 1478 } 1479 rx_data->packet_area = NULL; 1480 } 1481 1482 void 1483 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1484 { 1485 if (rx_data == NULL) 1486 return; 1487 1488 mutex_destroy(&rx_data->freelist_lock); 1489 mutex_destroy(&rx_data->recycle_lock); 1490 1491 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1492 } 1493 1494 /* 1495 * Check if the link is up 1496 */ 1497 static boolean_t 1498 e1000g_link_up(struct e1000g *Adapter) 1499 { 1500 struct e1000_hw *hw; 1501 boolean_t link_up; 1502 1503 hw = &Adapter->shared; 1504 1505 (void) e1000_check_for_link(hw); 1506 1507 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1508 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1509 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1510 (hw->mac.serdes_has_link))) { 1511 link_up = B_TRUE; 1512 } else { 1513 link_up = B_FALSE; 1514 } 1515 1516 return (link_up); 1517 } 1518 1519 static void 1520 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1521 { 1522 struct iocblk *iocp; 1523 struct e1000g *e1000gp; 1524 enum ioc_reply status; 1525 1526 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1527 iocp->ioc_error = 0; 1528 e1000gp = (struct e1000g *)arg; 1529 1530 ASSERT(e1000gp); 1531 if (e1000gp == NULL) { 1532 miocnak(q, mp, 0, EINVAL); 1533 return; 1534 } 1535 1536 rw_enter(&e1000gp->chip_lock, RW_READER); 1537 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1538 rw_exit(&e1000gp->chip_lock); 1539 miocnak(q, mp, 0, EINVAL); 1540 return; 1541 } 1542 rw_exit(&e1000gp->chip_lock); 1543 1544 switch (iocp->ioc_cmd) { 1545 1546 case LB_GET_INFO_SIZE: 1547 case LB_GET_INFO: 1548 case LB_GET_MODE: 1549 case LB_SET_MODE: 1550 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1551 break; 1552 1553 1554 #ifdef E1000G_DEBUG 1555 case E1000G_IOC_REG_PEEK: 1556 case E1000G_IOC_REG_POKE: 1557 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1558 break; 1559 case E1000G_IOC_CHIP_RESET: 1560 e1000gp->reset_count++; 1561 if (e1000g_reset_adapter(e1000gp)) 1562 status = IOC_ACK; 1563 else 1564 status = IOC_INVAL; 1565 break; 1566 #endif 1567 default: 1568 status = IOC_INVAL; 1569 break; 1570 } 1571 1572 /* 1573 * Decide how to reply 1574 */ 1575 switch (status) { 1576 default: 1577 case IOC_INVAL: 1578 /* 1579 * Error, reply with a NAK and EINVAL or the specified error 1580 */ 1581 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1582 EINVAL : iocp->ioc_error); 1583 break; 1584 1585 case IOC_DONE: 1586 /* 1587 * OK, reply already sent 1588 */ 1589 break; 1590 1591 case IOC_ACK: 1592 /* 1593 * OK, reply with an ACK 1594 */ 1595 miocack(q, mp, 0, 0); 1596 break; 1597 1598 case IOC_REPLY: 1599 /* 1600 * OK, send prepared reply as ACK or NAK 1601 */ 1602 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1603 M_IOCACK : M_IOCNAK; 1604 qreply(q, mp); 1605 break; 1606 } 1607 } 1608 1609 /* 1610 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1611 * capable of supporting only one interrupt and we shouldn't disable 1612 * the physical interrupt. In this case we let the interrupt come and 1613 * we queue the packets in the rx ring itself in case we are in polling 1614 * mode (better latency but slightly lower performance and a very 1615 * high intrrupt count in mpstat which is harmless). 1616 * 1617 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1618 * which can be disabled in poll mode. This gives better overall 1619 * throughput (compared to the mode above), shows very low interrupt 1620 * count but has slightly higher latency since we pick the packets when 1621 * the poll thread does polling. 1622 * 1623 * Currently, this flag should be enabled only while doing performance 1624 * measurement or when it can be guaranteed that entire NIC going 1625 * in poll mode will not harm any traffic like cluster heartbeat etc. 1626 */ 1627 int e1000g_poll_mode = 0; 1628 1629 /* 1630 * Called from the upper layers when driver is in polling mode to 1631 * pick up any queued packets. Care should be taken to not block 1632 * this thread. 1633 */ 1634 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1635 { 1636 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1637 mblk_t *mp = NULL; 1638 mblk_t *tail; 1639 struct e1000g *adapter; 1640 1641 adapter = rx_ring->adapter; 1642 1643 rw_enter(&adapter->chip_lock, RW_READER); 1644 1645 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1646 rw_exit(&adapter->chip_lock); 1647 return (NULL); 1648 } 1649 1650 mutex_enter(&rx_ring->rx_lock); 1651 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1652 mutex_exit(&rx_ring->rx_lock); 1653 rw_exit(&adapter->chip_lock); 1654 return (mp); 1655 } 1656 1657 static int 1658 e1000g_m_start(void *arg) 1659 { 1660 struct e1000g *Adapter = (struct e1000g *)arg; 1661 1662 rw_enter(&Adapter->chip_lock, RW_WRITER); 1663 1664 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1665 rw_exit(&Adapter->chip_lock); 1666 return (ECANCELED); 1667 } 1668 1669 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1670 rw_exit(&Adapter->chip_lock); 1671 return (ENOTACTIVE); 1672 } 1673 1674 Adapter->e1000g_state |= E1000G_STARTED; 1675 1676 rw_exit(&Adapter->chip_lock); 1677 1678 /* Enable and start the watchdog timer */ 1679 enable_watchdog_timer(Adapter); 1680 1681 return (0); 1682 } 1683 1684 static int 1685 e1000g_start(struct e1000g *Adapter, boolean_t global) 1686 { 1687 e1000g_rx_data_t *rx_data; 1688 1689 if (global) { 1690 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1691 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1692 goto start_fail; 1693 } 1694 1695 /* Allocate dma resources for descriptors and buffers */ 1696 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1697 e1000g_log(Adapter, CE_WARN, 1698 "Alloc DMA resources failed"); 1699 goto start_fail; 1700 } 1701 Adapter->rx_buffer_setup = B_FALSE; 1702 } 1703 1704 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1705 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1706 e1000g_log(Adapter, CE_WARN, 1707 "Adapter initialization failed"); 1708 goto start_fail; 1709 } 1710 } 1711 1712 /* Setup and initialize the transmit structures */ 1713 e1000g_tx_setup(Adapter); 1714 msec_delay(5); 1715 1716 /* Setup and initialize the receive structures */ 1717 e1000g_rx_setup(Adapter); 1718 msec_delay(5); 1719 1720 /* Restore the e1000g promiscuous mode */ 1721 e1000g_restore_promisc(Adapter); 1722 1723 e1000g_mask_interrupt(Adapter); 1724 1725 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1726 1727 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1728 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1729 goto start_fail; 1730 } 1731 1732 return (DDI_SUCCESS); 1733 1734 start_fail: 1735 rx_data = Adapter->rx_ring->rx_data; 1736 1737 if (global) { 1738 e1000g_release_dma_resources(Adapter); 1739 e1000g_free_rx_pending_buffers(rx_data); 1740 e1000g_free_rx_data(rx_data); 1741 } 1742 1743 mutex_enter(&e1000g_nvm_lock); 1744 (void) e1000_reset_hw(&Adapter->shared); 1745 mutex_exit(&e1000g_nvm_lock); 1746 1747 return (DDI_FAILURE); 1748 } 1749 1750 static void 1751 e1000g_m_stop(void *arg) 1752 { 1753 struct e1000g *Adapter = (struct e1000g *)arg; 1754 1755 /* Drain tx sessions */ 1756 (void) e1000g_tx_drain(Adapter); 1757 1758 rw_enter(&Adapter->chip_lock, RW_WRITER); 1759 1760 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1761 rw_exit(&Adapter->chip_lock); 1762 return; 1763 } 1764 Adapter->e1000g_state &= ~E1000G_STARTED; 1765 e1000g_stop(Adapter, B_TRUE); 1766 1767 rw_exit(&Adapter->chip_lock); 1768 1769 /* Disable and stop all the timers */ 1770 disable_watchdog_timer(Adapter); 1771 stop_link_timer(Adapter); 1772 stop_82547_timer(Adapter->tx_ring); 1773 } 1774 1775 static void 1776 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1777 { 1778 private_devi_list_t *devi_node; 1779 e1000g_rx_data_t *rx_data; 1780 int result; 1781 1782 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1783 1784 /* Stop the chip and release pending resources */ 1785 1786 /* Tell firmware driver is no longer in control */ 1787 e1000g_release_driver_control(&Adapter->shared); 1788 1789 e1000g_clear_all_interrupts(Adapter); 1790 1791 mutex_enter(&e1000g_nvm_lock); 1792 result = e1000_reset_hw(&Adapter->shared); 1793 mutex_exit(&e1000g_nvm_lock); 1794 1795 if (result != E1000_SUCCESS) { 1796 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1797 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1798 } 1799 1800 /* Release resources still held by the TX descriptors */ 1801 e1000g_tx_clean(Adapter); 1802 1803 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1804 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1805 1806 /* Clean the pending rx jumbo packet fragment */ 1807 e1000g_rx_clean(Adapter); 1808 1809 if (global) { 1810 e1000g_release_dma_resources(Adapter); 1811 1812 mutex_enter(&e1000g_rx_detach_lock); 1813 rx_data = Adapter->rx_ring->rx_data; 1814 rx_data->flag |= E1000G_RX_STOPPED; 1815 1816 if (rx_data->pending_count == 0) { 1817 e1000g_free_rx_pending_buffers(rx_data); 1818 e1000g_free_rx_data(rx_data); 1819 } else { 1820 devi_node = rx_data->priv_devi_node; 1821 if (devi_node != NULL) 1822 atomic_inc_32(&devi_node->pending_rx_count); 1823 else 1824 atomic_inc_32(&Adapter->pending_rx_count); 1825 } 1826 mutex_exit(&e1000g_rx_detach_lock); 1827 } 1828 1829 if (Adapter->link_state == LINK_STATE_UP) { 1830 Adapter->link_state = LINK_STATE_UNKNOWN; 1831 mac_link_update(Adapter->mh, Adapter->link_state); 1832 } 1833 } 1834 1835 static void 1836 e1000g_rx_clean(struct e1000g *Adapter) 1837 { 1838 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 1839 1840 if (rx_data == NULL) 1841 return; 1842 1843 if (rx_data->rx_mblk != NULL) { 1844 freemsg(rx_data->rx_mblk); 1845 rx_data->rx_mblk = NULL; 1846 rx_data->rx_mblk_tail = NULL; 1847 rx_data->rx_mblk_len = 0; 1848 } 1849 } 1850 1851 static void 1852 e1000g_tx_clean(struct e1000g *Adapter) 1853 { 1854 e1000g_tx_ring_t *tx_ring; 1855 p_tx_sw_packet_t packet; 1856 mblk_t *mp; 1857 mblk_t *nmp; 1858 uint32_t packet_count; 1859 1860 tx_ring = Adapter->tx_ring; 1861 1862 /* 1863 * Here we don't need to protect the lists using 1864 * the usedlist_lock and freelist_lock, for they 1865 * have been protected by the chip_lock. 1866 */ 1867 mp = NULL; 1868 nmp = NULL; 1869 packet_count = 0; 1870 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1871 while (packet != NULL) { 1872 if (packet->mp != NULL) { 1873 /* Assemble the message chain */ 1874 if (mp == NULL) { 1875 mp = packet->mp; 1876 nmp = packet->mp; 1877 } else { 1878 nmp->b_next = packet->mp; 1879 nmp = packet->mp; 1880 } 1881 /* Disconnect the message from the sw packet */ 1882 packet->mp = NULL; 1883 } 1884 1885 e1000g_free_tx_swpkt(packet); 1886 packet_count++; 1887 1888 packet = (p_tx_sw_packet_t) 1889 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1890 } 1891 1892 if (mp != NULL) 1893 freemsgchain(mp); 1894 1895 if (packet_count > 0) { 1896 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1897 QUEUE_INIT_LIST(&tx_ring->used_list); 1898 1899 /* Setup TX descriptor pointers */ 1900 tx_ring->tbd_next = tx_ring->tbd_first; 1901 tx_ring->tbd_oldest = tx_ring->tbd_first; 1902 1903 /* Setup our HW Tx Head & Tail descriptor pointers */ 1904 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1905 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1906 } 1907 } 1908 1909 static boolean_t 1910 e1000g_tx_drain(struct e1000g *Adapter) 1911 { 1912 int i; 1913 boolean_t done; 1914 e1000g_tx_ring_t *tx_ring; 1915 1916 tx_ring = Adapter->tx_ring; 1917 1918 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1919 for (i = 0; i < TX_DRAIN_TIME; i++) { 1920 mutex_enter(&tx_ring->usedlist_lock); 1921 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1922 mutex_exit(&tx_ring->usedlist_lock); 1923 1924 if (done) 1925 break; 1926 1927 msec_delay(1); 1928 } 1929 1930 return (done); 1931 } 1932 1933 static boolean_t 1934 e1000g_rx_drain(struct e1000g *Adapter) 1935 { 1936 int i; 1937 boolean_t done; 1938 1939 /* 1940 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 1941 */ 1942 for (i = 0; i < RX_DRAIN_TIME; i++) { 1943 done = (Adapter->pending_rx_count == 0); 1944 1945 if (done) 1946 break; 1947 1948 msec_delay(1); 1949 } 1950 1951 return (done); 1952 } 1953 1954 static boolean_t 1955 e1000g_reset_adapter(struct e1000g *Adapter) 1956 { 1957 /* Disable and stop all the timers */ 1958 disable_watchdog_timer(Adapter); 1959 stop_link_timer(Adapter); 1960 stop_82547_timer(Adapter->tx_ring); 1961 1962 rw_enter(&Adapter->chip_lock, RW_WRITER); 1963 1964 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1965 rw_exit(&Adapter->chip_lock); 1966 return (B_TRUE); 1967 } 1968 1969 e1000g_stop(Adapter, B_FALSE); 1970 1971 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1972 rw_exit(&Adapter->chip_lock); 1973 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1974 return (B_FALSE); 1975 } 1976 1977 rw_exit(&Adapter->chip_lock); 1978 1979 /* Enable and start the watchdog timer */ 1980 enable_watchdog_timer(Adapter); 1981 1982 return (B_TRUE); 1983 } 1984 1985 boolean_t 1986 e1000g_global_reset(struct e1000g *Adapter) 1987 { 1988 /* Disable and stop all the timers */ 1989 disable_watchdog_timer(Adapter); 1990 stop_link_timer(Adapter); 1991 stop_82547_timer(Adapter->tx_ring); 1992 1993 rw_enter(&Adapter->chip_lock, RW_WRITER); 1994 1995 e1000g_stop(Adapter, B_TRUE); 1996 1997 Adapter->init_count = 0; 1998 1999 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2000 rw_exit(&Adapter->chip_lock); 2001 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2002 return (B_FALSE); 2003 } 2004 2005 rw_exit(&Adapter->chip_lock); 2006 2007 /* Enable and start the watchdog timer */ 2008 enable_watchdog_timer(Adapter); 2009 2010 return (B_TRUE); 2011 } 2012 2013 /* 2014 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2015 * 2016 * This interrupt service routine is for PCI-Express adapters. 2017 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2018 * bit is set. 2019 */ 2020 static uint_t 2021 e1000g_intr_pciexpress(caddr_t arg) 2022 { 2023 struct e1000g *Adapter; 2024 uint32_t icr; 2025 2026 Adapter = (struct e1000g *)(uintptr_t)arg; 2027 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2028 2029 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2030 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2031 2032 if (icr & E1000_ICR_INT_ASSERTED) { 2033 /* 2034 * E1000_ICR_INT_ASSERTED bit was set: 2035 * Read(Clear) the ICR, claim this interrupt, 2036 * look for work to do. 2037 */ 2038 e1000g_intr_work(Adapter, icr); 2039 return (DDI_INTR_CLAIMED); 2040 } else { 2041 /* 2042 * E1000_ICR_INT_ASSERTED bit was not set: 2043 * Don't claim this interrupt, return immediately. 2044 */ 2045 return (DDI_INTR_UNCLAIMED); 2046 } 2047 } 2048 2049 /* 2050 * e1000g_intr - ISR for PCI/PCI-X chipsets 2051 * 2052 * This interrupt service routine is for PCI/PCI-X adapters. 2053 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2054 * bit is set or not. 2055 */ 2056 static uint_t 2057 e1000g_intr(caddr_t arg) 2058 { 2059 struct e1000g *Adapter; 2060 uint32_t icr; 2061 2062 Adapter = (struct e1000g *)(uintptr_t)arg; 2063 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2064 2065 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2066 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2067 2068 if (icr) { 2069 /* 2070 * Any bit was set in ICR: 2071 * Read(Clear) the ICR, claim this interrupt, 2072 * look for work to do. 2073 */ 2074 e1000g_intr_work(Adapter, icr); 2075 return (DDI_INTR_CLAIMED); 2076 } else { 2077 /* 2078 * No bit was set in ICR: 2079 * Don't claim this interrupt, return immediately. 2080 */ 2081 return (DDI_INTR_UNCLAIMED); 2082 } 2083 } 2084 2085 /* 2086 * e1000g_intr_work - actual processing of ISR 2087 * 2088 * Read(clear) the ICR contents and call appropriate interrupt 2089 * processing routines. 2090 */ 2091 static void 2092 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2093 { 2094 struct e1000_hw *hw; 2095 hw = &Adapter->shared; 2096 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2097 2098 Adapter->rx_pkt_cnt = 0; 2099 Adapter->tx_pkt_cnt = 0; 2100 2101 rw_enter(&Adapter->chip_lock, RW_READER); 2102 2103 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2104 rw_exit(&Adapter->chip_lock); 2105 return; 2106 } 2107 /* 2108 * Here we need to check the "e1000g_state" flag within the chip_lock to 2109 * ensure the receive routine will not execute when the adapter is 2110 * being reset. 2111 */ 2112 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2113 rw_exit(&Adapter->chip_lock); 2114 return; 2115 } 2116 2117 if (icr & E1000_ICR_RXT0) { 2118 mblk_t *mp = NULL; 2119 mblk_t *tail = NULL; 2120 e1000g_rx_ring_t *rx_ring; 2121 2122 rx_ring = Adapter->rx_ring; 2123 mutex_enter(&rx_ring->rx_lock); 2124 /* 2125 * Sometimes with legacy interrupts, it possible that 2126 * there is a single interrupt for Rx/Tx. In which 2127 * case, if poll flag is set, we shouldn't really 2128 * be doing Rx processing. 2129 */ 2130 if (!rx_ring->poll_flag) 2131 mp = e1000g_receive(rx_ring, &tail, 2132 E1000G_CHAIN_NO_LIMIT); 2133 mutex_exit(&rx_ring->rx_lock); 2134 rw_exit(&Adapter->chip_lock); 2135 if (mp != NULL) 2136 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2137 mp, rx_ring->ring_gen_num); 2138 } else 2139 rw_exit(&Adapter->chip_lock); 2140 2141 if (icr & E1000_ICR_TXDW) { 2142 if (!Adapter->tx_intr_enable) 2143 e1000g_clear_tx_interrupt(Adapter); 2144 2145 /* Recycle the tx descriptors */ 2146 rw_enter(&Adapter->chip_lock, RW_READER); 2147 (void) e1000g_recycle(tx_ring); 2148 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2149 rw_exit(&Adapter->chip_lock); 2150 2151 if (tx_ring->resched_needed && 2152 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2153 tx_ring->resched_needed = B_FALSE; 2154 mac_tx_update(Adapter->mh); 2155 E1000G_STAT(tx_ring->stat_reschedule); 2156 } 2157 } 2158 2159 /* 2160 * The Receive Sequence errors RXSEQ and the link status change LSC 2161 * are checked to detect that the cable has been pulled out. For 2162 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2163 * are an indication that cable is not connected. 2164 */ 2165 if ((icr & E1000_ICR_RXSEQ) || 2166 (icr & E1000_ICR_LSC) || 2167 (icr & E1000_ICR_GPI_EN1)) { 2168 boolean_t link_changed; 2169 timeout_id_t tid = 0; 2170 2171 stop_watchdog_timer(Adapter); 2172 2173 rw_enter(&Adapter->chip_lock, RW_WRITER); 2174 2175 /* 2176 * Because we got a link-status-change interrupt, force 2177 * e1000_check_for_link() to look at phy 2178 */ 2179 Adapter->shared.mac.get_link_status = B_TRUE; 2180 2181 /* e1000g_link_check takes care of link status change */ 2182 link_changed = e1000g_link_check(Adapter); 2183 2184 /* Get new phy state */ 2185 e1000g_get_phy_state(Adapter); 2186 2187 /* 2188 * If the link timer has not timed out, we'll not notify 2189 * the upper layer with any link state until the link is up. 2190 */ 2191 if (link_changed && !Adapter->link_complete) { 2192 if (Adapter->link_state == LINK_STATE_UP) { 2193 mutex_enter(&Adapter->link_lock); 2194 Adapter->link_complete = B_TRUE; 2195 tid = Adapter->link_tid; 2196 Adapter->link_tid = 0; 2197 mutex_exit(&Adapter->link_lock); 2198 } else { 2199 link_changed = B_FALSE; 2200 } 2201 } 2202 rw_exit(&Adapter->chip_lock); 2203 2204 if (link_changed) { 2205 if (tid != 0) 2206 (void) untimeout(tid); 2207 2208 /* 2209 * Workaround for esb2. Data stuck in fifo on a link 2210 * down event. Stop receiver here and reset in watchdog. 2211 */ 2212 if ((Adapter->link_state == LINK_STATE_DOWN) && 2213 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2214 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2215 E1000_WRITE_REG(hw, E1000_RCTL, 2216 rctl & ~E1000_RCTL_EN); 2217 e1000g_log(Adapter, CE_WARN, 2218 "ESB2 receiver disabled"); 2219 Adapter->esb2_workaround = B_TRUE; 2220 } 2221 if (!Adapter->reset_flag) 2222 mac_link_update(Adapter->mh, 2223 Adapter->link_state); 2224 if (Adapter->link_state == LINK_STATE_UP) 2225 Adapter->reset_flag = B_FALSE; 2226 } 2227 2228 start_watchdog_timer(Adapter); 2229 } 2230 } 2231 2232 static void 2233 e1000g_init_unicst(struct e1000g *Adapter) 2234 { 2235 struct e1000_hw *hw; 2236 int slot; 2237 2238 hw = &Adapter->shared; 2239 2240 if (Adapter->init_count == 0) { 2241 /* Initialize the multiple unicast addresses */ 2242 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2243 2244 /* Workaround for an erratum of 82571 chipst */ 2245 if ((hw->mac.type == e1000_82571) && 2246 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2247 Adapter->unicst_total--; 2248 2249 Adapter->unicst_avail = Adapter->unicst_total; 2250 2251 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2252 /* Clear both the flag and MAC address */ 2253 Adapter->unicst_addr[slot].reg.high = 0; 2254 Adapter->unicst_addr[slot].reg.low = 0; 2255 } 2256 } else { 2257 /* Workaround for an erratum of 82571 chipst */ 2258 if ((hw->mac.type == e1000_82571) && 2259 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2260 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2261 2262 /* Re-configure the RAR registers */ 2263 for (slot = 0; slot < Adapter->unicst_total; slot++) 2264 if (Adapter->unicst_addr[slot].mac.set == 1) 2265 e1000_rar_set(hw, 2266 Adapter->unicst_addr[slot].mac.addr, slot); 2267 } 2268 2269 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2270 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2271 } 2272 2273 static int 2274 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2275 int slot) 2276 { 2277 struct e1000_hw *hw; 2278 2279 hw = &Adapter->shared; 2280 2281 /* 2282 * The first revision of Wiseman silicon (rev 2.0) has an errata 2283 * that requires the receiver to be in reset when any of the 2284 * receive address registers (RAR regs) are accessed. The first 2285 * rev of Wiseman silicon also requires MWI to be disabled when 2286 * a global reset or a receive reset is issued. So before we 2287 * initialize the RARs, we check the rev of the Wiseman controller 2288 * and work around any necessary HW errata. 2289 */ 2290 if ((hw->mac.type == e1000_82542) && 2291 (hw->revision_id == E1000_REVISION_2)) { 2292 e1000_pci_clear_mwi(hw); 2293 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2294 msec_delay(5); 2295 } 2296 if (mac_addr == NULL) { 2297 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2298 E1000_WRITE_FLUSH(hw); 2299 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2300 E1000_WRITE_FLUSH(hw); 2301 /* Clear both the flag and MAC address */ 2302 Adapter->unicst_addr[slot].reg.high = 0; 2303 Adapter->unicst_addr[slot].reg.low = 0; 2304 } else { 2305 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2306 ETHERADDRL); 2307 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2308 Adapter->unicst_addr[slot].mac.set = 1; 2309 } 2310 2311 /* Workaround for an erratum of 82571 chipst */ 2312 if (slot == 0) { 2313 if ((hw->mac.type == e1000_82571) && 2314 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2315 if (mac_addr == NULL) { 2316 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2317 slot << 1, 0); 2318 E1000_WRITE_FLUSH(hw); 2319 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2320 (slot << 1) + 1, 0); 2321 E1000_WRITE_FLUSH(hw); 2322 } else { 2323 e1000_rar_set(hw, (uint8_t *)mac_addr, 2324 LAST_RAR_ENTRY); 2325 } 2326 } 2327 2328 /* 2329 * If we are using Wiseman rev 2.0 silicon, we will have previously 2330 * put the receive in reset, and disabled MWI, to work around some 2331 * HW errata. Now we should take the receiver out of reset, and 2332 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2333 */ 2334 if ((hw->mac.type == e1000_82542) && 2335 (hw->revision_id == E1000_REVISION_2)) { 2336 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2337 msec_delay(1); 2338 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2339 e1000_pci_set_mwi(hw); 2340 e1000g_rx_setup(Adapter); 2341 } 2342 2343 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2344 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2345 return (EIO); 2346 } 2347 2348 return (0); 2349 } 2350 2351 static int 2352 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2353 { 2354 struct e1000_hw *hw = &Adapter->shared; 2355 struct ether_addr *newtable; 2356 size_t new_len; 2357 size_t old_len; 2358 int res = 0; 2359 2360 if ((multiaddr[0] & 01) == 0) { 2361 res = EINVAL; 2362 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2363 goto done; 2364 } 2365 2366 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2367 res = ENOENT; 2368 e1000g_log(Adapter, CE_WARN, 2369 "Adapter requested more than %d mcast addresses", 2370 Adapter->mcast_max_num); 2371 goto done; 2372 } 2373 2374 2375 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2376 old_len = Adapter->mcast_alloc_count * 2377 sizeof (struct ether_addr); 2378 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2379 sizeof (struct ether_addr); 2380 2381 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2382 if (newtable == NULL) { 2383 res = ENOMEM; 2384 e1000g_log(Adapter, CE_WARN, 2385 "Not enough memory to alloc mcast table"); 2386 goto done; 2387 } 2388 2389 if (Adapter->mcast_table != NULL) { 2390 bcopy(Adapter->mcast_table, newtable, old_len); 2391 kmem_free(Adapter->mcast_table, old_len); 2392 } 2393 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2394 Adapter->mcast_table = newtable; 2395 } 2396 2397 bcopy(multiaddr, 2398 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2399 Adapter->mcast_count++; 2400 2401 /* 2402 * Update the MC table in the hardware 2403 */ 2404 e1000g_clear_interrupt(Adapter); 2405 2406 e1000g_setup_multicast(Adapter); 2407 2408 if ((hw->mac.type == e1000_82542) && 2409 (hw->revision_id == E1000_REVISION_2)) 2410 e1000g_rx_setup(Adapter); 2411 2412 e1000g_mask_interrupt(Adapter); 2413 2414 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2415 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2416 res = EIO; 2417 } 2418 2419 done: 2420 return (res); 2421 } 2422 2423 static int 2424 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2425 { 2426 struct e1000_hw *hw = &Adapter->shared; 2427 struct ether_addr *newtable; 2428 size_t new_len; 2429 size_t old_len; 2430 unsigned i; 2431 2432 for (i = 0; i < Adapter->mcast_count; i++) { 2433 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2434 ETHERADDRL) == 0) { 2435 for (i++; i < Adapter->mcast_count; i++) { 2436 Adapter->mcast_table[i - 1] = 2437 Adapter->mcast_table[i]; 2438 } 2439 Adapter->mcast_count--; 2440 break; 2441 } 2442 } 2443 2444 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2445 MCAST_ALLOC_SIZE) { 2446 old_len = Adapter->mcast_alloc_count * 2447 sizeof (struct ether_addr); 2448 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2449 sizeof (struct ether_addr); 2450 2451 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2452 if (newtable != NULL) { 2453 bcopy(Adapter->mcast_table, newtable, new_len); 2454 kmem_free(Adapter->mcast_table, old_len); 2455 2456 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2457 Adapter->mcast_table = newtable; 2458 } 2459 } 2460 2461 /* 2462 * Update the MC table in the hardware 2463 */ 2464 e1000g_clear_interrupt(Adapter); 2465 2466 e1000g_setup_multicast(Adapter); 2467 2468 if ((hw->mac.type == e1000_82542) && 2469 (hw->revision_id == E1000_REVISION_2)) 2470 e1000g_rx_setup(Adapter); 2471 2472 e1000g_mask_interrupt(Adapter); 2473 2474 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2475 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2476 return (EIO); 2477 } 2478 2479 return (0); 2480 } 2481 2482 static void 2483 e1000g_release_multicast(struct e1000g *Adapter) 2484 { 2485 if (Adapter->mcast_table != NULL) { 2486 kmem_free(Adapter->mcast_table, 2487 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2488 Adapter->mcast_table = NULL; 2489 } 2490 } 2491 2492 /* 2493 * e1000g_setup_multicast - setup multicast data structures 2494 * 2495 * This routine initializes all of the multicast related structures. 2496 */ 2497 void 2498 e1000g_setup_multicast(struct e1000g *Adapter) 2499 { 2500 uint8_t *mc_addr_list; 2501 uint32_t mc_addr_count; 2502 uint32_t rctl; 2503 struct e1000_hw *hw; 2504 2505 hw = &Adapter->shared; 2506 2507 /* 2508 * The e1000g has the ability to do perfect filtering of 16 2509 * addresses. The driver uses one of the e1000g's 16 receive 2510 * address registers for its node/network/mac/individual address. 2511 * So, we have room for up to 15 multicast addresses in the CAM, 2512 * additional MC addresses are handled by the MTA (Multicast Table 2513 * Array) 2514 */ 2515 2516 rctl = E1000_READ_REG(hw, E1000_RCTL); 2517 2518 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2519 2520 ASSERT(Adapter->mcast_count <= Adapter->mcast_max_num); 2521 2522 mc_addr_count = Adapter->mcast_count; 2523 /* 2524 * The Wiseman 2.0 silicon has an errata by which the receiver will 2525 * hang while writing to the receive address registers if the receiver 2526 * is not in reset before writing to the registers. Updating the RAR 2527 * is done during the setting up of the multicast table, hence the 2528 * receiver has to be put in reset before updating the multicast table 2529 * and then taken out of reset at the end 2530 */ 2531 /* 2532 * if WMI was enabled then dis able it before issueing the global 2533 * reset to the hardware. 2534 */ 2535 /* 2536 * Only required for WISEMAN_2_0 2537 */ 2538 if ((hw->mac.type == e1000_82542) && 2539 (hw->revision_id == E1000_REVISION_2)) { 2540 e1000_pci_clear_mwi(hw); 2541 /* 2542 * The e1000g must be in reset before changing any RA 2543 * registers. Reset receive unit. The chip will remain in 2544 * the reset state until software explicitly restarts it. 2545 */ 2546 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2547 /* Allow receiver time to go in to reset */ 2548 msec_delay(5); 2549 } 2550 2551 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2552 Adapter->unicst_total, hw->mac.rar_entry_count); 2553 2554 /* 2555 * Only for Wiseman_2_0 2556 * If MWI was enabled then re-enable it after issueing (as we 2557 * disabled it up there) the receive reset command. 2558 * Wainwright does not have a receive reset command and only thing 2559 * close to it is global reset which will require tx setup also 2560 */ 2561 if ((hw->mac.type == e1000_82542) && 2562 (hw->revision_id == E1000_REVISION_2)) { 2563 /* 2564 * if WMI was enabled then reenable it after issueing the 2565 * global or receive reset to the hardware. 2566 */ 2567 2568 /* 2569 * Take receiver out of reset 2570 * clear E1000_RCTL_RST bit (and all others) 2571 */ 2572 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2573 msec_delay(5); 2574 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2575 e1000_pci_set_mwi(hw); 2576 } 2577 2578 /* 2579 * Restore original value 2580 */ 2581 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2582 } 2583 2584 int 2585 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2586 { 2587 struct e1000g *Adapter = (struct e1000g *)arg; 2588 int result; 2589 2590 rw_enter(&Adapter->chip_lock, RW_WRITER); 2591 2592 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2593 result = ECANCELED; 2594 goto done; 2595 } 2596 2597 result = (add) ? multicst_add(Adapter, addr) 2598 : multicst_remove(Adapter, addr); 2599 2600 done: 2601 rw_exit(&Adapter->chip_lock); 2602 return (result); 2603 2604 } 2605 2606 int 2607 e1000g_m_promisc(void *arg, boolean_t on) 2608 { 2609 struct e1000g *Adapter = (struct e1000g *)arg; 2610 uint32_t rctl; 2611 2612 rw_enter(&Adapter->chip_lock, RW_WRITER); 2613 2614 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2615 rw_exit(&Adapter->chip_lock); 2616 return (ECANCELED); 2617 } 2618 2619 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2620 2621 if (on) 2622 rctl |= 2623 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2624 else 2625 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2626 2627 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2628 2629 Adapter->e1000g_promisc = on; 2630 2631 rw_exit(&Adapter->chip_lock); 2632 2633 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2634 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2635 return (EIO); 2636 } 2637 2638 return (0); 2639 } 2640 2641 /* 2642 * Entry points to enable and disable interrupts at the granularity of 2643 * a group. 2644 * Turns the poll_mode for the whole adapter on and off to enable or 2645 * override the ring level polling control over the hardware interrupts. 2646 */ 2647 static int 2648 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2649 { 2650 struct e1000g *adapter = (struct e1000g *)arg; 2651 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2652 2653 /* 2654 * Later interrupts at the granularity of the this ring will 2655 * invoke mac_rx() with NULL, indicating the need for another 2656 * software classification. 2657 * We have a single ring usable per adapter now, so we only need to 2658 * reset the rx handle for that one. 2659 * When more RX rings can be used, we should update each one of them. 2660 */ 2661 mutex_enter(&rx_ring->rx_lock); 2662 rx_ring->mrh = NULL; 2663 adapter->poll_mode = B_FALSE; 2664 mutex_exit(&rx_ring->rx_lock); 2665 return (0); 2666 } 2667 2668 static int 2669 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2670 { 2671 struct e1000g *adapter = (struct e1000g *)arg; 2672 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2673 2674 mutex_enter(&rx_ring->rx_lock); 2675 2676 /* 2677 * Later interrupts at the granularity of the this ring will 2678 * invoke mac_rx() with the handle for this ring; 2679 */ 2680 adapter->poll_mode = B_TRUE; 2681 rx_ring->mrh = rx_ring->mrh_init; 2682 mutex_exit(&rx_ring->rx_lock); 2683 return (0); 2684 } 2685 2686 /* 2687 * Entry points to enable and disable interrupts at the granularity of 2688 * a ring. 2689 * adapter poll_mode controls whether we actually proceed with hardware 2690 * interrupt toggling. 2691 */ 2692 static int 2693 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2694 { 2695 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2696 struct e1000g *adapter = rx_ring->adapter; 2697 struct e1000_hw *hw = &adapter->shared; 2698 uint32_t intr_mask; 2699 2700 rw_enter(&adapter->chip_lock, RW_READER); 2701 2702 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2703 rw_exit(&adapter->chip_lock); 2704 return (0); 2705 } 2706 2707 mutex_enter(&rx_ring->rx_lock); 2708 rx_ring->poll_flag = 0; 2709 mutex_exit(&rx_ring->rx_lock); 2710 2711 /* Rx interrupt enabling for MSI and legacy */ 2712 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2713 intr_mask |= E1000_IMS_RXT0; 2714 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2715 E1000_WRITE_FLUSH(hw); 2716 2717 /* Trigger a Rx interrupt to check Rx ring */ 2718 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2719 E1000_WRITE_FLUSH(hw); 2720 2721 rw_exit(&adapter->chip_lock); 2722 return (0); 2723 } 2724 2725 static int 2726 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2727 { 2728 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2729 struct e1000g *adapter = rx_ring->adapter; 2730 struct e1000_hw *hw = &adapter->shared; 2731 2732 rw_enter(&adapter->chip_lock, RW_READER); 2733 2734 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2735 rw_exit(&adapter->chip_lock); 2736 return (0); 2737 } 2738 mutex_enter(&rx_ring->rx_lock); 2739 rx_ring->poll_flag = 1; 2740 mutex_exit(&rx_ring->rx_lock); 2741 2742 /* Rx interrupt disabling for MSI and legacy */ 2743 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2744 E1000_WRITE_FLUSH(hw); 2745 2746 rw_exit(&adapter->chip_lock); 2747 return (0); 2748 } 2749 2750 /* 2751 * e1000g_unicst_find - Find the slot for the specified unicast address 2752 */ 2753 static int 2754 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2755 { 2756 int slot; 2757 2758 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2759 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2760 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2761 mac_addr, ETHERADDRL) == 0)) 2762 return (slot); 2763 } 2764 2765 return (-1); 2766 } 2767 2768 /* 2769 * Entry points to add and remove a MAC address to a ring group. 2770 * The caller takes care of adding and removing the MAC addresses 2771 * to the filter via these two routines. 2772 */ 2773 2774 static int 2775 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2776 { 2777 struct e1000g *Adapter = (struct e1000g *)arg; 2778 int slot, err; 2779 2780 rw_enter(&Adapter->chip_lock, RW_WRITER); 2781 2782 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2783 rw_exit(&Adapter->chip_lock); 2784 return (ECANCELED); 2785 } 2786 2787 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2788 /* The same address is already in slot */ 2789 rw_exit(&Adapter->chip_lock); 2790 return (0); 2791 } 2792 2793 if (Adapter->unicst_avail == 0) { 2794 /* no slots available */ 2795 rw_exit(&Adapter->chip_lock); 2796 return (ENOSPC); 2797 } 2798 2799 /* Search for a free slot */ 2800 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2801 if (Adapter->unicst_addr[slot].mac.set == 0) 2802 break; 2803 } 2804 ASSERT(slot < Adapter->unicst_total); 2805 2806 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2807 if (err == 0) 2808 Adapter->unicst_avail--; 2809 2810 rw_exit(&Adapter->chip_lock); 2811 2812 return (err); 2813 } 2814 2815 static int 2816 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2817 { 2818 struct e1000g *Adapter = (struct e1000g *)arg; 2819 int slot, err; 2820 2821 rw_enter(&Adapter->chip_lock, RW_WRITER); 2822 2823 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2824 rw_exit(&Adapter->chip_lock); 2825 return (ECANCELED); 2826 } 2827 2828 slot = e1000g_unicst_find(Adapter, mac_addr); 2829 if (slot == -1) { 2830 rw_exit(&Adapter->chip_lock); 2831 return (EINVAL); 2832 } 2833 2834 ASSERT(Adapter->unicst_addr[slot].mac.set); 2835 2836 /* Clear this slot */ 2837 err = e1000g_unicst_set(Adapter, NULL, slot); 2838 if (err == 0) 2839 Adapter->unicst_avail++; 2840 2841 rw_exit(&Adapter->chip_lock); 2842 2843 return (err); 2844 } 2845 2846 static int 2847 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2848 { 2849 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2850 2851 mutex_enter(&rx_ring->rx_lock); 2852 rx_ring->ring_gen_num = mr_gen_num; 2853 mutex_exit(&rx_ring->rx_lock); 2854 return (0); 2855 } 2856 2857 /* 2858 * Callback funtion for MAC layer to register all rings. 2859 * 2860 * The hardware supports a single group with currently only one ring 2861 * available. 2862 * Though not offering virtualization ability per se, exposing the 2863 * group/ring still enables the polling and interrupt toggling. 2864 */ 2865 void 2866 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2867 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2868 { 2869 struct e1000g *Adapter = (struct e1000g *)arg; 2870 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2871 mac_intr_t *mintr; 2872 2873 /* 2874 * We advertised only RX group/rings, so the MAC framework shouldn't 2875 * ask for any thing else. 2876 */ 2877 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2878 2879 rx_ring->mrh = rx_ring->mrh_init = rh; 2880 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2881 infop->mri_start = e1000g_ring_start; 2882 infop->mri_stop = NULL; 2883 infop->mri_poll = e1000g_poll_ring; 2884 2885 /* Ring level interrupts */ 2886 mintr = &infop->mri_intr; 2887 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2888 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2889 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2890 } 2891 2892 static void 2893 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2894 mac_group_info_t *infop, mac_group_handle_t gh) 2895 { 2896 struct e1000g *Adapter = (struct e1000g *)arg; 2897 mac_intr_t *mintr; 2898 2899 /* 2900 * We advertised a single RX ring. Getting a request for anything else 2901 * signifies a bug in the MAC framework. 2902 */ 2903 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2904 2905 Adapter->rx_group = gh; 2906 2907 infop->mgi_driver = (mac_group_driver_t)Adapter; 2908 infop->mgi_start = NULL; 2909 infop->mgi_stop = NULL; 2910 infop->mgi_addmac = e1000g_addmac; 2911 infop->mgi_remmac = e1000g_remmac; 2912 infop->mgi_count = 1; 2913 2914 /* Group level interrupts */ 2915 mintr = &infop->mgi_intr; 2916 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2917 mintr->mi_enable = e1000g_rx_group_intr_enable; 2918 mintr->mi_disable = e1000g_rx_group_intr_disable; 2919 } 2920 2921 static boolean_t 2922 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2923 { 2924 struct e1000g *Adapter = (struct e1000g *)arg; 2925 2926 switch (cap) { 2927 case MAC_CAPAB_HCKSUM: { 2928 uint32_t *txflags = cap_data; 2929 2930 if (Adapter->tx_hcksum_enable) 2931 *txflags = HCKSUM_IPHDRCKSUM | 2932 HCKSUM_INET_PARTIAL; 2933 else 2934 return (B_FALSE); 2935 break; 2936 } 2937 2938 case MAC_CAPAB_LSO: { 2939 mac_capab_lso_t *cap_lso = cap_data; 2940 2941 if (Adapter->lso_enable) { 2942 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2943 cap_lso->lso_basic_tcp_ipv4.lso_max = 2944 E1000_LSO_MAXLEN; 2945 } else 2946 return (B_FALSE); 2947 break; 2948 } 2949 case MAC_CAPAB_RINGS: { 2950 mac_capab_rings_t *cap_rings = cap_data; 2951 2952 /* No TX rings exposed yet */ 2953 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2954 return (B_FALSE); 2955 2956 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2957 cap_rings->mr_rnum = 1; 2958 cap_rings->mr_gnum = 1; 2959 cap_rings->mr_rget = e1000g_fill_ring; 2960 cap_rings->mr_gget = e1000g_fill_group; 2961 break; 2962 } 2963 default: 2964 return (B_FALSE); 2965 } 2966 return (B_TRUE); 2967 } 2968 2969 static boolean_t 2970 e1000g_param_locked(mac_prop_id_t pr_num) 2971 { 2972 /* 2973 * All en_* parameters are locked (read-only) while 2974 * the device is in any sort of loopback mode ... 2975 */ 2976 switch (pr_num) { 2977 case MAC_PROP_EN_1000FDX_CAP: 2978 case MAC_PROP_EN_1000HDX_CAP: 2979 case MAC_PROP_EN_100FDX_CAP: 2980 case MAC_PROP_EN_100HDX_CAP: 2981 case MAC_PROP_EN_10FDX_CAP: 2982 case MAC_PROP_EN_10HDX_CAP: 2983 case MAC_PROP_AUTONEG: 2984 case MAC_PROP_FLOWCTRL: 2985 return (B_TRUE); 2986 } 2987 return (B_FALSE); 2988 } 2989 2990 /* 2991 * callback function for set/get of properties 2992 */ 2993 static int 2994 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2995 uint_t pr_valsize, const void *pr_val) 2996 { 2997 struct e1000g *Adapter = arg; 2998 struct e1000_mac_info *mac = &Adapter->shared.mac; 2999 struct e1000_phy_info *phy = &Adapter->shared.phy; 3000 struct e1000_hw *hw = &Adapter->shared; 3001 struct e1000_fc_info *fc = &Adapter->shared.fc; 3002 int err = 0; 3003 link_flowctrl_t flowctrl; 3004 uint32_t cur_mtu, new_mtu; 3005 uint64_t tmp = 0; 3006 3007 rw_enter(&Adapter->chip_lock, RW_WRITER); 3008 3009 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3010 rw_exit(&Adapter->chip_lock); 3011 return (ECANCELED); 3012 } 3013 3014 if (Adapter->loopback_mode != E1000G_LB_NONE && 3015 e1000g_param_locked(pr_num)) { 3016 /* 3017 * All en_* parameters are locked (read-only) 3018 * while the device is in any sort of loopback mode. 3019 */ 3020 rw_exit(&Adapter->chip_lock); 3021 return (EBUSY); 3022 } 3023 3024 switch (pr_num) { 3025 case MAC_PROP_EN_1000FDX_CAP: 3026 if (hw->phy.media_type != e1000_media_type_copper) { 3027 err = ENOTSUP; 3028 break; 3029 } 3030 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3031 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3032 goto reset; 3033 case MAC_PROP_EN_100FDX_CAP: 3034 if (hw->phy.media_type != e1000_media_type_copper) { 3035 err = ENOTSUP; 3036 break; 3037 } 3038 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3039 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3040 goto reset; 3041 case MAC_PROP_EN_100HDX_CAP: 3042 if (hw->phy.media_type != e1000_media_type_copper) { 3043 err = ENOTSUP; 3044 break; 3045 } 3046 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3047 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3048 goto reset; 3049 case MAC_PROP_EN_10FDX_CAP: 3050 if (hw->phy.media_type != e1000_media_type_copper) { 3051 err = ENOTSUP; 3052 break; 3053 } 3054 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3055 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3056 goto reset; 3057 case MAC_PROP_EN_10HDX_CAP: 3058 if (hw->phy.media_type != e1000_media_type_copper) { 3059 err = ENOTSUP; 3060 break; 3061 } 3062 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3063 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3064 goto reset; 3065 case MAC_PROP_AUTONEG: 3066 if (hw->phy.media_type != e1000_media_type_copper) { 3067 err = ENOTSUP; 3068 break; 3069 } 3070 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3071 goto reset; 3072 case MAC_PROP_FLOWCTRL: 3073 fc->send_xon = B_TRUE; 3074 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3075 3076 switch (flowctrl) { 3077 default: 3078 err = EINVAL; 3079 break; 3080 case LINK_FLOWCTRL_NONE: 3081 fc->requested_mode = e1000_fc_none; 3082 break; 3083 case LINK_FLOWCTRL_RX: 3084 fc->requested_mode = e1000_fc_rx_pause; 3085 break; 3086 case LINK_FLOWCTRL_TX: 3087 fc->requested_mode = e1000_fc_tx_pause; 3088 break; 3089 case LINK_FLOWCTRL_BI: 3090 fc->requested_mode = e1000_fc_full; 3091 break; 3092 } 3093 reset: 3094 if (err == 0) { 3095 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3096 err = EINVAL; 3097 } 3098 break; 3099 case MAC_PROP_ADV_1000FDX_CAP: 3100 case MAC_PROP_ADV_1000HDX_CAP: 3101 case MAC_PROP_ADV_100FDX_CAP: 3102 case MAC_PROP_ADV_100HDX_CAP: 3103 case MAC_PROP_ADV_10FDX_CAP: 3104 case MAC_PROP_ADV_10HDX_CAP: 3105 case MAC_PROP_EN_1000HDX_CAP: 3106 case MAC_PROP_STATUS: 3107 case MAC_PROP_SPEED: 3108 case MAC_PROP_DUPLEX: 3109 err = ENOTSUP; /* read-only prop. Can't set this. */ 3110 break; 3111 case MAC_PROP_MTU: 3112 cur_mtu = Adapter->default_mtu; 3113 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3114 if (new_mtu == cur_mtu) { 3115 err = 0; 3116 break; 3117 } 3118 3119 tmp = new_mtu + sizeof (struct ether_vlan_header) + 3120 ETHERFCSL; 3121 if ((tmp < DEFAULT_FRAME_SIZE) || 3122 (tmp > MAXIMUM_FRAME_SIZE)) { 3123 err = EINVAL; 3124 break; 3125 } 3126 3127 /* ich8 does not support jumbo frames */ 3128 if ((mac->type == e1000_ich8lan) && 3129 (tmp > DEFAULT_FRAME_SIZE)) { 3130 err = EINVAL; 3131 break; 3132 } 3133 /* ich9 does not do jumbo frames on one phy type */ 3134 if ((mac->type == e1000_ich9lan) && 3135 (phy->type == e1000_phy_ife) && 3136 (tmp > DEFAULT_FRAME_SIZE)) { 3137 err = EINVAL; 3138 break; 3139 } 3140 if (Adapter->e1000g_state & E1000G_STARTED) { 3141 err = EBUSY; 3142 break; 3143 } 3144 3145 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3146 if (err == 0) { 3147 Adapter->max_frame_size = (uint32_t)tmp; 3148 Adapter->default_mtu = new_mtu; 3149 e1000g_set_bufsize(Adapter); 3150 } 3151 break; 3152 case MAC_PROP_PRIVATE: 3153 err = e1000g_set_priv_prop(Adapter, pr_name, 3154 pr_valsize, pr_val); 3155 break; 3156 default: 3157 err = ENOTSUP; 3158 break; 3159 } 3160 rw_exit(&Adapter->chip_lock); 3161 return (err); 3162 } 3163 3164 static int 3165 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3166 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3167 { 3168 struct e1000g *Adapter = arg; 3169 struct e1000_fc_info *fc = &Adapter->shared.fc; 3170 struct e1000_hw *hw = &Adapter->shared; 3171 int err = 0; 3172 link_flowctrl_t flowctrl; 3173 uint64_t tmp = 0; 3174 3175 if (pr_valsize == 0) 3176 return (EINVAL); 3177 3178 *perm = MAC_PROP_PERM_RW; 3179 3180 bzero(pr_val, pr_valsize); 3181 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3182 return (e1000g_get_def_val(Adapter, pr_num, 3183 pr_valsize, pr_val)); 3184 } 3185 3186 switch (pr_num) { 3187 case MAC_PROP_DUPLEX: 3188 *perm = MAC_PROP_PERM_READ; 3189 if (pr_valsize >= sizeof (link_duplex_t)) { 3190 bcopy(&Adapter->link_duplex, pr_val, 3191 sizeof (link_duplex_t)); 3192 } else 3193 err = EINVAL; 3194 break; 3195 case MAC_PROP_SPEED: 3196 *perm = MAC_PROP_PERM_READ; 3197 if (pr_valsize >= sizeof (uint64_t)) { 3198 tmp = Adapter->link_speed * 1000000ull; 3199 bcopy(&tmp, pr_val, sizeof (tmp)); 3200 } else 3201 err = EINVAL; 3202 break; 3203 case MAC_PROP_AUTONEG: 3204 if (hw->phy.media_type != e1000_media_type_copper) 3205 *perm = MAC_PROP_PERM_READ; 3206 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3207 break; 3208 case MAC_PROP_FLOWCTRL: 3209 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3210 switch (fc->current_mode) { 3211 case e1000_fc_none: 3212 flowctrl = LINK_FLOWCTRL_NONE; 3213 break; 3214 case e1000_fc_rx_pause: 3215 flowctrl = LINK_FLOWCTRL_RX; 3216 break; 3217 case e1000_fc_tx_pause: 3218 flowctrl = LINK_FLOWCTRL_TX; 3219 break; 3220 case e1000_fc_full: 3221 flowctrl = LINK_FLOWCTRL_BI; 3222 break; 3223 } 3224 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3225 } else 3226 err = EINVAL; 3227 break; 3228 case MAC_PROP_ADV_1000FDX_CAP: 3229 *perm = MAC_PROP_PERM_READ; 3230 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3231 break; 3232 case MAC_PROP_EN_1000FDX_CAP: 3233 if (hw->phy.media_type != e1000_media_type_copper) 3234 *perm = MAC_PROP_PERM_READ; 3235 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3236 break; 3237 case MAC_PROP_ADV_1000HDX_CAP: 3238 *perm = MAC_PROP_PERM_READ; 3239 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3240 break; 3241 case MAC_PROP_EN_1000HDX_CAP: 3242 *perm = MAC_PROP_PERM_READ; 3243 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3244 break; 3245 case MAC_PROP_ADV_100FDX_CAP: 3246 *perm = MAC_PROP_PERM_READ; 3247 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3248 break; 3249 case MAC_PROP_EN_100FDX_CAP: 3250 if (hw->phy.media_type != e1000_media_type_copper) 3251 *perm = MAC_PROP_PERM_READ; 3252 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3253 break; 3254 case MAC_PROP_ADV_100HDX_CAP: 3255 *perm = MAC_PROP_PERM_READ; 3256 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3257 break; 3258 case MAC_PROP_EN_100HDX_CAP: 3259 if (hw->phy.media_type != e1000_media_type_copper) 3260 *perm = MAC_PROP_PERM_READ; 3261 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3262 break; 3263 case MAC_PROP_ADV_10FDX_CAP: 3264 *perm = MAC_PROP_PERM_READ; 3265 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3266 break; 3267 case MAC_PROP_EN_10FDX_CAP: 3268 if (hw->phy.media_type != e1000_media_type_copper) 3269 *perm = MAC_PROP_PERM_READ; 3270 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3271 break; 3272 case MAC_PROP_ADV_10HDX_CAP: 3273 *perm = MAC_PROP_PERM_READ; 3274 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3275 break; 3276 case MAC_PROP_EN_10HDX_CAP: 3277 if (hw->phy.media_type != e1000_media_type_copper) 3278 *perm = MAC_PROP_PERM_READ; 3279 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3280 break; 3281 case MAC_PROP_ADV_100T4_CAP: 3282 case MAC_PROP_EN_100T4_CAP: 3283 *perm = MAC_PROP_PERM_READ; 3284 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3285 break; 3286 case MAC_PROP_PRIVATE: 3287 err = e1000g_get_priv_prop(Adapter, pr_name, 3288 pr_flags, pr_valsize, pr_val, perm); 3289 break; 3290 case MAC_PROP_MTU: { 3291 struct e1000_mac_info *mac = &Adapter->shared.mac; 3292 struct e1000_phy_info *phy = &Adapter->shared.phy; 3293 mac_propval_range_t range; 3294 3295 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3296 return (ENOTSUP); 3297 if (pr_valsize < sizeof (mac_propval_range_t)) 3298 return (EINVAL); 3299 range.mpr_count = 1; 3300 range.mpr_type = MAC_PROPVAL_UINT32; 3301 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3302 range.range_uint32[0].mpur_max = MAXIMUM_MTU; 3303 /* following MAC type do not support jumbo frames */ 3304 if ((mac->type == e1000_ich8lan) || 3305 ((mac->type == e1000_ich9lan) && (phy->type == 3306 e1000_phy_ife))) { 3307 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3308 } 3309 bcopy(&range, pr_val, sizeof (range)); 3310 break; 3311 } 3312 default: 3313 err = ENOTSUP; 3314 break; 3315 } 3316 return (err); 3317 } 3318 3319 /* ARGSUSED2 */ 3320 static int 3321 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3322 uint_t pr_valsize, const void *pr_val) 3323 { 3324 int err = 0; 3325 long result; 3326 struct e1000_hw *hw = &Adapter->shared; 3327 3328 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3329 if (pr_val == NULL) { 3330 err = EINVAL; 3331 return (err); 3332 } 3333 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3334 if (result < MIN_TX_BCOPY_THRESHOLD || 3335 result > MAX_TX_BCOPY_THRESHOLD) 3336 err = EINVAL; 3337 else { 3338 Adapter->tx_bcopy_thresh = (uint32_t)result; 3339 } 3340 return (err); 3341 } 3342 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3343 if (pr_val == NULL) { 3344 err = EINVAL; 3345 return (err); 3346 } 3347 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3348 if (result < 0 || result > 1) 3349 err = EINVAL; 3350 else { 3351 Adapter->tx_intr_enable = (result == 1) ? 3352 B_TRUE: B_FALSE; 3353 if (Adapter->tx_intr_enable) 3354 e1000g_mask_tx_interrupt(Adapter); 3355 else 3356 e1000g_clear_tx_interrupt(Adapter); 3357 if (e1000g_check_acc_handle( 3358 Adapter->osdep.reg_handle) != DDI_FM_OK) 3359 ddi_fm_service_impact(Adapter->dip, 3360 DDI_SERVICE_DEGRADED); 3361 } 3362 return (err); 3363 } 3364 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3365 if (pr_val == NULL) { 3366 err = EINVAL; 3367 return (err); 3368 } 3369 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3370 if (result < MIN_TX_INTR_DELAY || 3371 result > MAX_TX_INTR_DELAY) 3372 err = EINVAL; 3373 else { 3374 Adapter->tx_intr_delay = (uint32_t)result; 3375 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3376 if (e1000g_check_acc_handle( 3377 Adapter->osdep.reg_handle) != DDI_FM_OK) 3378 ddi_fm_service_impact(Adapter->dip, 3379 DDI_SERVICE_DEGRADED); 3380 } 3381 return (err); 3382 } 3383 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3384 if (pr_val == NULL) { 3385 err = EINVAL; 3386 return (err); 3387 } 3388 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3389 if (result < MIN_TX_INTR_ABS_DELAY || 3390 result > MAX_TX_INTR_ABS_DELAY) 3391 err = EINVAL; 3392 else { 3393 Adapter->tx_intr_abs_delay = (uint32_t)result; 3394 E1000_WRITE_REG(hw, E1000_TADV, 3395 Adapter->tx_intr_abs_delay); 3396 if (e1000g_check_acc_handle( 3397 Adapter->osdep.reg_handle) != DDI_FM_OK) 3398 ddi_fm_service_impact(Adapter->dip, 3399 DDI_SERVICE_DEGRADED); 3400 } 3401 return (err); 3402 } 3403 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3404 if (pr_val == NULL) { 3405 err = EINVAL; 3406 return (err); 3407 } 3408 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3409 if (result < MIN_RX_BCOPY_THRESHOLD || 3410 result > MAX_RX_BCOPY_THRESHOLD) 3411 err = EINVAL; 3412 else 3413 Adapter->rx_bcopy_thresh = (uint32_t)result; 3414 return (err); 3415 } 3416 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3417 if (pr_val == NULL) { 3418 err = EINVAL; 3419 return (err); 3420 } 3421 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3422 if (result < MIN_RX_LIMIT_ON_INTR || 3423 result > MAX_RX_LIMIT_ON_INTR) 3424 err = EINVAL; 3425 else 3426 Adapter->rx_limit_onintr = (uint32_t)result; 3427 return (err); 3428 } 3429 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3430 if (pr_val == NULL) { 3431 err = EINVAL; 3432 return (err); 3433 } 3434 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3435 if (result < MIN_RX_INTR_DELAY || 3436 result > MAX_RX_INTR_DELAY) 3437 err = EINVAL; 3438 else { 3439 Adapter->rx_intr_delay = (uint32_t)result; 3440 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3441 if (e1000g_check_acc_handle( 3442 Adapter->osdep.reg_handle) != DDI_FM_OK) 3443 ddi_fm_service_impact(Adapter->dip, 3444 DDI_SERVICE_DEGRADED); 3445 } 3446 return (err); 3447 } 3448 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3449 if (pr_val == NULL) { 3450 err = EINVAL; 3451 return (err); 3452 } 3453 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3454 if (result < MIN_RX_INTR_ABS_DELAY || 3455 result > MAX_RX_INTR_ABS_DELAY) 3456 err = EINVAL; 3457 else { 3458 Adapter->rx_intr_abs_delay = (uint32_t)result; 3459 E1000_WRITE_REG(hw, E1000_RADV, 3460 Adapter->rx_intr_abs_delay); 3461 if (e1000g_check_acc_handle( 3462 Adapter->osdep.reg_handle) != DDI_FM_OK) 3463 ddi_fm_service_impact(Adapter->dip, 3464 DDI_SERVICE_DEGRADED); 3465 } 3466 return (err); 3467 } 3468 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3469 if (pr_val == NULL) { 3470 err = EINVAL; 3471 return (err); 3472 } 3473 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3474 if (result < MIN_INTR_THROTTLING || 3475 result > MAX_INTR_THROTTLING) 3476 err = EINVAL; 3477 else { 3478 if (hw->mac.type >= e1000_82540) { 3479 Adapter->intr_throttling_rate = 3480 (uint32_t)result; 3481 E1000_WRITE_REG(hw, E1000_ITR, 3482 Adapter->intr_throttling_rate); 3483 if (e1000g_check_acc_handle( 3484 Adapter->osdep.reg_handle) != DDI_FM_OK) 3485 ddi_fm_service_impact(Adapter->dip, 3486 DDI_SERVICE_DEGRADED); 3487 } else 3488 err = EINVAL; 3489 } 3490 return (err); 3491 } 3492 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3493 if (pr_val == NULL) { 3494 err = EINVAL; 3495 return (err); 3496 } 3497 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3498 if (result < 0 || result > 1) 3499 err = EINVAL; 3500 else { 3501 if (hw->mac.type >= e1000_82540) { 3502 Adapter->intr_adaptive = (result == 1) ? 3503 B_TRUE : B_FALSE; 3504 } else { 3505 err = EINVAL; 3506 } 3507 } 3508 return (err); 3509 } 3510 return (ENOTSUP); 3511 } 3512 3513 static int 3514 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3515 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3516 { 3517 int err = ENOTSUP; 3518 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3519 int value; 3520 3521 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3522 *perm = MAC_PROP_PERM_READ; 3523 if (is_default) 3524 goto done; 3525 value = Adapter->param_adv_pause; 3526 err = 0; 3527 goto done; 3528 } 3529 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3530 *perm = MAC_PROP_PERM_READ; 3531 if (is_default) 3532 goto done; 3533 value = Adapter->param_adv_asym_pause; 3534 err = 0; 3535 goto done; 3536 } 3537 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3538 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3539 Adapter->tx_bcopy_thresh); 3540 err = 0; 3541 goto done; 3542 } 3543 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3544 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3545 Adapter->tx_intr_enable); 3546 err = 0; 3547 goto done; 3548 } 3549 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3550 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3551 Adapter->tx_intr_delay); 3552 err = 0; 3553 goto done; 3554 } 3555 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3556 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3557 Adapter->tx_intr_abs_delay); 3558 err = 0; 3559 goto done; 3560 } 3561 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3562 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3563 Adapter->rx_bcopy_thresh); 3564 err = 0; 3565 goto done; 3566 } 3567 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3568 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3569 Adapter->rx_limit_onintr); 3570 err = 0; 3571 goto done; 3572 } 3573 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3574 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3575 Adapter->rx_intr_delay); 3576 err = 0; 3577 goto done; 3578 } 3579 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3580 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3581 Adapter->rx_intr_abs_delay); 3582 err = 0; 3583 goto done; 3584 } 3585 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3586 value = (is_default ? DEFAULT_INTR_THROTTLING : 3587 Adapter->intr_throttling_rate); 3588 err = 0; 3589 goto done; 3590 } 3591 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3592 value = (is_default ? 1 : Adapter->intr_adaptive); 3593 err = 0; 3594 goto done; 3595 } 3596 done: 3597 if (err == 0) { 3598 (void) snprintf(pr_val, pr_valsize, "%d", value); 3599 } 3600 return (err); 3601 } 3602 3603 /* 3604 * e1000g_get_conf - get configurations set in e1000g.conf 3605 * This routine gets user-configured values out of the configuration 3606 * file e1000g.conf. 3607 * 3608 * For each configurable value, there is a minimum, a maximum, and a 3609 * default. 3610 * If user does not configure a value, use the default. 3611 * If user configures below the minimum, use the minumum. 3612 * If user configures above the maximum, use the maxumum. 3613 */ 3614 static void 3615 e1000g_get_conf(struct e1000g *Adapter) 3616 { 3617 struct e1000_hw *hw = &Adapter->shared; 3618 boolean_t tbi_compatibility = B_FALSE; 3619 3620 /* 3621 * get each configurable property from e1000g.conf 3622 */ 3623 3624 /* 3625 * NumTxDescriptors 3626 */ 3627 Adapter->tx_desc_num = 3628 e1000g_get_prop(Adapter, "NumTxDescriptors", 3629 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3630 DEFAULT_NUM_TX_DESCRIPTOR); 3631 3632 /* 3633 * NumRxDescriptors 3634 */ 3635 Adapter->rx_desc_num = 3636 e1000g_get_prop(Adapter, "NumRxDescriptors", 3637 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3638 DEFAULT_NUM_RX_DESCRIPTOR); 3639 3640 /* 3641 * NumRxFreeList 3642 */ 3643 Adapter->rx_freelist_num = 3644 e1000g_get_prop(Adapter, "NumRxFreeList", 3645 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3646 DEFAULT_NUM_RX_FREELIST); 3647 3648 /* 3649 * NumTxPacketList 3650 */ 3651 Adapter->tx_freelist_num = 3652 e1000g_get_prop(Adapter, "NumTxPacketList", 3653 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3654 DEFAULT_NUM_TX_FREELIST); 3655 3656 /* 3657 * FlowControl 3658 */ 3659 hw->fc.send_xon = B_TRUE; 3660 hw->fc.requested_mode = 3661 e1000g_get_prop(Adapter, "FlowControl", 3662 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3663 /* 4 is the setting that says "let the eeprom decide" */ 3664 if (hw->fc.requested_mode == 4) 3665 hw->fc.requested_mode = e1000_fc_default; 3666 3667 /* 3668 * Max Num Receive Packets on Interrupt 3669 */ 3670 Adapter->rx_limit_onintr = 3671 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3672 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3673 DEFAULT_RX_LIMIT_ON_INTR); 3674 3675 /* 3676 * PHY master slave setting 3677 */ 3678 hw->phy.ms_type = 3679 e1000g_get_prop(Adapter, "SetMasterSlave", 3680 e1000_ms_hw_default, e1000_ms_auto, 3681 e1000_ms_hw_default); 3682 3683 /* 3684 * Parameter which controls TBI mode workaround, which is only 3685 * needed on certain switches such as Cisco 6500/Foundry 3686 */ 3687 tbi_compatibility = 3688 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3689 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3690 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3691 3692 /* 3693 * MSI Enable 3694 */ 3695 Adapter->msi_enable = 3696 e1000g_get_prop(Adapter, "MSIEnable", 3697 0, 1, DEFAULT_MSI_ENABLE); 3698 3699 /* 3700 * Interrupt Throttling Rate 3701 */ 3702 Adapter->intr_throttling_rate = 3703 e1000g_get_prop(Adapter, "intr_throttling_rate", 3704 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3705 DEFAULT_INTR_THROTTLING); 3706 3707 /* 3708 * Adaptive Interrupt Blanking Enable/Disable 3709 * It is enabled by default 3710 */ 3711 Adapter->intr_adaptive = 3712 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3713 B_TRUE : B_FALSE; 3714 3715 /* 3716 * Hardware checksum enable/disable parameter 3717 */ 3718 Adapter->tx_hcksum_enable = 3719 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3720 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3721 /* 3722 * Checksum on/off selection via global parameters. 3723 * 3724 * If the chip is flagged as not capable of (correctly) 3725 * handling checksumming, we don't enable it on either 3726 * Rx or Tx side. Otherwise, we take this chip's settings 3727 * from the patchable global defaults. 3728 * 3729 * We advertise our capabilities only if TX offload is 3730 * enabled. On receive, the stack will accept checksummed 3731 * packets anyway, even if we haven't said we can deliver 3732 * them. 3733 */ 3734 switch (hw->mac.type) { 3735 case e1000_82540: 3736 case e1000_82544: 3737 case e1000_82545: 3738 case e1000_82545_rev_3: 3739 case e1000_82546: 3740 case e1000_82546_rev_3: 3741 case e1000_82571: 3742 case e1000_82572: 3743 case e1000_82573: 3744 case e1000_80003es2lan: 3745 break; 3746 /* 3747 * For the following Intel PRO/1000 chipsets, we have not 3748 * tested the hardware checksum offload capability, so we 3749 * disable the capability for them. 3750 * e1000_82542, 3751 * e1000_82543, 3752 * e1000_82541, 3753 * e1000_82541_rev_2, 3754 * e1000_82547, 3755 * e1000_82547_rev_2, 3756 */ 3757 default: 3758 Adapter->tx_hcksum_enable = B_FALSE; 3759 } 3760 3761 /* 3762 * Large Send Offloading(LSO) Enable/Disable 3763 * If the tx hardware checksum is not enabled, LSO should be 3764 * disabled. 3765 */ 3766 Adapter->lso_enable = 3767 e1000g_get_prop(Adapter, "lso_enable", 3768 0, 1, DEFAULT_LSO_ENABLE); 3769 3770 switch (hw->mac.type) { 3771 case e1000_82546: 3772 case e1000_82546_rev_3: 3773 if (Adapter->lso_enable) 3774 Adapter->lso_premature_issue = B_TRUE; 3775 /* FALLTHRU */ 3776 case e1000_82571: 3777 case e1000_82572: 3778 case e1000_82573: 3779 case e1000_80003es2lan: 3780 break; 3781 default: 3782 Adapter->lso_enable = B_FALSE; 3783 } 3784 3785 if (!Adapter->tx_hcksum_enable) { 3786 Adapter->lso_premature_issue = B_FALSE; 3787 Adapter->lso_enable = B_FALSE; 3788 } 3789 3790 /* 3791 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3792 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3793 * will not cross 64k boundary. 3794 */ 3795 Adapter->mem_workaround_82546 = 3796 e1000g_get_prop(Adapter, "mem_workaround_82546", 3797 0, 1, DEFAULT_MEM_WORKAROUND_82546); 3798 3799 /* 3800 * Max number of multicast addresses 3801 */ 3802 Adapter->mcast_max_num = 3803 e1000g_get_prop(Adapter, "mcast_max_num", 3804 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32); 3805 } 3806 3807 /* 3808 * e1000g_get_prop - routine to read properties 3809 * 3810 * Get a user-configure property value out of the configuration 3811 * file e1000g.conf. 3812 * 3813 * Caller provides name of the property, a default value, a minimum 3814 * value, and a maximum value. 3815 * 3816 * Return configured value of the property, with default, minimum and 3817 * maximum properly applied. 3818 */ 3819 static int 3820 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3821 char *propname, /* name of the property */ 3822 int minval, /* minimum acceptable value */ 3823 int maxval, /* maximim acceptable value */ 3824 int defval) /* default value */ 3825 { 3826 int propval; /* value returned for requested property */ 3827 int *props; /* point to array of properties returned */ 3828 uint_t nprops; /* number of property value returned */ 3829 3830 /* 3831 * get the array of properties from the config file 3832 */ 3833 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3834 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3835 /* got some properties, test if we got enough */ 3836 if (Adapter->instance < nprops) { 3837 propval = props[Adapter->instance]; 3838 } else { 3839 /* not enough properties configured */ 3840 propval = defval; 3841 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3842 "Not Enough %s values found in e1000g.conf" 3843 " - set to %d\n", 3844 propname, propval); 3845 } 3846 3847 /* free memory allocated for properties */ 3848 ddi_prop_free(props); 3849 3850 } else { 3851 propval = defval; 3852 } 3853 3854 /* 3855 * enforce limits 3856 */ 3857 if (propval > maxval) { 3858 propval = maxval; 3859 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3860 "Too High %s value in e1000g.conf - set to %d\n", 3861 propname, propval); 3862 } 3863 3864 if (propval < minval) { 3865 propval = minval; 3866 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3867 "Too Low %s value in e1000g.conf - set to %d\n", 3868 propname, propval); 3869 } 3870 3871 return (propval); 3872 } 3873 3874 static boolean_t 3875 e1000g_link_check(struct e1000g *Adapter) 3876 { 3877 uint16_t speed, duplex, phydata; 3878 boolean_t link_changed = B_FALSE; 3879 struct e1000_hw *hw; 3880 uint32_t reg_tarc; 3881 3882 hw = &Adapter->shared; 3883 3884 if (e1000g_link_up(Adapter)) { 3885 /* 3886 * The Link is up, check whether it was marked as down earlier 3887 */ 3888 if (Adapter->link_state != LINK_STATE_UP) { 3889 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3890 Adapter->link_speed = speed; 3891 Adapter->link_duplex = duplex; 3892 Adapter->link_state = LINK_STATE_UP; 3893 link_changed = B_TRUE; 3894 3895 if (Adapter->link_speed == SPEED_1000) 3896 Adapter->stall_threshold = TX_STALL_TIME_2S; 3897 else 3898 Adapter->stall_threshold = TX_STALL_TIME_8S; 3899 3900 Adapter->tx_link_down_timeout = 0; 3901 3902 if ((hw->mac.type == e1000_82571) || 3903 (hw->mac.type == e1000_82572)) { 3904 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3905 if (speed == SPEED_1000) 3906 reg_tarc |= (1 << 21); 3907 else 3908 reg_tarc &= ~(1 << 21); 3909 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3910 } 3911 } 3912 Adapter->smartspeed = 0; 3913 } else { 3914 if (Adapter->link_state != LINK_STATE_DOWN) { 3915 Adapter->link_speed = 0; 3916 Adapter->link_duplex = 0; 3917 Adapter->link_state = LINK_STATE_DOWN; 3918 link_changed = B_TRUE; 3919 3920 /* 3921 * SmartSpeed workaround for Tabor/TanaX, When the 3922 * driver loses link disable auto master/slave 3923 * resolution. 3924 */ 3925 if (hw->phy.type == e1000_phy_igp) { 3926 (void) e1000_read_phy_reg(hw, 3927 PHY_1000T_CTRL, &phydata); 3928 phydata |= CR_1000T_MS_ENABLE; 3929 (void) e1000_write_phy_reg(hw, 3930 PHY_1000T_CTRL, phydata); 3931 } 3932 } else { 3933 e1000g_smartspeed(Adapter); 3934 } 3935 3936 if (Adapter->e1000g_state & E1000G_STARTED) { 3937 if (Adapter->tx_link_down_timeout < 3938 MAX_TX_LINK_DOWN_TIMEOUT) { 3939 Adapter->tx_link_down_timeout++; 3940 } else if (Adapter->tx_link_down_timeout == 3941 MAX_TX_LINK_DOWN_TIMEOUT) { 3942 e1000g_tx_clean(Adapter); 3943 Adapter->tx_link_down_timeout++; 3944 } 3945 } 3946 } 3947 3948 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3949 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3950 3951 return (link_changed); 3952 } 3953 3954 /* 3955 * e1000g_reset_link - Using the link properties to setup the link 3956 */ 3957 int 3958 e1000g_reset_link(struct e1000g *Adapter) 3959 { 3960 struct e1000_mac_info *mac; 3961 struct e1000_phy_info *phy; 3962 struct e1000_hw *hw; 3963 boolean_t invalid; 3964 3965 mac = &Adapter->shared.mac; 3966 phy = &Adapter->shared.phy; 3967 hw = &Adapter->shared; 3968 invalid = B_FALSE; 3969 3970 if (hw->phy.media_type != e1000_media_type_copper) 3971 goto out; 3972 3973 if (Adapter->param_adv_autoneg == 1) { 3974 mac->autoneg = B_TRUE; 3975 phy->autoneg_advertised = 0; 3976 3977 /* 3978 * 1000hdx is not supported for autonegotiation 3979 */ 3980 if (Adapter->param_adv_1000fdx == 1) 3981 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3982 3983 if (Adapter->param_adv_100fdx == 1) 3984 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3985 3986 if (Adapter->param_adv_100hdx == 1) 3987 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3988 3989 if (Adapter->param_adv_10fdx == 1) 3990 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3991 3992 if (Adapter->param_adv_10hdx == 1) 3993 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3994 3995 if (phy->autoneg_advertised == 0) 3996 invalid = B_TRUE; 3997 } else { 3998 mac->autoneg = B_FALSE; 3999 4000 /* 4001 * For Intel copper cards, 1000fdx and 1000hdx are not 4002 * supported for forced link 4003 */ 4004 if (Adapter->param_adv_100fdx == 1) 4005 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4006 else if (Adapter->param_adv_100hdx == 1) 4007 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4008 else if (Adapter->param_adv_10fdx == 1) 4009 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4010 else if (Adapter->param_adv_10hdx == 1) 4011 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4012 else 4013 invalid = B_TRUE; 4014 4015 } 4016 4017 if (invalid) { 4018 e1000g_log(Adapter, CE_WARN, 4019 "Invalid link sets. Setup link to" 4020 "support autonegotiation with all link capabilities."); 4021 mac->autoneg = B_TRUE; 4022 phy->autoneg_advertised = ADVERTISE_1000_FULL | 4023 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 4024 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 4025 } 4026 4027 out: 4028 return (e1000_setup_link(&Adapter->shared)); 4029 } 4030 4031 static void 4032 e1000g_timer_tx_resched(struct e1000g *Adapter) 4033 { 4034 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4035 4036 rw_enter(&Adapter->chip_lock, RW_READER); 4037 4038 if (tx_ring->resched_needed && 4039 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4040 drv_usectohz(1000000)) && 4041 (Adapter->e1000g_state & E1000G_STARTED) && 4042 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4043 tx_ring->resched_needed = B_FALSE; 4044 mac_tx_update(Adapter->mh); 4045 E1000G_STAT(tx_ring->stat_reschedule); 4046 E1000G_STAT(tx_ring->stat_timer_reschedule); 4047 } 4048 4049 rw_exit(&Adapter->chip_lock); 4050 } 4051 4052 static void 4053 e1000g_local_timer(void *ws) 4054 { 4055 struct e1000g *Adapter = (struct e1000g *)ws; 4056 struct e1000_hw *hw; 4057 e1000g_ether_addr_t ether_addr; 4058 boolean_t link_changed; 4059 4060 hw = &Adapter->shared; 4061 4062 if (Adapter->e1000g_state & E1000G_ERROR) { 4063 rw_enter(&Adapter->chip_lock, RW_WRITER); 4064 Adapter->e1000g_state &= ~E1000G_ERROR; 4065 rw_exit(&Adapter->chip_lock); 4066 4067 Adapter->reset_count++; 4068 if (e1000g_global_reset(Adapter)) { 4069 ddi_fm_service_impact(Adapter->dip, 4070 DDI_SERVICE_RESTORED); 4071 e1000g_timer_tx_resched(Adapter); 4072 } else 4073 ddi_fm_service_impact(Adapter->dip, 4074 DDI_SERVICE_LOST); 4075 return; 4076 } 4077 4078 if (e1000g_stall_check(Adapter)) { 4079 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4080 "Tx stall detected. Activate automatic recovery.\n"); 4081 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4082 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4083 Adapter->reset_count++; 4084 if (e1000g_reset_adapter(Adapter)) { 4085 ddi_fm_service_impact(Adapter->dip, 4086 DDI_SERVICE_RESTORED); 4087 e1000g_timer_tx_resched(Adapter); 4088 } 4089 return; 4090 } 4091 4092 link_changed = B_FALSE; 4093 rw_enter(&Adapter->chip_lock, RW_READER); 4094 if (Adapter->link_complete) 4095 link_changed = e1000g_link_check(Adapter); 4096 rw_exit(&Adapter->chip_lock); 4097 4098 if (link_changed) { 4099 if (!Adapter->reset_flag) 4100 mac_link_update(Adapter->mh, Adapter->link_state); 4101 if (Adapter->link_state == LINK_STATE_UP) 4102 Adapter->reset_flag = B_FALSE; 4103 } 4104 /* 4105 * Workaround for esb2. Data stuck in fifo on a link 4106 * down event. Reset the adapter to recover it. 4107 */ 4108 if (Adapter->esb2_workaround) { 4109 Adapter->esb2_workaround = B_FALSE; 4110 (void) e1000g_reset_adapter(Adapter); 4111 return; 4112 } 4113 4114 /* 4115 * With 82571 controllers, any locally administered address will 4116 * be overwritten when there is a reset on the other port. 4117 * Detect this circumstance and correct it. 4118 */ 4119 if ((hw->mac.type == e1000_82571) && 4120 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4121 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4122 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4123 4124 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4125 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4126 4127 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4128 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4129 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4130 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4131 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4132 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4133 e1000_rar_set(hw, hw->mac.addr, 0); 4134 } 4135 } 4136 4137 /* 4138 * Long TTL workaround for 82541/82547 4139 */ 4140 (void) e1000_igp_ttl_workaround_82547(hw); 4141 4142 /* 4143 * Check for Adaptive IFS settings If there are lots of collisions 4144 * change the value in steps... 4145 * These properties should only be set for 10/100 4146 */ 4147 if ((hw->phy.media_type == e1000_media_type_copper) && 4148 ((Adapter->link_speed == SPEED_100) || 4149 (Adapter->link_speed == SPEED_10))) { 4150 e1000_update_adaptive(hw); 4151 } 4152 /* 4153 * Set Timer Interrupts 4154 */ 4155 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4156 4157 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4158 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4159 else 4160 e1000g_timer_tx_resched(Adapter); 4161 4162 restart_watchdog_timer(Adapter); 4163 } 4164 4165 /* 4166 * The function e1000g_link_timer() is called when the timer for link setup 4167 * is expired, which indicates the completion of the link setup. The link 4168 * state will not be updated until the link setup is completed. And the 4169 * link state will not be sent to the upper layer through mac_link_update() 4170 * in this function. It will be updated in the local timer routine or the 4171 * interrupt service routine after the interface is started (plumbed). 4172 */ 4173 static void 4174 e1000g_link_timer(void *arg) 4175 { 4176 struct e1000g *Adapter = (struct e1000g *)arg; 4177 4178 mutex_enter(&Adapter->link_lock); 4179 Adapter->link_complete = B_TRUE; 4180 Adapter->link_tid = 0; 4181 mutex_exit(&Adapter->link_lock); 4182 } 4183 4184 /* 4185 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4186 * 4187 * This function read the forced speed and duplex for 10/100 Mbps speeds 4188 * and also for 1000 Mbps speeds from the e1000g.conf file 4189 */ 4190 static void 4191 e1000g_force_speed_duplex(struct e1000g *Adapter) 4192 { 4193 int forced; 4194 struct e1000_mac_info *mac = &Adapter->shared.mac; 4195 struct e1000_phy_info *phy = &Adapter->shared.phy; 4196 4197 /* 4198 * get value out of config file 4199 */ 4200 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4201 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 4202 4203 switch (forced) { 4204 case GDIAG_10_HALF: 4205 /* 4206 * Disable Auto Negotiation 4207 */ 4208 mac->autoneg = B_FALSE; 4209 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4210 break; 4211 case GDIAG_10_FULL: 4212 /* 4213 * Disable Auto Negotiation 4214 */ 4215 mac->autoneg = B_FALSE; 4216 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4217 break; 4218 case GDIAG_100_HALF: 4219 /* 4220 * Disable Auto Negotiation 4221 */ 4222 mac->autoneg = B_FALSE; 4223 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4224 break; 4225 case GDIAG_100_FULL: 4226 /* 4227 * Disable Auto Negotiation 4228 */ 4229 mac->autoneg = B_FALSE; 4230 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4231 break; 4232 case GDIAG_1000_FULL: 4233 /* 4234 * The gigabit spec requires autonegotiation. Therefore, 4235 * when the user wants to force the speed to 1000Mbps, we 4236 * enable AutoNeg, but only allow the harware to advertise 4237 * 1000Mbps. This is different from 10/100 operation, where 4238 * we are allowed to link without any negotiation. 4239 */ 4240 mac->autoneg = B_TRUE; 4241 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4242 break; 4243 default: /* obey the setting of AutoNegAdvertised */ 4244 mac->autoneg = B_TRUE; 4245 phy->autoneg_advertised = 4246 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 4247 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4248 AUTONEG_ADVERTISE_SPEED_DEFAULT); 4249 break; 4250 } /* switch */ 4251 } 4252 4253 /* 4254 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4255 * 4256 * This function reads MaxFrameSize from e1000g.conf 4257 */ 4258 static void 4259 e1000g_get_max_frame_size(struct e1000g *Adapter) 4260 { 4261 int max_frame; 4262 struct e1000_mac_info *mac = &Adapter->shared.mac; 4263 struct e1000_phy_info *phy = &Adapter->shared.phy; 4264 4265 /* 4266 * get value out of config file 4267 */ 4268 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 4269 4270 switch (max_frame) { 4271 case 0: 4272 Adapter->default_mtu = ETHERMTU; 4273 break; 4274 /* 4275 * To avoid excessive memory allocation for rx buffers, 4276 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4277 */ 4278 case 1: 4279 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4280 sizeof (struct ether_vlan_header) - ETHERFCSL - 4281 E1000G_IPALIGNPRESERVEROOM; 4282 break; 4283 case 2: 4284 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4285 sizeof (struct ether_vlan_header) - ETHERFCSL - 4286 E1000G_IPALIGNPRESERVEROOM; 4287 break; 4288 case 3: 4289 if (mac->type >= e1000_82571) 4290 Adapter->default_mtu = MAXIMUM_MTU; 4291 else 4292 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4293 sizeof (struct ether_vlan_header) - ETHERFCSL - 4294 E1000G_IPALIGNPRESERVEROOM; 4295 break; 4296 default: 4297 Adapter->default_mtu = ETHERMTU; 4298 break; 4299 } /* switch */ 4300 4301 Adapter->max_frame_size = Adapter->default_mtu + 4302 sizeof (struct ether_vlan_header) + ETHERFCSL; 4303 4304 /* ich8 does not do jumbo frames */ 4305 if (mac->type == e1000_ich8lan) { 4306 Adapter->default_mtu = ETHERMTU; 4307 Adapter->max_frame_size = ETHERMTU + 4308 sizeof (struct ether_vlan_header) + ETHERFCSL; 4309 } 4310 4311 /* ich9 does not do jumbo frames on one phy type */ 4312 if ((mac->type == e1000_ich9lan) && 4313 (phy->type == e1000_phy_ife)) { 4314 Adapter->default_mtu = ETHERMTU; 4315 Adapter->max_frame_size = ETHERMTU + 4316 sizeof (struct ether_vlan_header) + ETHERFCSL; 4317 } 4318 } 4319 4320 static void 4321 arm_watchdog_timer(struct e1000g *Adapter) 4322 { 4323 Adapter->watchdog_tid = 4324 timeout(e1000g_local_timer, 4325 (void *)Adapter, 1 * drv_usectohz(1000000)); 4326 } 4327 #pragma inline(arm_watchdog_timer) 4328 4329 static void 4330 enable_watchdog_timer(struct e1000g *Adapter) 4331 { 4332 mutex_enter(&Adapter->watchdog_lock); 4333 4334 if (!Adapter->watchdog_timer_enabled) { 4335 Adapter->watchdog_timer_enabled = B_TRUE; 4336 Adapter->watchdog_timer_started = B_TRUE; 4337 arm_watchdog_timer(Adapter); 4338 } 4339 4340 mutex_exit(&Adapter->watchdog_lock); 4341 } 4342 4343 static void 4344 disable_watchdog_timer(struct e1000g *Adapter) 4345 { 4346 timeout_id_t tid; 4347 4348 mutex_enter(&Adapter->watchdog_lock); 4349 4350 Adapter->watchdog_timer_enabled = B_FALSE; 4351 Adapter->watchdog_timer_started = B_FALSE; 4352 tid = Adapter->watchdog_tid; 4353 Adapter->watchdog_tid = 0; 4354 4355 mutex_exit(&Adapter->watchdog_lock); 4356 4357 if (tid != 0) 4358 (void) untimeout(tid); 4359 } 4360 4361 static void 4362 start_watchdog_timer(struct e1000g *Adapter) 4363 { 4364 mutex_enter(&Adapter->watchdog_lock); 4365 4366 if (Adapter->watchdog_timer_enabled) { 4367 if (!Adapter->watchdog_timer_started) { 4368 Adapter->watchdog_timer_started = B_TRUE; 4369 arm_watchdog_timer(Adapter); 4370 } 4371 } 4372 4373 mutex_exit(&Adapter->watchdog_lock); 4374 } 4375 4376 static void 4377 restart_watchdog_timer(struct e1000g *Adapter) 4378 { 4379 mutex_enter(&Adapter->watchdog_lock); 4380 4381 if (Adapter->watchdog_timer_started) 4382 arm_watchdog_timer(Adapter); 4383 4384 mutex_exit(&Adapter->watchdog_lock); 4385 } 4386 4387 static void 4388 stop_watchdog_timer(struct e1000g *Adapter) 4389 { 4390 timeout_id_t tid; 4391 4392 mutex_enter(&Adapter->watchdog_lock); 4393 4394 Adapter->watchdog_timer_started = B_FALSE; 4395 tid = Adapter->watchdog_tid; 4396 Adapter->watchdog_tid = 0; 4397 4398 mutex_exit(&Adapter->watchdog_lock); 4399 4400 if (tid != 0) 4401 (void) untimeout(tid); 4402 } 4403 4404 static void 4405 stop_link_timer(struct e1000g *Adapter) 4406 { 4407 timeout_id_t tid; 4408 4409 /* Disable the link timer */ 4410 mutex_enter(&Adapter->link_lock); 4411 4412 tid = Adapter->link_tid; 4413 Adapter->link_tid = 0; 4414 4415 mutex_exit(&Adapter->link_lock); 4416 4417 if (tid != 0) 4418 (void) untimeout(tid); 4419 } 4420 4421 static void 4422 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4423 { 4424 timeout_id_t tid; 4425 4426 /* Disable the tx timer for 82547 chipset */ 4427 mutex_enter(&tx_ring->tx_lock); 4428 4429 tx_ring->timer_enable_82547 = B_FALSE; 4430 tid = tx_ring->timer_id_82547; 4431 tx_ring->timer_id_82547 = 0; 4432 4433 mutex_exit(&tx_ring->tx_lock); 4434 4435 if (tid != 0) 4436 (void) untimeout(tid); 4437 } 4438 4439 void 4440 e1000g_clear_interrupt(struct e1000g *Adapter) 4441 { 4442 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4443 0xffffffff & ~E1000_IMS_RXSEQ); 4444 } 4445 4446 void 4447 e1000g_mask_interrupt(struct e1000g *Adapter) 4448 { 4449 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4450 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4451 4452 if (Adapter->tx_intr_enable) 4453 e1000g_mask_tx_interrupt(Adapter); 4454 } 4455 4456 /* 4457 * This routine is called by e1000g_quiesce(), therefore must not block. 4458 */ 4459 void 4460 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4461 { 4462 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4463 } 4464 4465 void 4466 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4467 { 4468 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4469 } 4470 4471 void 4472 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4473 { 4474 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4475 } 4476 4477 static void 4478 e1000g_smartspeed(struct e1000g *Adapter) 4479 { 4480 struct e1000_hw *hw = &Adapter->shared; 4481 uint16_t phy_status; 4482 uint16_t phy_ctrl; 4483 4484 /* 4485 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4486 * advertising 1000Full, we don't even use the workaround 4487 */ 4488 if ((hw->phy.type != e1000_phy_igp) || 4489 !hw->mac.autoneg || 4490 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4491 return; 4492 4493 /* 4494 * True if this is the first call of this function or after every 4495 * 30 seconds of not having link 4496 */ 4497 if (Adapter->smartspeed == 0) { 4498 /* 4499 * If Master/Slave config fault is asserted twice, we 4500 * assume back-to-back 4501 */ 4502 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4503 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4504 return; 4505 4506 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4507 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4508 return; 4509 /* 4510 * We're assuming back-2-back because our status register 4511 * insists! there's a fault in the master/slave 4512 * relationship that was "negotiated" 4513 */ 4514 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4515 /* 4516 * Is the phy configured for manual configuration of 4517 * master/slave? 4518 */ 4519 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4520 /* 4521 * Yes. Then disable manual configuration (enable 4522 * auto configuration) of master/slave 4523 */ 4524 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4525 (void) e1000_write_phy_reg(hw, 4526 PHY_1000T_CTRL, phy_ctrl); 4527 /* 4528 * Effectively starting the clock 4529 */ 4530 Adapter->smartspeed++; 4531 /* 4532 * Restart autonegotiation 4533 */ 4534 if (!e1000_phy_setup_autoneg(hw) && 4535 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4536 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4537 MII_CR_RESTART_AUTO_NEG); 4538 (void) e1000_write_phy_reg(hw, 4539 PHY_CONTROL, phy_ctrl); 4540 } 4541 } 4542 return; 4543 /* 4544 * Has 6 seconds transpired still without link? Remember, 4545 * you should reset the smartspeed counter once you obtain 4546 * link 4547 */ 4548 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4549 /* 4550 * Yes. Remember, we did at the start determine that 4551 * there's a master/slave configuration fault, so we're 4552 * still assuming there's someone on the other end, but we 4553 * just haven't yet been able to talk to it. We then 4554 * re-enable auto configuration of master/slave to see if 4555 * we're running 2/3 pair cables. 4556 */ 4557 /* 4558 * If still no link, perhaps using 2/3 pair cable 4559 */ 4560 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4561 phy_ctrl |= CR_1000T_MS_ENABLE; 4562 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4563 /* 4564 * Restart autoneg with phy enabled for manual 4565 * configuration of master/slave 4566 */ 4567 if (!e1000_phy_setup_autoneg(hw) && 4568 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4569 phy_ctrl |= 4570 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4571 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4572 } 4573 /* 4574 * Hopefully, there are no more faults and we've obtained 4575 * link as a result. 4576 */ 4577 } 4578 /* 4579 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4580 * seconds) 4581 */ 4582 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4583 Adapter->smartspeed = 0; 4584 } 4585 4586 static boolean_t 4587 is_valid_mac_addr(uint8_t *mac_addr) 4588 { 4589 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4590 const uint8_t addr_test2[6] = 4591 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4592 4593 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4594 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4595 return (B_FALSE); 4596 4597 return (B_TRUE); 4598 } 4599 4600 /* 4601 * e1000g_stall_check - check for tx stall 4602 * 4603 * This function checks if the adapter is stalled (in transmit). 4604 * 4605 * It is called each time the watchdog timeout is invoked. 4606 * If the transmit descriptor reclaim continuously fails, 4607 * the watchdog value will increment by 1. If the watchdog 4608 * value exceeds the threshold, the adapter is assumed to 4609 * have stalled and need to be reset. 4610 */ 4611 static boolean_t 4612 e1000g_stall_check(struct e1000g *Adapter) 4613 { 4614 e1000g_tx_ring_t *tx_ring; 4615 4616 tx_ring = Adapter->tx_ring; 4617 4618 if (Adapter->link_state != LINK_STATE_UP) 4619 return (B_FALSE); 4620 4621 (void) e1000g_recycle(tx_ring); 4622 4623 if (Adapter->stall_flag) { 4624 Adapter->stall_flag = B_FALSE; 4625 Adapter->reset_flag = B_TRUE; 4626 return (B_TRUE); 4627 } 4628 4629 return (B_FALSE); 4630 } 4631 4632 #ifdef E1000G_DEBUG 4633 static enum ioc_reply 4634 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4635 { 4636 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4637 e1000g_peekpoke_t *ppd; 4638 uint64_t mem_va; 4639 uint64_t maxoff; 4640 boolean_t peek; 4641 4642 switch (iocp->ioc_cmd) { 4643 4644 case E1000G_IOC_REG_PEEK: 4645 peek = B_TRUE; 4646 break; 4647 4648 case E1000G_IOC_REG_POKE: 4649 peek = B_FALSE; 4650 break; 4651 4652 deault: 4653 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4654 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4655 iocp->ioc_cmd); 4656 return (IOC_INVAL); 4657 } 4658 4659 /* 4660 * Validate format of ioctl 4661 */ 4662 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4663 return (IOC_INVAL); 4664 if (mp->b_cont == NULL) 4665 return (IOC_INVAL); 4666 4667 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4668 4669 /* 4670 * Validate request parameters 4671 */ 4672 switch (ppd->pp_acc_space) { 4673 4674 default: 4675 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4676 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4677 ppd->pp_acc_space); 4678 return (IOC_INVAL); 4679 4680 case E1000G_PP_SPACE_REG: 4681 /* 4682 * Memory-mapped I/O space 4683 */ 4684 ASSERT(ppd->pp_acc_size == 4); 4685 if (ppd->pp_acc_size != 4) 4686 return (IOC_INVAL); 4687 4688 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4689 return (IOC_INVAL); 4690 4691 mem_va = 0; 4692 maxoff = 0x10000; 4693 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4694 break; 4695 4696 case E1000G_PP_SPACE_E1000G: 4697 /* 4698 * E1000g data structure! 4699 */ 4700 mem_va = (uintptr_t)e1000gp; 4701 maxoff = sizeof (struct e1000g); 4702 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4703 break; 4704 4705 } 4706 4707 if (ppd->pp_acc_offset >= maxoff) 4708 return (IOC_INVAL); 4709 4710 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4711 return (IOC_INVAL); 4712 4713 /* 4714 * All OK - go! 4715 */ 4716 ppd->pp_acc_offset += mem_va; 4717 (*ppfn)(e1000gp, ppd); 4718 return (peek ? IOC_REPLY : IOC_ACK); 4719 } 4720 4721 static void 4722 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4723 { 4724 ddi_acc_handle_t handle; 4725 uint32_t *regaddr; 4726 4727 handle = e1000gp->osdep.reg_handle; 4728 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4729 (uintptr_t)ppd->pp_acc_offset); 4730 4731 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4732 } 4733 4734 static void 4735 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4736 { 4737 ddi_acc_handle_t handle; 4738 uint32_t *regaddr; 4739 uint32_t value; 4740 4741 handle = e1000gp->osdep.reg_handle; 4742 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4743 (uintptr_t)ppd->pp_acc_offset); 4744 value = (uint32_t)ppd->pp_acc_data; 4745 4746 ddi_put32(handle, regaddr, value); 4747 } 4748 4749 static void 4750 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4751 { 4752 uint64_t value; 4753 void *vaddr; 4754 4755 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4756 4757 switch (ppd->pp_acc_size) { 4758 case 1: 4759 value = *(uint8_t *)vaddr; 4760 break; 4761 4762 case 2: 4763 value = *(uint16_t *)vaddr; 4764 break; 4765 4766 case 4: 4767 value = *(uint32_t *)vaddr; 4768 break; 4769 4770 case 8: 4771 value = *(uint64_t *)vaddr; 4772 break; 4773 } 4774 4775 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4776 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4777 (void *)e1000gp, (void *)ppd, value, vaddr); 4778 4779 ppd->pp_acc_data = value; 4780 } 4781 4782 static void 4783 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4784 { 4785 uint64_t value; 4786 void *vaddr; 4787 4788 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4789 value = ppd->pp_acc_data; 4790 4791 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4792 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4793 (void *)e1000gp, (void *)ppd, value, vaddr); 4794 4795 switch (ppd->pp_acc_size) { 4796 case 1: 4797 *(uint8_t *)vaddr = (uint8_t)value; 4798 break; 4799 4800 case 2: 4801 *(uint16_t *)vaddr = (uint16_t)value; 4802 break; 4803 4804 case 4: 4805 *(uint32_t *)vaddr = (uint32_t)value; 4806 break; 4807 4808 case 8: 4809 *(uint64_t *)vaddr = (uint64_t)value; 4810 break; 4811 } 4812 } 4813 #endif 4814 4815 /* 4816 * Loopback Support 4817 */ 4818 static lb_property_t lb_normal = 4819 { normal, "normal", E1000G_LB_NONE }; 4820 static lb_property_t lb_external1000 = 4821 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4822 static lb_property_t lb_external100 = 4823 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4824 static lb_property_t lb_external10 = 4825 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4826 static lb_property_t lb_phy = 4827 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4828 4829 static enum ioc_reply 4830 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4831 { 4832 lb_info_sz_t *lbsp; 4833 lb_property_t *lbpp; 4834 struct e1000_hw *hw; 4835 uint32_t *lbmp; 4836 uint32_t size; 4837 uint32_t value; 4838 4839 hw = &Adapter->shared; 4840 4841 if (mp->b_cont == NULL) 4842 return (IOC_INVAL); 4843 4844 if (!e1000g_check_loopback_support(hw)) { 4845 e1000g_log(NULL, CE_WARN, 4846 "Loopback is not supported on e1000g%d", Adapter->instance); 4847 return (IOC_INVAL); 4848 } 4849 4850 switch (iocp->ioc_cmd) { 4851 default: 4852 return (IOC_INVAL); 4853 4854 case LB_GET_INFO_SIZE: 4855 size = sizeof (lb_info_sz_t); 4856 if (iocp->ioc_count != size) 4857 return (IOC_INVAL); 4858 4859 rw_enter(&Adapter->chip_lock, RW_WRITER); 4860 e1000g_get_phy_state(Adapter); 4861 4862 /* 4863 * Workaround for hardware faults. In order to get a stable 4864 * state of phy, we will wait for a specific interval and 4865 * try again. The time delay is an experiential value based 4866 * on our testing. 4867 */ 4868 msec_delay(100); 4869 e1000g_get_phy_state(Adapter); 4870 rw_exit(&Adapter->chip_lock); 4871 4872 value = sizeof (lb_normal); 4873 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4874 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4875 (hw->phy.media_type == e1000_media_type_fiber) || 4876 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4877 value += sizeof (lb_phy); 4878 switch (hw->mac.type) { 4879 case e1000_82571: 4880 case e1000_82572: 4881 case e1000_80003es2lan: 4882 value += sizeof (lb_external1000); 4883 break; 4884 } 4885 } 4886 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4887 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4888 value += sizeof (lb_external100); 4889 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4890 value += sizeof (lb_external10); 4891 4892 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4893 *lbsp = value; 4894 break; 4895 4896 case LB_GET_INFO: 4897 value = sizeof (lb_normal); 4898 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4899 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4900 (hw->phy.media_type == e1000_media_type_fiber) || 4901 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4902 value += sizeof (lb_phy); 4903 switch (hw->mac.type) { 4904 case e1000_82571: 4905 case e1000_82572: 4906 case e1000_80003es2lan: 4907 value += sizeof (lb_external1000); 4908 break; 4909 } 4910 } 4911 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4912 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4913 value += sizeof (lb_external100); 4914 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4915 value += sizeof (lb_external10); 4916 4917 size = value; 4918 if (iocp->ioc_count != size) 4919 return (IOC_INVAL); 4920 4921 value = 0; 4922 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4923 lbpp[value++] = lb_normal; 4924 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4925 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4926 (hw->phy.media_type == e1000_media_type_fiber) || 4927 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4928 lbpp[value++] = lb_phy; 4929 switch (hw->mac.type) { 4930 case e1000_82571: 4931 case e1000_82572: 4932 case e1000_80003es2lan: 4933 lbpp[value++] = lb_external1000; 4934 break; 4935 } 4936 } 4937 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4938 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4939 lbpp[value++] = lb_external100; 4940 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4941 lbpp[value++] = lb_external10; 4942 break; 4943 4944 case LB_GET_MODE: 4945 size = sizeof (uint32_t); 4946 if (iocp->ioc_count != size) 4947 return (IOC_INVAL); 4948 4949 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4950 *lbmp = Adapter->loopback_mode; 4951 break; 4952 4953 case LB_SET_MODE: 4954 size = 0; 4955 if (iocp->ioc_count != sizeof (uint32_t)) 4956 return (IOC_INVAL); 4957 4958 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4959 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4960 return (IOC_INVAL); 4961 break; 4962 } 4963 4964 iocp->ioc_count = size; 4965 iocp->ioc_error = 0; 4966 4967 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4968 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4969 return (IOC_INVAL); 4970 } 4971 4972 return (IOC_REPLY); 4973 } 4974 4975 static boolean_t 4976 e1000g_check_loopback_support(struct e1000_hw *hw) 4977 { 4978 switch (hw->mac.type) { 4979 case e1000_82540: 4980 case e1000_82545: 4981 case e1000_82545_rev_3: 4982 case e1000_82546: 4983 case e1000_82546_rev_3: 4984 case e1000_82541: 4985 case e1000_82541_rev_2: 4986 case e1000_82547: 4987 case e1000_82547_rev_2: 4988 case e1000_82571: 4989 case e1000_82572: 4990 case e1000_82573: 4991 case e1000_82574: 4992 case e1000_80003es2lan: 4993 case e1000_ich9lan: 4994 case e1000_ich10lan: 4995 return (B_TRUE); 4996 } 4997 return (B_FALSE); 4998 } 4999 5000 static boolean_t 5001 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5002 { 5003 struct e1000_hw *hw; 5004 int i, times; 5005 boolean_t link_up; 5006 5007 if (mode == Adapter->loopback_mode) 5008 return (B_TRUE); 5009 5010 hw = &Adapter->shared; 5011 times = 0; 5012 5013 Adapter->loopback_mode = mode; 5014 5015 if (mode == E1000G_LB_NONE) { 5016 /* Reset the chip */ 5017 hw->phy.autoneg_wait_to_complete = B_TRUE; 5018 (void) e1000g_reset_adapter(Adapter); 5019 hw->phy.autoneg_wait_to_complete = B_FALSE; 5020 return (B_TRUE); 5021 } 5022 5023 again: 5024 5025 rw_enter(&Adapter->chip_lock, RW_WRITER); 5026 5027 switch (mode) { 5028 default: 5029 rw_exit(&Adapter->chip_lock); 5030 return (B_FALSE); 5031 5032 case E1000G_LB_EXTERNAL_1000: 5033 e1000g_set_external_loopback_1000(Adapter); 5034 break; 5035 5036 case E1000G_LB_EXTERNAL_100: 5037 e1000g_set_external_loopback_100(Adapter); 5038 break; 5039 5040 case E1000G_LB_EXTERNAL_10: 5041 e1000g_set_external_loopback_10(Adapter); 5042 break; 5043 5044 case E1000G_LB_INTERNAL_PHY: 5045 e1000g_set_internal_loopback(Adapter); 5046 break; 5047 } 5048 5049 times++; 5050 5051 rw_exit(&Adapter->chip_lock); 5052 5053 /* Wait for link up */ 5054 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5055 msec_delay(100); 5056 5057 rw_enter(&Adapter->chip_lock, RW_WRITER); 5058 5059 link_up = e1000g_link_up(Adapter); 5060 5061 rw_exit(&Adapter->chip_lock); 5062 5063 if (!link_up) { 5064 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5065 "Failed to get the link up"); 5066 if (times < 2) { 5067 /* Reset the link */ 5068 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5069 "Reset the link ..."); 5070 (void) e1000g_reset_adapter(Adapter); 5071 goto again; 5072 } 5073 } 5074 5075 return (B_TRUE); 5076 } 5077 5078 /* 5079 * The following loopback settings are from Intel's technical 5080 * document - "How To Loopback". All the register settings and 5081 * time delay values are directly inherited from the document 5082 * without more explanations available. 5083 */ 5084 static void 5085 e1000g_set_internal_loopback(struct e1000g *Adapter) 5086 { 5087 struct e1000_hw *hw; 5088 uint32_t ctrl; 5089 uint32_t status; 5090 uint16_t phy_ctrl; 5091 uint16_t phy_reg; 5092 uint32_t txcw; 5093 5094 hw = &Adapter->shared; 5095 5096 /* Disable Smart Power Down */ 5097 phy_spd_state(hw, B_FALSE); 5098 5099 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5100 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5101 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5102 5103 switch (hw->mac.type) { 5104 case e1000_82540: 5105 case e1000_82545: 5106 case e1000_82545_rev_3: 5107 case e1000_82546: 5108 case e1000_82546_rev_3: 5109 case e1000_82573: 5110 /* Auto-MDI/MDIX off */ 5111 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5112 /* Reset PHY to update Auto-MDI/MDIX */ 5113 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5114 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5115 /* Reset PHY to auto-neg off and force 1000 */ 5116 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5117 phy_ctrl | MII_CR_RESET); 5118 /* 5119 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5120 * See comments above e1000g_set_internal_loopback() for the 5121 * background. 5122 */ 5123 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5124 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5125 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5126 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5127 break; 5128 case e1000_80003es2lan: 5129 /* Force Link Up */ 5130 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5131 0x1CC); 5132 /* Sets PCS loopback at 1Gbs */ 5133 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5134 0x1046); 5135 break; 5136 } 5137 5138 /* 5139 * The following registers should be set for e1000_phy_bm phy type. 5140 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5141 * For others, we do not need to set these registers. 5142 */ 5143 if (hw->phy.type == e1000_phy_bm) { 5144 /* Set Default MAC Interface speed to 1GB */ 5145 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5146 phy_reg &= ~0x0007; 5147 phy_reg |= 0x006; 5148 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5149 /* Assert SW reset for above settings to take effect */ 5150 (void) e1000_phy_commit(hw); 5151 msec_delay(1); 5152 /* Force Full Duplex */ 5153 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5154 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5155 phy_reg | 0x000C); 5156 /* Set Link Up (in force link) */ 5157 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5158 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5159 phy_reg | 0x0040); 5160 /* Force Link */ 5161 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5162 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5163 phy_reg | 0x0040); 5164 /* Set Early Link Enable */ 5165 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5166 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5167 phy_reg | 0x0400); 5168 } 5169 5170 /* Set loopback */ 5171 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5172 5173 msec_delay(250); 5174 5175 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5176 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5177 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5178 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5179 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5180 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5181 E1000_CTRL_FD); /* Force Duplex to FULL */ 5182 5183 switch (hw->mac.type) { 5184 case e1000_82540: 5185 case e1000_82545: 5186 case e1000_82545_rev_3: 5187 case e1000_82546: 5188 case e1000_82546_rev_3: 5189 /* 5190 * For some serdes we'll need to commit the writes now 5191 * so that the status is updated on link 5192 */ 5193 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5194 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5195 msec_delay(100); 5196 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5197 } 5198 5199 if (hw->phy.media_type == e1000_media_type_copper) { 5200 /* Invert Loss of Signal */ 5201 ctrl |= E1000_CTRL_ILOS; 5202 } else { 5203 /* Set ILOS on fiber nic if half duplex is detected */ 5204 status = E1000_READ_REG(hw, E1000_STATUS); 5205 if ((status & E1000_STATUS_FD) == 0) 5206 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5207 } 5208 break; 5209 5210 case e1000_82571: 5211 case e1000_82572: 5212 /* 5213 * The fiber/SerDes versions of this adapter do not contain an 5214 * accessible PHY. Therefore, loopback beyond MAC must be done 5215 * using SerDes analog loopback. 5216 */ 5217 if (hw->phy.media_type != e1000_media_type_copper) { 5218 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5219 txcw = E1000_READ_REG(hw, E1000_TXCW); 5220 txcw &= ~((uint32_t)1 << 31); 5221 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5222 5223 /* 5224 * Write 0x410 to Serdes Control register 5225 * to enable Serdes analog loopback 5226 */ 5227 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5228 msec_delay(10); 5229 } 5230 5231 status = E1000_READ_REG(hw, E1000_STATUS); 5232 /* Set ILOS on fiber nic if half duplex is detected */ 5233 if ((hw->phy.media_type == e1000_media_type_fiber) && 5234 ((status & E1000_STATUS_FD) == 0 || 5235 (status & E1000_STATUS_LU) == 0)) 5236 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5237 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5238 ctrl |= E1000_CTRL_SLU; 5239 break; 5240 5241 case e1000_82573: 5242 ctrl |= E1000_CTRL_ILOS; 5243 break; 5244 case e1000_ich9lan: 5245 case e1000_ich10lan: 5246 ctrl |= E1000_CTRL_SLU; 5247 break; 5248 } 5249 if (hw->phy.type == e1000_phy_bm) 5250 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5251 5252 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5253 } 5254 5255 static void 5256 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5257 { 5258 struct e1000_hw *hw; 5259 uint32_t rctl; 5260 uint32_t ctrl_ext; 5261 uint32_t ctrl; 5262 uint32_t status; 5263 uint32_t txcw; 5264 uint16_t phydata; 5265 5266 hw = &Adapter->shared; 5267 5268 /* Disable Smart Power Down */ 5269 phy_spd_state(hw, B_FALSE); 5270 5271 switch (hw->mac.type) { 5272 case e1000_82571: 5273 case e1000_82572: 5274 switch (hw->phy.media_type) { 5275 case e1000_media_type_copper: 5276 /* Force link up (Must be done before the PHY writes) */ 5277 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5278 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5279 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5280 5281 rctl = E1000_READ_REG(hw, E1000_RCTL); 5282 rctl |= (E1000_RCTL_EN | 5283 E1000_RCTL_SBP | 5284 E1000_RCTL_UPE | 5285 E1000_RCTL_MPE | 5286 E1000_RCTL_LPE | 5287 E1000_RCTL_BAM); /* 0x803E */ 5288 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5289 5290 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5291 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5292 E1000_CTRL_EXT_SDP6_DATA | 5293 E1000_CTRL_EXT_SDP7_DATA | 5294 E1000_CTRL_EXT_SDP4_DIR | 5295 E1000_CTRL_EXT_SDP6_DIR | 5296 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 5297 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5298 5299 /* 5300 * This sequence tunes the PHY's SDP and no customer 5301 * settable values. For background, see comments above 5302 * e1000g_set_internal_loopback(). 5303 */ 5304 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5305 msec_delay(10); 5306 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5307 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5308 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5309 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5310 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5311 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5312 5313 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5314 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5315 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5316 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5317 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5318 5319 msec_delay(50); 5320 break; 5321 case e1000_media_type_fiber: 5322 case e1000_media_type_internal_serdes: 5323 status = E1000_READ_REG(hw, E1000_STATUS); 5324 if (((status & E1000_STATUS_LU) == 0) || 5325 (hw->phy.media_type == 5326 e1000_media_type_internal_serdes)) { 5327 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5328 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5329 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5330 } 5331 5332 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5333 txcw = E1000_READ_REG(hw, E1000_TXCW); 5334 txcw &= ~((uint32_t)1 << 31); 5335 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5336 5337 /* 5338 * Write 0x410 to Serdes Control register 5339 * to enable Serdes analog loopback 5340 */ 5341 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5342 msec_delay(10); 5343 break; 5344 default: 5345 break; 5346 } 5347 break; 5348 case e1000_82574: 5349 case e1000_80003es2lan: 5350 case e1000_ich9lan: 5351 case e1000_ich10lan: 5352 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5353 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5354 phydata | (1 << 5)); 5355 Adapter->param_adv_autoneg = 1; 5356 Adapter->param_adv_1000fdx = 1; 5357 (void) e1000g_reset_link(Adapter); 5358 break; 5359 } 5360 } 5361 5362 static void 5363 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5364 { 5365 struct e1000_hw *hw; 5366 uint32_t ctrl; 5367 uint16_t phy_ctrl; 5368 5369 hw = &Adapter->shared; 5370 5371 /* Disable Smart Power Down */ 5372 phy_spd_state(hw, B_FALSE); 5373 5374 phy_ctrl = (MII_CR_FULL_DUPLEX | 5375 MII_CR_SPEED_100); 5376 5377 /* Force 100/FD, reset PHY */ 5378 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5379 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5380 msec_delay(10); 5381 5382 /* Force 100/FD */ 5383 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5384 phy_ctrl); /* 0x2100 */ 5385 msec_delay(10); 5386 5387 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5388 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5389 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5390 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5391 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5392 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5393 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5394 E1000_CTRL_FD); /* Force Duplex to FULL */ 5395 5396 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5397 } 5398 5399 static void 5400 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5401 { 5402 struct e1000_hw *hw; 5403 uint32_t ctrl; 5404 uint16_t phy_ctrl; 5405 5406 hw = &Adapter->shared; 5407 5408 /* Disable Smart Power Down */ 5409 phy_spd_state(hw, B_FALSE); 5410 5411 phy_ctrl = (MII_CR_FULL_DUPLEX | 5412 MII_CR_SPEED_10); 5413 5414 /* Force 10/FD, reset PHY */ 5415 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5416 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5417 msec_delay(10); 5418 5419 /* Force 10/FD */ 5420 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5421 phy_ctrl); /* 0x0100 */ 5422 msec_delay(10); 5423 5424 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5425 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5426 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5427 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5428 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5429 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5430 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5431 E1000_CTRL_FD); /* Force Duplex to FULL */ 5432 5433 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5434 } 5435 5436 #ifdef __sparc 5437 static boolean_t 5438 e1000g_find_mac_address(struct e1000g *Adapter) 5439 { 5440 struct e1000_hw *hw = &Adapter->shared; 5441 uchar_t *bytes; 5442 struct ether_addr sysaddr; 5443 uint_t nelts; 5444 int err; 5445 boolean_t found = B_FALSE; 5446 5447 /* 5448 * The "vendor's factory-set address" may already have 5449 * been extracted from the chip, but if the property 5450 * "local-mac-address" is set we use that instead. 5451 * 5452 * We check whether it looks like an array of 6 5453 * bytes (which it should, if OBP set it). If we can't 5454 * make sense of it this way, we'll ignore it. 5455 */ 5456 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5457 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5458 if (err == DDI_PROP_SUCCESS) { 5459 if (nelts == ETHERADDRL) { 5460 while (nelts--) 5461 hw->mac.addr[nelts] = bytes[nelts]; 5462 found = B_TRUE; 5463 } 5464 ddi_prop_free(bytes); 5465 } 5466 5467 /* 5468 * Look up the OBP property "local-mac-address?". If the user has set 5469 * 'local-mac-address? = false', use "the system address" instead. 5470 */ 5471 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5472 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5473 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5474 if (localetheraddr(NULL, &sysaddr) != 0) { 5475 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5476 found = B_TRUE; 5477 } 5478 } 5479 ddi_prop_free(bytes); 5480 } 5481 5482 /* 5483 * Finally(!), if there's a valid "mac-address" property (created 5484 * if we netbooted from this interface), we must use this instead 5485 * of any of the above to ensure that the NFS/install server doesn't 5486 * get confused by the address changing as Solaris takes over! 5487 */ 5488 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5489 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5490 if (err == DDI_PROP_SUCCESS) { 5491 if (nelts == ETHERADDRL) { 5492 while (nelts--) 5493 hw->mac.addr[nelts] = bytes[nelts]; 5494 found = B_TRUE; 5495 } 5496 ddi_prop_free(bytes); 5497 } 5498 5499 if (found) { 5500 bcopy(hw->mac.addr, hw->mac.perm_addr, 5501 ETHERADDRL); 5502 } 5503 5504 return (found); 5505 } 5506 #endif 5507 5508 static int 5509 e1000g_add_intrs(struct e1000g *Adapter) 5510 { 5511 dev_info_t *devinfo; 5512 int intr_types; 5513 int rc; 5514 5515 devinfo = Adapter->dip; 5516 5517 /* Get supported interrupt types */ 5518 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5519 5520 if (rc != DDI_SUCCESS) { 5521 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5522 "Get supported interrupt types failed: %d\n", rc); 5523 return (DDI_FAILURE); 5524 } 5525 5526 /* 5527 * Based on Intel Technical Advisory document (TA-160), there are some 5528 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5529 * that it supports MSI, but in fact has problems. 5530 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5531 * PCI/PCI-X NICs. 5532 */ 5533 if (Adapter->shared.mac.type < e1000_82571) 5534 Adapter->msi_enable = B_FALSE; 5535 5536 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5537 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5538 5539 if (rc != DDI_SUCCESS) { 5540 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5541 "Add MSI failed, trying Legacy interrupts\n"); 5542 } else { 5543 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5544 } 5545 } 5546 5547 if ((Adapter->intr_type == 0) && 5548 (intr_types & DDI_INTR_TYPE_FIXED)) { 5549 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5550 5551 if (rc != DDI_SUCCESS) { 5552 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5553 "Add Legacy interrupts failed\n"); 5554 return (DDI_FAILURE); 5555 } 5556 5557 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5558 } 5559 5560 if (Adapter->intr_type == 0) { 5561 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5562 "No interrupts registered\n"); 5563 return (DDI_FAILURE); 5564 } 5565 5566 return (DDI_SUCCESS); 5567 } 5568 5569 /* 5570 * e1000g_intr_add() handles MSI/Legacy interrupts 5571 */ 5572 static int 5573 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5574 { 5575 dev_info_t *devinfo; 5576 int count, avail, actual; 5577 int x, y, rc, inum = 0; 5578 int flag; 5579 ddi_intr_handler_t *intr_handler; 5580 5581 devinfo = Adapter->dip; 5582 5583 /* get number of interrupts */ 5584 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5585 if ((rc != DDI_SUCCESS) || (count == 0)) { 5586 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5587 "Get interrupt number failed. Return: %d, count: %d\n", 5588 rc, count); 5589 return (DDI_FAILURE); 5590 } 5591 5592 /* get number of available interrupts */ 5593 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5594 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5595 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5596 "Get interrupt available number failed. " 5597 "Return: %d, available: %d\n", rc, avail); 5598 return (DDI_FAILURE); 5599 } 5600 5601 if (avail < count) { 5602 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5603 "Interrupts count: %d, available: %d\n", 5604 count, avail); 5605 } 5606 5607 /* Allocate an array of interrupt handles */ 5608 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5609 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5610 5611 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5612 flag = DDI_INTR_ALLOC_NORMAL; 5613 5614 /* call ddi_intr_alloc() */ 5615 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5616 count, &actual, flag); 5617 5618 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5619 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5620 "Allocate interrupts failed: %d\n", rc); 5621 5622 kmem_free(Adapter->htable, Adapter->intr_size); 5623 return (DDI_FAILURE); 5624 } 5625 5626 if (actual < count) { 5627 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5628 "Interrupts requested: %d, received: %d\n", 5629 count, actual); 5630 } 5631 5632 Adapter->intr_cnt = actual; 5633 5634 /* Get priority for first msi, assume remaining are all the same */ 5635 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5636 5637 if (rc != DDI_SUCCESS) { 5638 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5639 "Get interrupt priority failed: %d\n", rc); 5640 5641 /* Free already allocated intr */ 5642 for (y = 0; y < actual; y++) 5643 (void) ddi_intr_free(Adapter->htable[y]); 5644 5645 kmem_free(Adapter->htable, Adapter->intr_size); 5646 return (DDI_FAILURE); 5647 } 5648 5649 /* 5650 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5651 * use the interrupt service routine e1000g_intr_pciexpress() 5652 * to avoid interrupt stealing when sharing interrupt with other 5653 * devices. 5654 */ 5655 if (Adapter->shared.mac.type < e1000_82571) 5656 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5657 else 5658 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5659 5660 /* Call ddi_intr_add_handler() */ 5661 for (x = 0; x < actual; x++) { 5662 rc = ddi_intr_add_handler(Adapter->htable[x], 5663 intr_handler, (caddr_t)Adapter, NULL); 5664 5665 if (rc != DDI_SUCCESS) { 5666 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5667 "Add interrupt handler failed: %d\n", rc); 5668 5669 /* Remove already added handler */ 5670 for (y = 0; y < x; y++) 5671 (void) ddi_intr_remove_handler( 5672 Adapter->htable[y]); 5673 5674 /* Free already allocated intr */ 5675 for (y = 0; y < actual; y++) 5676 (void) ddi_intr_free(Adapter->htable[y]); 5677 5678 kmem_free(Adapter->htable, Adapter->intr_size); 5679 return (DDI_FAILURE); 5680 } 5681 } 5682 5683 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5684 5685 if (rc != DDI_SUCCESS) { 5686 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5687 "Get interrupt cap failed: %d\n", rc); 5688 5689 /* Free already allocated intr */ 5690 for (y = 0; y < actual; y++) { 5691 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5692 (void) ddi_intr_free(Adapter->htable[y]); 5693 } 5694 5695 kmem_free(Adapter->htable, Adapter->intr_size); 5696 return (DDI_FAILURE); 5697 } 5698 5699 return (DDI_SUCCESS); 5700 } 5701 5702 static int 5703 e1000g_rem_intrs(struct e1000g *Adapter) 5704 { 5705 int x; 5706 int rc; 5707 5708 for (x = 0; x < Adapter->intr_cnt; x++) { 5709 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5710 if (rc != DDI_SUCCESS) { 5711 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5712 "Remove intr handler failed: %d\n", rc); 5713 return (DDI_FAILURE); 5714 } 5715 5716 rc = ddi_intr_free(Adapter->htable[x]); 5717 if (rc != DDI_SUCCESS) { 5718 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5719 "Free intr failed: %d\n", rc); 5720 return (DDI_FAILURE); 5721 } 5722 } 5723 5724 kmem_free(Adapter->htable, Adapter->intr_size); 5725 5726 return (DDI_SUCCESS); 5727 } 5728 5729 static int 5730 e1000g_enable_intrs(struct e1000g *Adapter) 5731 { 5732 int x; 5733 int rc; 5734 5735 /* Enable interrupts */ 5736 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5737 /* Call ddi_intr_block_enable() for MSI */ 5738 rc = ddi_intr_block_enable(Adapter->htable, 5739 Adapter->intr_cnt); 5740 if (rc != DDI_SUCCESS) { 5741 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5742 "Enable block intr failed: %d\n", rc); 5743 return (DDI_FAILURE); 5744 } 5745 } else { 5746 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5747 for (x = 0; x < Adapter->intr_cnt; x++) { 5748 rc = ddi_intr_enable(Adapter->htable[x]); 5749 if (rc != DDI_SUCCESS) { 5750 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5751 "Enable intr failed: %d\n", rc); 5752 return (DDI_FAILURE); 5753 } 5754 } 5755 } 5756 5757 return (DDI_SUCCESS); 5758 } 5759 5760 static int 5761 e1000g_disable_intrs(struct e1000g *Adapter) 5762 { 5763 int x; 5764 int rc; 5765 5766 /* Disable all interrupts */ 5767 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5768 rc = ddi_intr_block_disable(Adapter->htable, 5769 Adapter->intr_cnt); 5770 if (rc != DDI_SUCCESS) { 5771 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5772 "Disable block intr failed: %d\n", rc); 5773 return (DDI_FAILURE); 5774 } 5775 } else { 5776 for (x = 0; x < Adapter->intr_cnt; x++) { 5777 rc = ddi_intr_disable(Adapter->htable[x]); 5778 if (rc != DDI_SUCCESS) { 5779 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5780 "Disable intr failed: %d\n", rc); 5781 return (DDI_FAILURE); 5782 } 5783 } 5784 } 5785 5786 return (DDI_SUCCESS); 5787 } 5788 5789 /* 5790 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5791 */ 5792 static void 5793 e1000g_get_phy_state(struct e1000g *Adapter) 5794 { 5795 struct e1000_hw *hw = &Adapter->shared; 5796 5797 if (hw->phy.media_type == e1000_media_type_copper) { 5798 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5799 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5800 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 5801 &Adapter->phy_an_adv); 5802 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 5803 &Adapter->phy_an_exp); 5804 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 5805 &Adapter->phy_ext_status); 5806 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 5807 &Adapter->phy_1000t_ctrl); 5808 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5809 &Adapter->phy_1000t_status); 5810 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 5811 &Adapter->phy_lp_able); 5812 5813 Adapter->param_autoneg_cap = 5814 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5815 Adapter->param_pause_cap = 5816 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5817 Adapter->param_asym_pause_cap = 5818 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5819 Adapter->param_1000fdx_cap = 5820 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5821 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5822 Adapter->param_1000hdx_cap = 5823 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5824 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5825 Adapter->param_100t4_cap = 5826 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5827 Adapter->param_100fdx_cap = 5828 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5829 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5830 Adapter->param_100hdx_cap = 5831 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5832 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5833 Adapter->param_10fdx_cap = 5834 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5835 Adapter->param_10hdx_cap = 5836 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5837 5838 Adapter->param_adv_autoneg = hw->mac.autoneg; 5839 Adapter->param_adv_pause = 5840 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5841 Adapter->param_adv_asym_pause = 5842 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5843 Adapter->param_adv_1000hdx = 5844 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5845 Adapter->param_adv_100t4 = 5846 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5847 if (Adapter->param_adv_autoneg == 1) { 5848 Adapter->param_adv_1000fdx = 5849 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 5850 ? 1 : 0; 5851 Adapter->param_adv_100fdx = 5852 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 5853 ? 1 : 0; 5854 Adapter->param_adv_100hdx = 5855 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 5856 ? 1 : 0; 5857 Adapter->param_adv_10fdx = 5858 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5859 Adapter->param_adv_10hdx = 5860 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5861 } 5862 5863 Adapter->param_lp_autoneg = 5864 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5865 Adapter->param_lp_pause = 5866 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5867 Adapter->param_lp_asym_pause = 5868 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5869 Adapter->param_lp_1000fdx = 5870 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5871 Adapter->param_lp_1000hdx = 5872 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5873 Adapter->param_lp_100t4 = 5874 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5875 Adapter->param_lp_100fdx = 5876 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5877 Adapter->param_lp_100hdx = 5878 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5879 Adapter->param_lp_10fdx = 5880 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5881 Adapter->param_lp_10hdx = 5882 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5883 } else { 5884 /* 5885 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 5886 * it can only work with 1Gig Full Duplex Link Partner. 5887 */ 5888 Adapter->param_autoneg_cap = 0; 5889 Adapter->param_pause_cap = 1; 5890 Adapter->param_asym_pause_cap = 1; 5891 Adapter->param_1000fdx_cap = 1; 5892 Adapter->param_1000hdx_cap = 0; 5893 Adapter->param_100t4_cap = 0; 5894 Adapter->param_100fdx_cap = 0; 5895 Adapter->param_100hdx_cap = 0; 5896 Adapter->param_10fdx_cap = 0; 5897 Adapter->param_10hdx_cap = 0; 5898 5899 Adapter->param_adv_autoneg = 0; 5900 Adapter->param_adv_pause = 1; 5901 Adapter->param_adv_asym_pause = 1; 5902 Adapter->param_adv_1000fdx = 1; 5903 Adapter->param_adv_1000hdx = 0; 5904 Adapter->param_adv_100t4 = 0; 5905 Adapter->param_adv_100fdx = 0; 5906 Adapter->param_adv_100hdx = 0; 5907 Adapter->param_adv_10fdx = 0; 5908 Adapter->param_adv_10hdx = 0; 5909 5910 Adapter->param_lp_autoneg = 0; 5911 Adapter->param_lp_pause = 0; 5912 Adapter->param_lp_asym_pause = 0; 5913 Adapter->param_lp_1000fdx = 0; 5914 Adapter->param_lp_1000hdx = 0; 5915 Adapter->param_lp_100t4 = 0; 5916 Adapter->param_lp_100fdx = 0; 5917 Adapter->param_lp_100hdx = 0; 5918 Adapter->param_lp_10fdx = 0; 5919 Adapter->param_lp_10hdx = 0; 5920 } 5921 } 5922 5923 /* 5924 * FMA support 5925 */ 5926 5927 int 5928 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5929 { 5930 ddi_fm_error_t de; 5931 5932 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5933 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5934 return (de.fme_status); 5935 } 5936 5937 int 5938 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5939 { 5940 ddi_fm_error_t de; 5941 5942 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5943 return (de.fme_status); 5944 } 5945 5946 /* 5947 * The IO fault service error handling callback function 5948 */ 5949 /* ARGSUSED2 */ 5950 static int 5951 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5952 { 5953 /* 5954 * as the driver can always deal with an error in any dma or 5955 * access handle, we can just return the fme_status value. 5956 */ 5957 pci_ereport_post(dip, err, NULL); 5958 return (err->fme_status); 5959 } 5960 5961 static void 5962 e1000g_fm_init(struct e1000g *Adapter) 5963 { 5964 ddi_iblock_cookie_t iblk; 5965 int fma_acc_flag, fma_dma_flag; 5966 5967 /* Only register with IO Fault Services if we have some capability */ 5968 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5969 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5970 fma_acc_flag = 1; 5971 } else { 5972 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5973 fma_acc_flag = 0; 5974 } 5975 5976 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5977 fma_dma_flag = 1; 5978 } else { 5979 fma_dma_flag = 0; 5980 } 5981 5982 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5983 5984 if (Adapter->fm_capabilities) { 5985 5986 /* Register capabilities with IO Fault Services */ 5987 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5988 5989 /* 5990 * Initialize pci ereport capabilities if ereport capable 5991 */ 5992 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5993 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5994 pci_ereport_setup(Adapter->dip); 5995 5996 /* 5997 * Register error callback if error callback capable 5998 */ 5999 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6000 ddi_fm_handler_register(Adapter->dip, 6001 e1000g_fm_error_cb, (void*) Adapter); 6002 } 6003 } 6004 6005 static void 6006 e1000g_fm_fini(struct e1000g *Adapter) 6007 { 6008 /* Only unregister FMA capabilities if we registered some */ 6009 if (Adapter->fm_capabilities) { 6010 6011 /* 6012 * Release any resources allocated by pci_ereport_setup() 6013 */ 6014 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6015 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6016 pci_ereport_teardown(Adapter->dip); 6017 6018 /* 6019 * Un-register error callback if error callback capable 6020 */ 6021 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6022 ddi_fm_handler_unregister(Adapter->dip); 6023 6024 /* Unregister from IO Fault Services */ 6025 mutex_enter(&e1000g_rx_detach_lock); 6026 ddi_fm_fini(Adapter->dip); 6027 if (Adapter->priv_dip != NULL) { 6028 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6029 } 6030 mutex_exit(&e1000g_rx_detach_lock); 6031 } 6032 } 6033 6034 void 6035 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6036 { 6037 uint64_t ena; 6038 char buf[FM_MAX_CLASS]; 6039 6040 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6041 ena = fm_ena_generate(0, FM_ENA_FMT1); 6042 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6043 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6044 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6045 } 6046 } 6047 6048 /* 6049 * quiesce(9E) entry point. 6050 * 6051 * This function is called when the system is single-threaded at high 6052 * PIL with preemption disabled. Therefore, this function must not be 6053 * blocked. 6054 * 6055 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6056 * DDI_FAILURE indicates an error condition and should almost never happen. 6057 */ 6058 static int 6059 e1000g_quiesce(dev_info_t *devinfo) 6060 { 6061 struct e1000g *Adapter; 6062 6063 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6064 6065 if (Adapter == NULL) 6066 return (DDI_FAILURE); 6067 6068 e1000g_clear_all_interrupts(Adapter); 6069 6070 (void) e1000_reset_hw(&Adapter->shared); 6071 6072 /* Setup our HW Tx Head & Tail descriptor pointers */ 6073 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6074 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6075 6076 /* Setup our HW Rx Head & Tail descriptor pointers */ 6077 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6078 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6079 6080 return (DDI_SUCCESS); 6081 } 6082 6083 static int 6084 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 6085 uint_t pr_valsize, void *pr_val) 6086 { 6087 link_flowctrl_t fl; 6088 struct e1000_hw *hw = &Adapter->shared; 6089 int err = 0; 6090 6091 ASSERT(pr_valsize > 0); 6092 switch (pr_num) { 6093 case MAC_PROP_AUTONEG: 6094 if (hw->phy.media_type != e1000_media_type_copper) 6095 *(uint8_t *)pr_val = 0; 6096 else 6097 *(uint8_t *)pr_val = 6098 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) 6099 ? 1 : 0); 6100 break; 6101 case MAC_PROP_FLOWCTRL: 6102 if (pr_valsize < sizeof (link_flowctrl_t)) 6103 return (EINVAL); 6104 fl = LINK_FLOWCTRL_BI; 6105 bcopy(&fl, pr_val, sizeof (fl)); 6106 break; 6107 case MAC_PROP_ADV_1000FDX_CAP: 6108 case MAC_PROP_EN_1000FDX_CAP: 6109 if (hw->phy.media_type != e1000_media_type_copper) 6110 *(uint8_t *)pr_val = 1; 6111 else 6112 *(uint8_t *)pr_val = 6113 ((Adapter->phy_ext_status & 6114 IEEE_ESR_1000T_FD_CAPS) || 6115 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) 6116 ? 1 : 0; 6117 break; 6118 case MAC_PROP_ADV_1000HDX_CAP: 6119 case MAC_PROP_EN_1000HDX_CAP: 6120 *(uint8_t *)pr_val = 0; 6121 break; 6122 case MAC_PROP_ADV_100FDX_CAP: 6123 case MAC_PROP_EN_100FDX_CAP: 6124 if (hw->phy.media_type != e1000_media_type_copper) 6125 *(uint8_t *)pr_val = 0; 6126 else 6127 *(uint8_t *)pr_val = 6128 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6129 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 6130 ? 1 : 0; 6131 break; 6132 case MAC_PROP_ADV_100HDX_CAP: 6133 case MAC_PROP_EN_100HDX_CAP: 6134 if (hw->phy.media_type != e1000_media_type_copper) 6135 *(uint8_t *)pr_val = 0; 6136 else 6137 *(uint8_t *)pr_val = 6138 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6139 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 6140 ? 1 : 0; 6141 break; 6142 case MAC_PROP_ADV_10FDX_CAP: 6143 case MAC_PROP_EN_10FDX_CAP: 6144 if (hw->phy.media_type != e1000_media_type_copper) 6145 *(uint8_t *)pr_val = 0; 6146 else 6147 *(uint8_t *)pr_val = 6148 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6149 break; 6150 case MAC_PROP_ADV_10HDX_CAP: 6151 case MAC_PROP_EN_10HDX_CAP: 6152 if (hw->phy.media_type != e1000_media_type_copper) 6153 *(uint8_t *)pr_val = 0; 6154 else 6155 *(uint8_t *)pr_val = 6156 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6157 break; 6158 default: 6159 err = ENOTSUP; 6160 break; 6161 } 6162 return (err); 6163 } 6164 6165 /* 6166 * synchronize the adv* and en* parameters. 6167 * 6168 * See comments in <sys/dld.h> for details of the *_en_* 6169 * parameters. The usage of ndd for setting adv parameters will 6170 * synchronize all the en parameters with the e1000g parameters, 6171 * implicitly disabling any settings made via dladm. 6172 */ 6173 static void 6174 e1000g_param_sync(struct e1000g *Adapter) 6175 { 6176 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6177 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6178 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6179 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6180 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6181 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6182 } 6183 6184 /* 6185 * e1000g_get_driver_control - tell manageability firmware that the driver 6186 * has control. 6187 */ 6188 static void 6189 e1000g_get_driver_control(struct e1000_hw *hw) 6190 { 6191 uint32_t ctrl_ext; 6192 uint32_t swsm; 6193 6194 /* tell manageability firmware the driver has taken over */ 6195 switch (hw->mac.type) { 6196 case e1000_82573: 6197 swsm = E1000_READ_REG(hw, E1000_SWSM); 6198 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6199 break; 6200 case e1000_82571: 6201 case e1000_82572: 6202 case e1000_82574: 6203 case e1000_80003es2lan: 6204 case e1000_ich8lan: 6205 case e1000_ich9lan: 6206 case e1000_ich10lan: 6207 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6208 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6209 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6210 break; 6211 default: 6212 /* no manageability firmware: do nothing */ 6213 break; 6214 } 6215 } 6216 6217 /* 6218 * e1000g_release_driver_control - tell manageability firmware that the driver 6219 * has released control. 6220 */ 6221 static void 6222 e1000g_release_driver_control(struct e1000_hw *hw) 6223 { 6224 uint32_t ctrl_ext; 6225 uint32_t swsm; 6226 6227 /* tell manageability firmware the driver has released control */ 6228 switch (hw->mac.type) { 6229 case e1000_82573: 6230 swsm = E1000_READ_REG(hw, E1000_SWSM); 6231 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6232 break; 6233 case e1000_82571: 6234 case e1000_82572: 6235 case e1000_82574: 6236 case e1000_80003es2lan: 6237 case e1000_ich8lan: 6238 case e1000_ich9lan: 6239 case e1000_ich10lan: 6240 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6241 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6242 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6243 break; 6244 default: 6245 /* no manageability firmware: do nothing */ 6246 break; 6247 } 6248 } 6249 6250 /* 6251 * Restore e1000g promiscuous mode. 6252 */ 6253 static void 6254 e1000g_restore_promisc(struct e1000g *Adapter) 6255 { 6256 if (Adapter->e1000g_promisc) { 6257 uint32_t rctl; 6258 6259 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6260 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6261 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6262 } 6263 } 6264