175eba5b6SRobert Mustacchi /****************************************************************************** 275eba5b6SRobert Mustacchi 3*42cc51e0SRobert Mustacchi Copyright (c) 2001-2015, Intel Corporation 475eba5b6SRobert Mustacchi All rights reserved. 575eba5b6SRobert Mustacchi 675eba5b6SRobert Mustacchi Redistribution and use in source and binary forms, with or without 775eba5b6SRobert Mustacchi modification, are permitted provided that the following conditions are met: 875eba5b6SRobert Mustacchi 975eba5b6SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 1075eba5b6SRobert Mustacchi this list of conditions and the following disclaimer. 1175eba5b6SRobert Mustacchi 1275eba5b6SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 1375eba5b6SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 1475eba5b6SRobert Mustacchi documentation and/or other materials provided with the distribution. 1575eba5b6SRobert Mustacchi 1675eba5b6SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 1775eba5b6SRobert Mustacchi contributors may be used to endorse or promote products derived from 1875eba5b6SRobert Mustacchi this software without specific prior written permission. 1975eba5b6SRobert Mustacchi 2075eba5b6SRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2175eba5b6SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2275eba5b6SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2375eba5b6SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2475eba5b6SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2575eba5b6SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2675eba5b6SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2775eba5b6SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2875eba5b6SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2975eba5b6SRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3075eba5b6SRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 3175eba5b6SRobert Mustacchi 3275eba5b6SRobert Mustacchi ******************************************************************************/ 3375eba5b6SRobert Mustacchi /*$FreeBSD$*/ 3475eba5b6SRobert Mustacchi 3575eba5b6SRobert Mustacchi #ifndef _E1000_MBX_H_ 3675eba5b6SRobert Mustacchi #define _E1000_MBX_H_ 3775eba5b6SRobert Mustacchi 3875eba5b6SRobert Mustacchi #include "e1000_api.h" 3975eba5b6SRobert Mustacchi 4075eba5b6SRobert Mustacchi /* Define mailbox register bits */ 4175eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */ 4275eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_ACK 0x00000002 /* Ack PF message received */ 4375eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */ 4475eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */ 4575eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */ 4675eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */ 4775eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_RSTI 0x00000040 /* PF has reset indication */ 4875eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */ 4975eba5b6SRobert Mustacchi #define E1000_V2PMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */ 5075eba5b6SRobert Mustacchi 5175eba5b6SRobert Mustacchi #define E1000_P2VMAILBOX_STS 0x00000001 /* Initiate message send to VF */ 5275eba5b6SRobert Mustacchi #define E1000_P2VMAILBOX_ACK 0x00000002 /* Ack message recv'd from VF */ 5375eba5b6SRobert Mustacchi #define E1000_P2VMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */ 5475eba5b6SRobert Mustacchi #define E1000_P2VMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */ 5575eba5b6SRobert Mustacchi #define E1000_P2VMAILBOX_RVFU 0x00000010 /* Reset VFU - used when VF stuck */ 5675eba5b6SRobert Mustacchi 5775eba5b6SRobert Mustacchi #define E1000_MBVFICR_VFREQ_MASK 0x000000FF /* bits for VF messages */ 5875eba5b6SRobert Mustacchi #define E1000_MBVFICR_VFREQ_VF1 0x00000001 /* bit for VF 1 message */ 5975eba5b6SRobert Mustacchi #define E1000_MBVFICR_VFACK_MASK 0x00FF0000 /* bits for VF acks */ 6075eba5b6SRobert Mustacchi #define E1000_MBVFICR_VFACK_VF1 0x00010000 /* bit for VF 1 ack */ 6175eba5b6SRobert Mustacchi 6275eba5b6SRobert Mustacchi #define E1000_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */ 6375eba5b6SRobert Mustacchi 6475eba5b6SRobert Mustacchi /* If it's a E1000_VF_* msg then it originates in the VF and is sent to the 6575eba5b6SRobert Mustacchi * PF. The reverse is TRUE if it is E1000_PF_*. 6675eba5b6SRobert Mustacchi * Message ACK's are the value or'd with 0xF0000000 6775eba5b6SRobert Mustacchi */ 68c124a83eSRobert Mustacchi /* Msgs below or'd with this are the ACK */ 69c124a83eSRobert Mustacchi #define E1000_VT_MSGTYPE_ACK 0x80000000 70c124a83eSRobert Mustacchi /* Msgs below or'd with this are the NACK */ 71c124a83eSRobert Mustacchi #define E1000_VT_MSGTYPE_NACK 0x40000000 72c124a83eSRobert Mustacchi /* Indicates that VF is still clear to send requests */ 73c124a83eSRobert Mustacchi #define E1000_VT_MSGTYPE_CTS 0x20000000 7475eba5b6SRobert Mustacchi #define E1000_VT_MSGINFO_SHIFT 16 75c124a83eSRobert Mustacchi /* bits 23:16 are used for extra info for certain messages */ 7675eba5b6SRobert Mustacchi #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT) 7775eba5b6SRobert Mustacchi 7875eba5b6SRobert Mustacchi #define E1000_VF_RESET 0x01 /* VF requests reset */ 7975eba5b6SRobert Mustacchi #define E1000_VF_SET_MAC_ADDR 0x02 /* VF requests to set MAC addr */ 8075eba5b6SRobert Mustacchi #define E1000_VF_SET_MULTICAST 0x03 /* VF requests to set MC addr */ 8175eba5b6SRobert Mustacchi #define E1000_VF_SET_MULTICAST_COUNT_MASK (0x1F << E1000_VT_MSGINFO_SHIFT) 8275eba5b6SRobert Mustacchi #define E1000_VF_SET_MULTICAST_OVERFLOW (0x80 << E1000_VT_MSGINFO_SHIFT) 8375eba5b6SRobert Mustacchi #define E1000_VF_SET_VLAN 0x04 /* VF requests to set VLAN */ 8475eba5b6SRobert Mustacchi #define E1000_VF_SET_VLAN_ADD (0x01 << E1000_VT_MSGINFO_SHIFT) 85c124a83eSRobert Mustacchi #define E1000_VF_SET_LPE 0x05 /* reqs to set VMOLR.LPE */ 86c124a83eSRobert Mustacchi #define E1000_VF_SET_PROMISC 0x06 /* reqs to clear VMOLR.ROPE/MPME*/ 8775eba5b6SRobert Mustacchi #define E1000_VF_SET_PROMISC_UNICAST (0x01 << E1000_VT_MSGINFO_SHIFT) 8875eba5b6SRobert Mustacchi #define E1000_VF_SET_PROMISC_MULTICAST (0x02 << E1000_VT_MSGINFO_SHIFT) 8975eba5b6SRobert Mustacchi 9075eba5b6SRobert Mustacchi #define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */ 9175eba5b6SRobert Mustacchi 9275eba5b6SRobert Mustacchi #define E1000_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */ 9375eba5b6SRobert Mustacchi #define E1000_VF_MBX_INIT_DELAY 500 /* microseconds between retries */ 9475eba5b6SRobert Mustacchi 9575eba5b6SRobert Mustacchi s32 e1000_read_mbx(struct e1000_hw *, u32 *, u16, u16); 9675eba5b6SRobert Mustacchi s32 e1000_write_mbx(struct e1000_hw *, u32 *, u16, u16); 9775eba5b6SRobert Mustacchi s32 e1000_read_posted_mbx(struct e1000_hw *, u32 *, u16, u16); 9875eba5b6SRobert Mustacchi s32 e1000_write_posted_mbx(struct e1000_hw *, u32 *, u16, u16); 9975eba5b6SRobert Mustacchi s32 e1000_check_for_msg(struct e1000_hw *, u16); 10075eba5b6SRobert Mustacchi s32 e1000_check_for_ack(struct e1000_hw *, u16); 10175eba5b6SRobert Mustacchi s32 e1000_check_for_rst(struct e1000_hw *, u16); 10275eba5b6SRobert Mustacchi void e1000_init_mbx_ops_generic(struct e1000_hw *hw); 10375eba5b6SRobert Mustacchi s32 e1000_init_mbx_params_vf(struct e1000_hw *); 10475eba5b6SRobert Mustacchi s32 e1000_init_mbx_params_pf(struct e1000_hw *); 10575eba5b6SRobert Mustacchi 10675eba5b6SRobert Mustacchi #endif /* _E1000_MBX_H_ */ 107