1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 support code. 14 * 15 * Copyright (C) 2010-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __CXGBE_OSDEP_H 24 #define __CXGBE_OSDEP_H 25 26 #include <sys/ddi.h> 27 #include <sys/sunddi.h> 28 #include <sys/byteorder.h> 29 #include <sys/cmn_err.h> 30 #include <sys/pcie.h> 31 #include <sys/sysmacros.h> 32 #include <sys/inttypes.h> 33 34 /* sys/user.h defines u, and that bothers us. */ 35 #undef u 36 37 #define isdigit(x) ((x) >= '0' && (x) <= '9') 38 #define isspace(x) ((x) == ' ' || (x) == '\t') 39 #define toupper(x) (((x) >= 'a' && (x) <= 'z') ? (x) - 'a' + 'A' : (x)) 40 #define fls(x) ddi_fls(x) 41 42 #define CH_ERR(sc, ...) cxgb_printf(sc->dip, CE_WARN, ##__VA_ARGS__) 43 #define CH_WARN(sc, ...) cxgb_printf(sc->dip, CE_WARN, ##__VA_ARGS__) 44 #define CH_WARN_RATELIMIT(sc, ...) cxgb_printf(sc->dip, CE_WARN, ##__VA_ARGS__) 45 #define CH_ALERT(sc, ...) cxgb_printf(sc->dip, CE_NOTE, ##__VA_ARGS__) 46 47 #define MII_BMCR 0x00 48 #define MII_BMSR 0x01 49 #define MII_PHYSID1 0x02 50 #define MII_PHYSID2 0x03 51 #define MII_ADVERTISE 0x04 52 #define MII_LPA 0x05 53 #define MII_EXPANSION 0x06 54 #define MII_CTRL1000 0x09 55 #define MII_DCOUNTER 0x12 56 #define MII_FCSCOUNTER 0x13 57 #define MII_NWAYTEST 0x14 58 #define MII_RERRCOUNTER 0x15 59 #define MII_SREVISION 0x16 60 #define MII_RESV1 0x17 61 #define MII_LBRERROR 0x18 62 #define MII_PHYADDR 0x19 63 #define MII_RESV2 0x1a 64 #define MII_TPISTATUS 0x1b 65 #define MII_NCONFIG 0x1c 66 67 #define BMCR_RESV 0x007f 68 #define BMCR_SPEED1000 0x0040 69 #define BMCR_CTST 0x0080 70 #define BMCR_FULLDPLX 0x0100 71 #define BMCR_ANRESTART 0x0200 72 #define BMCR_ISOLATE 0x0400 73 #define BMCR_PDOWN 0x0800 74 #define BMCR_ANENABLE 0x1000 75 #define BMCR_SPEED100 0x2000 76 #define BMCR_LOOPBACK 0x4000 77 #define BMCR_RESET 0x8000 78 79 #define BMSR_ERCAP 0x0001 80 #define BMSR_JCD 0x0002 81 #define BMSR_LSTATUS 0x0004 82 #define BMSR_ANEGCAPABLE 0x0008 83 #define BMSR_RFAULT 0x0010 84 #define BMSR_ANEGCOMPLETE 0x0020 85 #define BMSR_RESV 0x07c0 86 #define BMSR_10HALF 0x0800 87 #define BMSR_10FULL 0x1000 88 #define BMSR_100HALF 0x2000 89 #define BMSR_100FULL 0x4000 90 #define BMSR_100BASE4 0x8000 91 92 #define ADVERTISE_SLCT 0x001f 93 #define ADVERTISE_CSMA 0x0001 94 #define ADVERTISE_10HALF 0x0020 95 #define ADVERTISE_1000XFULL 0x0020 96 #define ADVERTISE_10FULL 0x0040 97 #define ADVERTISE_1000XHALF 0x0040 98 #define ADVERTISE_100HALF 0x0080 99 #define ADVERTISE_1000XPAUSE 0x0080 100 #define ADVERTISE_100FULL 0x0100 101 #define ADVERTISE_1000XPSE_ASYM 0x0100 102 #define ADVERTISE_100BASE4 0x0200 103 #define ADVERTISE_PAUSE_CAP 0x0400 104 #define ADVERTISE_PAUSE_ASYM 0x0800 105 #define ADVERTISE_RESV 0x1c00 106 #define ADVERTISE_RFAULT 0x2000 107 #define ADVERTISE_LPACK 0x4000 108 #define ADVERTISE_NPAGE 0x8000 109 110 #define ADVERTISE_1000FULL 0x0200 111 #define ADVERTISE_1000HALF 0x0100 112 113 #define PCI_CAP_ID_EXP PCI_CAP_ID_PCI_E 114 #define PCI_EXP_DEVCTL PCIE_DEVCTL 115 #define PCI_EXP_DEVCTL_PAYLOAD PCIE_DEVCTL_MAX_PAYLOAD_MASK 116 #define PCI_EXP_DEVCTL_READRQ PCIE_DEVCTL_MAX_READ_REQ_MASK 117 #define PCI_EXP_LNKCTL PCIE_LINKCTL 118 #define PCI_EXP_LNKSTA PCIE_LINKSTS 119 #define PCI_EXP_LNKSTA_CLS PCIE_LINKSTS_SPEED_MASK 120 #define PCI_EXP_LNKSTA_NLW PCIE_LINKSTS_NEG_WIDTH_MASK 121 122 #define PCI_VPD_ADDR 2 123 #define PCI_VPD_ADDR_F 0x8000 124 #define PCI_VPD_DATA 4 125 126 #define __devinit 127 #ifndef ARRAY_SIZE 128 #define ARRAY_SIZE(x) (sizeof (x) / sizeof ((x)[0])) 129 #endif 130 #define DIV_ROUND_UP(x, y) howmany(x, y) 131 132 #define udelay(x) drv_usecwait(x) 133 #define msleep(x) delay(drv_usectohz(1000ULL * (x))) 134 #define mdelay(x) drv_usecwait(1000UL * (x)) 135 136 #define le16_to_cpu(x) LE_16((uint16_t)(x)) 137 #define le32_to_cpu(x) LE_32((uint32_t)(x)) 138 #define le64_to_cpu(x) LE_64((uint64_t)(x)) 139 #define cpu_to_le16(x) LE_16((uint16_t)(x)) 140 #define cpu_to_le32(x) LE_32((uint32_t)(x)) 141 #define cpu_to_le64(x) LE_64((uint64_t)(x)) 142 #define be16_to_cpu(x) BE_16((uint16_t)(x)) 143 #define be32_to_cpu(x) BE_32((uint32_t)(x)) 144 #define be64_to_cpu(x) BE_64((uint64_t)(x)) 145 #define cpu_to_be16(x) BE_16((uint16_t)(x)) 146 #define cpu_to_be32(x) BE_32((uint32_t)(x)) 147 #define cpu_to_be64(x) BE_64((uint64_t)(x)) 148 #define swab32(x) BSWAP_32(x) 149 150 typedef uint8_t u8; 151 typedef uint16_t u16; 152 typedef uint32_t u32; 153 typedef uint64_t u64; 154 155 typedef uint8_t __u8; 156 typedef uint16_t __u16; 157 typedef uint32_t __u32; 158 typedef uint64_t __u64; 159 typedef uint8_t __be8; 160 typedef uint16_t __be16; 161 typedef uint32_t __be32; 162 typedef uint64_t __be64; 163 164 typedef boolean_t bool; 165 #define true B_TRUE 166 #define false B_FALSE 167 168 #if defined(__sparc) 169 #define __BIG_ENDIAN_BITFIELD 170 #define PAGE_SIZE 8192 171 #define PAGE_SHIFT 13 172 #define CACHE_LINE 64 173 #else 174 #define __LITTLE_ENDIAN_BITFIELD 175 #define PAGE_SIZE 4096 176 #define PAGE_SHIFT 12 177 #define CACHE_LINE 32 178 #endif 179 180 #define SUPPORTED_10baseT_Half (1 << 0) 181 #define SUPPORTED_10baseT_Full (1 << 1) 182 #define SUPPORTED_100baseT_Half (1 << 2) 183 #define SUPPORTED_100baseT_Full (1 << 3) 184 #define SUPPORTED_1000baseT_Half (1 << 4) 185 #define SUPPORTED_1000baseT_Full (1 << 5) 186 #define SUPPORTED_Autoneg (1 << 6) 187 #define SUPPORTED_TP (1 << 7) 188 #define SUPPORTED_AUI (1 << 8) 189 #define SUPPORTED_MII (1 << 9) 190 #define SUPPORTED_FIBRE (1 << 10) 191 #define SUPPORTED_BNC (1 << 11) 192 #define SUPPORTED_10000baseT_Full (1 << 12) 193 #define SUPPORTED_Pause (1 << 13) 194 #define SUPPORTED_Asym_Pause (1 << 14) 195 196 #define ADVERTISED_10baseT_Half (1 << 0) 197 #define ADVERTISED_10baseT_Full (1 << 1) 198 #define ADVERTISED_100baseT_Half (1 << 2) 199 #define ADVERTISED_100baseT_Full (1 << 3) 200 #define ADVERTISED_1000baseT_Half (1 << 4) 201 #define ADVERTISED_1000baseT_Full (1 << 5) 202 #define ADVERTISED_Autoneg (1 << 6) 203 #define ADVERTISED_TP (1 << 7) 204 #define ADVERTISED_AUI (1 << 8) 205 #define ADVERTISED_MII (1 << 9) 206 #define ADVERTISED_FIBRE (1 << 10) 207 #define ADVERTISED_BNC (1 << 11) 208 #define ADVERTISED_10000baseT_Full (1 << 12) 209 #define ADVERTISED_Pause (1 << 13) 210 #define ADVERTISED_Asym_Pause (1 << 14) 211 212 #define AUTONEG_DISABLE 0 213 #define AUTONEG_ENABLE 1 214 #define SPEED_10 10 215 #define SPEED_100 100 216 #define SPEED_1000 1000 217 #define SPEED_10000 10000 218 #define DUPLEX_HALF 0 219 #define DUPLEX_FULL 1 220 221 int ilog2(long x); 222 unsigned char *strstrip(unsigned char *s); 223 224 #endif /* __CXGBE_OSDEP_H */ 225