1*56b2bdd1SGireesh Nagabhushana /* 2*56b2bdd1SGireesh Nagabhushana * This file and its contents are supplied under the terms of the 3*56b2bdd1SGireesh Nagabhushana * Common Development and Distribution License ("CDDL"), version 1.0. 4*56b2bdd1SGireesh Nagabhushana * You may only use this file in accordance with the terms of version 5*56b2bdd1SGireesh Nagabhushana * 1.0 of the CDDL. 6*56b2bdd1SGireesh Nagabhushana * 7*56b2bdd1SGireesh Nagabhushana * A full copy of the text of the CDDL should have accompanied this 8*56b2bdd1SGireesh Nagabhushana * source. A copy of the CDDL is also available via the Internet at 9*56b2bdd1SGireesh Nagabhushana * http://www.illumos.org/license/CDDL. 10*56b2bdd1SGireesh Nagabhushana */ 11*56b2bdd1SGireesh Nagabhushana 12*56b2bdd1SGireesh Nagabhushana /* 13*56b2bdd1SGireesh Nagabhushana * This file is part of the Chelsio T4 support code. 14*56b2bdd1SGireesh Nagabhushana * 15*56b2bdd1SGireesh Nagabhushana * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved. 16*56b2bdd1SGireesh Nagabhushana * 17*56b2bdd1SGireesh Nagabhushana * This program is distributed in the hope that it will be useful, but WITHOUT 18*56b2bdd1SGireesh Nagabhushana * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19*56b2bdd1SGireesh Nagabhushana * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20*56b2bdd1SGireesh Nagabhushana * release for licensing terms and conditions. 21*56b2bdd1SGireesh Nagabhushana */ 22*56b2bdd1SGireesh Nagabhushana 23*56b2bdd1SGireesh Nagabhushana #include "common.h" 24*56b2bdd1SGireesh Nagabhushana 25*56b2bdd1SGireesh Nagabhushana uint32_t 26*56b2bdd1SGireesh Nagabhushana t4_read_reg(struct adapter *sc, uint32_t reg) 27*56b2bdd1SGireesh Nagabhushana { 28*56b2bdd1SGireesh Nagabhushana /* LINTED: E_BAD_PTR_CAST_ALIGN */ 29*56b2bdd1SGireesh Nagabhushana return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg))); 30*56b2bdd1SGireesh Nagabhushana } 31*56b2bdd1SGireesh Nagabhushana 32*56b2bdd1SGireesh Nagabhushana void 33*56b2bdd1SGireesh Nagabhushana t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 34*56b2bdd1SGireesh Nagabhushana { 35*56b2bdd1SGireesh Nagabhushana /* LINTED: E_BAD_PTR_CAST_ALIGN */ 36*56b2bdd1SGireesh Nagabhushana ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val); 37*56b2bdd1SGireesh Nagabhushana } 38*56b2bdd1SGireesh Nagabhushana 39*56b2bdd1SGireesh Nagabhushana void 40*56b2bdd1SGireesh Nagabhushana t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 41*56b2bdd1SGireesh Nagabhushana { 42*56b2bdd1SGireesh Nagabhushana *val = pci_config_get8(sc->pci_regh, reg); 43*56b2bdd1SGireesh Nagabhushana } 44*56b2bdd1SGireesh Nagabhushana 45*56b2bdd1SGireesh Nagabhushana void 46*56b2bdd1SGireesh Nagabhushana t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 47*56b2bdd1SGireesh Nagabhushana { 48*56b2bdd1SGireesh Nagabhushana pci_config_put8(sc->pci_regh, reg, val); 49*56b2bdd1SGireesh Nagabhushana } 50*56b2bdd1SGireesh Nagabhushana 51*56b2bdd1SGireesh Nagabhushana void 52*56b2bdd1SGireesh Nagabhushana t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 53*56b2bdd1SGireesh Nagabhushana { 54*56b2bdd1SGireesh Nagabhushana *val = pci_config_get16(sc->pci_regh, reg); 55*56b2bdd1SGireesh Nagabhushana } 56*56b2bdd1SGireesh Nagabhushana 57*56b2bdd1SGireesh Nagabhushana void 58*56b2bdd1SGireesh Nagabhushana t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 59*56b2bdd1SGireesh Nagabhushana { 60*56b2bdd1SGireesh Nagabhushana pci_config_put16(sc->pci_regh, reg, val); 61*56b2bdd1SGireesh Nagabhushana } 62*56b2bdd1SGireesh Nagabhushana 63*56b2bdd1SGireesh Nagabhushana void 64*56b2bdd1SGireesh Nagabhushana t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 65*56b2bdd1SGireesh Nagabhushana { 66*56b2bdd1SGireesh Nagabhushana *val = pci_config_get32(sc->pci_regh, reg); 67*56b2bdd1SGireesh Nagabhushana } 68*56b2bdd1SGireesh Nagabhushana 69*56b2bdd1SGireesh Nagabhushana void 70*56b2bdd1SGireesh Nagabhushana t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 71*56b2bdd1SGireesh Nagabhushana { 72*56b2bdd1SGireesh Nagabhushana pci_config_put32(sc->pci_regh, reg, val); 73*56b2bdd1SGireesh Nagabhushana } 74*56b2bdd1SGireesh Nagabhushana 75*56b2bdd1SGireesh Nagabhushana uint64_t 76*56b2bdd1SGireesh Nagabhushana t4_read_reg64(struct adapter *sc, uint32_t reg) 77*56b2bdd1SGireesh Nagabhushana { 78*56b2bdd1SGireesh Nagabhushana /* LINTED: E_BAD_PTR_CAST_ALIGN */ 79*56b2bdd1SGireesh Nagabhushana return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg))); 80*56b2bdd1SGireesh Nagabhushana } 81*56b2bdd1SGireesh Nagabhushana 82*56b2bdd1SGireesh Nagabhushana void 83*56b2bdd1SGireesh Nagabhushana t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 84*56b2bdd1SGireesh Nagabhushana { 85*56b2bdd1SGireesh Nagabhushana /* LINTED: E_BAD_PTR_CAST_ALIGN */ 86*56b2bdd1SGireesh Nagabhushana ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val); 87*56b2bdd1SGireesh Nagabhushana } 88*56b2bdd1SGireesh Nagabhushana 89*56b2bdd1SGireesh Nagabhushana struct port_info * 90*56b2bdd1SGireesh Nagabhushana adap2pinfo(struct adapter *sc, int idx) 91*56b2bdd1SGireesh Nagabhushana { 92*56b2bdd1SGireesh Nagabhushana return (sc->port[idx]); 93*56b2bdd1SGireesh Nagabhushana } 94*56b2bdd1SGireesh Nagabhushana 95*56b2bdd1SGireesh Nagabhushana void 96*56b2bdd1SGireesh Nagabhushana t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 97*56b2bdd1SGireesh Nagabhushana { 98*56b2bdd1SGireesh Nagabhushana bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL); 99*56b2bdd1SGireesh Nagabhushana } 100*56b2bdd1SGireesh Nagabhushana 101*56b2bdd1SGireesh Nagabhushana bool 102*56b2bdd1SGireesh Nagabhushana is_10G_port(const struct port_info *pi) 103*56b2bdd1SGireesh Nagabhushana { 104*56b2bdd1SGireesh Nagabhushana return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 105*56b2bdd1SGireesh Nagabhushana } 106*56b2bdd1SGireesh Nagabhushana 107*56b2bdd1SGireesh Nagabhushana struct sge_rxq * 108*56b2bdd1SGireesh Nagabhushana iq_to_rxq(struct sge_iq *iq) 109*56b2bdd1SGireesh Nagabhushana { 110*56b2bdd1SGireesh Nagabhushana return (container_of(iq, struct sge_rxq, iq)); 111*56b2bdd1SGireesh Nagabhushana } 112*56b2bdd1SGireesh Nagabhushana 113*56b2bdd1SGireesh Nagabhushana int 114*56b2bdd1SGireesh Nagabhushana t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m) 115*56b2bdd1SGireesh Nagabhushana { 116*56b2bdd1SGireesh Nagabhushana int rc; 117*56b2bdd1SGireesh Nagabhushana 118*56b2bdd1SGireesh Nagabhushana TXQ_LOCK(wrq); 119*56b2bdd1SGireesh Nagabhushana rc = t4_wrq_tx_locked(sc, wrq, m); 120*56b2bdd1SGireesh Nagabhushana TXQ_UNLOCK(wrq); 121*56b2bdd1SGireesh Nagabhushana return (rc); 122*56b2bdd1SGireesh Nagabhushana } 123