1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * This file is part of the Chelsio T1 Ethernet driver. 29 * 30 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 31 */ 32 33 #ifndef _CHELSIO_OSCHTOE_H 34 #define _CHELSIO_OSCHTOE_H 35 36 #pragma ident "%Z%%M% %I% %E% SMI" 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 typedef struct _pesge pesge; 43 44 /* looks like this should really be with mc5.h */ 45 #define DEFAULT_SERVER_REGION_LEN 256 46 #define DEFAULT_RT_REGION_LEN 1024 47 48 /* 49 * Bits used to configure driver behavior. 50 */ 51 #define CFGDMP_RSPQ 0x00000001 /* dump respq info */ 52 #define CFGDMP_CMDQ0 0x00000010 /* dump cmdq0 info */ 53 #define CFGDMP_CMDQ0MB 0x00000020 /* dump cmdq0 mbufs */ 54 #define CFGDMP_CMDQ1 0x00000040 /* dump cmdq1 info */ 55 #define CFGDMP_CMDQ1MB 0x00000080 /* dump cmdq1 mbufs */ 56 #define CFGDMP_FLQ0 0x00000100 /* dump flq0 info */ 57 #define CFGDMP_FLQ0MB 0x00000200 /* dump flq0 mbufs */ 58 #define CFGDMP_FLQ1 0x00000400 /* dump flq1 info */ 59 #define CFGDMP_FLQ1MB 0x00000800 /* dump flq1 mbufs */ 60 #define CFGDMP_ISRC 0x00001000 /* dump ISR 32 bit cause */ 61 #define CFGDMP_ISR 0x00002000 /* dump ISR info */ 62 #define CFGDMP_OUT 0x00004000 /* dump OUT info */ 63 #define CFGDMP_GMACC 0x00010000 /* dump GMAC cause bits */ 64 #define CFGDMP_PCIXC 0x00020000 /* dump PCIX cause bits */ 65 #define CFGDMP_TPC 0x00040000 /* dump TP cause bits */ 66 #define CFGDMP_MC5C 0x00080000 /* dump MC5 cause bits */ 67 68 #define CFGMD_RINGB 0x00100000 /* Store all packets in ring buffer */ 69 #define CFGMD_PROFILE 0x00200000 /* Enable driver profiling */ 70 71 #define CFGDMP_ERR 0x01000000 /* dump errors */ 72 #define CFGDMP_WRN 0x02000000 /* dump warnings */ 73 #define CFGDMP_STA 0x04000000 /* dump status info */ 74 #define CFGDMP_PTH 0x08000000 /* dump function paths */ 75 76 #define CFGMD_TUNNEL 0x10000000 /* Global tunnel mode ( 0-offload mode ) */ 77 #define CFGMD_144BIT 0x20000000 /* Puts MC5 in 144 bit mode */ 78 #define CFGMD_CPLBPF 0x40000000 /* Include CPL header when bpf_map called */ 79 80 /* 81 * Structure used to store drivers configuration information. 82 * Some of this information will be move out later or 83 * stored elsewhere. For now, it helps with development. 84 */ 85 typedef struct pe_config_data { 86 uint32_t gtm; /* run in Global Tunnel Mode */ 87 uint32_t global_config; /* override global debug value */ 88 89 uint32_t is_asic; 90 91 /* 92 * 5-auto-neg 93 * 2-1000Gbps(force); 94 * 1-100Gbps(force); 95 * 0-10Gbps(force) 96 */ 97 uint32_t link_speed; 98 99 uint32_t num_of_ports; /* Set the number of ports [1-4] */ 100 101 uint32_t tp_reset_cm; /* reset CM memory map */ 102 103 uint32_t phy_tx_fifo; /* phy's tx fifo depth */ 104 uint32_t phy_rx_fifo; /* phy's rx fifo depth */ 105 uint32_t phy_force_master; /* force link always in master mode */ 106 107 uint32_t mc5_rtbl_size; /* TCAM routing table size */ 108 uint32_t mc5_dbsvr_size; /* TCAM server size */ 109 uint32_t mc5_mode; /* 72 bit or 144 bit mode */ 110 uint32_t mc5_parity; /* Enable parity error checking */ 111 uint32_t mc5_issue_syn; /* Allow for transaction overlap */ 112 113 uint32_t packet_tracing; 114 115 uint32_t server_region_len; 116 uint32_t rt_region_len; 117 118 uint32_t offload_ip_cksum; /* on/off checksum offloading */ 119 uint32_t offload_udp_cksum; 120 uint32_t offload_tcp_cksum; 121 122 uint32_t sge_cmdq_sp; /* set sw schedule policy */ 123 uint32_t sge_cmdq_threshold; /* used w/ sw schedule policy */ 124 uint32_t sge_flq_threshold; /* set SGE's flq threshold register */ 125 126 uint32_t sge_cmdq0_cnt; /* set # entries of cmdq0 */ 127 uint32_t sge_cmdq1_cnt; /* set # entries of cmdq1 */ 128 uint32_t sge_flq0_cnt; /* set # entries of flq0 */ 129 uint32_t sge_flq1_cnt; /* set # entries of flq1 */ 130 uint32_t sge_respq_cnt; /* set # entries of respq */ 131 132 133 /* 134 * Update MAC stats automatically. 135 * Sometimes we don't want this to 136 * happen when debugging 137 */ 138 uint32_t stats; 139 140 /* 141 * Add microsecond delay to packets 142 * sent in Tx direction. This is useful 143 * in testing hardware. 144 */ 145 uint32_t tx_delay_us; 146 147 /* 148 * Can change chip revision support 149 * settting -1 default. Uses hardware 150 * lookup table. 151 * 0 force T1A 152 * 1 force T1B 153 */ 154 uint32_t chip; 155 156 /* 157 * Used to only initialize PCI so 158 * read/write registers work. The 159 * driver does not initialize anything 160 * of the HW blocks. 161 */ 162 uint32_t exit_early; 163 164 /* local ring buffer */ 165 uint32_t rb_num_of_entries; /* number of entries */ 166 uint32_t rb_size_of_entries; /* bytes size of an entry */ 167 uint32_t rb_flag; /* varies flags */ 168 169 /* Opt values used to store CATP options. */ 170 uint32_t type; 171 uint64_t cat_opt0; 172 uint64_t cat_opt1; 173 174 } pe_config_data_t; 175 176 struct pe_port_t { 177 uint8_t enaddr[6]; 178 struct cmac *mac; 179 struct cphy *phy; 180 struct link_config link_config; 181 u32 line_up; 182 }; 183 184 #define DBGASSERT(c) ASSERT(c) 185 186 #define t1_is_T1A(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1A) 187 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B) 188 #define t1_is_T1C(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1C) 189 190 #ifdef __cplusplus 191 } 192 #endif 193 194 #endif /* _CHELSIO_OSCHTOE_H */ 195