1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/types.h> 35 36 37 /* 38 * First section: 39 * Identification of the various Broadcom chips 40 * 41 * Note: the various ID values are *not* all unique ;-( 42 * 43 * Note: the presence of an ID here does *not* imply that the chip is 44 * supported. At this time, only the 5703C, 5704C, and 5704S devices 45 * used on the motherboards of certain Sun products are supported. 46 * 47 * Note: the revision-id values in the PCI revision ID register are 48 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 49 */ 50 51 #define VENDOR_ID_BROADCOM 0x14e4 52 #define VENDOR_ID_SUN 0x108e 53 54 #define DEVICE_ID_5700 0x1644 55 #define DEVICE_ID_5700x 0x0003 56 #define DEVICE_ID_5701 0x1645 57 #define DEVICE_ID_5702 0x16a6 58 #define DEVICE_ID_5702fe 0x164d 59 #define DEVICE_ID_5703C 0x1647 60 #define DEVICE_ID_5703S 0x16a7 61 #define DEVICE_ID_5703 0x16c7 62 #define DEVICE_ID_5704C 0x1648 63 #define DEVICE_ID_5704S 0x16a8 64 #define DEVICE_ID_5704 0x1649 65 #define DEVICE_ID_5705C 0x1653 66 #define DEVICE_ID_5705_2 0x1654 67 #define DEVICE_ID_5705M 0x165d 68 #define DEVICE_ID_5705MA3 0x165e 69 #define DEVICE_ID_5705F 0x166e 70 #define DEVICE_ID_5706 0x164a 71 #define DEVICE_ID_5780 0x166a 72 #define DEVICE_ID_5782 0x1696 73 #define DEVICE_ID_5787 0x169b 74 #define DEVICE_ID_5787M 0x1693 75 #define DEVICE_ID_5788 0x169c 76 #define DEVICE_ID_5789 0x169d 77 #define DEVICE_ID_5751 0x1677 78 #define DEVICE_ID_5751M 0x167d 79 #define DEVICE_ID_5752 0x1600 80 #define DEVICE_ID_5752M 0x1601 81 #define DEVICE_ID_5753 0x16fd 82 #define DEVICE_ID_5754 0x167a 83 #define DEVICE_ID_5755 0x167b 84 #define DEVICE_ID_5755M 0x1673 85 #define DEVICE_ID_5721 0x1659 86 #define DEVICE_ID_5722 0x165a 87 #define DEVICE_ID_5714C 0x1668 88 #define DEVICE_ID_5714S 0x1669 89 #define DEVICE_ID_5715C 0x1678 90 #define DEVICE_ID_5715S 0x1679 91 #define DEVICE_ID_5906 0x1712 92 #define DEVICE_ID_5906M 0x1713 93 94 #define REVISION_ID_5700_B0 0x10 95 #define REVISION_ID_5700_B2 0x12 96 #define REVISION_ID_5700_B3 0x13 97 #define REVISION_ID_5700_C0 0x20 98 #define REVISION_ID_5700_C1 0x21 99 #define REVISION_ID_5700_C2 0x22 100 101 #define REVISION_ID_5701_A0 0x08 102 #define REVISION_ID_5701_A2 0x12 103 #define REVISION_ID_5701_A3 0x15 104 105 #define REVISION_ID_5702_A0 0x00 106 107 #define REVISION_ID_5703_A0 0x00 108 #define REVISION_ID_5703_A1 0x01 109 #define REVISION_ID_5703_A2 0x02 110 111 #define REVISION_ID_5704_A0 0x00 112 #define REVISION_ID_5704_A1 0x01 113 #define REVISION_ID_5704_A2 0x02 114 #define REVISION_ID_5704_A3 0x03 115 #define REVISION_ID_5704_B0 0x10 116 117 #define REVISION_ID_5705_A0 0x00 118 #define REVISION_ID_5705_A1 0x01 119 #define REVISION_ID_5705_A2 0x02 120 #define REVISION_ID_5705_A3 0x03 121 122 #define REVISION_ID_5721_A0 0x00 123 #define REVISION_ID_5721_A1 0x01 124 125 #define REVISION_ID_5751_A0 0x00 126 #define REVISION_ID_5751_A1 0x01 127 128 #define REVISION_ID_5714_A0 0x00 129 #define REVISION_ID_5714_A1 0x01 130 #define REVISION_ID_5714_A2 0xA2 131 #define REVISION_ID_5714_A3 0xA3 132 133 #define REVISION_ID_5715_A0 0x00 134 #define REVISION_ID_5715_A1 0x01 135 #define REVISION_ID_5715_A2 0xA2 136 137 #define REVISION_ID_5715S_A0 0x00 138 #define REVISION_ID_5715S_A1 0x01 139 140 #define REVISION_ID_5754_A0 0x00 141 #define REVISION_ID_5754_A1 0x01 142 143 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 144 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 145 (bgep->chipid.device == DEVICE_ID_5701) ||\ 146 (bgep->chipid.device == DEVICE_ID_5702) ||\ 147 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 148 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 149 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 150 (bgep->chipid.device == DEVICE_ID_5703) ||\ 151 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 152 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 153 (bgep->chipid.device == DEVICE_ID_5704)) 154 155 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 156 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 157 (bgep->chipid.device == DEVICE_ID_5702fe)) 158 159 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 160 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 161 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 162 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 163 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 164 (bgep->chipid.device == DEVICE_ID_5780) ||\ 165 (bgep->chipid.device == DEVICE_ID_5782) ||\ 166 (bgep->chipid.device == DEVICE_ID_5788) ||\ 167 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 168 (bgep->chipid.device == DEVICE_ID_5754) ||\ 169 (bgep->chipid.device == DEVICE_ID_5755) ||\ 170 (bgep->chipid.device == DEVICE_ID_5753)) 171 172 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 173 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 174 (bgep->chipid.device == DEVICE_ID_5751) ||\ 175 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 176 (bgep->chipid.device == DEVICE_ID_5752) ||\ 177 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 178 (bgep->chipid.device == DEVICE_ID_5789)) 179 180 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 181 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 182 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 183 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 184 (bgep->chipid.device == DEVICE_ID_5715S)) 185 186 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 187 ((bgep->chipid.device == DEVICE_ID_5906) ||\ 188 (bgep->chipid.device == DEVICE_ID_5906M)) 189 190 /* 191 * Second section: 192 * Offsets of important registers & definitions for bits therein 193 */ 194 195 /* 196 * PCI-X registers & bits 197 */ 198 #define PCIX_CONF_COMM 0x42 199 #define PCIX_COMM_RELAXED 0x0002 200 201 /* 202 * Miscellaneous Host Control Register, in PCI config space 203 */ 204 #define PCI_CONF_BGE_MHCR 0x68 205 #define MHCR_CHIP_REV_MASK 0xffff0000 206 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 207 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 208 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 209 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 210 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 211 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 212 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 213 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 214 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 215 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 216 217 #define MHCR_CHIP_REV_5700_B0 0x71000000 218 #define MHCR_CHIP_REV_5700_B2 0x71020000 219 #define MHCR_CHIP_REV_5700_B3 0x71030000 220 #define MHCR_CHIP_REV_5700_C0 0x72000000 221 #define MHCR_CHIP_REV_5700_C1 0x72010000 222 #define MHCR_CHIP_REV_5700_C2 0x72020000 223 224 #define MHCR_CHIP_REV_5701_A0 0x00000000 225 #define MHCR_CHIP_REV_5701_A2 0x00020000 226 #define MHCR_CHIP_REV_5701_A3 0x00030000 227 #define MHCR_CHIP_REV_5701_A5 0x01050000 228 229 #define MHCR_CHIP_REV_5702_A0 0x10000000 230 #define MHCR_CHIP_REV_5702_A1 0x10010000 231 #define MHCR_CHIP_REV_5702_A2 0x10020000 232 233 #define MHCR_CHIP_REV_5703_A0 0x10000000 234 #define MHCR_CHIP_REV_5703_A1 0x10010000 235 #define MHCR_CHIP_REV_5703_A2 0x10020000 236 #define MHCR_CHIP_REV_5703_B0 0x11000000 237 #define MHCR_CHIP_REV_5703_B1 0x11010000 238 239 #define MHCR_CHIP_REV_5704_A0 0x20000000 240 #define MHCR_CHIP_REV_5704_A1 0x20010000 241 #define MHCR_CHIP_REV_5704_A2 0x20020000 242 #define MHCR_CHIP_REV_5704_A3 0x20030000 243 #define MHCR_CHIP_REV_5704_B0 0x21000000 244 245 #define MHCR_CHIP_REV_5705_A0 0x30000000 246 #define MHCR_CHIP_REV_5705_A1 0x30010000 247 #define MHCR_CHIP_REV_5705_A2 0x30020000 248 #define MHCR_CHIP_REV_5705_A3 0x30030000 249 #define MHCR_CHIP_REV_5705_A5 0x30050000 250 251 #define MHCR_CHIP_REV_5782_A0 0x30030000 252 #define MHCR_CHIP_REV_5782_A1 0x30030088 253 254 #define MHCR_CHIP_REV_5788_A1 0x30050000 255 256 #define MHCR_CHIP_REV_5751_A0 0x40000000 257 #define MHCR_CHIP_REV_5751_A1 0x40010000 258 259 #define MHCR_CHIP_REV_5721_A0 0x41000000 260 #define MHCR_CHIP_REV_5721_A1 0x41010000 261 262 #define MHCR_CHIP_REV_5714_A0 0x50000000 263 #define MHCR_CHIP_REV_5714_A1 0x90010000 264 265 #define MHCR_CHIP_REV_5715_A0 0x50000000 266 #define MHCR_CHIP_REV_5715_A1 0x90010000 267 268 #define MHCR_CHIP_REV_5715S_A0 0x50000000 269 #define MHCR_CHIP_REV_5715S_A1 0x90010000 270 271 #define MHCR_CHIP_REV_5754_A0 0xb0000000 272 #define MHCR_CHIP_REV_5754_A1 0xb0010000 273 274 #define MHCR_CHIP_REV_5787_A0 0xb0000000 275 #define MHCR_CHIP_REV_5787_A1 0xb0010000 276 #define MHCR_CHIP_REV_5787_A2 0xb0020000 277 278 #define MHCR_CHIP_REV_5755_A0 0xa0000000 279 #define MHCR_CHIP_REV_5755_A1 0xa0010000 280 281 #define MHCR_CHIP_REV_5906_A0 0xc0000000 282 #define MHCR_CHIP_REV_5906_A1 0xc0010000 283 #define MHCR_CHIP_REV_5906_A2 0xc0020000 284 285 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 286 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 287 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 288 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 289 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 290 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 291 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 292 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 293 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 294 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 295 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 296 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 297 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 298 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 299 300 301 /* 302 * PCI DMA read/write Control Register, in PCI config space 303 * 304 * Note that several fields previously defined here have been deleted 305 * as they are not implemented in the 5703/4. 306 * 307 * Note: the value of this register is critical. It is possible to 308 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 309 * by programming the wrong value. The value #defined below has been 310 * tested and shown to avoid all known problems. If it is to be changed, 311 * correct operation must be reverified on all supported platforms. 312 * 313 * In particular, we set both watermark fields to 2xCacheLineSize (128) 314 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 315 * with Tomatillo's internal pipelines, that otherwise result in stalls, 316 * repeated retries, and DTOs. 317 */ 318 #define PCI_CONF_BGE_PDRWCR 0x6c 319 #define PDRWCR_RWCMD_MASK 0xFF000000 320 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 321 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 322 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 323 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 324 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 325 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 326 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 327 328 /* 329 * These are the actual values to be put into the fields shown above 330 */ 331 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 332 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 333 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 334 #define PDRWCR_MIN_BEATS 0x00000000 335 336 #define PDRWCR_VAR_DEFAULT 0x761b0000 337 #define PDRWCR_VAR_5721 0x76180000 338 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 339 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 340 341 /* 342 * PCI State Register, in PCI config space 343 * 344 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 345 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 346 */ 347 #define PCI_CONF_BGE_PCISTATE 0x70 348 #define PCISTATE_RETRY_SAME_DMA 0x00002000 349 #define PCISTATE_FLAT_VIEW 0x00000100 350 #define PCISTATE_EXT_ROM_RETRY 0x00000040 351 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 352 #define PCISTATE_BUS_IS_32_BIT 0x00000010 353 #define PCISTATE_BUS_IS_FAST 0x00000008 354 #define PCISTATE_BUS_IS_PCI 0x00000004 355 #define PCISTATE_INTA_STATE 0x00000002 356 #define PCISTATE_FORCE_RESET 0x00000001 357 358 /* 359 * PCI Clock Control Register, in PCI config space 360 */ 361 #define PCI_CONF_BGE_CLKCTL 0x74 362 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 363 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 364 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 365 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 366 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 367 #define CLKCTL_PCIE_A0_FIX 0x00101000 368 369 /* 370 * Dual MAC Control Register, in PCI config space 371 */ 372 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 373 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 374 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 375 376 /* 377 * Register Indirect Access Address Register, 0x78 in PCI config 378 * space. Once this is set, accesses to the Register Indirect 379 * Access Data Register (0x80) refer to the register whose address 380 * is given by *this* register. This allows access to all the 381 * operating registers, while using only config space accesses. 382 * 383 * Note that the address written to the RIIAR should lie in one 384 * of the following ranges: 385 * 0x00000000 <= address < 0x00008000 (regular registers) 386 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 387 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 388 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 389 */ 390 #define PCI_CONF_BGE_RIAAR 0x78 391 #define PCI_CONF_BGE_RIADR 0x80 392 393 #define RIAAR_REGISTER_MIN 0x00000000 394 #define RIAAR_REGISTER_MAX 0x00008000 395 #define RIAAR_RX_SCRATCH_MIN 0x00030000 396 #define RIAAR_RX_SCRATCH_MAX 0x00034000 397 #define RIAAR_TX_SCRATCH_MIN 0x00034000 398 #define RIAAR_TX_SCRATCH_MAX 0x00038000 399 #define RIAAR_RXROM_MIN 0x00038000 400 #define RIAAR_RXROM_MAX 0x00038800 401 402 /* 403 * Memory Window Base Address Register, 0x7c in PCI config space 404 * Once this is set, accesses to the Memory Window Data Access Register 405 * (0x84) refer to the word of NIC-local memory whose address is given 406 * by this register. When used in this way, the whole of the address 407 * written to this register is significant. 408 * 409 * This register also provides the 32K-aligned base address for a 32K 410 * region of NIC-local memory that the host can directly address in 411 * the upper 32K of the 64K of PCI memory space allocated to the chip. 412 * In this case, the bottom 15 bits of the register are ignored. 413 * 414 * Note that the address written to the MWBAR should lie in the range 415 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 416 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 417 * memory were present, but it's only supported on the 5700, not the 418 * 5701/5703/5704. 419 */ 420 #define PCI_CONF_BGE_MWBAR 0x7c 421 #define PCI_CONF_BGE_MWDAR 0x84 422 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 423 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 424 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 425 426 /* 427 * The PCI express device control register and device status register 428 * which are only applicable on BCM5751 and BCM5721. 429 */ 430 #define PCI_CONF_DEV_CTRL 0xd8 431 #define READ_REQ_SIZE_MAX 0x5000 432 #define DEV_CTRL_NO_SNOOP 0x0800 433 #define DEV_CTRL_RELAXED 0x0010 434 435 #define PCI_CONF_DEV_STUS 0xda 436 #define DEVICE_ERROR_STUS 0xf 437 438 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 439 440 /* 441 * Where to find things in NIC-local (on-chip) memory 442 */ 443 #define NIC_MEM_SEND_RINGS 0x0100 444 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 445 #define NIC_MEM_RECV_RINGS 0x0200 446 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 447 #define NIC_MEM_STATISTICS 0x0300 448 #define NIC_MEM_STATISTICS_SIZE 0x0800 449 #define NIC_MEM_STATUS_BLOCK 0x0b00 450 #define NIC_MEM_STATUS_SIZE 0x0050 451 #define NIC_MEM_GENCOMM 0x0b50 452 453 454 /* 455 * Note: the (non-bogus) values below are appropriate for systems 456 * without external memory. They would be different on a 5700 with 457 * external memory. 458 * 459 * Note: The higher send ring addresses and the mini ring shadow 460 * buffer address are dummies - systems without external memory 461 * are limited to 4 send rings and no mini receive ring. 462 */ 463 #define NIC_MEM_SHADOW_DMA 0x2000 464 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 465 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 466 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 467 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 468 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 469 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 470 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 471 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 472 473 /* 474 * Put this in the GENCOMM port to tell the firmware not to run PXE 475 */ 476 #define T3_MAGIC_NUMBER 0x4b657654u 477 478 /* 479 * The remaining registers appear in the low 32K of regular 480 * PCI Memory Address Space 481 */ 482 483 /* 484 * All the state machine control registers below have at least a 485 * <RESET> bit and an <ENABLE> bit as defined below. Some also 486 * have an <ATTN_ENABLE> bit. 487 */ 488 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 489 #define STATE_MACHINE_ENABLE_BIT 0x00000002 490 #define STATE_MACHINE_RESET_BIT 0x00000001 491 492 #define TRANSMIT_MAC_MODE_REG 0x045c 493 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 494 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 495 #define SEND_BD_SELECTOR_MODE_REG 0x1400 496 #define SEND_BD_INITIATOR_MODE_REG 0x1800 497 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 498 499 #define RECEIVE_MAC_MODE_REG 0x0468 500 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 501 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 502 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 503 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 504 #define RCV_BD_COMPLETION_MODE_REG 0x3000 505 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 506 507 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 508 #define HOST_COALESCE_MODE_REG 0x3c00 509 #define MEMORY_ARBITER_MODE_REG 0x4000 510 #define BUFFER_MANAGER_MODE_REG 0x4400 511 #define READ_DMA_MODE_REG 0x4800 512 #define WRITE_DMA_MODE_REG 0x4c00 513 #define DMA_COMPLETION_MODE_REG 0x6400 514 515 /* 516 * Other bits in some of the above state machine control registers 517 */ 518 519 /* 520 * Transmit MAC Mode Register 521 * (TRANSMIT_MAC_MODE_REG, 0x045c) 522 */ 523 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 524 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 525 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 526 527 /* 528 * Receive MAC Mode Register 529 * (RECEIVE_MAC_MODE_REG, 0x0468) 530 */ 531 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 532 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 533 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 534 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 535 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 536 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 537 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 538 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 539 540 /* 541 * Receive BD Initiator Mode Register 542 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 543 * 544 * Each of these bits controls whether ATTN is asserted 545 * on a particular condition 546 */ 547 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 548 549 /* 550 * Receive Data & Receive BD Initiator Mode Register 551 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 552 * 553 * Each of these bits controls whether ATTN is asserted 554 * on a particular condition 555 */ 556 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 557 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 558 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 559 560 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 561 562 /* 563 * Host Coalescing Mode Control Register 564 * (HOST_COALESCE_MODE_REG, 0x3c00) 565 */ 566 #define COALESCE_64_BYTE_RINGS 12 567 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 568 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 569 #define COALESCE_CLR_TICKS_TX 0x00000400 570 #define COALESCE_CLR_TICKS_RX 0x00000200 571 #define COALESCE_32_BYTE_STATUS 0x00000100 572 #define COALESCE_64_BYTE_STATUS 0x00000080 573 #define COALESCE_NOW 0x00000008 574 575 /* 576 * Memory Arbiter Mode Register 577 * (MEMORY_ARBITER_MODE_REG, 0x4000) 578 */ 579 #define MEMORY_ARBITER_ENABLE 0x00000002 580 581 /* 582 * Buffer Manager Mode Register 583 * (BUFFER_MANAGER_MODE_REG, 0x4400) 584 * 585 * In addition to the usual error-attn common to most state machines 586 * this register has a separate bit for attn on running-low-on-mbufs 587 */ 588 #define BUFF_MGR_TEST_MODE 0x00000008 589 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 590 591 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 592 593 /* 594 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 595 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 596 * 597 * These registers each contain a 2-bit priority field, which controls 598 * the relative priority of that type of DMA (read vs. write vs. MSI), 599 * and a set of bits that control whether ATTN is asserted on each 600 * particular condition 601 */ 602 #define DMA_PRIORITY_MASK 0xc0000000 603 #define DMA_PRIORITY_SHIFT 30 604 #define ALL_DMA_ATTN_BITS 0x000003fc 605 606 /* 607 * BCM5755, 5755M, 5906, 5906M only 608 * 1 - Enable Fix. Device will send out the status block before 609 * the interrupt message 610 * 0 - Disable fix. Device will send out the interrupt message 611 * before the status block 612 */ 613 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 614 615 /* 616 * End of state machine control register definitions 617 */ 618 619 620 /* 621 * High priority mailbox registers. 622 * Mailbox Registers (8 bytes each, but high half unused) 623 */ 624 #define INTERRUPT_MBOX_0_REG 0x0200 625 #define INTERRUPT_MBOX_1_REG 0x0208 626 #define INTERRUPT_MBOX_2_REG 0x0210 627 #define INTERRUPT_MBOX_3_REG 0x0218 628 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 629 630 /* 631 * Low priority mailbox registers, for BCM5906, BCM5906M. 632 */ 633 #define INTERRUPT_LP_MBOX_0_REG 0x5800 634 635 /* 636 * Ring Producer/Consumer Index (Mailbox) Registers 637 */ 638 #define RECV_STD_PROD_INDEX_REG 0x0268 639 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 640 #define RECV_MINI_PROD_INDEX_REG 0x0278 641 #define RECV_RING_CONS_INDEX_REGS 0x0280 642 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 643 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 644 645 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 646 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 647 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 648 649 /* 650 * Ethernet MAC Mode Register 651 */ 652 #define ETHERNET_MAC_MODE_REG 0x0400 653 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 654 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 655 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 656 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 657 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 658 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 659 #define ETHERNET_MODE_SEND_CFGS 0x00020000 660 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 661 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 662 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 663 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 664 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 665 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 666 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 667 #define ETHERNET_MODE_MAX_DEFER 0x00000200 668 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 669 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 670 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 671 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 672 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 673 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 674 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 675 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 676 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 677 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 678 679 /* 680 * Ethernet MAC Status & Event Registers 681 */ 682 #define ETHERNET_MAC_STATUS_REG 0x0404 683 #define ETHERNET_STATUS_MI_INT 0x00800000 684 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 685 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 686 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 687 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 688 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 689 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 690 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 691 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 692 693 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 694 #define ETHERNET_EVENT_MI_INT 0x00800000 695 #define ETHERNET_EVENT_LINK_INT 0x00001000 696 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 697 698 /* 699 * Ethernet MAC LED Control Register 700 * 701 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 702 * the external LED driver circuitry is wired up to assume that this mode 703 * will always be selected. Software must not change it! 704 */ 705 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 706 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 707 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 708 #define LED_CONTROL_LED_MODE_MASK 0x00001800 709 #define LED_CONTROL_LED_MODE_5700 0x00000000 710 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 711 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 712 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 713 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 714 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 715 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 716 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 717 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 718 #define LED_CONTROL_TRAFFIC_LED 0x00000020 719 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 720 #define LED_CONTROL_10MBPS_LED 0x00000008 721 #define LED_CONTROL_100MBPS_LED 0x00000004 722 #define LED_CONTROL_1000MBPS_LED 0x00000002 723 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 724 #define LED_CONTROL_DEFAULT 0x02000800 725 726 /* 727 * MAC Address registers 728 * 729 * These four eight-byte registers each hold one unicast address 730 * (six bytes), right justified & zero-filled on the left. 731 * They will normally all be set to the same value, as a station 732 * usually only has one h/w address. The value in register 0 is 733 * used for pause packets; any of the four can be specified for 734 * substitution into other transmitted packets if required. 735 */ 736 #define MAC_ADDRESS_0_REG 0x0410 737 #define MAC_ADDRESS_1_REG 0x0418 738 #define MAC_ADDRESS_2_REG 0x0420 739 #define MAC_ADDRESS_3_REG 0x0428 740 741 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 742 #define MAC_ADDRESS_REGS_MAX 4 743 744 /* 745 * More MAC Registers ... 746 */ 747 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 748 #define MAC_RX_MTU_SIZE_REG 0x043c 749 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 750 #define MAC_TX_LENGTHS_REG 0x0464 751 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 752 753 /* 754 * MII access registers 755 */ 756 #define MI_COMMS_REG 0x044c 757 #define MI_COMMS_START 0x20000000 758 #define MI_COMMS_READ_FAILED 0x10000000 759 #define MI_COMMS_COMMAND_MASK 0x0c000000 760 #define MI_COMMS_COMMAND_READ 0x08000000 761 #define MI_COMMS_COMMAND_WRITE 0x04000000 762 #define MI_COMMS_ADDRESS_MASK 0x03e00000 763 #define MI_COMMS_ADDRESS_SHIFT 21 764 #define MI_COMMS_REGISTER_MASK 0x001f0000 765 #define MI_COMMS_REGISTER_SHIFT 16 766 #define MI_COMMS_DATA_MASK 0x0000ffff 767 #define MI_COMMS_DATA_SHIFT 0 768 769 #define MI_STATUS_REG 0x0450 770 #define MI_STATUS_10MBPS 0x00000002 771 #define MI_STATUS_LINK 0x00000001 772 773 #define MI_MODE_REG 0x0454 774 #define MI_MODE_CLOCK_MASK 0x001f0000 775 #define MI_MODE_AUTOPOLL 0x00000010 776 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 777 #define MI_MODE_DEFAULT 0x000c0000 778 779 #define MI_AUTOPOLL_STATUS_REG 0x0458 780 #define MI_AUTOPOLL_ERROR 0x00000001 781 782 #define TRANSMIT_MAC_STATUS_REG 0x0460 783 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 784 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 785 #define TRANSMIT_STATUS_LINK_UP 0x00000008 786 #define TRANSMIT_STATUS_SENT_XON 0x00000004 787 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 788 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 789 790 #define RECEIVE_MAC_STATUS_REG 0x046c 791 #define RECEIVE_STATUS_RCVD_XON 0x00000004 792 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 793 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 794 795 /* 796 * These four-byte registers constitute a hash table for deciding 797 * whether to accept incoming multicast packets. The bits are 798 * numbered in big-endian fashion, from hash 0 => the MSB of 799 * register 0 to hash 127 => the LSB of the highest-numbered 800 * register. 801 * 802 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 803 * enabled by setting the appropriate bit in the Rx MAC mode 804 * register. Otherwise, and on all earlier chips, the table 805 * is only 128 bits (registers 0-3). 806 */ 807 #define MAC_HASH_0_REG 0x0470 808 #define MAC_HASH_1_REG 0x0474 809 #define MAC_HASH_2_REG 0x0478 810 #define MAC_HASH_3_REG 0x047c 811 #define MAC_HASH_4_REG 0x???? 812 #define MAC_HASH_5_REG 0x???? 813 #define MAC_HASH_6_REG 0x???? 814 #define MAC_HASH_7_REG 0x???? 815 #define MAC_HASH_REG(n) (0x470+4*(n)) 816 817 /* 818 * Receive Rules Registers: 16 pairs of control+mask/value pairs 819 */ 820 #define RCV_RULES_CONTROL_0_REG 0x0480 821 #define RCV_RULES_MASK_0_REG 0x0484 822 #define RCV_RULES_CONTROL_15_REG 0x04f8 823 #define RCV_RULES_MASK_15_REG 0x04fc 824 #define RCV_RULES_CONFIG_REG 0x0500 825 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 826 827 #define RECV_RULES_NUM_MAX 16 828 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 829 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 830 831 #define RECV_RULE_CTL_ENABLE 0x80000000 832 #define RECV_RULE_CTL_AND 0x40000000 833 #define RECV_RULE_CTL_P1 0x20000000 834 #define RECV_RULE_CTL_P2 0x10000000 835 #define RECV_RULE_CTL_P3 0x08000000 836 #define RECV_RULE_CTL_MASK 0x04000000 837 #define RECV_RULE_CTL_DISCARD 0x02000000 838 #define RECV_RULE_CTL_MAP 0x01000000 839 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 840 #define RECV_RULE_CTL_OP 0x00030000 841 #define RECV_RULE_CTL_OP_EQ 0x00000000 842 #define RECV_RULE_CTL_OP_NEQ 0x00010000 843 #define RECV_RULE_CTL_OP_GREAT 0x00020000 844 #define RECV_RULE_CTL_OP_LESS 0x00030000 845 #define RECV_RULE_CTL_HEADER 0x0000e000 846 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 847 #define RECV_RULE_CTL_HEADER_IP 0x00002000 848 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 849 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 850 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 851 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 852 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 853 RECV_RULE_CTL_CLASS_BITS) 854 #define RECV_RULE_CTL_OFFSET 0x000000ff 855 856 /* 857 * Receive Rules definition 858 */ 859 #define RULE_MATCH_TO_RING 2 860 /* ring that traffic will go into when recv rule matches. */ 861 /* value is between 1 and 16, not 0 and 15 */ 862 863 #define IPHEADER_PROTO_OFFSET 0x08 864 #define IPHEADER_SIP_OFFSET 0x0c 865 866 #define RULE_PROTO_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_MASK | \ 867 RECV_RULE_CTL_OP_EQ | \ 868 RECV_RULE_CTL_HEADER_IP | \ 869 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 870 IPHEADER_PROTO_OFFSET) 871 #define RULE_TCP_MASK_VALUE 0x00ff0006 872 #define RULE_UDP_MASK_VALUE 0x00ff0011 873 #define RULE_ICMP_MASK_VALUE 0x00ff0001 874 875 #define RULE_SIP_ADDR 0x0a000001 876 /* ip address in 32-bit integer,such as, 0x0a000001 is "10.0.0.1" */ 877 878 #define RULE_SIP_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 879 RECV_RULE_CTL_HEADER_IP | \ 880 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 881 IPHEADER_SIP_OFFSET) 882 #define RULE_SIP_MASK_VALUE RULE_SIP_ADDR 883 884 /* 885 * 1000BaseX low-level access registers 886 */ 887 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 888 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 889 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 890 #define TX_1000BASEX_AUTONEG_REG 0x0444 891 #define RX_1000BASEX_AUTONEG_REG 0x0448 892 893 /* 894 * Autoneg code bits for the 1000BASE-X AUTONEG registers 895 */ 896 #define AUTONEG_CODE_PAUSE 0x00008000 897 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 898 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 899 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 900 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 901 #define AUTONEG_CODE_FAULT_MASK 0x00000030 902 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 903 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 904 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 905 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 906 907 /* 908 * SerDes Registers (5703S/5704S only) 909 */ 910 #define SERDES_CONTROL_REG 0x0590 911 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 912 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 913 #define SERDES_CONTROL_TX_DISABLE 0x00004000 914 #define SERDES_STATUS_REG 0x0594 915 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 916 #define SERDES_STATUS_RXSTAT 0x000000ff 917 918 /* 919 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 920 */ 921 #define STAT_IFHCOUT_OCTETS_REG 0x0800 922 #define STAT_ETHER_COLLIS_REG 0x0808 923 #define STAT_OUTXON_SENT_REG 0x080c 924 #define STAT_OUTXOFF_SENT_REG 0x0810 925 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 926 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 927 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 928 #define STAT_DOT3_DEFERED_TX_REG 0x0824 929 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 930 #define STAT_DOT3_LATE_COLLI_REG 0x0830 931 #define STAT_IFHCOUT_UPKGS_REG 0x086c 932 #define STAT_IFHCOUT_MPKGS_REG 0x0870 933 #define STAT_IFHCOUT_BPKGS_REG 0x0874 934 935 #define STAT_IFHCIN_OCTETS_REG 0x0880 936 #define STAT_ETHER_FRAGMENT_REG 0x0888 937 #define STAT_IFHCIN_UPKGS_REG 0x088c 938 #define STAT_IFHCIN_MPKGS_REG 0x0890 939 #define STAT_IFHCIN_BPKGS_REG 0x0894 940 941 #define STAT_DOT3_FCS_ERR_REG 0x0898 942 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 943 #define STAT_XON_PAUSE_RX_REG 0x08a0 944 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 945 #define STAT_MAC_CTRL_RX_REG 0x08a8 946 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 947 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 948 #define STAT_ETHER_JABBERS_REG 0x08b4 949 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 950 #define SIZE_OF_STATISTIC_REG 0x1B 951 /* 952 * Send Data Initiator Registers 953 */ 954 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 955 #define SEND_INIT_STATS_ZERO 0x00000010 956 #define SEND_INIT_STATS_FLUSH 0x00000008 957 #define SEND_INIT_STATS_CLEAR 0x00000004 958 #define SEND_INIT_STATS_FASTER 0x00000002 959 #define SEND_INIT_STATS_ENABLE 0x00000001 960 961 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 962 963 /* 964 * Send Buffer Descriptor Selector Control Registers 965 */ 966 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 967 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 968 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 969 970 /* 971 * Receive List Placement Registers 972 */ 973 #define RCV_LP_CONFIG_REG 0x2010 974 #define RCV_LP_CONFIG_DEFAULT 0x00000009 975 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 976 977 #define RCV_LP_STATS_CONTROL_REG 0x2014 978 #define RCV_LP_STATS_ZERO 0x00000010 979 #define RCV_LP_STATS_FLUSH 0x00000008 980 #define RCV_LP_STATS_CLEAR 0x00000004 981 #define RCV_LP_STATS_FASTER 0x00000002 982 #define RCV_LP_STATS_ENABLE 0x00000001 983 984 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 985 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 986 987 /* 988 * Receive Data & BD Initiator Registers 989 */ 990 #define RCV_INITIATOR_STATUS_REG 0x2404 991 992 /* 993 * Receive Buffer Descriptor Ring Control Block Registers 994 * NB: sixteen bytes (128 bits) each 995 */ 996 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 997 #define STD_RCV_BD_RING_RCB_REG 0x2450 998 #define MINI_RCV_BD_RING_RCB_REG 0x2460 999 1000 /* 1001 * Receive Buffer Descriptor Ring Replenish Threshold Registers 1002 */ 1003 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 1004 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 1005 #define STD_RCV_BD_REPLENISH_REG 0x2c18 1006 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 1007 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 1008 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 1009 1010 /* 1011 * Host Coalescing Engine Control Registers 1012 */ 1013 #define RCV_COALESCE_TICKS_REG 0x3c08 1014 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1015 #define SEND_COALESCE_TICKS_REG 0x3c0c 1016 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1017 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1018 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1019 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1020 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1021 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1022 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1023 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1024 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1025 #define RCV_COALESCE_INT_BD_REG 0x3c20 1026 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1027 #define SEND_COALESCE_INT_BD_REG 0x3c24 1028 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1029 #define STATISTICS_TICKS_REG 0x3c28 1030 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1031 #define STATISTICS_HOST_ADDR_REG 0x3c30 1032 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1033 #define STATISTICS_BASE_ADDR_REG 0x3c40 1034 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1035 #define FLOW_ATTN_REG 0x3c48 1036 1037 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1038 #define NIC_STD_RECV_INDEX_REG 0x3c54 1039 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1040 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1041 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1042 1043 /* 1044 * Mbuf Pool Initialisation & Watermark Registers 1045 * 1046 * There are some conflicts in the PRM; compare the recommendations 1047 * on pp. 115, 236, and 339. The values here were recommended by 1048 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1049 */ 1050 #define BUFFER_MANAGER_STATUS_REG 0x4404 1051 #define MBUF_POOL_BASE_REG 0x4408 1052 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1053 #define MBUF_POOL_BASE_5721 0x00010000 1054 #define MBUF_POOL_BASE_5704 0x00010000 1055 #define MBUF_POOL_BASE_5705 0x00010000 1056 #define MBUF_POOL_LENGTH_REG 0x440c 1057 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1058 #define MBUF_POOL_LENGTH_5704 0x00010000 1059 #define MBUF_POOL_LENGTH_5705 0x00008000 1060 #define MBUF_POOL_LENGTH_5721 0x00008000 1061 #define RDMA_MBUF_LOWAT_REG 0x4410 1062 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1063 #define RDMA_MBUF_LOWAT_5705 0x00000000 1064 #define RDMA_MBUF_LOWAT_5906 0x00000000 1065 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1066 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1067 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1068 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1069 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1070 #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1071 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1072 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1073 #define MBUF_HIWAT_REG 0x4418 1074 #define MBUF_HIWAT_DEFAULT 0x00000060 1075 #define MBUF_HIWAT_5705 0x00000060 1076 #define MBUF_HIWAT_5906 0x00000010 1077 #define MBUF_HIWAT_JUMBO 0x0000017c 1078 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1079 1080 /* 1081 * DMA Descriptor Pool Initialisation & Watermark Registers 1082 */ 1083 #define DMAD_POOL_BASE_REG 0x442c 1084 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1085 #define DMAD_POOL_LENGTH_REG 0x4430 1086 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1087 #define DMAD_POOL_LOWAT_REG 0x4434 1088 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1089 #define DMAD_POOL_HIWAT_REG 0x4438 1090 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1091 1092 /* 1093 * More threshold/watermark registers ... 1094 */ 1095 #define RECV_FLOW_THRESHOLD_REG 0x4458 1096 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1097 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1098 1099 /* 1100 * Read/Write DMA Status Registers 1101 */ 1102 #define READ_DMA_STATUS_REG 0x4804 1103 #define WRITE_DMA_STATUS_REG 0x4c04 1104 1105 /* 1106 * RX/TX RISC Registers 1107 */ 1108 #define RX_RISC_MODE_REG 0x5000 1109 #define RX_RISC_STATE_REG 0x5004 1110 #define RX_RISC_PC_REG 0x501c 1111 #define TX_RISC_MODE_REG 0x5400 1112 #define TX_RISC_STATE_REG 0x5404 1113 #define TX_RISC_PC_REG 0x541c 1114 1115 /* 1116 * V? RISC Registerss 1117 */ 1118 #define VCPU_STATUS_REG 0x5100 1119 #define VCPU_INIT_DONE 0x04000000 1120 #define VCPU_DRV_RESET 0x08000000 1121 1122 #define VCPU_EXT_CTL 0x6890 1123 #define VCPU_EXT_CTL_HALF 0x00400000 1124 1125 #define FTQ_RESET_REG 0x5c00 1126 1127 #define MSI_MODE_REG 0x6000 1128 #define MSI_PRI_HIGHEST 0xc0000000 1129 #define MSI_MSI_ENABLE 0x00000002 1130 #define MSI_ERROR_ATTENTION 0x0000001c 1131 1132 #define MSI_STATUS_REG 0x6004 1133 1134 #define MODE_CONTROL_REG 0x6800 1135 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1136 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1137 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1138 #define MODE_INT_ON_DMA_ATTN 0x08000000 1139 #define MODE_INT_ON_MAC_ATTN 0x04000000 1140 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1141 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1142 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1143 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1144 #define MODE_HOST_SEND_BDS 0x00020000 1145 #define MODE_HOST_STACK_UP 0x00010000 1146 #define MODE_FORCE_32_BIT_PCI 0x00008000 1147 #define MODE_NO_INT_ON_RECV 0x00004000 1148 #define MODE_NO_INT_ON_SEND 0x00002000 1149 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1150 #define MODE_NO_CRC 0x00000400 1151 #define MODE_NO_FRAME_CRACKING 0x00000200 1152 #define MODE_WORD_SWAP_FRAME 0x00000020 1153 #define MODE_BYTE_SWAP_FRAME 0x00000010 1154 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1155 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1156 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1157 1158 /* 1159 * Miscellaneous Configuration Register 1160 * 1161 * This contains various bits relating to power control (which differ 1162 * among different members of the chip family), but the important bits 1163 * for our purposes are the RESET bit and the Timer Prescaler field. 1164 * 1165 * The RESET bit in this register serves to reset the whole chip, even 1166 * including the PCI interface(!) Once it's set, the chip will not 1167 * respond to ANY accesses -- not even CONFIG space -- until the reset 1168 * completes internally. According to the PRM, this should take less 1169 * than 100us. Any access during this period will get a bus error. 1170 * 1171 * The Timer Prescaler field must be programmed so that the timer period 1172 * is as near as possible to 1us. The value in this field should be 1173 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1174 * the Core Clock should always be 66MHz (independently of the bus speed, 1175 * at least for PCI rather than PCI-X), so this register must be set to 1176 * the value 0x82 ((66-1) << 1). 1177 */ 1178 #define CORE_CLOCK_MHZ 66 1179 #define MISC_CONFIG_REG 0x6804 1180 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1181 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1182 #define MISC_CONFIG_POWERDOWN 0x00100000 1183 #define MISC_CONFIG_POWER_STATE 0x00060000 1184 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1185 #define MISC_CONFIG_RESET_BIT 0x00000001 1186 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1187 #define MISC_CONFIG_EPHY_IDDQ 0x00200000 1188 1189 /* 1190 * Miscellaneous Local Control Register (MLCR) 1191 */ 1192 #define MISC_LOCAL_CONTROL_REG 0x6808 1193 #define MLCR_PCI_CTRL_SELECT 0x10000000 1194 #define MLCR_LEGACY_PCI_MODE 0x08000000 1195 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1196 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1197 #define MLCR_SSRAM_TYPE 0x00400000 1198 #define MLCR_BANK_SELECT 0x00200000 1199 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1200 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1201 1202 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1203 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1204 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1205 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1206 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1207 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1208 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1209 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1210 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1211 1212 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1213 #define MLCR_SET_INT 0x00000004 /* W/O */ 1214 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1215 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1216 1217 /* 1218 * This value defines all GPIO bits as INPUTS, but sets their default 1219 * values as outputs to HIGH, on the assumption that external circuits 1220 * (if any) will probably be active-LOW with passive pullups. 1221 * 1222 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1223 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1224 * enable writing. Otherwise, the SEEPROM is protected. 1225 */ 1226 #define MLCR_DEFAULT 0x0101c000 1227 #define MLCR_DEFAULT_5714 0x1901c000 1228 1229 /* 1230 * Serial EEPROM Data/Address Registers (auto-access mode) 1231 */ 1232 #define SERIAL_EEPROM_DATA_REG 0x683c 1233 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1234 #define SEEPROM_ACCESS_READ 0x80000000 1235 #define SEEPROM_ACCESS_WRITE 0x00000000 1236 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1237 #define SEEPROM_ACCESS_RESET 0x20000000 1238 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1239 #define SEEPROM_ACCESS_START 0x02000000 1240 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1241 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1242 1243 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1244 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1245 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1246 1247 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1248 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1249 1250 /* 1251 * "Linearised" address mask, treating multiple devices as consecutive 1252 */ 1253 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1254 1255 /* 1256 * Non-Volatile Memory Interface Registers 1257 * Note: on chips that support the flash interface (5702+), flash is the 1258 * default and the legacy seeprom interface must be explicitly enabled 1259 * if required. On older chips (5700/01), SEEPROM is the default (and 1260 * only) non-volatile memory available, and these registers don't exist! 1261 */ 1262 #define NVM_FLASH_CMD_REG 0x7000 1263 #define NVM_FLASH_CMD_LAST 0x00000100 1264 #define NVM_FLASH_CMD_FIRST 0x00000080 1265 #define NVM_FLASH_CMD_RD 0x00000000 1266 #define NVM_FLASH_CMD_WR 0x00000020 1267 #define NVM_FLASH_CMD_DOIT 0x00000010 1268 #define NVM_FLASH_CMD_DONE 0x00000008 1269 1270 #define NVM_FLASH_WRITE_REG 0x7008 1271 #define NVM_FLASH_READ_REG 0x7010 1272 1273 #define NVM_FLASH_ADDR_REG 0x700c 1274 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1275 1276 #define NVM_CONFIG1_REG 0x7014 1277 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1278 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1279 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1280 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1281 #define NVM_CFG1_FLASH_MODE 0x00000001 1282 1283 #define NVM_SW_ARBITRATION_REG 0x7020 1284 #define NVM_READ_REQ3 0X00008000 1285 #define NVM_READ_REQ2 0X00004000 1286 #define NVM_READ_REQ1 0X00002000 1287 #define NVM_READ_REQ0 0X00001000 1288 #define NVM_WON_REQ3 0X00000800 1289 #define NVM_WON_REQ2 0X00000400 1290 #define NVM_WON_REQ1 0X00000200 1291 #define NVM_WON_REQ0 0X00000100 1292 #define NVM_RESET_REQ3 0X00000080 1293 #define NVM_RESET_REQ2 0X00000040 1294 #define NVM_RESET_REQ1 0X00000020 1295 #define NVM_RESET_REQ0 0X00000010 1296 #define NVM_SET_REQ3 0X00000008 1297 #define NVM_SET_REQ2 0X00000004 1298 #define NVM_SET_REQ1 0X00000002 1299 #define NVM_SET_REQ0 0X00000001 1300 1301 /* 1302 * NVM access register 1303 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1304 * and BCM5715 only. 1305 */ 1306 #define NVM_ACCESS_REG 0X7024 1307 #define NVM_WRITE_ENABLE 0X00000002 1308 #define NVM_ACCESS_ENABLE 0X00000001 1309 1310 /* 1311 * TLP Control Register 1312 * Applicable to BCM5721 and BCM5751 only 1313 */ 1314 #define TLP_CONTROL_REG 0x7c00 1315 #define TLP_DATA_FIFO_PROTECT 0x02000000 1316 1317 /* 1318 * PHY Test Control Register 1319 * Applicable to BCM5721 and BCM5751 only 1320 */ 1321 #define PHY_TEST_CTRL_REG 0x7e2c 1322 #define PHY_PCIE_SCRAM_MODE 0x20 1323 #define PHY_PCIE_LTASS_MODE 0x40 1324 1325 /* 1326 * The internal firmware expects a certain layout of the non-volatile 1327 * memory (if fitted), and will check for it during startup, and use the 1328 * contents to initialise various internal parameters if it looks good. 1329 * 1330 * The offsets and field definitions below refer to where to find some 1331 * important values, and how to interpret them ... 1332 */ 1333 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1334 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 1335 1336 /* 1337 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1338 */ 1339 1340 #define MII_AN_LPNXTPG 8 1341 #define MII_1000BASE_T_CONTROL 9 1342 #define MII_1000BASE_T_STATUS 10 1343 #define MII_IEEE_EXT_STATUS 15 1344 1345 /* 1346 * New bits in the MII_CONTROL register 1347 */ 1348 #define MII_CONTROL_1000MB 0x0040 1349 1350 /* 1351 * New bits in the MII_AN_ADVERT register 1352 */ 1353 #define MII_ABILITY_ASYM_PAUSE 0x0800 1354 #define MII_ABILITY_PAUSE 0x0400 1355 1356 /* 1357 * Values for the <selector> field of the MII_AN_ADVERT register 1358 */ 1359 #define MII_AN_SELECTOR_8023 0x0001 1360 1361 /* 1362 * Bits in the MII_1000BASE_T_CONTROL register 1363 * 1364 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1365 * (otherwise, roles are automatically negotiated). When this bit is set, 1366 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1367 */ 1368 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1369 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1370 #define MII_1000BT_CTL_ADV_FDX 0x0200 1371 #define MII_1000BT_CTL_ADV_HDX 0x0100 1372 1373 /* 1374 * Bits in the MII_1000BASE_T_STATUS register 1375 */ 1376 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1377 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1378 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1379 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1380 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1381 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1382 1383 /* 1384 * Vendor-specific MII registers 1385 */ 1386 #define MII_EXT_CONTROL MII_VENDOR(0) 1387 #define MII_EXT_STATUS MII_VENDOR(1) 1388 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1389 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1390 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1391 #define MII_AUX_CONTROL MII_VENDOR(8) 1392 #define MII_AUX_STATUS MII_VENDOR(9) 1393 #define MII_INTR_STATUS MII_VENDOR(10) 1394 #define MII_INTR_MASK MII_VENDOR(11) 1395 #define MII_HCD_STATUS MII_VENDOR(13) 1396 1397 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1398 1399 /* 1400 * Bits in the MII_EXT_CONTROL register 1401 */ 1402 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1403 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1404 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1405 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1406 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1407 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1408 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1409 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1410 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1411 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1412 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1413 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1414 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1415 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1416 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1417 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1418 1419 /* 1420 * Bits in the MII_EXT_STATUS register 1421 */ 1422 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1423 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1424 #define MII_EXT_STAT_MDIX_STATE 0x2000 1425 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1426 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1427 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1428 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1429 #define MII_EXT_STAT_LINK_STATUS 0x0100 1430 #define MII_EXT_STAT_CRC_ERROR 0x0080 1431 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1432 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1433 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1434 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1435 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1436 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1437 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1438 1439 /* 1440 * The AUX CONTROL register is seriously weird! 1441 * 1442 * It hides (up to) eight 'shadow' registers. When writing, which one 1443 * of them is written is determined by the low-order bits of the data 1444 * written(!), but when reading, which one is read is determined by the 1445 * value previously written to (part of) one of the shadow registers!!! 1446 */ 1447 1448 /* 1449 * Shadow register numbers 1450 */ 1451 #define MII_AUX_CTRL_NORMAL 0 1452 #define MII_AUX_CTRL_10BASE_T 1 1453 #define MII_AUX_CTRL_POWER 2 1454 #define MII_AUX_CTRL_TEST_1 4 1455 #define MII_AUX_CTRL_MISC 7 1456 1457 /* 1458 * Selected bits in some of the shadow registers ... 1459 */ 1460 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1461 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1462 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1463 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1464 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1465 1466 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1467 1468 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1469 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1470 1471 /* 1472 * Write this value to the AUX control register 1473 * to select which shadow register will be read 1474 */ 1475 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1476 1477 /* 1478 * Bits in the MII_AUX_STATUS register 1479 */ 1480 #define MII_AUX_STATUS_MODE_MASK 0x0700 1481 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1482 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1483 #define MII_AUX_STATUS_MODE_100_F 0x0500 1484 #define MII_AUX_STATUS_MODE_100_4 0x0400 1485 #define MII_AUX_STATUS_MODE_100_H 0x0300 1486 #define MII_AUX_STATUS_MODE_10_F 0x0200 1487 #define MII_AUX_STATUS_MODE_10_H 0x0100 1488 #define MII_AUX_STATUS_MODE_NONE 0x0000 1489 #define MII_AUX_STATUS_MODE_SHIFT 8 1490 1491 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1492 #define MII_AUX_STATUS_REM_FAULT 0x0040 1493 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1494 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1495 1496 #define MII_AUX_STATUS_LINKUP 0x0004 1497 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1498 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1499 1500 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 1501 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 1502 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 1503 1504 /* 1505 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1506 */ 1507 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1508 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1509 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1510 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1511 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1512 1513 1514 /* 1515 * Third section: 1516 * Hardware-defined data structures 1517 * 1518 * Note that the chip is naturally BIG-endian, so, for a big-endian 1519 * host, the structures defined below match those described in the PRM. 1520 * For little-endian hosts, some structures have to be swapped around. 1521 */ 1522 1523 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1524 #error Host endianness not defined 1525 #endif 1526 1527 /* 1528 * Architectural constants: absolute maximum numbers of each type of ring 1529 */ 1530 #ifdef BGE_EXT_MEM 1531 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1532 #else 1533 #define BGE_SEND_RINGS_MAX 4 1534 #endif 1535 #define BGE_SEND_RINGS_MAX_5705 1 1536 #define BGE_RECV_RINGS_MAX 16 1537 #define BGE_RECV_RINGS_MAX_5705 1 1538 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1539 /* only with ext mem) */ 1540 1541 #define BGE_SEND_SLOTS_MAX 512 1542 #define BGE_STD_SLOTS_MAX 512 1543 #define BGE_JUMBO_SLOTS_MAX 256 1544 #define BGE_MINI_SLOTS_MAX 1024 1545 #define BGE_RECV_SLOTS_MAX 2048 1546 #define BGE_RECV_SLOTS_5705 512 1547 #define BGE_RECV_SLOTS_5782 512 1548 #define BGE_RECV_SLOTS_5721 512 1549 1550 /* 1551 * Hardware-defined Ring Control Block 1552 */ 1553 typedef struct { 1554 uint64_t host_ring_addr; 1555 #ifdef _BIG_ENDIAN 1556 uint16_t max_len; 1557 uint16_t flags; 1558 uint32_t nic_ring_addr; 1559 #else 1560 uint32_t nic_ring_addr; 1561 uint16_t flags; 1562 uint16_t max_len; 1563 #endif /* _BIG_ENDIAN */ 1564 } bge_rcb_t; 1565 1566 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1567 #define RCB_FLAG_RING_DISABLED 0x0002 1568 1569 /* 1570 * Hardware-defined Send Buffer Descriptor 1571 */ 1572 typedef struct { 1573 uint64_t host_buf_addr; 1574 #ifdef _BIG_ENDIAN 1575 uint16_t len; 1576 uint16_t flags; 1577 uint16_t reserved; 1578 uint16_t vlan_tci; 1579 #else 1580 uint16_t vlan_tci; 1581 uint16_t reserved; 1582 uint16_t flags; 1583 uint16_t len; 1584 #endif /* _BIG_ENDIAN */ 1585 } bge_sbd_t; 1586 1587 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1588 #define SBD_FLAG_IP_CKSUM 0x0002 1589 #define SBD_FLAG_PACKET_END 0x0004 1590 #define SBD_FLAG_IP_FRAG 0x0008 1591 #define SBD_FLAG_IP_FRAG_END 0x0010 1592 1593 #define SBD_FLAG_VLAN_TAG 0x0040 1594 #define SBD_FLAG_COAL_NOW 0x0080 1595 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1596 #define SBD_FLAG_CPU_POST_DMA 0x0200 1597 1598 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1599 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1600 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1601 1602 /* 1603 * Hardware-defined Receive Buffer Descriptor 1604 */ 1605 typedef struct { 1606 uint64_t host_buf_addr; 1607 #ifdef _BIG_ENDIAN 1608 uint16_t index; 1609 uint16_t len; 1610 uint16_t type; 1611 uint16_t flags; 1612 uint16_t ip_cksum; 1613 uint16_t tcp_udp_cksum; 1614 uint16_t error_flag; 1615 uint16_t vlan_tci; 1616 uint32_t reserved; 1617 uint32_t opaque; 1618 #else 1619 uint16_t flags; 1620 uint16_t type; 1621 uint16_t len; 1622 uint16_t index; 1623 uint16_t vlan_tci; 1624 uint16_t error_flag; 1625 uint16_t tcp_udp_cksum; 1626 uint16_t ip_cksum; 1627 uint32_t opaque; 1628 uint32_t reserved; 1629 #endif /* _BIG_ENDIAN */ 1630 } bge_rbd_t; 1631 1632 #define RBD_FLAG_STD_RING 0x0000 1633 #define RBD_FLAG_PACKET_END 0x0004 1634 1635 #define RBD_FLAG_JUMBO_RING 0x0020 1636 #define RBD_FLAG_VLAN_TAG 0x0040 1637 1638 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1639 #define RBD_FLAG_MINI_RING 0x0800 1640 #define RBD_FLAG_IP_CHECKSUM 0x1000 1641 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1642 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1643 1644 #define RBD_FLAG_DEFAULT 0x0000 1645 1646 #define RBD_ERROR_BAD_CRC 0x00010000 1647 #define RBD_ERROR_COLL_DETECT 0x00020000 1648 #define RBD_ERROR_LINK_LOST 0x00040000 1649 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1650 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1651 #define RBD_ERROR_MAC_ABORT 0x00200000 1652 #define RBD_ERROR_LEN_LESS_64 0x00400000 1653 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1654 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1655 1656 /* 1657 * Hardware-defined Status Block,Size of status block 1658 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1659 * alignment.For BCM5705/5788/5721/5751/5752/5714 1660 * and 5715,there is only 1 recv and send ring index,but 1661 * driver defined 16 indexs here,please pay attention only 1662 * one ring is enabled in these chipsets. 1663 */ 1664 typedef struct { 1665 uint64_t flags_n_tag; 1666 uint16_t buff_cons_index[4]; 1667 struct { 1668 #ifdef _BIG_ENDIAN 1669 uint16_t send_cons_index; 1670 uint16_t recv_prod_index; 1671 #else 1672 uint16_t recv_prod_index; 1673 uint16_t send_cons_index; 1674 #endif /* _BIG_ENDIAN */ 1675 } index[16]; 1676 } bge_status_t; 1677 1678 /* 1679 * Hardware-defined Receive BD Rule 1680 */ 1681 typedef struct { 1682 uint32_t control; 1683 uint32_t mask_value; 1684 } bge_recv_rule_t; 1685 1686 /* 1687 * Indexes into the <buff_cons_index> array 1688 */ 1689 #ifdef _BIG_ENDIAN 1690 #define STATUS_STD_BUFF_CONS_INDEX 0 1691 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1692 #define STATUS_MINI_BUFF_CONS_INDEX 3 1693 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1694 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1695 #else 1696 #define STATUS_STD_BUFF_CONS_INDEX 3 1697 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1698 #define STATUS_MINI_BUFF_CONS_INDEX 0 1699 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1700 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1701 #endif /* _BIG_ENDIAN */ 1702 1703 /* 1704 * Bits in the <flags_n_tag> word 1705 */ 1706 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1707 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1708 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1709 #define STATUS_TAG_MASK 0x00000000000000FFull 1710 1711 /* 1712 * The tag from the status block is fed back to Interrupt Mailbox 0 1713 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1714 * lets the chip know what updates have been processed, so it can 1715 * reassert its interrupt if more updates have occurred since. 1716 * 1717 * These macros extract the tag from the <flags_n_tag> word, shift 1718 * it to the proper position in the Mailbox register, and provide 1719 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1720 * or enable interrupts 1721 */ 1722 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1723 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1724 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1725 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1726 1727 /* 1728 * Hardware-defined Statistics Block Offsets 1729 * 1730 * These are given in the manual as addresses in NIC memory, starting 1731 * from the NIC statistics area base address of 0x300; but here we 1732 * convert them into indexes into an array of (uint64_t)s, so we can 1733 * use them directly for accessing the copy of the statistics block 1734 * that the chip DMAs into main memory ... 1735 */ 1736 1737 #define KS_BASE 0x300 1738 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1739 1740 typedef enum { 1741 KS_ifHCInOctets = KS_ADDR(0x400), 1742 KS_etherStatsFragments = KS_ADDR(0x410), 1743 KS_ifHCInUcastPkts, 1744 KS_ifHCInMulticastPkts, 1745 KS_ifHCInBroadcastPkts, 1746 KS_dot3StatsFCSErrors, 1747 KS_dot3StatsAlignmentErrors, 1748 KS_xonPauseFramesReceived, 1749 KS_xoffPauseFramesReceived, 1750 KS_macControlFramesReceived, 1751 KS_xoffStateEntered, 1752 KS_dot3StatsFrameTooLongs, 1753 KS_etherStatsJabbers, 1754 KS_etherStatsUndersizePkts, 1755 KS_inRangeLengthError, 1756 KS_outRangeLengthError, 1757 KS_etherStatsPkts64Octets, 1758 KS_etherStatsPkts65to127Octets, 1759 KS_etherStatsPkts128to255Octets, 1760 KS_etherStatsPkts256to511Octets, 1761 KS_etherStatsPkts512to1023Octets, 1762 KS_etherStatsPkts1024to1518Octets, 1763 KS_etherStatsPkts1519to2047Octets, 1764 KS_etherStatsPkts2048to4095Octets, 1765 KS_etherStatsPkts4096to8191Octets, 1766 KS_etherStatsPkts8192to9022Octets, 1767 1768 KS_ifHCOutOctets = KS_ADDR(0x600), 1769 KS_etherStatsCollisions = KS_ADDR(0x610), 1770 KS_outXonSent, 1771 KS_outXoffSent, 1772 KS_flowControlDone, 1773 KS_dot3StatsInternalMacTransmitErrors, 1774 KS_dot3StatsSingleCollisionFrames, 1775 KS_dot3StatsMultipleCollisionFrames, 1776 KS_dot3StatsDeferredTransmissions, 1777 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1778 KS_dot3StatsLateCollisions, 1779 KS_dot3Collided2Times, 1780 KS_dot3Collided3Times, 1781 KS_dot3Collided4Times, 1782 KS_dot3Collided5Times, 1783 KS_dot3Collided6Times, 1784 KS_dot3Collided7Times, 1785 KS_dot3Collided8Times, 1786 KS_dot3Collided9Times, 1787 KS_dot3Collided10Times, 1788 KS_dot3Collided11Times, 1789 KS_dot3Collided12Times, 1790 KS_dot3Collided13Times, 1791 KS_dot3Collided14Times, 1792 KS_dot3Collided15Times, 1793 KS_ifHCOutUcastPkts, 1794 KS_ifHCOutMulticastPkts, 1795 KS_ifHCOutBroadcastPkts, 1796 KS_dot3StatsCarrierSenseErrors, 1797 KS_ifOutDiscards, 1798 KS_ifOutErrors, 1799 1800 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1801 KS_COSIfHCInPkts_2, 1802 KS_COSIfHCInPkts_3, 1803 KS_COSIfHCInPkts_4, 1804 KS_COSIfHCInPkts_5, 1805 KS_COSIfHCInPkts_6, 1806 KS_COSIfHCInPkts_7, 1807 KS_COSIfHCInPkts_8, 1808 KS_COSIfHCInPkts_9, 1809 KS_COSIfHCInPkts_10, 1810 KS_COSIfHCInPkts_11, 1811 KS_COSIfHCInPkts_12, 1812 KS_COSIfHCInPkts_13, 1813 KS_COSIfHCInPkts_14, 1814 KS_COSIfHCInPkts_15, 1815 KS_COSIfHCInPkts_16, 1816 KS_COSFramesDroppedDueToFilters, 1817 KS_nicDmaWriteQueueFull, 1818 KS_nicDmaWriteHighPriQueueFull, 1819 KS_nicNoMoreRxBDs, 1820 KS_ifInDiscards, 1821 KS_ifInErrors, 1822 KS_nicRecvThresholdHit, 1823 1824 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1825 KS_COSIfHCOutPkts_2, 1826 KS_COSIfHCOutPkts_3, 1827 KS_COSIfHCOutPkts_4, 1828 KS_COSIfHCOutPkts_5, 1829 KS_COSIfHCOutPkts_6, 1830 KS_COSIfHCOutPkts_7, 1831 KS_COSIfHCOutPkts_8, 1832 KS_COSIfHCOutPkts_9, 1833 KS_COSIfHCOutPkts_10, 1834 KS_COSIfHCOutPkts_11, 1835 KS_COSIfHCOutPkts_12, 1836 KS_COSIfHCOutPkts_13, 1837 KS_COSIfHCOutPkts_14, 1838 KS_COSIfHCOutPkts_15, 1839 KS_COSIfHCOutPkts_16, 1840 KS_nicDmaReadQueueFull, 1841 KS_nicDmaReadHighPriQueueFull, 1842 KS_nicSendDataCompQueueFull, 1843 KS_nicRingSetSendProdIndex, 1844 KS_nicRingStatusUpdate, 1845 KS_nicInterrupts, 1846 KS_nicAvoidedInterrupts, 1847 KS_nicSendThresholdHit, 1848 1849 KS_STATS_SIZE = KS_ADDR(0xb00) 1850 } bge_stats_offset_t; 1851 1852 /* 1853 * Hardware-defined Statistics Block 1854 * 1855 * Another view of the statistic block, as a array and a structure ... 1856 */ 1857 1858 typedef union { 1859 uint64_t a[KS_STATS_SIZE]; 1860 struct { 1861 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1862 1863 uint64_t ifHCInOctets; /* 0x0400 */ 1864 uint64_t spare2[1]; 1865 uint64_t etherStatsFragments; 1866 uint64_t ifHCInUcastPkts; 1867 uint64_t ifHCInMulticastPkts; 1868 uint64_t ifHCInBroadcastPkts; 1869 uint64_t dot3StatsFCSErrors; 1870 uint64_t dot3StatsAlignmentErrors; 1871 uint64_t xonPauseFramesReceived; 1872 uint64_t xoffPauseFramesReceived; 1873 uint64_t macControlFramesReceived; 1874 uint64_t xoffStateEntered; 1875 uint64_t dot3StatsFrameTooLongs; 1876 uint64_t etherStatsJabbers; 1877 uint64_t etherStatsUndersizePkts; 1878 uint64_t inRangeLengthError; 1879 uint64_t outRangeLengthError; 1880 uint64_t etherStatsPkts64Octets; 1881 uint64_t etherStatsPkts65to127Octets; 1882 uint64_t etherStatsPkts128to255Octets; 1883 uint64_t etherStatsPkts256to511Octets; 1884 uint64_t etherStatsPkts512to1023Octets; 1885 uint64_t etherStatsPkts1024to1518Octets; 1886 uint64_t etherStatsPkts1519to2047Octets; 1887 uint64_t etherStatsPkts2048to4095Octets; 1888 uint64_t etherStatsPkts4096to8191Octets; 1889 uint64_t etherStatsPkts8192to9022Octets; 1890 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1891 1892 uint64_t ifHCOutOctets; /* 0x0600 */ 1893 uint64_t spare4[1]; 1894 uint64_t etherStatsCollisions; 1895 uint64_t outXonSent; 1896 uint64_t outXoffSent; 1897 uint64_t flowControlDone; 1898 uint64_t dot3StatsInternalMacTransmitErrors; 1899 uint64_t dot3StatsSingleCollisionFrames; 1900 uint64_t dot3StatsMultipleCollisionFrames; 1901 uint64_t dot3StatsDeferredTransmissions; 1902 uint64_t spare5[1]; 1903 uint64_t dot3StatsExcessiveCollisions; 1904 uint64_t dot3StatsLateCollisions; 1905 uint64_t dot3Collided2Times; 1906 uint64_t dot3Collided3Times; 1907 uint64_t dot3Collided4Times; 1908 uint64_t dot3Collided5Times; 1909 uint64_t dot3Collided6Times; 1910 uint64_t dot3Collided7Times; 1911 uint64_t dot3Collided8Times; 1912 uint64_t dot3Collided9Times; 1913 uint64_t dot3Collided10Times; 1914 uint64_t dot3Collided11Times; 1915 uint64_t dot3Collided12Times; 1916 uint64_t dot3Collided13Times; 1917 uint64_t dot3Collided14Times; 1918 uint64_t dot3Collided15Times; 1919 uint64_t ifHCOutUcastPkts; 1920 uint64_t ifHCOutMulticastPkts; 1921 uint64_t ifHCOutBroadcastPkts; 1922 uint64_t dot3StatsCarrierSenseErrors; 1923 uint64_t ifOutDiscards; 1924 uint64_t ifOutErrors; 1925 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1926 1927 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1928 uint64_t COSFramesDroppedDueToFilters; 1929 uint64_t nicDmaWriteQueueFull; 1930 uint64_t nicDmaWriteHighPriQueueFull; 1931 uint64_t nicNoMoreRxBDs; 1932 uint64_t ifInDiscards; 1933 uint64_t ifInErrors; 1934 uint64_t nicRecvThresholdHit; 1935 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1936 1937 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1938 uint64_t nicDmaReadQueueFull; 1939 uint64_t nicDmaReadHighPriQueueFull; 1940 uint64_t nicSendDataCompQueueFull; 1941 uint64_t nicRingSetSendProdIndex; 1942 uint64_t nicRingStatusUpdate; 1943 uint64_t nicInterrupts; 1944 uint64_t nicAvoidedInterrupts; 1945 uint64_t nicSendThresholdHit; 1946 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1947 } s; 1948 } bge_statistics_t; 1949 1950 #define KS_STAT_REG_SIZE (0x1B) 1951 #define KS_STAT_REG_BASE (0x800) 1952 1953 typedef struct { 1954 uint32_t ifHCOutOctets; 1955 uint32_t etherStatsCollisions; 1956 uint32_t outXonSent; 1957 uint32_t outXoffSent; 1958 uint32_t dot3StatsInternalMacTransmitErrors; 1959 uint32_t dot3StatsSingleCollisionFrames; 1960 uint32_t dot3StatsMultipleCollisionFrames; 1961 uint32_t dot3StatsDeferredTransmissions; 1962 uint32_t dot3StatsExcessiveCollisions; 1963 uint32_t dot3StatsLateCollisions; 1964 uint32_t ifHCOutUcastPkts; 1965 uint32_t ifHCOutMulticastPkts; 1966 uint32_t ifHCOutBroadcastPkts; 1967 uint32_t ifHCInOctets; 1968 uint32_t etherStatsFragments; 1969 uint32_t ifHCInUcastPkts; 1970 uint32_t ifHCInMulticastPkts; 1971 uint32_t ifHCInBroadcastPkts; 1972 uint32_t dot3StatsFCSErrors; 1973 uint32_t dot3StatsAlignmentErrors; 1974 uint32_t xonPauseFramesReceived; 1975 uint32_t xoffPauseFramesReceived; 1976 uint32_t macControlFramesReceived; 1977 uint32_t xoffStateEntered; 1978 uint32_t dot3StatsFrameTooLongs; 1979 uint32_t etherStatsJabbers; 1980 uint32_t etherStatsUndersizePkts; 1981 } bge_statistics_reg_t; 1982 1983 1984 #ifdef BGE_IPMI_ASF 1985 1986 /* 1987 * Device internal memory entries 1988 */ 1989 1990 #define BGE_FIRMWARE_MAILBOX 0x0b50 1991 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1992 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1993 1994 1995 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1996 #define BGE_NIC_DATA_SIG 0x4b657654 1997 1998 1999 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 2000 2001 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 2002 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 2003 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 2004 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 2005 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 2006 2007 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 2008 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 2009 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 2010 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 2011 2012 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 2013 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 2014 #define BGE_NIC_CFG_EEPROM_WP 0x000100 2015 #define BGE_NIC_CFG_POWER_SAVING 0x000200 2016 #define BGE_NIC_CFG_SWAP_PORT 0x000800 2017 #define BGE_NIC_CFG_MINI_PCI 0x001000 2018 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 2019 #define BGE_NIC_CFG_5753_12x12 0x100000 2020 2021 2022 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 2023 2024 2025 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 2026 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 2027 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 2028 2029 2030 #define BGE_CMD_MAILBOX 0x0b78 2031 #define BGE_CMD_NICDRV_ALIVE 0x00000001 2032 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 2033 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 2034 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 2035 2036 2037 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2038 #define BGE_CMD_DATA_MAILBOX 0x0b80 2039 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2040 2041 #define BGE_DRV_STATE_MAILBOX 0x0c04 2042 #define BGE_DRV_STATE_START 0x00000001 2043 #define BGE_DRV_STATE_START_DONE 0x80000001 2044 #define BGE_DRV_STATE_UNLOAD 0x00000002 2045 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2046 #define BGE_DRV_STATE_WOL 0x00000003 2047 #define BGE_DRV_STATE_SUSPEND 0x00000004 2048 2049 2050 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2051 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2052 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2053 2054 2055 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2056 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2057 2058 2059 /* 2060 * RX-RISC event register 2061 */ 2062 #define RX_RISC_EVENT_REG 0x6810 2063 #define RRER_ASF_EVENT 0x4000 2064 2065 #endif /* BGE_IPMI_ASF */ 2066 2067 #ifdef __cplusplus 2068 } 2069 #endif 2070 2071 #endif /* _BGE_HW_H */ 2072