1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "sys/bge_impl2.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 0 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 0 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * Property names 56 */ 57 static char knownids_propname[] = "bge-known-subsystems"; 58 59 /* 60 * Patchable globals: 61 * 62 * bge_autorecover 63 * Enables/disables automatic recovery after fault detection 64 * 65 * bge_mlcr_default 66 * Value to program into the MLCR; controls the chip's GPIO pins 67 * 68 * bge_dma_{rd,wr}prio 69 * Relative priorities of DMA reads & DMA writes respectively. 70 * These may each be patched to any value 0-3. Equal values 71 * will give "fair" (round-robin) arbitration for PCI access. 72 * Unequal values will give one or the other function priority. 73 * 74 * bge_dma_rwctrl 75 * Value to put in the Read/Write DMA control register. See 76 * the Broadcom PRM for things you can fiddle with in this 77 * register ... 78 * 79 * bge_{tx,rx}_{count,ticks}_{norm,intr} 80 * Send/receive interrupt coalescing parameters. Counts are 81 * #s of descriptors, ticks are in microseconds. *norm* values 82 * apply between status updates/interrupts; the *intr* values 83 * refer to the 'during-interrupt' versions - see the PRM. 84 * 85 * NOTE: these values have been determined by measurement. They 86 * differ significantly from the values recommended in the PRM. 87 */ 88 static uint32_t bge_autorecover = 1; 89 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 boolean_t bge_jumbo_enable = B_TRUE; 155 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 156 157 /* 158 * ========== Low-level chip & ring buffer manipulation ========== 159 */ 160 161 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 162 163 164 /* 165 * Config space read-modify-write routines 166 */ 167 168 #if BGE_CFG_IO8 169 170 /* 171 * 8- and 16-bit set/clr operations are not used; all the config registers 172 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 173 * code here, though, in case we ever find that we do want it after all ... 174 */ 175 176 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 177 #pragma inline(bge_cfg_set8) 178 179 static void 180 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 181 { 182 uint8_t regval; 183 184 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get8(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval | bits)); 191 192 regval |= bits; 193 pci_config_put8(bgep->cfg_handle, regno, regval); 194 } 195 196 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 197 #pragma inline(bge_cfg_clr8) 198 199 static void 200 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 201 { 202 uint8_t regval; 203 204 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get8(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put8(bgep->cfg_handle, regno, regval); 214 } 215 216 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 217 #pragma inline(bge_cfg_set16) 218 219 static void 220 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 221 { 222 uint16_t regval; 223 224 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 225 (void *)bgep, regno, bits)); 226 227 regval = pci_config_get16(bgep->cfg_handle, regno); 228 229 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 230 (void *)bgep, regno, bits, regval, regval | bits)); 231 232 regval |= bits; 233 pci_config_put16(bgep->cfg_handle, regno, regval); 234 } 235 236 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 237 #pragma inline(bge_cfg_clr16) 238 239 static void 240 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 241 { 242 uint16_t regval; 243 244 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 245 (void *)bgep, regno, bits)); 246 247 regval = pci_config_get16(bgep->cfg_handle, regno); 248 249 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 250 (void *)bgep, regno, bits, regval, regval & ~bits)); 251 252 regval &= ~bits; 253 pci_config_put16(bgep->cfg_handle, regno, regval); 254 } 255 256 #endif /* BGE_CFG_IO8 */ 257 258 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 259 #pragma inline(bge_cfg_set32) 260 261 static void 262 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 263 { 264 uint32_t regval; 265 266 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 267 (void *)bgep, regno, bits)); 268 269 regval = pci_config_get32(bgep->cfg_handle, regno); 270 271 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 272 (void *)bgep, regno, bits, regval, regval | bits)); 273 274 regval |= bits; 275 pci_config_put32(bgep->cfg_handle, regno, regval); 276 } 277 278 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 279 #pragma inline(bge_cfg_clr32) 280 281 static void 282 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 283 { 284 uint32_t regval; 285 286 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 287 (void *)bgep, regno, bits)); 288 289 regval = pci_config_get32(bgep->cfg_handle, regno); 290 291 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 292 (void *)bgep, regno, bits, regval, regval & ~bits)); 293 294 regval &= ~bits; 295 pci_config_put32(bgep->cfg_handle, regno, regval); 296 } 297 298 #if BGE_IND_IO32 299 300 /* 301 * Indirect access to registers & RISC scratchpads, using config space 302 * accesses only. 303 * 304 * This isn't currently used, but someday we might want to use it for 305 * restoring the Subsystem Device/Vendor registers (which aren't directly 306 * writable in Config Space), or for downloading firmware into the RISCs 307 * 308 * In any case there are endian issues to be resolved before this code is 309 * enabled; the bizarre way that bytes get twisted by this chip AND by 310 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 311 * it's been thoroughly tested for all access sizes on all supported 312 * architectures (SPARC *and* x86!). 313 */ 314 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 315 #pragma inline(bge_ind_get32) 316 317 static uint32_t 318 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 319 { 320 uint32_t val; 321 322 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 323 324 ASSERT(mutex_owned(bgep->genlock)); 325 326 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 327 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 328 329 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 330 (void *)bgep, regno, val)); 331 332 return (val); 333 } 334 335 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 336 #pragma inline(bge_ind_put32) 337 338 static void 339 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 340 { 341 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 342 (void *)bgep, regno, val)); 343 344 ASSERT(mutex_owned(bgep->genlock)); 345 346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 347 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 348 } 349 350 #endif /* BGE_IND_IO32 */ 351 352 #if BGE_DEBUGGING 353 354 static void bge_pci_check(bge_t *bgep); 355 #pragma no_inline(bge_pci_check) 356 357 static void 358 bge_pci_check(bge_t *bgep) 359 { 360 uint16_t pcistatus; 361 362 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 363 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 364 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 365 (void *)bgep, pcistatus)); 366 } 367 368 #endif /* BGE_DEBUGGING */ 369 370 /* 371 * Perform first-stage chip (re-)initialisation, using only config-space 372 * accesses: 373 * 374 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 375 * returning the data in the structure pointed to by <idp>. 376 * + Configure the target-mode endianness (swap) options. 377 * + Disable interrupts and enable Memory Space accesses. 378 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 379 * 380 * This sequence is adapted from Broadcom document 570X-PG102-R, 381 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 382 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 383 * 384 * This function MUST be called before any non-config-space accesses 385 * are made; on this first call <enable_dma> is B_FALSE, and it 386 * effectively performs steps 3-1(!) of the initialisation sequence 387 * (the rest are not required but should be harmless). 388 * 389 * It MUST also be called also after a chip reset, as this disables 390 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 391 * it is effectively performing steps 6-8. 392 */ 393 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 394 #pragma no_inline(bge_chip_cfg_init) 395 396 void 397 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 398 { 399 ddi_acc_handle_t handle; 400 uint16_t command; 401 uint32_t mhcr; 402 uint16_t value16; 403 int i; 404 405 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 406 (void *)bgep, (void *)cidp, enable_dma)); 407 408 /* 409 * Step 3: save PCI cache line size and subsystem vendor ID 410 * 411 * Read all the config-space registers that characterise the 412 * chip, specifically vendor/device/revision/subsystem vendor 413 * and subsystem device id. We expect (but don't check) that 414 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 415 * 416 * Also save all bus-transation related registers (cache-line 417 * size, bus-grant/latency parameters, etc). Some of these are 418 * cleared by reset, so we'll have to restore them later. This 419 * comes from the Broadcom document 570X-PG102-R ... 420 * 421 * Note: Broadcom document 570X-PG102-R seems to be in error 422 * here w.r.t. the offsets of the Subsystem Vendor ID and 423 * Subsystem (Device) ID registers, which are the opposite way 424 * round according to the PCI standard. For good measure, we 425 * save/restore both anyway. 426 */ 427 handle = bgep->cfg_handle; 428 429 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 430 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 431 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 432 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 433 434 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 435 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 436 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 437 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 438 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 439 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 440 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 441 442 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 443 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 444 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 445 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 446 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 447 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 448 cidp->vendor, cidp->device, cidp->revision)); 449 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 450 cidp->subven, cidp->subdev, cidp->asic_rev)); 451 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 452 cidp->clsize, cidp->latency, cidp->command)); 453 454 /* 455 * Step 2 (also step 6): disable and clear interrupts. 456 * Steps 11-13: configure PIO endianness options, and enable 457 * indirect register access. We'll also select any other 458 * options controlled by the MHCR (eg tagged status, mask 459 * interrupt mode) at this stage ... 460 * 461 * Note: internally, the chip is 64-bit and BIG-endian, but 462 * since it talks to the host over a (LITTLE-endian) PCI bus, 463 * it normally swaps bytes around at the PCI interface. 464 * However, the PCI host bridge on SPARC systems normally 465 * swaps the byte lanes around too, since SPARCs are also 466 * BIG-endian. So it turns out that on SPARC, the right 467 * option is to tell the chip to swap (and the host bridge 468 * will swap back again), whereas on x86 we ask the chip 469 * NOT to swap, so the natural little-endianness of the 470 * PCI bus is assumed. Then the only thing that doesn't 471 * automatically work right is access to an 8-byte register 472 * by a little-endian host; but we don't want to set the 473 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 474 * accesses don't go where expected ;-( So we live with 475 * that, and perform word-swaps in software in the few cases 476 * where a chip register is defined as an 8-byte value -- 477 * see the code below for details ... 478 * 479 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 480 * very clear in the register description in the PRM, but 481 * Broadcom document 570X-PG104-R page 248 explains a little 482 * more (under "Broadcom Mask Mode"). The bit changes the way 483 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 484 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 485 * way as the 5700 did, which isn't very convenient. Setting 486 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 487 * bit do just what its name says -- MASK the PCI #INTA output 488 * (i.e. deassert the signal at the pin) leaving all internal 489 * state unchanged. This is much more convenient for our 490 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 491 * 492 * Note: the inconvenient semantics of the interrupt mailbox 493 * (nonzero disables and acknowledges/clears the interrupt, 494 * zero enables AND CLEARS it) would make race conditions 495 * likely in the interrupt handler: 496 * 497 * (1) acknowledge & disable interrupts 498 * (2) while (more to do) 499 * process packets 500 * (3) enable interrupts -- also clears pending 501 * 502 * If the chip received more packets and internally generated 503 * an interrupt between the check at (2) and the mbox write 504 * at (3), this interrupt would be lost :-( 505 * 506 * The best way to avoid this is to use TAGGED STATUS mode, 507 * where the chip includes a unique tag in each status block 508 * update, and the host, when re-enabling interrupts, passes 509 * the last tag it saw back to the chip; then the chip can 510 * see whether the host is truly up to date, and regenerate 511 * its interrupt if not. 512 */ 513 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 514 MHCR_ENABLE_TAGGED_STATUS_MODE | 515 MHCR_MASK_INTERRUPT_MODE | 516 MHCR_CLEAR_INTERRUPT_INTA; 517 518 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 519 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 520 521 #ifdef _BIG_ENDIAN 522 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 523 #endif /* _BIG_ENDIAN */ 524 525 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 526 527 #ifdef BGE_IPMI_ASF 528 bgep->asf_wordswapped = B_FALSE; 529 #endif 530 /* 531 * Step 1 (also step 7): Enable PCI Memory Space accesses 532 * Disable Memory Write/Invalidate 533 * Enable or disable Bus Mastering 534 * 535 * Note that all other bits are taken from the original value saved 536 * the first time through here, rather than from the current register 537 * value, 'cos that will have been cleared by a soft RESET since. 538 * In this way we preserve the OBP/nexus-parent's preferred settings 539 * of the parity-error and system-error enable bits across multiple 540 * chip RESETs. 541 * 542 * Step 8: Disable PCI-X Relaxed Ordering -- doesn't apply 543 */ 544 command = bgep->chipid.command | PCI_COMM_MAE; 545 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 546 if (enable_dma) 547 command |= PCI_COMM_ME; 548 /* 549 * on BCM5714 revision A0, false parity error gets generated 550 * due to a logic bug. Provide a workaround by disabling parrity 551 * error. 552 */ 553 if (((cidp->device == DEVICE_ID_5714C) || 554 (cidp->device == DEVICE_ID_5714S)) && 555 (cidp->revision == REVISION_ID_5714_A0)) { 556 command &= ~PCI_COMM_PARITY_DETECT; 557 } 558 pci_config_put16(handle, PCI_CONF_COMM, command); 559 560 /* 561 * On some PCI-E device, there were instances when 562 * the device was still link training. 563 */ 564 if (bgep->chipid.pci_type == BGE_PCI_E) { 565 i = 0; 566 value16 = pci_config_get16(handle, PCI_CONF_COMM); 567 while ((value16 != command) && (i < 100)) { 568 drv_usecwait(200); 569 value16 = pci_config_get16(handle, PCI_CONF_COMM); 570 ++i; 571 } 572 } 573 574 /* 575 * Clear any remaining error status bits 576 */ 577 pci_config_put16(handle, PCI_CONF_STAT, ~0); 578 579 /* 580 * Make sure these indirect-access registers are sane 581 * rather than random after power-up or reset 582 */ 583 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 584 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 585 } 586 587 #ifdef __amd64 588 /* 589 * Distinguish CPU types 590 * 591 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 592 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 593 * for PCI-Express based network interface card. This is the work-around 594 * for those nics. 595 */ 596 static boolean_t bge_get_em64t_type(void); 597 #pragma inline(bge_get_em64t_type) 598 599 static boolean_t 600 bge_get_em64t_type(void) 601 { 602 603 return (x86_vendor == X86_VENDOR_Intel); 604 } 605 #endif 606 607 /* 608 * Operating register get/set access routines 609 */ 610 611 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 612 #pragma inline(bge_reg_get32) 613 614 uint32_t 615 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 616 { 617 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 618 (void *)bgep, regno)); 619 620 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 621 } 622 623 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 624 #pragma inline(bge_reg_put32) 625 626 void 627 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 628 { 629 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 630 (void *)bgep, regno, data)); 631 632 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 633 BGE_PCICHK(bgep); 634 } 635 636 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 637 #pragma inline(bge_reg_set32) 638 639 void 640 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 641 { 642 uint32_t regval; 643 644 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 645 (void *)bgep, regno, bits)); 646 647 regval = bge_reg_get32(bgep, regno); 648 regval |= bits; 649 bge_reg_put32(bgep, regno, regval); 650 } 651 652 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 653 #pragma inline(bge_reg_clr32) 654 655 void 656 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 657 { 658 uint32_t regval; 659 660 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 661 (void *)bgep, regno, bits)); 662 663 regval = bge_reg_get32(bgep, regno); 664 regval &= ~bits; 665 bge_reg_put32(bgep, regno, regval); 666 } 667 668 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 669 #pragma inline(bge_reg_get64) 670 671 static uint64_t 672 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 673 { 674 uint64_t regval; 675 676 #ifdef __amd64 677 if (bge_get_em64t_type()) { 678 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 679 regval <<= 32; 680 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 681 } else { 682 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 683 } 684 #else 685 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 686 #endif 687 688 #ifdef _LITTLE_ENDIAN 689 regval = (regval >> 32) | (regval << 32); 690 #endif /* _LITTLE_ENDIAN */ 691 692 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 693 (void *)bgep, regno, regval)); 694 695 return (regval); 696 } 697 698 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 699 #pragma inline(bge_reg_put64) 700 701 static void 702 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 703 { 704 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 705 (void *)bgep, regno, data)); 706 707 #ifdef _LITTLE_ENDIAN 708 data = ((data >> 32) | (data << 32)); 709 #endif /* _LITTLE_ENDIAN */ 710 711 #ifdef __amd64 712 if (bge_get_em64t_type()) { 713 ddi_put32(bgep->io_handle, 714 PIO_ADDR(bgep, regno), (uint32_t)data); 715 BGE_PCICHK(bgep); 716 ddi_put32(bgep->io_handle, 717 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 718 719 } else { 720 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 721 } 722 #else 723 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 724 #endif 725 726 BGE_PCICHK(bgep); 727 } 728 729 /* 730 * The DDI doesn't provide get/put functions for 128 bit data 731 * so we put RCBs out as two 64-bit chunks instead. 732 */ 733 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 734 #pragma inline(bge_reg_putrcb) 735 736 static void 737 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 738 { 739 uint64_t *p; 740 741 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 742 (void *)bgep, addr, rcbp->host_ring_addr, 743 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 744 745 ASSERT((addr % sizeof (*rcbp)) == 0); 746 747 p = (void *)rcbp; 748 bge_reg_put64(bgep, addr, *p++); 749 bge_reg_put64(bgep, addr+8, *p); 750 } 751 752 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 753 #pragma inline(bge_mbx_put) 754 755 void 756 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 757 { 758 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 759 (void *)bgep, regno, data)); 760 761 /* 762 * Mailbox registers are nominally 64 bits on the 5701, but 763 * the MSW isn't used. On the 5703, they're only 32 bits 764 * anyway. So here we just write the lower(!) 32 bits - 765 * remembering that the chip is big-endian, even though the 766 * PCI bus is little-endian ... 767 */ 768 #ifdef _BIG_ENDIAN 769 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 770 #else 771 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 772 #endif /* _BIG_ENDIAN */ 773 BGE_PCICHK(bgep); 774 } 775 776 #if BGE_DEBUGGING 777 778 void bge_led_mark(bge_t *bgep); 779 #pragma no_inline(bge_led_mark) 780 781 void 782 bge_led_mark(bge_t *bgep) 783 { 784 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 785 LED_CONTROL_1000MBPS_LED | 786 LED_CONTROL_100MBPS_LED | 787 LED_CONTROL_10MBPS_LED; 788 789 /* 790 * Blink all three LINK LEDs on simultaneously, then all off, 791 * then restore to automatic hardware control. This is used 792 * in laboratory testing to trigger a logic analyser or scope. 793 */ 794 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 795 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 796 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 797 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 798 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 799 } 800 801 #endif /* BGE_DEBUGGING */ 802 803 /* 804 * NIC on-chip memory access routines 805 * 806 * Only 32K of NIC memory is visible at a time, controlled by the 807 * Memory Window Base Address Register (in PCI config space). Once 808 * this is set, the 32K region of NIC-local memory that it refers 809 * to can be directly addressed in the upper 32K of the 64K of PCI 810 * memory space used for the device. 811 */ 812 813 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 814 #pragma inline(bge_nic_setwin) 815 816 static void 817 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 818 { 819 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 820 (void *)bgep, base)); 821 822 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 823 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 824 } 825 826 827 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 828 #pragma inline(bge_nic_get32) 829 830 static uint32_t 831 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 832 { 833 uint32_t data; 834 835 #ifdef BGE_IPMI_ASF 836 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 837 /* workaround for word swap error */ 838 if (addr & 4) 839 addr = addr - 4; 840 else 841 addr = addr + 4; 842 } 843 #endif 844 845 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 846 addr &= MWBAR_GRANULE_MASK; 847 addr += NIC_MEM_WINDOW_OFFSET; 848 849 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 850 851 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 852 (void *)bgep, addr, data)); 853 854 return (data); 855 } 856 857 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 858 #pragma inline(bge_nic_put32) 859 860 void 861 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 862 { 863 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 864 (void *)bgep, addr, data)); 865 866 #ifdef BGE_IPMI_ASF 867 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 868 /* workaround for word swap error */ 869 if (addr & 4) 870 addr = addr - 4; 871 else 872 addr = addr + 4; 873 } 874 #endif 875 876 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 877 addr &= MWBAR_GRANULE_MASK; 878 addr += NIC_MEM_WINDOW_OFFSET; 879 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 880 BGE_PCICHK(bgep); 881 } 882 883 884 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 885 #pragma inline(bge_nic_get64) 886 887 static uint64_t 888 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 889 { 890 uint64_t data; 891 892 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 893 addr &= MWBAR_GRANULE_MASK; 894 addr += NIC_MEM_WINDOW_OFFSET; 895 896 #ifdef __amd64 897 if (bge_get_em64t_type()) { 898 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 899 data <<= 32; 900 data |= ddi_get32(bgep->io_handle, 901 PIO_ADDR(bgep, addr + 4)); 902 } else { 903 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 904 } 905 #else 906 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 907 #endif 908 909 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 910 (void *)bgep, addr, data)); 911 912 return (data); 913 } 914 915 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 916 #pragma inline(bge_nic_put64) 917 918 static void 919 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 920 { 921 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 922 (void *)bgep, addr, data)); 923 924 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 925 addr &= MWBAR_GRANULE_MASK; 926 addr += NIC_MEM_WINDOW_OFFSET; 927 928 #ifdef __amd64 929 if (bge_get_em64t_type()) { 930 ddi_put32(bgep->io_handle, 931 PIO_ADDR(bgep, addr), (uint32_t)data); 932 BGE_PCICHK(bgep); 933 ddi_put32(bgep->io_handle, 934 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 935 } else { 936 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 937 } 938 #else 939 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 940 #endif 941 942 BGE_PCICHK(bgep); 943 } 944 945 /* 946 * The DDI doesn't provide get/put functions for 128 bit data 947 * so we put RCBs out as two 64-bit chunks instead. 948 */ 949 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 950 #pragma inline(bge_nic_putrcb) 951 952 static void 953 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 954 { 955 uint64_t *p; 956 957 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 958 (void *)bgep, addr, rcbp->host_ring_addr, 959 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 960 961 ASSERT((addr % sizeof (*rcbp)) == 0); 962 963 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 964 addr &= MWBAR_GRANULE_MASK; 965 addr += NIC_MEM_WINDOW_OFFSET; 966 967 p = (void *)rcbp; 968 #ifdef __amd64 969 if (bge_get_em64t_type()) { 970 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 971 (uint32_t)(*p)); 972 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 973 (uint32_t)(*p >> 32)); 974 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 975 (uint32_t)(*(p + 1))); 976 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 977 (uint32_t)(*p >> 32)); 978 979 } else { 980 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 981 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 982 } 983 #else 984 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 985 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 986 #endif 987 988 BGE_PCICHK(bgep); 989 } 990 991 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 992 #pragma inline(bge_nic_zero) 993 994 static void 995 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 996 { 997 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 998 (void *)bgep, addr, nbytes)); 999 1000 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1001 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1002 1003 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1004 addr &= MWBAR_GRANULE_MASK; 1005 addr += NIC_MEM_WINDOW_OFFSET; 1006 1007 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1008 nbytes, 1, DDI_DATA_SZ08_ACC); 1009 BGE_PCICHK(bgep); 1010 } 1011 1012 /* 1013 * MII (PHY) register get/set access routines 1014 * 1015 * These use the chip's MII auto-access method, controlled by the 1016 * MII Communication register at 0x044c, so the CPU doesn't have 1017 * to fiddle with the individual bits. 1018 */ 1019 1020 #undef BGE_DBG 1021 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1022 1023 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1024 uint16_t data, uint32_t cmd); 1025 #pragma no_inline(bge_mii_access) 1026 1027 static uint16_t 1028 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1029 { 1030 uint32_t timeout; 1031 uint32_t regval1; 1032 uint32_t regval2; 1033 1034 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1035 (void *)bgep, regno, data, cmd)); 1036 1037 ASSERT(mutex_owned(bgep->genlock)); 1038 1039 /* 1040 * Assemble the command ... 1041 */ 1042 cmd |= data << MI_COMMS_DATA_SHIFT; 1043 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1044 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1045 cmd |= MI_COMMS_START; 1046 1047 /* 1048 * Wait for any command already in progress ... 1049 * 1050 * Note: this *shouldn't* ever find that there is a command 1051 * in progress, because we already hold the <genlock> mutex. 1052 * Nonetheless, we have sometimes seen the MI_COMMS_START 1053 * bit set here -- it seems that the chip can initiate MII 1054 * accesses internally, even with polling OFF. 1055 */ 1056 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1057 for (timeout = 1000; ; ) { 1058 if ((regval2 & MI_COMMS_START) == 0) { 1059 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1060 break; 1061 } 1062 if (--timeout == 0) 1063 break; 1064 drv_usecwait(10); 1065 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1066 } 1067 1068 if (timeout != 1000) 1069 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1070 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1071 cmd, 10*(1000-timeout), regval1, regval2)); 1072 1073 ASSERT(timeout != 0); 1074 if (timeout == 0) 1075 return ((uint16_t)~0u); 1076 1077 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1078 for (timeout = 1000; ; ) { 1079 if ((regval1 & MI_COMMS_START) == 0) 1080 break; 1081 if (--timeout == 0) 1082 break; 1083 drv_usecwait(10); 1084 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1085 } 1086 1087 /* 1088 * Drop out early if the READ FAILED bit is set -- this chip 1089 * could be a 5703/4S, with a SerDes instead of a PHY! 1090 */ 1091 if (regval2 & MI_COMMS_READ_FAILED) 1092 return ((uint16_t)~0u); 1093 1094 ASSERT(timeout != 0); 1095 if (timeout == 0) 1096 return ((uint16_t)~0u); 1097 1098 /* 1099 * The PRM says to wait 5us after seeing the START bit clear 1100 * and then re-read the register to get the final value of the 1101 * data field, in order to avoid a race condition where the 1102 * START bit is clear but the data field isn't yet valid. 1103 * 1104 * Note: we don't actually seem to be encounter this race; 1105 * except when the START bit is seen set again (see below), 1106 * the data field doesn't change during this 5us interval. 1107 */ 1108 drv_usecwait(5); 1109 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1110 1111 /* 1112 * Unfortunately, when following the PRMs instructions above, 1113 * we have occasionally seen the START bit set again(!) in the 1114 * value read after the 5us delay. This seems to be due to the 1115 * chip autonomously starting another MII access internally. 1116 * In such cases, the command/data/etc fields relate to the 1117 * internal command, rather than the one that we thought had 1118 * just finished. So in this case, we fall back to returning 1119 * the data from the original read that showed START clear. 1120 */ 1121 if (regval2 & MI_COMMS_START) { 1122 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1123 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1124 cmd, regval1, regval2)); 1125 regval2 = regval1; 1126 } 1127 1128 ASSERT((regval2 & MI_COMMS_START) == 0); 1129 if (regval2 & MI_COMMS_START) 1130 return ((uint16_t)~0u); 1131 1132 ASSERT((regval2 & MI_COMMS_READ_FAILED) == 0); 1133 if (regval2 & MI_COMMS_READ_FAILED) 1134 return ((uint16_t)~0u); 1135 1136 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1137 } 1138 1139 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1140 #pragma no_inline(bge_mii_get16) 1141 1142 uint16_t 1143 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1144 { 1145 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1146 (void *)bgep, regno)); 1147 1148 ASSERT(mutex_owned(bgep->genlock)); 1149 1150 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1151 } 1152 1153 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1154 #pragma no_inline(bge_mii_put16) 1155 1156 void 1157 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1158 { 1159 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1160 (void *)bgep, regno, data)); 1161 1162 ASSERT(mutex_owned(bgep->genlock)); 1163 1164 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1165 } 1166 1167 #undef BGE_DBG 1168 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1169 1170 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1171 1172 /* 1173 * Basic SEEPROM get/set access routine 1174 * 1175 * This uses the chip's SEEPROM auto-access method, controlled by the 1176 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1177 * doesn't have to fiddle with the individual bits. 1178 * 1179 * The caller should hold <genlock> and *also* have already acquired 1180 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1181 * 1182 * Return value: 1183 * 0 on success, 1184 * ENODATA on access timeout (maybe retryable: device may just be busy) 1185 * EPROTO on other h/w or s/w errors. 1186 * 1187 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1188 * from a (successful) SEEPROM_ACCESS_READ. 1189 */ 1190 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1191 uint32_t *dp); 1192 #pragma no_inline(bge_seeprom_access) 1193 1194 static int 1195 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1196 { 1197 uint32_t tries; 1198 uint32_t regval; 1199 1200 ASSERT(mutex_owned(bgep->genlock)); 1201 1202 /* 1203 * On the newer chips that support both SEEPROM & Flash, we need 1204 * to specifically enable SEEPROM access (Flash is the default). 1205 * On older chips, we don't; SEEPROM is the only NVtype supported, 1206 * and the NVM control registers don't exist ... 1207 */ 1208 switch (bgep->chipid.nvtype) { 1209 case BGE_NVTYPE_NONE: 1210 case BGE_NVTYPE_UNKNOWN: 1211 _NOTE(NOTREACHED) 1212 case BGE_NVTYPE_SEEPROM: 1213 break; 1214 1215 case BGE_NVTYPE_LEGACY_SEEPROM: 1216 case BGE_NVTYPE_UNBUFFERED_FLASH: 1217 case BGE_NVTYPE_BUFFERED_FLASH: 1218 default: 1219 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1220 NVM_CFG1_LEGACY_SEEPROM_MODE); 1221 break; 1222 } 1223 1224 /* 1225 * Check there's no command in progress. 1226 * 1227 * Note: this *shouldn't* ever find that there is a command 1228 * in progress, because we already hold the <genlock> mutex. 1229 * Also, to ensure we don't have a conflict with the chip's 1230 * internal firmware or a process accessing the same (shared) 1231 * SEEPROM through the other port of a 5704, we've already 1232 * been through the "software arbitration" protocol. 1233 * So this is just a final consistency check: we shouldn't 1234 * see EITHER the START bit (command started but not complete) 1235 * OR the COMPLETE bit (command completed but not cleared). 1236 */ 1237 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1238 if (regval & SEEPROM_ACCESS_START) 1239 return (EPROTO); 1240 if (regval & SEEPROM_ACCESS_COMPLETE) 1241 return (EPROTO); 1242 1243 /* 1244 * Assemble the command ... 1245 */ 1246 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1247 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1248 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1249 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1250 cmd |= SEEPROM_ACCESS_START; 1251 cmd |= SEEPROM_ACCESS_COMPLETE; 1252 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1253 1254 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1255 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1256 1257 /* 1258 * By observation, a successful access takes ~20us on a 5703/4, 1259 * but apparently much longer (up to 1000us) on the obsolescent 1260 * BCM5700/BCM5701. We want to be sure we don't get any false 1261 * timeouts here; but OTOH, we don't want a bogus access to lock 1262 * out interrupts for longer than necessary. So we'll allow up 1263 * to 1000us ... 1264 */ 1265 for (tries = 0; tries < 1000; ++tries) { 1266 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1267 if (regval & SEEPROM_ACCESS_COMPLETE) 1268 break; 1269 drv_usecwait(1); 1270 } 1271 1272 ASSERT((regval & SEEPROM_ACCESS_START) == 0); 1273 if (regval & SEEPROM_ACCESS_COMPLETE) { 1274 /* 1275 * All OK; read the SEEPROM data register, then write back 1276 * the value read from the address register in order to 1277 * clear the <complete> bit and leave the SEEPROM access 1278 * state machine idle, ready for the next access ... 1279 */ 1280 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1281 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1282 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1283 return (0); 1284 } 1285 1286 /* 1287 * Hmm ... what happened here? 1288 * 1289 * Most likely, the user addressed an non-existent SEEPROM. Or 1290 * maybe the SEEPROM was busy internally (e.g. processing a write) 1291 * and didn't respond to being addressed. Either way, it's left 1292 * the SEEPROM access state machine wedged. So we'll reset it 1293 * before we leave, so it's ready for next time ... 1294 */ 1295 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1296 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1297 return (ENODATA); 1298 } 1299 1300 /* 1301 * Basic Flash get/set access routine 1302 * 1303 * These use the chip's Flash auto-access method, controlled by the 1304 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1305 * fiddle with the individual bits. 1306 * 1307 * The caller should hold <genlock> and *also* have already acquired 1308 * the right to access the Flash, via bge_nvmem_acquire() above. 1309 * 1310 * Return value: 1311 * 0 on success, 1312 * ENODATA on access timeout (maybe retryable: device may just be busy) 1313 * ENODEV if the NVmem device is missing or otherwise unusable 1314 * 1315 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1316 * from a (successful) NVM_FLASH_CMD_RD. 1317 */ 1318 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1319 uint32_t *dp); 1320 #pragma no_inline(bge_flash_access) 1321 1322 static int 1323 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1324 { 1325 uint32_t tries; 1326 uint32_t regval; 1327 1328 ASSERT(mutex_owned(bgep->genlock)); 1329 1330 /* 1331 * On the newer chips that support both SEEPROM & Flash, we need 1332 * to specifically disable SEEPROM access while accessing Flash. 1333 * The older chips don't support Flash, and the NVM registers don't 1334 * exist, so we shouldn't be here at all! 1335 */ 1336 switch (bgep->chipid.nvtype) { 1337 case BGE_NVTYPE_NONE: 1338 case BGE_NVTYPE_UNKNOWN: 1339 _NOTE(NOTREACHED) 1340 case BGE_NVTYPE_SEEPROM: 1341 return (ENODEV); 1342 1343 case BGE_NVTYPE_LEGACY_SEEPROM: 1344 case BGE_NVTYPE_UNBUFFERED_FLASH: 1345 case BGE_NVTYPE_BUFFERED_FLASH: 1346 default: 1347 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1348 NVM_CFG1_LEGACY_SEEPROM_MODE); 1349 break; 1350 } 1351 1352 /* 1353 * Assemble the command ... 1354 */ 1355 addr &= NVM_FLASH_ADDR_MASK; 1356 cmd |= NVM_FLASH_CMD_DOIT; 1357 cmd |= NVM_FLASH_CMD_FIRST; 1358 cmd |= NVM_FLASH_CMD_LAST; 1359 cmd |= NVM_FLASH_CMD_DONE; 1360 1361 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1362 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1363 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1364 1365 /* 1366 * Allow up to 1000ms ... 1367 */ 1368 for (tries = 0; tries < 1000; ++tries) { 1369 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1370 if (regval & NVM_FLASH_CMD_DONE) 1371 break; 1372 drv_usecwait(1); 1373 } 1374 1375 if (regval & NVM_FLASH_CMD_DONE) { 1376 /* 1377 * All OK; read the data from the Flash read register 1378 */ 1379 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1380 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1381 return (0); 1382 } 1383 1384 /* 1385 * Hmm ... what happened here? 1386 * 1387 * Most likely, the user addressed an non-existent Flash. Or 1388 * maybe the Flash was busy internally (e.g. processing a write) 1389 * and didn't respond to being addressed. Either way, there's 1390 * nothing we can here ... 1391 */ 1392 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1393 return (ENODATA); 1394 } 1395 1396 /* 1397 * The next two functions regulate access to the NVram (if fitted). 1398 * 1399 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1400 * (SPI) interface, but they can be accessed through either port. These 1401 * are managed by different instance of this driver and have no software 1402 * state in common. 1403 * 1404 * In addition (and even on a single core chip) the chip's internal 1405 * firmware can access the SEEPROM/Flash, most notably after a RESET 1406 * when it may download code to run internally. 1407 * 1408 * So we need to arbitrate between these various software agents. For 1409 * this purpose, the chip provides the Software Arbitration Register, 1410 * which implements hardware(!) arbitration. 1411 * 1412 * This functionality didn't exist on older (5700/5701) chips, so there's 1413 * nothing we can do by way of arbitration on those; also, if there's no 1414 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1415 * nothing to do. 1416 * 1417 * The internal firmware appears to use Request 0, which is the highest 1418 * priority. So we'd like to use Request 2, leaving one higher and one 1419 * lower for any future developments ... but apparently this doesn't 1420 * always work. So for now, the code uses Request 1 ;-( 1421 */ 1422 1423 #define NVM_READ_REQ NVM_READ_REQ1 1424 #define NVM_RESET_REQ NVM_RESET_REQ1 1425 #define NVM_SET_REQ NVM_SET_REQ1 1426 1427 static void bge_nvmem_relinquish(bge_t *bgep); 1428 #pragma no_inline(bge_nvmem_relinquish) 1429 1430 static void 1431 bge_nvmem_relinquish(bge_t *bgep) 1432 { 1433 uint32_t regval; 1434 1435 ASSERT(mutex_owned(bgep->genlock)); 1436 1437 switch (bgep->chipid.nvtype) { 1438 case BGE_NVTYPE_NONE: 1439 case BGE_NVTYPE_UNKNOWN: 1440 _NOTE(NOTREACHED) 1441 return; 1442 1443 case BGE_NVTYPE_SEEPROM: 1444 /* 1445 * No arbitration performed, no release needed 1446 */ 1447 return; 1448 1449 case BGE_NVTYPE_LEGACY_SEEPROM: 1450 case BGE_NVTYPE_UNBUFFERED_FLASH: 1451 case BGE_NVTYPE_BUFFERED_FLASH: 1452 default: 1453 break; 1454 } 1455 1456 /* 1457 * Our own request should be present (whether or not granted) ... 1458 */ 1459 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1460 ASSERT((regval & NVM_READ_REQ) != 0); 1461 1462 /* 1463 * ... this will make it go away. 1464 */ 1465 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1466 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1467 ASSERT((regval & NVM_READ_REQ) == 0); 1468 } 1469 1470 /* 1471 * Arbitrate for access to the NVmem, if necessary 1472 * 1473 * Return value: 1474 * 0 on success 1475 * EAGAIN if the device is in use (retryable) 1476 * ENODEV if the NVmem device is missing or otherwise unusable 1477 */ 1478 static int bge_nvmem_acquire(bge_t *bgep); 1479 #pragma no_inline(bge_nvmem_acquire) 1480 1481 static int 1482 bge_nvmem_acquire(bge_t *bgep) 1483 { 1484 uint32_t regval; 1485 uint32_t tries; 1486 1487 ASSERT(mutex_owned(bgep->genlock)); 1488 1489 switch (bgep->chipid.nvtype) { 1490 case BGE_NVTYPE_NONE: 1491 case BGE_NVTYPE_UNKNOWN: 1492 /* 1493 * Access denied: no (recognisable) device fitted 1494 */ 1495 return (ENODEV); 1496 1497 case BGE_NVTYPE_SEEPROM: 1498 /* 1499 * Access granted: no arbitration needed (or possible) 1500 */ 1501 return (0); 1502 1503 case BGE_NVTYPE_LEGACY_SEEPROM: 1504 case BGE_NVTYPE_UNBUFFERED_FLASH: 1505 case BGE_NVTYPE_BUFFERED_FLASH: 1506 default: 1507 /* 1508 * Access conditional: conduct arbitration protocol 1509 */ 1510 break; 1511 } 1512 1513 /* 1514 * We're holding the per-port mutex <genlock>, so no-one other 1515 * threads can be attempting to access the NVmem through *this* 1516 * port. But it could be in use by the *other* port (of a 5704), 1517 * or by the chip's internal firmware, so we have to go through 1518 * the full (hardware) arbitration protocol ... 1519 * 1520 * Note that *because* we're holding <genlock>, the interrupt handler 1521 * won't be able to progress. So we're only willing to spin for a 1522 * fairly short time. Specifically: 1523 * 1524 * We *must* wait long enough for the hardware to resolve all 1525 * requests and determine the winner. Fortunately, this is 1526 * "almost instantaneous", even as observed by GHz CPUs. 1527 * 1528 * A successful access by another Solaris thread (via either 1529 * port) typically takes ~20us. So waiting a bit longer than 1530 * that will give a good chance of success, if the other user 1531 * *is* another thread on the other port. 1532 * 1533 * However, the internal firmware can hold on to the NVmem 1534 * for *much* longer: at least 10 milliseconds just after a 1535 * RESET, and maybe even longer if the NVmem actually contains 1536 * code to download and run on the internal CPUs. 1537 * 1538 * So, we'll allow 50us; if that's not enough then it's up to the 1539 * caller to retry later (hence the choice of return code EAGAIN). 1540 */ 1541 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1542 ASSERT((regval & NVM_READ_REQ) == 0); 1543 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1544 1545 for (tries = 0; tries < 50; ++tries) { 1546 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1547 ASSERT((regval & NVM_READ_REQ) != 0); 1548 if (regval & NVM_WON_REQ1) 1549 break; 1550 drv_usecwait(1); 1551 } 1552 1553 if (regval & NVM_WON_REQ1) { 1554 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1555 return (0); 1556 } 1557 1558 /* 1559 * Somebody else must be accessing the NVmem, so abandon our 1560 * attempt take control of it. The caller can try again later ... 1561 */ 1562 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1563 bge_nvmem_relinquish(bgep); 1564 return (EAGAIN); 1565 } 1566 1567 /* 1568 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1569 * write protect line in such a way that the NVmem is protected when 1570 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1571 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1572 * 1573 * Note: there's only one set of GPIO pins on a 5704, even though they 1574 * can be accessed through either port. So the chip has to resolve what 1575 * happens if the two ports program a single pin differently ... the rule 1576 * it uses is that if the ports disagree about the *direction* of a pin, 1577 * "output" wins over "input", but if they disagree about its *value* as 1578 * an output, then the pin is TRISTATED instead! In such a case, no-one 1579 * wins, and the external signal does whatever the external circuitry 1580 * defines as the default -- which we've assumed is the PROTECTED state. 1581 * So, we always change GPIO1 back to being an *input* whenever we're not 1582 * specifically using it to unprotect the NVmem. This allows either port 1583 * to update the NVmem, although obviously only one at a a time! 1584 * 1585 * The caller should hold <genlock> and *also* have already acquired the 1586 * right to access the NVmem, via bge_nvmem_acquire() above. 1587 */ 1588 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1589 #pragma inline(bge_nvmem_protect) 1590 1591 static void 1592 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1593 { 1594 uint32_t regval; 1595 1596 ASSERT(mutex_owned(bgep->genlock)); 1597 1598 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1599 if (protect) { 1600 regval |= MLCR_MISC_PINS_OUTPUT_1; 1601 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1602 } else { 1603 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1604 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1605 } 1606 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1607 } 1608 1609 /* 1610 * Now put it all together ... 1611 * 1612 * Try to acquire control of the NVmem; if successful, then: 1613 * unprotect it (if we want to write to it) 1614 * perform the requested access 1615 * reprotect it (after a write) 1616 * relinquish control 1617 * 1618 * Return value: 1619 * 0 on success, 1620 * EAGAIN if the device is in use (retryable) 1621 * ENODATA on access timeout (maybe retryable: device may just be busy) 1622 * ENODEV if the NVmem device is missing or otherwise unusable 1623 * EPROTO on other h/w or s/w errors. 1624 */ 1625 static int 1626 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1627 { 1628 int err; 1629 1630 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1631 switch (cmd) { 1632 case BGE_SEE_READ: 1633 err = bge_seeprom_access(bgep, 1634 SEEPROM_ACCESS_READ, addr, dp); 1635 break; 1636 1637 case BGE_SEE_WRITE: 1638 bge_nvmem_protect(bgep, B_FALSE); 1639 err = bge_seeprom_access(bgep, 1640 SEEPROM_ACCESS_WRITE, addr, dp); 1641 bge_nvmem_protect(bgep, B_TRUE); 1642 break; 1643 1644 case BGE_FLASH_READ: 1645 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1646 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1647 bge_reg_set32(bgep, NVM_ACCESS_REG, 1648 NVM_ACCESS_ENABLE); 1649 } 1650 err = bge_flash_access(bgep, 1651 NVM_FLASH_CMD_RD, addr, dp); 1652 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1653 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1654 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1655 NVM_ACCESS_ENABLE); 1656 } 1657 break; 1658 1659 case BGE_FLASH_WRITE: 1660 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1661 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1662 bge_reg_set32(bgep, NVM_ACCESS_REG, 1663 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1664 } 1665 bge_nvmem_protect(bgep, B_FALSE); 1666 err = bge_flash_access(bgep, 1667 NVM_FLASH_CMD_WR, addr, dp); 1668 bge_nvmem_protect(bgep, B_TRUE); 1669 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1670 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1671 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1672 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1673 } 1674 1675 break; 1676 1677 default: 1678 _NOTE(NOTREACHED) 1679 break; 1680 } 1681 bge_nvmem_relinquish(bgep); 1682 } 1683 1684 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1685 return (err); 1686 } 1687 1688 /* 1689 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1690 */ 1691 static uint64_t bge_get_nvmac(bge_t *bgep); 1692 #pragma no_inline(bge_get_nvmac) 1693 1694 static uint64_t 1695 bge_get_nvmac(bge_t *bgep) 1696 { 1697 uint32_t mac_high; 1698 uint32_t mac_low; 1699 uint32_t addr; 1700 uint32_t cmd; 1701 uint64_t mac; 1702 1703 BGE_TRACE(("bge_get_nvmac($%p)", 1704 (void *)bgep)); 1705 1706 switch (bgep->chipid.nvtype) { 1707 case BGE_NVTYPE_NONE: 1708 case BGE_NVTYPE_UNKNOWN: 1709 default: 1710 return (0ULL); 1711 1712 case BGE_NVTYPE_SEEPROM: 1713 case BGE_NVTYPE_LEGACY_SEEPROM: 1714 cmd = BGE_SEE_READ; 1715 break; 1716 1717 case BGE_NVTYPE_UNBUFFERED_FLASH: 1718 case BGE_NVTYPE_BUFFERED_FLASH: 1719 cmd = BGE_FLASH_READ; 1720 break; 1721 } 1722 1723 addr = NVMEM_DATA_MAC_ADDRESS; 1724 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1725 return (0ULL); 1726 addr += 4; 1727 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1728 return (0ULL); 1729 1730 /* 1731 * The Broadcom chip is natively BIG-endian, so that's how the 1732 * MAC address is represented in NVmem. We may need to swap it 1733 * around on a little-endian host ... 1734 */ 1735 #ifdef _BIG_ENDIAN 1736 mac = mac_high; 1737 mac = mac << 32; 1738 mac |= mac_low; 1739 #else 1740 mac = BGE_BSWAP_32(mac_high); 1741 mac = mac << 32; 1742 mac |= BGE_BSWAP_32(mac_low); 1743 #endif /* _BIG_ENDIAN */ 1744 1745 return (mac); 1746 } 1747 1748 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1749 1750 /* 1751 * Dummy version for when we're not supporting NVmem access 1752 */ 1753 static uint64_t bge_get_nvmac(bge_t *bgep); 1754 #pragma inline(bge_get_nvmac) 1755 1756 static uint64_t 1757 bge_get_nvmac(bge_t *bgep) 1758 { 1759 _NOTE(ARGUNUSED(bgep)) 1760 return (0ULL); 1761 } 1762 1763 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1764 1765 /* 1766 * Determine the type of NVmem that is (or may be) attached to this chip, 1767 */ 1768 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1769 #pragma no_inline(bge_nvmem_id) 1770 1771 static enum bge_nvmem_type 1772 bge_nvmem_id(bge_t *bgep) 1773 { 1774 enum bge_nvmem_type nvtype; 1775 uint32_t config1; 1776 1777 BGE_TRACE(("bge_nvmem_id($%p)", 1778 (void *)bgep)); 1779 1780 switch (bgep->chipid.device) { 1781 default: 1782 /* 1783 * We shouldn't get here; it means we don't recognise 1784 * the chip, which means we don't know how to determine 1785 * what sort of NVmem (if any) it has. So we'll say 1786 * NONE, to disable the NVmem access code ... 1787 */ 1788 nvtype = BGE_NVTYPE_NONE; 1789 break; 1790 1791 case DEVICE_ID_5700: 1792 case DEVICE_ID_5700x: 1793 case DEVICE_ID_5701: 1794 /* 1795 * These devices support *only* SEEPROMs 1796 */ 1797 nvtype = BGE_NVTYPE_SEEPROM; 1798 break; 1799 1800 case DEVICE_ID_5702: 1801 case DEVICE_ID_5702fe: 1802 case DEVICE_ID_5703C: 1803 case DEVICE_ID_5703S: 1804 case DEVICE_ID_5704C: 1805 case DEVICE_ID_5704S: 1806 case DEVICE_ID_5704: 1807 case DEVICE_ID_5705M: 1808 case DEVICE_ID_5705C: 1809 case DEVICE_ID_5706: 1810 case DEVICE_ID_5782: 1811 case DEVICE_ID_5788: 1812 case DEVICE_ID_5751: 1813 case DEVICE_ID_5751M: 1814 case DEVICE_ID_5721: 1815 case DEVICE_ID_5714C: 1816 case DEVICE_ID_5714S: 1817 case DEVICE_ID_5715C: 1818 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1819 if (config1 & NVM_CFG1_FLASH_MODE) 1820 if (config1 & NVM_CFG1_BUFFERED_MODE) 1821 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1822 else 1823 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1824 else 1825 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1826 break; 1827 } 1828 1829 return (nvtype); 1830 } 1831 1832 #undef BGE_DBG 1833 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1834 1835 static void 1836 bge_init_recv_rule(bge_t *bgep) 1837 { 1838 bge_recv_rule_t *rulep; 1839 uint32_t i; 1840 1841 /* 1842 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1843 * 1. to direct UDP traffic, set: 1844 * rulep->control = RULE_PROTO_CONTROL; 1845 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1846 * 2. to direct ICMP traffic, set: 1847 * rulep->control = RULE_PROTO_CONTROL; 1848 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1849 * 3. to direct traffic by source ip, set: 1850 * rulep->control = RULE_SIP_CONTROL; 1851 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1852 */ 1853 rulep = bgep->recv_rules; 1854 rulep->control = RULE_PROTO_CONTROL; 1855 rulep->mask_value = RULE_TCP_MASK_VALUE; 1856 1857 /* 1858 * set receive rule registers 1859 */ 1860 rulep = bgep->recv_rules; 1861 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1862 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1863 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1864 } 1865 } 1866 1867 /* 1868 * Using the values captured by bge_chip_cfg_init(), and additional probes 1869 * as required, characterise the chip fully: determine the label by which 1870 * to refer to this chip, the correct settings for various registers, and 1871 * of course whether the device and/or subsystem are supported! 1872 */ 1873 void bge_chip_id_init(bge_t *bgep); 1874 #pragma no_inline(bge_chip_id_init) 1875 1876 void 1877 bge_chip_id_init(bge_t *bgep) 1878 { 1879 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1880 boolean_t sys_ok; 1881 boolean_t dev_ok; 1882 chip_id_t *cidp; 1883 uint32_t subid; 1884 char *devname; 1885 char *sysname; 1886 int *ids; 1887 int err; 1888 uint_t i; 1889 1890 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1891 1892 sys_ok = dev_ok = B_FALSE; 1893 cidp = &bgep->chipid; 1894 1895 /* 1896 * Check the PCI device ID to determine the generic chip type and 1897 * select parameters that depend on this. 1898 * 1899 * Note: because the SPARC platforms in general don't fit the 1900 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1901 * as zero - which is why we use <asic_rev> rather than <revision> 1902 * below ... 1903 * 1904 * Note: in general we can't distinguish between the Copper/SerDes 1905 * versions by ID alone, as some Copper devices (e.g. some but not 1906 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1907 * treat them the same here, and the MII code works out the media 1908 * type later on ... 1909 */ 1910 cidp->mbuf_base = bge_mbuf_pool_base; 1911 cidp->mbuf_length = bge_mbuf_pool_len; 1912 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1913 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1914 cidp->pci_type = BGE_PCI_X; 1915 cidp->statistic_type = BGE_STAT_BLK; 1916 1917 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1918 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1919 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1920 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1921 1922 cidp->msi_enabled = B_FALSE; 1923 1924 switch (cidp->device) { 1925 case DEVICE_ID_5700: 1926 case DEVICE_ID_5700x: 1927 cidp->chip_label = 5700; 1928 cidp->flags |= CHIP_FLAG_NO_CSUM; 1929 break; 1930 1931 case DEVICE_ID_5701: 1932 cidp->chip_label = 5701; 1933 dev_ok = B_TRUE; 1934 cidp->flags |= CHIP_FLAG_NO_CSUM; 1935 break; 1936 1937 case DEVICE_ID_5702: 1938 case DEVICE_ID_5702fe: 1939 cidp->chip_label = 5702; 1940 dev_ok = B_TRUE; 1941 cidp->flags |= CHIP_FLAG_NO_CSUM; /* for now */ 1942 break; 1943 1944 case DEVICE_ID_5703C: 1945 case DEVICE_ID_5703S: 1946 case DEVICE_ID_5703: 1947 /* 1948 * Revision A0 of the 5703/5793 had various errata 1949 * that we can't or don't work around, so it's not 1950 * supported, but all later versions are 1951 */ 1952 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1953 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1954 dev_ok = B_TRUE; 1955 break; 1956 1957 case DEVICE_ID_5704C: 1958 case DEVICE_ID_5704S: 1959 case DEVICE_ID_5704: 1960 /* 1961 * Revision A0 of the 5704/5794 had various errata 1962 * but we have workarounds, so it *is* supported. 1963 */ 1964 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1965 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1966 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1967 dev_ok = B_TRUE; 1968 break; 1969 1970 case DEVICE_ID_5705C: 1971 case DEVICE_ID_5705M: 1972 case DEVICE_ID_5705MA3: 1973 case DEVICE_ID_5705F: 1974 cidp->chip_label = 5705; 1975 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1976 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1977 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1978 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1979 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 1980 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1981 cidp->statistic_type = BGE_STAT_REG; 1982 dev_ok = B_TRUE; 1983 break; 1984 1985 case DEVICE_ID_5706: 1986 cidp->chip_label = 5706; 1987 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1988 cidp->flags |= CHIP_FLAG_NO_CSUM; /* for now */ 1989 break; 1990 1991 case DEVICE_ID_5782: 1992 /* 1993 * Apart from the label, we treat this as a 5705(?) 1994 */ 1995 cidp->chip_label = 5782; 1996 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1997 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1998 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1999 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2000 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2001 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2002 cidp->statistic_type = BGE_STAT_REG; 2003 dev_ok = B_TRUE; 2004 break; 2005 2006 case DEVICE_ID_5788: 2007 /* 2008 * Apart from the label, we treat this as a 5705(?) 2009 */ 2010 cidp->chip_label = 5788; 2011 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2012 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2013 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2014 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2015 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2016 cidp->statistic_type = BGE_STAT_REG; 2017 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2018 dev_ok = B_TRUE; 2019 break; 2020 2021 case DEVICE_ID_5714C: 2022 if (cidp->revision >= REVISION_ID_5714_A2) 2023 cidp->msi_enabled = bge_enable_msi; 2024 /* FALLTHRU */ 2025 case DEVICE_ID_5714S: 2026 cidp->chip_label = 5714; 2027 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2028 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2029 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2030 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2031 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2032 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2033 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2034 cidp->pci_type = BGE_PCI_E; 2035 cidp->statistic_type = BGE_STAT_REG; 2036 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2037 dev_ok = B_TRUE; 2038 break; 2039 2040 case DEVICE_ID_5715C: 2041 cidp->chip_label = 5715; 2042 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2043 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2044 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2045 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2046 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2047 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2048 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2049 cidp->pci_type = BGE_PCI_E; 2050 cidp->statistic_type = BGE_STAT_REG; 2051 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2052 dev_ok = B_TRUE; 2053 break; 2054 2055 case DEVICE_ID_5721: 2056 cidp->chip_label = 5721; 2057 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2058 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2059 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2060 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2061 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2062 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2063 cidp->pci_type = BGE_PCI_E; 2064 cidp->statistic_type = BGE_STAT_REG; 2065 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2066 dev_ok = B_TRUE; 2067 break; 2068 2069 case DEVICE_ID_5751: 2070 case DEVICE_ID_5751M: 2071 cidp->chip_label = 5751; 2072 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2073 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2074 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2075 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2076 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2077 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2078 cidp->pci_type = BGE_PCI_E; 2079 cidp->statistic_type = BGE_STAT_REG; 2080 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2081 dev_ok = B_TRUE; 2082 break; 2083 2084 } 2085 2086 /* 2087 * Setup the default jumbo parameter. 2088 */ 2089 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 2090 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 2091 cidp->mbuf_hi_water = bge_mbuf_hi_water; 2092 cidp->ethmax_size = ETHERMAX; 2093 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2094 2095 /* 2096 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2097 * setup below jumbo specific parameters. 2098 */ 2099 if (bge_jumbo_enable && 2100 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2101 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2102 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2103 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_JUMBO; 2104 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_JUMBO; 2105 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2106 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2107 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2108 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2109 cidp->ethmax_size = cidp->default_mtu + 2110 sizeof (struct ether_header); 2111 } 2112 2113 /* 2114 * Identify the NV memory type: SEEPROM or Flash? 2115 */ 2116 cidp->nvtype = bge_nvmem_id(bgep); 2117 2118 /* 2119 * Now, we want to check whether this device is part of a 2120 * supported subsystem (e.g., on the motherboard of a Sun 2121 * branded platform). 2122 * 2123 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2124 */ 2125 if (cidp->subven == VENDOR_ID_SUN) 2126 sys_ok = B_TRUE; 2127 2128 /* 2129 * Rule 2: If it's on the list on known subsystems, then it's OK. 2130 * Note: 0x14e41647 should *not* appear in the list, but the code 2131 * doesn't enforce that. 2132 */ 2133 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2134 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2135 if (err == DDI_PROP_SUCCESS) { 2136 /* 2137 * Got the list; scan for a matching subsystem vendor/device 2138 */ 2139 subid = (cidp->subven << 16) | cidp->subdev; 2140 while (i--) 2141 if (ids[i] == subid) 2142 sys_ok = B_TRUE; 2143 ddi_prop_free(ids); 2144 } 2145 2146 /* 2147 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2148 * 2149 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2150 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2151 * we have to check specially for the exact device paths to the 2152 * motherboard devices on those platforms ;-( 2153 * 2154 * Note: we can't just use the "supported-subsystems" mechanism 2155 * above, because the entry would have to be 0x14e41647 -- which 2156 * would then accept *any* plugin card that *didn't* contain a 2157 * (valid) SEEPROM ;-( 2158 */ 2159 sysname = ddi_node_name(ddi_root_node()); 2160 devname = ddi_pathname(bgep->devinfo, buf); 2161 ASSERT(strlen(devname) > 0); 2162 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2163 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2164 sys_ok = B_TRUE; 2165 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2166 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2167 sys_ok = B_TRUE; 2168 2169 /* 2170 * Now check what we've discovered: is this truly a supported 2171 * chip on (the motherboard of) a supported platform? 2172 * 2173 * Possible problems here: 2174 * 1) it's a completely unheard-of chip (e.g. 5761) 2175 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2176 * 3) it's a chip we would support if it were on the motherboard 2177 * of a Sun platform, but this one isn't ;-( 2178 */ 2179 if (cidp->chip_label == 0) 2180 bge_problem(bgep, 2181 "Device 'pci%04x,%04x' not recognized (%d?)", 2182 cidp->vendor, cidp->device, cidp->device); 2183 else if (!dev_ok) 2184 bge_problem(bgep, 2185 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2186 cidp->vendor, cidp->device, cidp->chip_label, 2187 cidp->revision); 2188 #if BGE_DEBUGGING 2189 else if (!sys_ok) 2190 bge_problem(bgep, 2191 "%d-based subsystem 'pci%04x,%04x' not validated", 2192 cidp->chip_label, cidp->subven, cidp->subdev); 2193 #endif 2194 else 2195 cidp->flags |= CHIP_FLAG_SUPPORTED; 2196 } 2197 2198 void 2199 bge_chip_msi_trig(bge_t *bgep) 2200 { 2201 uint32_t regval; 2202 2203 regval = bgep->param_msi_cnt<<4; 2204 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2205 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2206 } 2207 2208 /* 2209 * Various registers that control the chip's internal engines (state 2210 * machines) have a <reset> and <enable> bits (fortunately, in the 2211 * same place in each such register :-). 2212 * 2213 * To reset the state machine, the <reset> bit must be written with 1; 2214 * it will then read back as 1 while the reset is in progress, but 2215 * self-clear to 0 when the reset completes. 2216 * 2217 * To enable a state machine, one must set the <enable> bit, which 2218 * will continue to read back as 0 until the state machine is running. 2219 * 2220 * To disable a state machine, the <enable> bit must be cleared, but 2221 * it will continue to read back as 1 until the state machine actually 2222 * stops. 2223 * 2224 * This routine implements polling for completion of a reset, enable 2225 * or disable operation, returning B_TRUE on success (bit reached the 2226 * required state) or B_FALSE on timeout (200*100us == 20ms). 2227 */ 2228 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2229 uint32_t mask, uint32_t val); 2230 #pragma no_inline(bge_chip_poll_engine) 2231 2232 static boolean_t 2233 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2234 uint32_t mask, uint32_t val) 2235 { 2236 uint32_t regval; 2237 uint32_t n; 2238 2239 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2240 (void *)bgep, regno, mask, val)); 2241 2242 for (n = 200; n; --n) { 2243 regval = bge_reg_get32(bgep, regno); 2244 if ((regval & mask) == val) 2245 return (B_TRUE); 2246 drv_usecwait(100); 2247 } 2248 2249 return (B_FALSE); 2250 } 2251 2252 /* 2253 * Various registers that control the chip's internal engines (state 2254 * machines) have a <reset> bit (fortunately, in the same place in 2255 * each such register :-). To reset the state machine, this bit must 2256 * be written with 1; it will then read back as 1 while the reset is 2257 * in progress, but self-clear to 0 when the reset completes. 2258 * 2259 * This code sets the bit, then polls for it to read back as zero. 2260 * The return value is B_TRUE on success (reset bit cleared itself), 2261 * or B_FALSE if the state machine didn't recover :( 2262 * 2263 * NOTE: the Core reset is similar to other resets, except that we 2264 * can't poll for completion, since the Core reset disables memory 2265 * access! So we just have to assume that it will all complete in 2266 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2267 */ 2268 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2269 #pragma no_inline(bge_chip_reset_engine) 2270 2271 static boolean_t 2272 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2273 { 2274 uint32_t regval; 2275 uint32_t val32; 2276 2277 regval = bge_reg_get32(bgep, regno); 2278 2279 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2280 (void *)bgep, regno)); 2281 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2282 regno, regval)); 2283 2284 regval |= STATE_MACHINE_RESET_BIT; 2285 2286 switch (regno) { 2287 case MISC_CONFIG_REG: 2288 /* 2289 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2290 * resetting PCIE block and bringing PCIE link down, bit 29 2291 * in the register needs to be set first, and then set it again 2292 * while the reset bit is written. 2293 * See:P500 of 57xx-PG102-RDS.pdf. 2294 */ 2295 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2296 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2297 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2298 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2299 if (bgep->chipid.pci_type == BGE_PCI_E) { 2300 if (bgep->chipid.asic_rev == 2301 MHCR_CHIP_REV_5751_A0 || 2302 bgep->chipid.asic_rev == 2303 MHCR_CHIP_REV_5721_A0) { 2304 val32 = bge_reg_get32(bgep, 2305 PHY_TEST_CTRL_REG); 2306 if (val32 == (PHY_PCIE_SCRAM_MODE | 2307 PHY_PCIE_LTASS_MODE)) 2308 bge_reg_put32(bgep, 2309 PHY_TEST_CTRL_REG, 2310 PHY_PCIE_SCRAM_MODE); 2311 val32 = pci_config_get32 2312 (bgep->cfg_handle, 2313 PCI_CONF_BGE_CLKCTL); 2314 val32 |= CLKCTL_PCIE_A0_FIX; 2315 pci_config_put32(bgep->cfg_handle, 2316 PCI_CONF_BGE_CLKCTL, val32); 2317 } 2318 bge_reg_set32(bgep, regno, 2319 MISC_CONFIG_GRC_RESET_DISABLE); 2320 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2321 } 2322 } 2323 2324 /* 2325 * Special case - causes Core reset 2326 * 2327 * On SPARC v9 we want to ensure that we don't start 2328 * timing until the I/O access has actually reached 2329 * the chip, otherwise we might make the next access 2330 * too early. And we can't just force the write out 2331 * by following it with a read (even to config space) 2332 * because that would cause the fault we're trying 2333 * to avoid. Hence the need for membar_sync() here. 2334 */ 2335 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2336 #ifdef __sparcv9 2337 membar_sync(); 2338 #endif /* __sparcv9 */ 2339 /* 2340 * On some platforms,system need about 300us for 2341 * link setup. 2342 */ 2343 drv_usecwait(300); 2344 2345 if (bgep->chipid.pci_type == BGE_PCI_E) { 2346 /* PCI-E device need more reset time */ 2347 drv_usecwait(120000); 2348 2349 /* Set PCIE max payload size and clear error status. */ 2350 if (bgep->chipid.chip_label == 5721 || 2351 bgep->chipid.chip_label == 5751) { 2352 pci_config_put16(bgep->cfg_handle, 2353 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2354 pci_config_put16(bgep->cfg_handle, 2355 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2356 } 2357 } 2358 2359 BGE_PCICHK(bgep); 2360 return (B_TRUE); 2361 2362 default: 2363 bge_reg_put32(bgep, regno, regval); 2364 return (bge_chip_poll_engine(bgep, regno, 2365 STATE_MACHINE_RESET_BIT, 0)); 2366 } 2367 } 2368 2369 /* 2370 * Various registers that control the chip's internal engines (state 2371 * machines) have an <enable> bit (fortunately, in the same place in 2372 * each such register :-). To stop the state machine, this bit must 2373 * be written with 0, then polled to see when the state machine has 2374 * actually stopped. 2375 * 2376 * The return value is B_TRUE on success (enable bit cleared), or 2377 * B_FALSE if the state machine didn't stop :( 2378 */ 2379 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2380 uint32_t morebits); 2381 #pragma no_inline(bge_chip_disable_engine) 2382 2383 static boolean_t 2384 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2385 { 2386 uint32_t regval; 2387 2388 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2389 (void *)bgep, regno, morebits)); 2390 2391 switch (regno) { 2392 case FTQ_RESET_REG: 2393 /* 2394 * Not quite like the others; it doesn't 2395 * have an <enable> bit, but instead we 2396 * have to set and then clear all the bits 2397 */ 2398 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2399 drv_usecwait(100); 2400 bge_reg_put32(bgep, regno, 0); 2401 return (B_TRUE); 2402 2403 default: 2404 regval = bge_reg_get32(bgep, regno); 2405 regval &= ~STATE_MACHINE_ENABLE_BIT; 2406 regval &= ~morebits; 2407 bge_reg_put32(bgep, regno, regval); 2408 return (bge_chip_poll_engine(bgep, regno, 2409 STATE_MACHINE_ENABLE_BIT, 0)); 2410 } 2411 } 2412 2413 /* 2414 * Various registers that control the chip's internal engines (state 2415 * machines) have an <enable> bit (fortunately, in the same place in 2416 * each such register :-). To start the state machine, this bit must 2417 * be written with 1, then polled to see when the state machine has 2418 * actually started. 2419 * 2420 * The return value is B_TRUE on success (enable bit set), or 2421 * B_FALSE if the state machine didn't start :( 2422 */ 2423 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2424 uint32_t morebits); 2425 #pragma no_inline(bge_chip_enable_engine) 2426 2427 static boolean_t 2428 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2429 { 2430 uint32_t regval; 2431 2432 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2433 (void *)bgep, regno, morebits)); 2434 2435 switch (regno) { 2436 case FTQ_RESET_REG: 2437 /* 2438 * Not quite like the others; it doesn't 2439 * have an <enable> bit, but instead we 2440 * have to set and then clear all the bits 2441 */ 2442 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2443 drv_usecwait(100); 2444 bge_reg_put32(bgep, regno, 0); 2445 return (B_TRUE); 2446 2447 default: 2448 regval = bge_reg_get32(bgep, regno); 2449 regval |= STATE_MACHINE_ENABLE_BIT; 2450 regval |= morebits; 2451 bge_reg_put32(bgep, regno, regval); 2452 return (bge_chip_poll_engine(bgep, regno, 2453 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2454 } 2455 } 2456 2457 /* 2458 * Reprogram the Ethernet, Transmit, and Receive MAC 2459 * modes to match the param_* variables 2460 */ 2461 static void bge_sync_mac_modes(bge_t *bgep); 2462 #pragma no_inline(bge_sync_mac_modes) 2463 2464 static void 2465 bge_sync_mac_modes(bge_t *bgep) 2466 { 2467 uint32_t macmode; 2468 uint32_t regval; 2469 2470 ASSERT(mutex_owned(bgep->genlock)); 2471 2472 /* 2473 * Reprogram the Ethernet MAC mode ... 2474 */ 2475 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2476 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2477 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2478 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2479 else 2480 macmode |= ETHERNET_MODE_LINK_POLARITY; 2481 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2482 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2483 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2484 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2485 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2486 macmode |= ETHERNET_MODE_PORTMODE_MII; 2487 else 2488 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2489 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2490 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2491 else 2492 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2493 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2494 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2495 else 2496 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2497 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2498 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2499 (void *)bgep, regval, macmode)); 2500 2501 /* 2502 * ... the Transmit MAC mode ... 2503 */ 2504 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2505 if (bgep->param_link_tx_pause) 2506 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2507 else 2508 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2509 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2510 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2511 (void *)bgep, regval, macmode)); 2512 2513 /* 2514 * ... and the Receive MAC mode 2515 */ 2516 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2517 if (bgep->param_link_rx_pause) 2518 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2519 else 2520 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2521 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2522 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2523 (void *)bgep, regval, macmode)); 2524 } 2525 2526 /* 2527 * bge_chip_sync() -- program the chip with the unicast MAC address, 2528 * the multicast hash table, the required level of promiscuity, and 2529 * the current loopback mode ... 2530 */ 2531 #ifdef BGE_IPMI_ASF 2532 void bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2533 #else 2534 void bge_chip_sync(bge_t *bgep); 2535 #endif 2536 #pragma no_inline(bge_chip_sync) 2537 2538 void 2539 #ifdef BGE_IPMI_ASF 2540 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2541 #else 2542 bge_chip_sync(bge_t *bgep) 2543 #endif 2544 { 2545 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2546 boolean_t promisc; 2547 uint64_t macaddr; 2548 uint32_t fill; 2549 int i; 2550 2551 BGE_TRACE(("bge_chip_sync($%p)", 2552 (void *)bgep)); 2553 2554 ASSERT(mutex_owned(bgep->genlock)); 2555 2556 promisc = B_FALSE; 2557 fill = ~(uint32_t)0; 2558 2559 if (bgep->promisc) 2560 promisc = B_TRUE; 2561 else 2562 fill = (uint32_t)0; 2563 2564 /* 2565 * If the TX/RX MAC engines are already running, we should stop 2566 * them (and reset the RX engine) before changing the parameters. 2567 * If they're not running, this will have no effect ... 2568 * 2569 * NOTE: this is currently disabled by default because stopping 2570 * and restarting the Tx engine may cause an outgoing packet in 2571 * transit to be truncated. Also, stopping and restarting the 2572 * Rx engine seems to not work correctly on the 5705. Testing 2573 * has not (yet!) revealed any problems with NOT stopping and 2574 * restarting these engines (and Broadcom say their drivers don't 2575 * do this), but if it is found to cause problems, this variable 2576 * can be patched to re-enable the old behaviour ... 2577 */ 2578 if (bge_stop_start_on_sync) { 2579 #ifdef BGE_IPMI_ASF 2580 if (bgep->asf_enabled) { 2581 (void) bge_chip_disable_engine(bgep, 2582 RECEIVE_MAC_MODE_REG, 0); 2583 } else { 2584 (void) bge_chip_disable_engine(bgep, 2585 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG); 2586 } 2587 #else 2588 (void) bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2589 RECEIVE_MODE_KEEP_VLAN_TAG); 2590 #endif 2591 (void) bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 2592 (void) bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG); 2593 } 2594 2595 /* 2596 * Reprogram the hashed multicast address table ... 2597 */ 2598 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2599 bge_reg_put32(bgep, MAC_HASH_REG(i), 2600 bgep->mcast_hash[i] | fill); 2601 2602 #ifdef BGE_IPMI_ASF 2603 if (!bgep->asf_enabled || !asf_keeplive) { 2604 #endif 2605 /* 2606 * Transform the MAC address from host to chip format, then 2607 * reprogram the transmit random backoff seed and the unicast 2608 * MAC address(es) ... 2609 */ 2610 for (i = 0, fill = 0, macaddr = 0ull; i < ETHERADDRL; ++i) { 2611 macaddr <<= 8; 2612 macaddr |= bgep->curr_addr.addr[i]; 2613 fill += bgep->curr_addr.addr[i]; 2614 } 2615 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2616 for (i = 0; i < MAC_ADDRESS_REGS_MAX; ++i) 2617 bge_reg_put64(bgep, MAC_ADDRESS_REG(i), macaddr); 2618 2619 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2620 (void *)bgep, macaddr)); 2621 #ifdef BGE_IPMI_ASF 2622 } 2623 #endif 2624 2625 /* 2626 * Set or clear the PROMISCUOUS mode bit 2627 */ 2628 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2629 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2630 2631 /* 2632 * Sync the rest of the MAC modes too ... 2633 */ 2634 bge_sync_mac_modes(bgep); 2635 2636 /* 2637 * Restart RX/TX MAC engines if required ... 2638 */ 2639 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2640 (void) bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 2641 #ifdef BGE_IPMI_ASF 2642 if (bgep->asf_enabled) { 2643 (void) bge_chip_enable_engine(bgep, 2644 RECEIVE_MAC_MODE_REG, 0); 2645 } else { 2646 (void) bge_chip_enable_engine(bgep, 2647 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG); 2648 } 2649 #else 2650 (void) bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2651 RECEIVE_MODE_KEEP_VLAN_TAG); 2652 #endif 2653 } 2654 } 2655 2656 /* 2657 * This array defines the sequence of state machine control registers 2658 * in which the <enable> bit must be cleared to bring the chip to a 2659 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2660 */ 2661 static bge_regno_t shutdown_engine_regs[] = { 2662 RECEIVE_MAC_MODE_REG, 2663 RCV_BD_INITIATOR_MODE_REG, 2664 RCV_LIST_PLACEMENT_MODE_REG, 2665 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2666 RCV_DATA_BD_INITIATOR_MODE_REG, 2667 RCV_DATA_COMPLETION_MODE_REG, 2668 RCV_BD_COMPLETION_MODE_REG, 2669 2670 SEND_BD_SELECTOR_MODE_REG, 2671 SEND_BD_INITIATOR_MODE_REG, 2672 SEND_DATA_INITIATOR_MODE_REG, 2673 READ_DMA_MODE_REG, 2674 SEND_DATA_COMPLETION_MODE_REG, 2675 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2676 SEND_BD_COMPLETION_MODE_REG, 2677 TRANSMIT_MAC_MODE_REG, 2678 2679 HOST_COALESCE_MODE_REG, 2680 WRITE_DMA_MODE_REG, 2681 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2682 FTQ_RESET_REG, /* special - see code */ 2683 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2684 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2685 BGE_REGNO_NONE /* terminator */ 2686 }; 2687 2688 /* 2689 * bge_chip_stop() -- stop all chip processing 2690 * 2691 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2692 * we've detected a problem internally; otherwise, this is a normal 2693 * (clean) stop (at user request i.e. the last STREAM has been closed). 2694 */ 2695 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2696 #pragma no_inline(bge_chip_stop) 2697 2698 void 2699 bge_chip_stop(bge_t *bgep, boolean_t fault) 2700 { 2701 bge_regno_t regno; 2702 bge_regno_t *rbp; 2703 boolean_t ok; 2704 2705 BGE_TRACE(("bge_chip_stop($%p)", 2706 (void *)bgep)); 2707 2708 ASSERT(mutex_owned(bgep->genlock)); 2709 2710 rbp = shutdown_engine_regs; 2711 /* 2712 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2713 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2714 * -ory arbiter should not be disabled. 2715 */ 2716 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2717 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2718 ok &= bge_chip_disable_engine(bgep, regno, 0); 2719 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2720 (regno != DMA_COMPLETION_MODE_REG) && 2721 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2722 (regno != BUFFER_MANAGER_MODE_REG) && 2723 (regno != MEMORY_ARBITER_MODE_REG)) 2724 ok &= bge_chip_disable_engine(bgep, 2725 regno, 0); 2726 } 2727 2728 /* 2729 * Finally, disable (all) MAC events & clear the MAC status 2730 */ 2731 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2732 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2733 2734 /* 2735 * Do we need to check whether everything completed OK? 2736 * Probably not ... it always works anyway. 2737 */ 2738 2739 if (fault) 2740 bgep->bge_chip_state = BGE_CHIP_FAULT; 2741 else 2742 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2743 } 2744 2745 /* 2746 * Poll for completion of chip's ROM firmware; also, at least on the 2747 * first time through, find and return the hardware MAC address, if any. 2748 */ 2749 static uint64_t bge_poll_firmware(bge_t *bgep); 2750 #pragma no_inline(bge_poll_firmware) 2751 2752 static uint64_t 2753 bge_poll_firmware(bge_t *bgep) 2754 { 2755 uint64_t magic; 2756 uint64_t mac; 2757 uint32_t gen; 2758 uint32_t i; 2759 2760 /* 2761 * Step 18: put the T3_MAGIC_NUMBER into the GENCOMM port 2762 * 2763 * Step 19: poll for firmware completion (GENCOMM port set 2764 * to the ones complement of T3_MAGIC_NUMBER). 2765 * 2766 * While we're at it, we also read the MAC address register; 2767 * at some stage the the firmware will load this with the 2768 * factory-set value. 2769 * 2770 * When both the magic number and the MAC address are set, 2771 * we're done; but we impose a time limit of one second 2772 * (1000*1000us) in case the firmware fails in some fashion 2773 * or the SEEPROM that provides that MAC address isn't fitted. 2774 * 2775 * After the first time through (chip state != INITIAL), we 2776 * don't need the MAC address to be set (we've already got it 2777 * or not, from the first time), so we don't wait for it, but 2778 * we still have to wait for the T3_MAGIC_NUMBER. 2779 * 2780 * Note: the magic number is only a 32-bit quantity, but the NIC 2781 * memory is 64-bit (and big-endian) internally. Addressing the 2782 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2783 * it work correctly on both big- and little-endian hosts. 2784 */ 2785 #ifdef BGE_IPMI_ASF 2786 if (!bgep->asf_enabled) { 2787 #endif 2788 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 2789 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 2790 BGE_DEBUG(("bge_poll_firmware: put T3 magic 0x%llx in GENCOMM" 2791 " 0x%lx", magic, NIC_MEM_GENCOMM)); 2792 #ifdef BGE_IPMI_ASF 2793 } 2794 #endif 2795 2796 for (i = 0; i < 1000; ++i) { 2797 drv_usecwait(1000); 2798 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2799 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2800 #ifdef BGE_IPMI_ASF 2801 if (!bgep->asf_enabled) { 2802 #endif 2803 if (gen != ~T3_MAGIC_NUMBER) 2804 continue; 2805 #ifdef BGE_IPMI_ASF 2806 } 2807 #endif 2808 if (mac != 0ULL) 2809 break; 2810 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2811 break; 2812 } 2813 2814 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2815 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2816 (void *)bgep, gen, i)); 2817 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2818 mac, magic)); 2819 2820 return (mac); 2821 } 2822 2823 #ifdef BGE_IPMI_ASF 2824 void bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 2825 #else 2826 void bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 2827 #endif 2828 #pragma no_inline(bge_chip_reset) 2829 2830 void 2831 #ifdef BGE_IPMI_ASF 2832 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 2833 #else 2834 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 2835 #endif 2836 { 2837 chip_id_t chipid; 2838 uint64_t mac; 2839 uint32_t modeflags; 2840 uint32_t mhcr; 2841 uint32_t sx0; 2842 uint32_t i; 2843 #ifdef BGE_IPMI_ASF 2844 uint32_t mailbox; 2845 #endif 2846 2847 BGE_TRACE(("bge_chip_reset($%p, %d)", 2848 (void *)bgep, enable_dma)); 2849 2850 ASSERT(mutex_owned(bgep->genlock)); 2851 2852 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 2853 (void *)bgep, enable_dma, bgep->bge_chip_state)); 2854 2855 /* 2856 * Do we need to stop the chip cleanly before resetting? 2857 */ 2858 switch (bgep->bge_chip_state) { 2859 default: 2860 ASSERT(!"can't get here"); 2861 _NOTE(NOTREACHED) 2862 return; 2863 2864 case BGE_CHIP_INITIAL: 2865 case BGE_CHIP_STOPPED: 2866 case BGE_CHIP_RESET: 2867 break; 2868 2869 case BGE_CHIP_RUNNING: 2870 case BGE_CHIP_ERROR: 2871 case BGE_CHIP_FAULT: 2872 bge_chip_stop(bgep, B_FALSE); 2873 break; 2874 } 2875 2876 #ifdef BGE_IPMI_ASF 2877 if (bgep->asf_enabled) { 2878 if (asf_mode == ASF_MODE_INIT) { 2879 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 2880 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 2881 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 2882 } 2883 } 2884 #endif 2885 /* 2886 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 2887 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 2888 * 2889 * Before reset Core clock,it is 2890 * also required to initialize the Memory Arbiter as specified in step9 2891 * and Misc Host Control Register as specified in step-13 2892 * Step 4-5: reset Core clock & wait for completion 2893 * Steps 6-8: are done by bge_chip_cfg_init() 2894 */ 2895 (void) bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 2896 2897 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 2898 MHCR_ENABLE_TAGGED_STATUS_MODE | 2899 MHCR_MASK_INTERRUPT_MODE | 2900 MHCR_MASK_PCI_INT_OUTPUT | 2901 MHCR_CLEAR_INTERRUPT_INTA; 2902 #ifdef _BIG_ENDIAN 2903 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 2904 #endif /* _BIG_ENDIAN */ 2905 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 2906 #ifdef BGE_IPMI_ASF 2907 if (bgep->asf_enabled) 2908 bgep->asf_wordswapped = B_FALSE; 2909 #endif 2910 (void) bge_chip_reset_engine(bgep, MISC_CONFIG_REG); 2911 bge_chip_cfg_init(bgep, &chipid, enable_dma); 2912 2913 /* 2914 * Step 8a: This may belong elsewhere, but BCM5721 needs 2915 * a bit set to avoid a fifo overflow/underflow bug. 2916 */ 2917 if (bgep->chipid.chip_label == 5721 || bgep->chipid.chip_label == 5751) 2918 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 2919 2920 2921 /* 2922 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 2923 * not be changed. 2924 */ 2925 (void) bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0); 2926 2927 /* 2928 * Steps 10-11: configure PIO endianness options and 2929 * enable indirect register access -- already done 2930 * Steps 12-13: enable writing to the PCI state & clock 2931 * control registers -- not required; we aren't going to 2932 * use those features. 2933 * Steps 14-15: Configure DMA endianness options. See 2934 * the comments on the setting of the MHCR above. 2935 */ 2936 #ifdef _BIG_ENDIAN 2937 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 2938 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 2939 #else 2940 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 2941 #endif /* _BIG_ENDIAN */ 2942 #ifdef BGE_IPMI_ASF 2943 if (bgep->asf_enabled) 2944 modeflags |= MODE_HOST_STACK_UP; 2945 #endif 2946 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 2947 2948 #ifdef BGE_IPMI_ASF 2949 if (bgep->asf_enabled) { 2950 if (asf_mode != ASF_MODE_NONE) { 2951 /* Wait for NVRAM init */ 2952 i = 0; 2953 drv_usecwait(5000); 2954 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 2955 while ((mailbox != (uint32_t) 2956 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 2957 (i < 10000)) { 2958 drv_usecwait(100); 2959 mailbox = bge_nic_get32(bgep, 2960 BGE_FIRMWARE_MAILBOX); 2961 i++; 2962 } 2963 if (!bgep->asf_newhandshake) { 2964 if ((asf_mode == ASF_MODE_INIT) || 2965 (asf_mode == ASF_MODE_POST_INIT)) { 2966 2967 bge_asf_post_reset_old_mode(bgep, 2968 BGE_INIT_RESET); 2969 } else { 2970 bge_asf_post_reset_old_mode(bgep, 2971 BGE_SHUTDOWN_RESET); 2972 } 2973 } 2974 } 2975 } 2976 #endif 2977 /* 2978 * Steps 16-17: poll for firmware completion 2979 */ 2980 mac = bge_poll_firmware(bgep); 2981 2982 /* 2983 * Step 18: enable external memory -- doesn't apply. 2984 * 2985 * However we take the opportunity to set the MLCR anyway, as 2986 * this register also controls the SEEPROM auto-access method 2987 * which we may want to use later ... 2988 * 2989 * The proper value here depends on the way the chip is wired 2990 * into the circuit board, as this register *also* controls which 2991 * of the "Miscellaneous I/O" pins are driven as outputs and the 2992 * values driven onto those pins! 2993 * 2994 * See also step 74 in the PRM ... 2995 */ 2996 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 2997 bgep->chipid.bge_mlcr_default); 2998 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 2999 3000 /* 3001 * Step 20: clear the Ethernet MAC mode register 3002 */ 3003 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3004 3005 /* 3006 * Step 21: restore cache-line-size, latency timer, and 3007 * subsystem ID registers to their original values (not 3008 * those read into the local structure <chipid>, 'cos 3009 * that was after they were cleared by the RESET). 3010 * 3011 * Note: the Subsystem Vendor/Device ID registers are not 3012 * directly writable in config space, so we use the shadow 3013 * copy in "Page Zero" of register space to restore them 3014 * both in one go ... 3015 */ 3016 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3017 bgep->chipid.clsize); 3018 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3019 bgep->chipid.latency); 3020 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3021 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3022 3023 /* 3024 * The SEND INDEX registers should be reset to zero by the 3025 * global chip reset; if they're not, there'll be trouble 3026 * later on -- usually in the form of an ASSERTion failure 3027 * in bge_send.c. So let's catch it early ... 3028 */ 3029 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3030 if (sx0 != 0) 3031 bge_problem(bgep, "send index %d: device didn't RESET!", sx0); 3032 ASSERT(sx0 == 0); 3033 3034 /* Enable MSI code */ 3035 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3036 bge_reg_set32(bgep, MSI_MODE_REG, 3037 MSI_PRI_HIGHEST|MSI_MSI_ENABLE); 3038 3039 /* 3040 * On the first time through, save the factory-set MAC address 3041 * (if any). If bge_poll_firmware() above didn't return one 3042 * (from a chip register) consider looking in the attached NV 3043 * memory device, if any. Once we have it, we save it in both 3044 * register-image (64-bit) and byte-array forms. All-zero and 3045 * all-one addresses are not valid, and we refuse to stash those. 3046 */ 3047 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3048 if (mac == 0ULL) 3049 mac = bge_get_nvmac(bgep); 3050 if (mac != 0ULL && mac != ~0ULL) { 3051 bgep->chipid.hw_mac_addr = mac; 3052 for (i = ETHERADDRL; i-- != 0; ) { 3053 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3054 mac >>= 8; 3055 } 3056 bgep->chipid.vendor_addr.set = 1; 3057 } 3058 } 3059 3060 #ifdef BGE_IPMI_ASF 3061 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3062 if (asf_mode != ASF_MODE_NONE) { 3063 if ((asf_mode == ASF_MODE_INIT) || 3064 (asf_mode == ASF_MODE_POST_INIT)) { 3065 3066 bge_asf_post_reset_new_mode(bgep, 3067 BGE_INIT_RESET); 3068 } else { 3069 bge_asf_post_reset_new_mode(bgep, 3070 BGE_SHUTDOWN_RESET); 3071 } 3072 } 3073 } 3074 #endif 3075 3076 /* 3077 * Record the new state 3078 */ 3079 bgep->chip_resets += 1; 3080 bgep->bge_chip_state = BGE_CHIP_RESET; 3081 } 3082 3083 /* 3084 * bge_chip_start() -- start the chip transmitting and/or receiving, 3085 * including enabling interrupts 3086 */ 3087 void bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3088 #pragma no_inline(bge_chip_start) 3089 3090 void 3091 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3092 { 3093 uint32_t coalmode; 3094 uint32_t ledctl; 3095 uint32_t mtu; 3096 uint32_t maxring; 3097 uint64_t ring; 3098 3099 BGE_TRACE(("bge_chip_start($%p)", 3100 (void *)bgep)); 3101 3102 ASSERT(mutex_owned(bgep->genlock)); 3103 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3104 ASSERT(bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)) == 0); 3105 3106 /* 3107 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3108 * The document specifies 95 separate steps to fully 3109 * initialise the chip!!!! 3110 * 3111 * The reset code above has already got us as far as step 3112 * 21, so we continue with ... 3113 * 3114 * Step 22: clear the MAC statistics block 3115 * (0x0300-0x0aff in NIC-local memory) 3116 */ 3117 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3118 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3119 NIC_MEM_STATISTICS_SIZE); 3120 3121 /* 3122 * Step 23: clear the status block (in host memory) 3123 */ 3124 DMA_ZERO(bgep->status_block); 3125 3126 /* 3127 * Step 24: set DMA read/write control register 3128 */ 3129 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3130 bgep->chipid.bge_dma_rwctrl); 3131 3132 /* 3133 * Step 25: Configure DMA endianness -- already done (16/17) 3134 * Step 26: Configure Host-Based Send Rings 3135 * Step 27: Indicate Host Stack Up 3136 */ 3137 bge_reg_set32(bgep, MODE_CONTROL_REG, 3138 MODE_HOST_SEND_BDS | 3139 MODE_HOST_STACK_UP); 3140 3141 /* 3142 * Step 28: Configure checksum options: 3143 * Solaris supports the hardware default checksum options 3144 * so there's nothing to do here. 3145 */ 3146 3147 /* 3148 * Step 29: configure Timer Prescaler. The value is always the 3149 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3150 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3151 * for the whole chip! 3152 */ 3153 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3154 3155 /* 3156 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3157 * 3158 * If the mbuf_length is specified as 0, we just leave these at 3159 * their hardware defaults, rather than explicitly setting them. 3160 * As the Broadcom HRM,driver better not change the parameters 3161 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3162 */ 3163 if ((bgep->chipid.mbuf_length != 0) && 3164 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3165 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3166 bgep->chipid.mbuf_base); 3167 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3168 bgep->chipid.mbuf_length); 3169 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3170 DMAD_POOL_BASE_DEFAULT); 3171 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3172 DMAD_POOL_LENGTH_DEFAULT); 3173 } 3174 3175 /* 3176 * Step 32: configure MAC memory pool watermarks 3177 */ 3178 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3179 bgep->chipid.mbuf_lo_water_rdma); 3180 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3181 bgep->chipid.mbuf_lo_water_rmac); 3182 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3183 bgep->chipid.mbuf_hi_water); 3184 3185 /* 3186 * Step 33: configure DMA resource watermarks 3187 */ 3188 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3189 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3190 bge_dmad_lo_water); 3191 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3192 bge_dmad_hi_water); 3193 } 3194 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3195 3196 /* 3197 * Steps 34-36: enable buffer manager & internal h/w queues 3198 */ 3199 (void) bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3200 STATE_MACHINE_ATTN_ENABLE_BIT); 3201 (void) bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0); 3202 3203 /* 3204 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3205 */ 3206 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3207 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3208 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3209 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3210 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3211 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3212 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3213 } 3214 3215 /* 3216 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3217 */ 3218 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3219 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3220 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3221 bge_replenish_jumbo); 3222 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3223 bge_replenish_mini); 3224 } 3225 3226 /* 3227 * Steps 41-43: clear Send Ring Producer Indices and initialise 3228 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3229 */ 3230 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3231 maxring = BGE_SEND_RINGS_MAX; 3232 else 3233 maxring = BGE_SEND_RINGS_MAX_5705; 3234 for (ring = 0; ring < maxring; ++ring) { 3235 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3236 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3237 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3238 &bgep->send[ring].hw_rcb); 3239 } 3240 3241 /* 3242 * Steps 44-45: initialise Receive Return Rings 3243 * (0x0200-0x02ff in NIC-local memory) 3244 */ 3245 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3246 maxring = BGE_RECV_RINGS_MAX; 3247 else 3248 maxring = BGE_RECV_RINGS_MAX_5705; 3249 for (ring = 0; ring < maxring; ++ring) 3250 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3251 &bgep->recv[ring].hw_rcb); 3252 3253 /* 3254 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3255 */ 3256 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3257 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3258 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3259 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3260 } 3261 /* 3262 * Step 47: configure the MAC unicast address 3263 * Step 48: configure the random backoff seed 3264 * Step 96: set up multicast filters 3265 */ 3266 #ifdef BGE_IPMI_ASF 3267 bge_chip_sync(bgep, B_FALSE); 3268 #else 3269 bge_chip_sync(bgep); 3270 #endif 3271 3272 /* 3273 * Step 49: configure the MTU 3274 */ 3275 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3276 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3277 3278 /* 3279 * Step 50: configure the IPG et al 3280 */ 3281 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3282 3283 /* 3284 * Step 51: configure the default Rx Return Ring 3285 */ 3286 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3287 3288 /* 3289 * Steps 52-54: configure Receive List Placement, 3290 * and enable Receive List Placement Statistics 3291 */ 3292 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3293 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3294 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3295 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3296 3297 if (bgep->chipid.rx_rings > 1) 3298 bge_init_recv_rule(bgep); 3299 3300 /* 3301 * Steps 55-56: enable Send Data Initiator Statistics 3302 */ 3303 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3304 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3305 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3306 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3307 } else { 3308 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3309 SEND_INIT_STATS_ENABLE); 3310 } 3311 /* 3312 * Steps 57-58: stop (?) the Host Coalescing Engine 3313 */ 3314 (void) bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0); 3315 3316 /* 3317 * Steps 59-62: initialise Host Coalescing parameters 3318 */ 3319 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3320 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3321 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3322 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3323 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3324 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3325 bge_tx_count_intr); 3326 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3327 bge_tx_ticks_intr); 3328 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3329 bge_rx_count_intr); 3330 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3331 bge_rx_ticks_intr); 3332 } 3333 3334 /* 3335 * Steps 63-64: initialise status block & statistics 3336 * host memory addresses 3337 * The statistic block does not exist in some chipsets 3338 * Step 65: initialise Statistics Coalescing Tick Counter 3339 */ 3340 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3341 bgep->status_block.cookie.dmac_laddress); 3342 3343 /* 3344 * Steps 66-67: initialise status block & statistics 3345 * NIC-local memory addresses 3346 */ 3347 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3348 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3349 bgep->statistics.cookie.dmac_laddress); 3350 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3351 STATISTICS_TICKS_DEFAULT); 3352 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3353 NIC_MEM_STATUS_BLOCK); 3354 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3355 NIC_MEM_STATISTICS); 3356 } 3357 3358 /* 3359 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3360 * Completion Engine, the Receive List Placement Engine, and the 3361 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3362 * and BCM5715. 3363 */ 3364 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3365 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3366 coalmode = COALESCE_64_BYTE_STATUS; 3367 else 3368 coalmode = 0; 3369 (void) bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode); 3370 (void) bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3371 STATE_MACHINE_ATTN_ENABLE_BIT); 3372 (void) bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0); 3373 3374 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3375 (void) bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3376 STATE_MACHINE_ATTN_ENABLE_BIT); 3377 3378 /* 3379 * Step 72: Enable MAC DMA engines 3380 * Step 73: Clear & enable MAC statistics 3381 */ 3382 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3383 ETHERNET_MODE_ENABLE_FHDE | 3384 ETHERNET_MODE_ENABLE_RDE | 3385 ETHERNET_MODE_ENABLE_TDE); 3386 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3387 ETHERNET_MODE_ENABLE_TX_STATS | 3388 ETHERNET_MODE_ENABLE_RX_STATS | 3389 ETHERNET_MODE_CLEAR_TX_STATS | 3390 ETHERNET_MODE_CLEAR_RX_STATS); 3391 3392 /* 3393 * Step 74: configure the MLCR (Miscellaneous Local Control 3394 * Register); not required, as we set up the MLCR in step 10 3395 * (part of the reset code) above. 3396 * 3397 * Step 75: clear Interrupt Mailbox 0 3398 */ 3399 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3400 3401 /* 3402 * Steps 76-87: Gentlemen, start your engines ... 3403 * 3404 * Enable the DMA Completion Engine, the Write DMA Engine, 3405 * the Read DMA Engine, Receive Data Completion Engine, 3406 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3407 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3408 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3409 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3410 * 3411 * Beware exhaust fumes? 3412 */ 3413 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3414 (void) bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0); 3415 (void) bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3416 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS); 3417 (void) bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3418 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS); 3419 (void) bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3420 STATE_MACHINE_ATTN_ENABLE_BIT); 3421 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3422 (void) bge_chip_enable_engine(bgep, 3423 MBUF_CLUSTER_FREE_MODE_REG, 0); 3424 (void) bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0); 3425 (void) bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3426 STATE_MACHINE_ATTN_ENABLE_BIT); 3427 (void) bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3428 RCV_BD_DISABLED_RING_ATTN); 3429 (void) bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3430 RCV_DATA_BD_ILL_RING_ATTN); 3431 (void) bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0); 3432 (void) bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3433 STATE_MACHINE_ATTN_ENABLE_BIT); 3434 (void) bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3435 STATE_MACHINE_ATTN_ENABLE_BIT); 3436 3437 /* 3438 * Step 88: download firmware -- doesn't apply 3439 * Steps 89-90: enable Transmit & Receive MAC Engines 3440 */ 3441 (void) bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0); 3442 #ifdef BGE_IPMI_ASF 3443 if (bgep->asf_enabled) { 3444 (void) bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0); 3445 } else { 3446 (void) bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3447 RECEIVE_MODE_KEEP_VLAN_TAG); 3448 } 3449 #else 3450 (void) bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3451 RECEIVE_MODE_KEEP_VLAN_TAG); 3452 #endif 3453 3454 /* 3455 * Step 91: disable auto-polling of PHY status 3456 */ 3457 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3458 3459 /* 3460 * Step 92: configure D0 power state (not required) 3461 * Step 93: initialise LED control register () 3462 */ 3463 ledctl = LED_CONTROL_DEFAULT; 3464 switch (bgep->chipid.device) { 3465 case DEVICE_ID_5700: 3466 case DEVICE_ID_5700x: 3467 case DEVICE_ID_5701: 3468 /* 3469 * Switch to 5700 (MAC) mode on these older chips 3470 */ 3471 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3472 ledctl |= LED_CONTROL_LED_MODE_5700; 3473 break; 3474 3475 default: 3476 break; 3477 } 3478 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3479 3480 /* 3481 * Step 94: activate link 3482 */ 3483 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3484 3485 /* 3486 * Step 95: set up physical layer (PHY/SerDes) 3487 * restart autoneg (if required) 3488 */ 3489 if (reset_phys) 3490 bge_phys_update(bgep); 3491 3492 /* 3493 * Extra step (DSG): hand over all the Receive Buffers to the chip 3494 */ 3495 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3496 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3497 bgep->buff[ring].rf_next); 3498 3499 /* 3500 * MSI bits:The least significant MSI 16-bit word. 3501 * ISR will be triggered different. 3502 */ 3503 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3504 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3505 3506 /* 3507 * Extra step (DSG): select which interrupts are enabled 3508 * 3509 * Program the Ethernet MAC engine to signal attention on 3510 * Link Change events, then enable interrupts on MAC, DMA, 3511 * and FLOW attention signals. 3512 */ 3513 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3514 ETHERNET_EVENT_LINK_INT | 3515 ETHERNET_STATUS_PCS_ERROR_INT); 3516 #ifdef BGE_IPMI_ASF 3517 if (bgep->asf_enabled) { 3518 bge_reg_set32(bgep, MODE_CONTROL_REG, 3519 MODE_INT_ON_FLOW_ATTN | 3520 MODE_INT_ON_DMA_ATTN | 3521 MODE_HOST_STACK_UP| 3522 MODE_INT_ON_MAC_ATTN); 3523 } else { 3524 #endif 3525 bge_reg_set32(bgep, MODE_CONTROL_REG, 3526 MODE_INT_ON_FLOW_ATTN | 3527 MODE_INT_ON_DMA_ATTN | 3528 MODE_INT_ON_MAC_ATTN); 3529 #ifdef BGE_IPMI_ASF 3530 } 3531 #endif 3532 3533 /* 3534 * Step 97: enable PCI interrupts!!! 3535 */ 3536 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3537 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3538 MHCR_MASK_PCI_INT_OUTPUT); 3539 3540 /* 3541 * All done! 3542 */ 3543 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3544 } 3545 3546 3547 /* 3548 * ========== Hardware interrupt handler ========== 3549 */ 3550 3551 #undef BGE_DBG 3552 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3553 3554 /* 3555 * Sync the status block, then atomically clear the specified bits in 3556 * the <flags-and-tag> field of the status block. 3557 * the <flags> word of the status block, returning the value of the 3558 * <tag> and the <flags> before the bits were cleared. 3559 */ 3560 static uint64_t bge_status_sync(bge_t *bgep, uint64_t bits); 3561 #pragma inline(bge_status_sync) 3562 3563 static uint64_t 3564 bge_status_sync(bge_t *bgep, uint64_t bits) 3565 { 3566 bge_status_t *bsp; 3567 uint64_t flags; 3568 3569 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3570 (void *)bgep, bits)); 3571 3572 ASSERT(bgep->bge_guard == BGE_GUARD); 3573 3574 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3575 bsp = DMA_VPTR(bgep->status_block); 3576 flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3577 3578 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3579 (void *)bgep, bits, flags)); 3580 3581 return (flags); 3582 } 3583 3584 static void bge_wake_factotum(bge_t *bgep); 3585 #pragma inline(bge_wake_factotum) 3586 3587 static void 3588 bge_wake_factotum(bge_t *bgep) 3589 { 3590 mutex_enter(bgep->softintrlock); 3591 if (bgep->factotum_flag == 0) { 3592 bgep->factotum_flag = 1; 3593 ddi_trigger_softintr(bgep->factotum_id); 3594 } 3595 mutex_exit(bgep->softintrlock); 3596 } 3597 3598 /* 3599 * bge_intr() -- handle chip interrupts 3600 */ 3601 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3602 #pragma no_inline(bge_intr) 3603 3604 uint_t 3605 bge_intr(caddr_t arg1, caddr_t arg2) 3606 { 3607 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3608 bge_status_t *bsp; 3609 uint64_t flags; 3610 uint32_t mlcr = 0; 3611 uint_t result; 3612 3613 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3614 3615 /* 3616 * GLD v2 checks that s/w setup is complete before passing 3617 * interrupts to this routine, thus eliminating the old 3618 * (and well-known) race condition around ddi_add_intr() 3619 */ 3620 ASSERT(bgep->progress & PROGRESS_HWINT); 3621 3622 /* 3623 * Check whether chip's says it's asserting #INTA; 3624 * if not, don't process or claim the interrupt. 3625 * 3626 * Note that the PCI signal is active low, so the 3627 * bit is *zero* when the interrupt is asserted. 3628 */ 3629 result = DDI_INTR_UNCLAIMED; 3630 mutex_enter(bgep->genlock); 3631 3632 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3633 mlcr = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3634 3635 BGE_DEBUG(("bge_intr($%p) ($%p) mlcr 0x%08x", arg1, arg2, mlcr)); 3636 3637 if ((mlcr & MLCR_INTA_STATE) == 0) { 3638 /* 3639 * Block further PCI interrupts ... 3640 */ 3641 result = DDI_INTR_CLAIMED; 3642 3643 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3644 bge_cfg_set32(bgep, PCI_CONF_BGE_MHCR, 3645 MHCR_MASK_PCI_INT_OUTPUT); 3646 3647 /* 3648 * Sync the status block and grab the flags-n-tag from it. 3649 * We count the number of interrupts where there doesn't 3650 * seem to have been a DMA update of the status block; if 3651 * it *has* been updated, the counter will be cleared in 3652 * the while() loop below ... 3653 */ 3654 bgep->missed_dmas += 1; 3655 bsp = DMA_VPTR(bgep->status_block); 3656 flags = bge_status_sync(bgep, STATUS_FLAG_UPDATED); 3657 3658 while (flags & STATUS_FLAG_UPDATED) { 3659 /* 3660 * Tell the chip that we're processing the interrupt 3661 */ 3662 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3663 INTERRUPT_MBOX_DISABLE(flags)); 3664 3665 /* 3666 * Drop the mutex while we: 3667 * Receive any newly-arrived packets 3668 * Recycle any newly-finished send buffers 3669 */ 3670 mutex_exit(bgep->genlock); 3671 bge_receive(bgep, bsp); 3672 bge_recycle(bgep, bsp); 3673 mutex_enter(bgep->genlock); 3674 3675 /* 3676 * Tell the chip we've finished processing, and 3677 * give it the tag that we got from the status 3678 * block earlier, so that it knows just how far 3679 * we've gone. If it's got more for us to do, 3680 * it will now update the status block and try 3681 * to assert an interrupt (but we've got the 3682 * #INTA blocked at present). If we see the 3683 * update, we'll loop around to do some more. 3684 * Eventually we'll get out of here ... 3685 */ 3686 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3687 INTERRUPT_MBOX_ENABLE(flags)); 3688 bgep->missed_dmas = 0; 3689 flags = bge_status_sync(bgep, STATUS_FLAG_UPDATED); 3690 } 3691 3692 /* 3693 * Check for exceptional conditions that we need to handle 3694 * 3695 * Link status changed 3696 * Status block not updated 3697 */ 3698 if (flags & STATUS_FLAG_LINK_CHANGED) 3699 bge_wake_factotum(bgep); 3700 3701 if (bgep->missed_dmas) { 3702 /* 3703 * Probably due to the internal status tag not 3704 * being reset. Force a status block update now; 3705 * this should ensure that we get an update and 3706 * a new interrupt. After that, we should be in 3707 * sync again ... 3708 */ 3709 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 3710 "not updated?", flags)); 3711 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 3712 COALESCE_NOW); 3713 3714 if (bgep->missed_dmas >= bge_dma_miss_limit) { 3715 /* 3716 * If this happens multiple times in a row, 3717 * it means DMA is just not working. Maybe 3718 * the chip's failed, or maybe there's a 3719 * problem on the PCI bus or in the host-PCI 3720 * bridge (Tomatillo). 3721 * 3722 * At all events, we want to stop further 3723 * interrupts and let the recovery code take 3724 * over to see whether anything can be done 3725 * about it ... 3726 */ 3727 #ifdef BGE_IPMI_ASF 3728 if (bgep->asf_enabled && 3729 (bgep->asf_status == ASF_STAT_RUN)) { 3730 /* 3731 * We must stop ASF heart beat before 3732 * bge_chip_stop(), otherwise some 3733 * computers (ex. IBM HS20 blade 3734 * server) may crash. 3735 */ 3736 bge_asf_update_status(bgep); 3737 bge_asf_stop_timer(bgep); 3738 bgep->asf_status = ASF_STAT_STOP; 3739 3740 bge_asf_pre_reset_operations(bgep, 3741 BGE_INIT_RESET); 3742 } 3743 #endif 3744 bge_chip_stop(bgep, B_TRUE); 3745 result = DDI_INTR_UNCLAIMED; 3746 } 3747 } 3748 3749 /* 3750 * Reenable assertion of #INTA, unless there's a DMA fault 3751 */ 3752 if (result == DDI_INTR_CLAIMED) { 3753 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3754 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3755 MHCR_MASK_PCI_INT_OUTPUT); 3756 } 3757 } 3758 3759 mutex_exit(bgep->genlock); 3760 return (result); 3761 } 3762 3763 /* 3764 * ========== Factotum, implemented as a softint handler ========== 3765 */ 3766 3767 #undef BGE_DBG 3768 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 3769 3770 static void bge_factotum_error_handler(bge_t *bgep); 3771 #pragma no_inline(bge_factotum_error_handler) 3772 3773 static void 3774 bge_factotum_error_handler(bge_t *bgep) 3775 { 3776 uint32_t flow; 3777 uint32_t rdma; 3778 uint32_t wdma; 3779 uint32_t tmac; 3780 uint32_t rmac; 3781 uint32_t rxrs; 3782 uint32_t txrs = 0; 3783 3784 ASSERT(mutex_owned(bgep->genlock)); 3785 3786 /* 3787 * Read all the registers that show the possible 3788 * reasons for the ERROR bit to be asserted 3789 */ 3790 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 3791 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 3792 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 3793 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 3794 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 3795 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 3796 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3797 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 3798 3799 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 3800 (void *)bgep, flow, rdma, wdma)); 3801 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 3802 (void *)bgep, tmac, rmac, rxrs, txrs)); 3803 3804 /* 3805 * For now, just clear all the errors ... 3806 */ 3807 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3808 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 3809 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 3810 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 3811 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 3812 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 3813 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 3814 } 3815 3816 /* 3817 * Handler for hardware link state change. 3818 * 3819 * When this routine is called, the hardware link state has changed 3820 * and the new state is reflected in the param_* variables. Here 3821 * we must update the softstate, reprogram the MAC to match, and 3822 * record the change in the log and/or on the console. 3823 */ 3824 static void bge_factotum_link_handler(bge_t *bgep); 3825 #pragma no_inline(bge_factotum_link_handler) 3826 3827 static void 3828 bge_factotum_link_handler(bge_t *bgep) 3829 { 3830 void (*logfn)(bge_t *bgep, const char *fmt, ...); 3831 const char *msg; 3832 hrtime_t deltat; 3833 3834 ASSERT(mutex_owned(bgep->genlock)); 3835 3836 /* 3837 * Update the s/w link_state 3838 */ 3839 if (bgep->param_link_up) 3840 bgep->link_state = LINK_STATE_UP; 3841 else 3842 bgep->link_state = LINK_STATE_DOWN; 3843 3844 /* 3845 * Reprogram the MAC modes to match 3846 */ 3847 bge_sync_mac_modes(bgep); 3848 3849 /* 3850 * Finally, we have to decide whether to write a message 3851 * on the console or only in the log. If the PHY has 3852 * been reprogrammed (at user request) "recently", then 3853 * the message only goes in the log. Otherwise it's an 3854 * "unexpected" event, and it goes on the console as well. 3855 */ 3856 deltat = bgep->phys_event_time - bgep->phys_write_time; 3857 if (deltat > BGE_LINK_SETTLE_TIME) 3858 msg = ""; 3859 else if (bgep->param_link_up) 3860 msg = bgep->link_up_msg; 3861 else 3862 msg = bgep->link_down_msg; 3863 3864 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 3865 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 3866 } 3867 3868 static boolean_t bge_factotum_link_check(bge_t *bgep); 3869 #pragma no_inline(bge_factotum_link_check) 3870 3871 static boolean_t 3872 bge_factotum_link_check(bge_t *bgep) 3873 { 3874 boolean_t check; 3875 uint64_t flags; 3876 uint32_t tmac_status; 3877 3878 ASSERT(mutex_owned(bgep->genlock)); 3879 3880 /* 3881 * Get & clear the writable status bits in the Tx status register 3882 * (some bits are write-1-to-clear, others are just readonly). 3883 */ 3884 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 3885 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 3886 3887 /* 3888 * Get & clear the ERROR and LINK_CHANGED bits from the status block 3889 */ 3890 flags = STATUS_FLAG_ERROR | STATUS_FLAG_LINK_CHANGED; 3891 flags = bge_status_sync(bgep, flags); 3892 3893 /* 3894 * Clear any errors flagged in the status block ... 3895 */ 3896 if (flags & STATUS_FLAG_ERROR) 3897 bge_factotum_error_handler(bgep); 3898 3899 /* 3900 * We need to check the link status if: 3901 * the status block says there's been a link change 3902 * or there's any discrepancy between the various 3903 * flags indicating the link state (link_state, 3904 * param_link_up, and the LINK STATE bit in the 3905 * Transmit MAC status register). 3906 */ 3907 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 3908 switch (bgep->link_state) { 3909 case LINK_STATE_UP: 3910 check |= (bgep->param_link_up == B_FALSE); 3911 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 3912 break; 3913 3914 case LINK_STATE_DOWN: 3915 check |= (bgep->param_link_up != B_FALSE); 3916 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 3917 break; 3918 3919 default: 3920 check = B_TRUE; 3921 break; 3922 } 3923 3924 /* 3925 * If <check> is false, we're sure the link hasn't changed. 3926 * If true, however, it's not yet definitive; we have to call 3927 * bge_phys_check() to determine whether the link has settled 3928 * into a new state yet ... and if it has, then call the link 3929 * state change handler.But when the chip is 5700 in Dell 6650 3930 * ,even if check is false, the link may have changed.So we 3931 * have to call bge_phys_check() to determine the link state. 3932 */ 3933 if (check || bgep->chipid.device == DEVICE_ID_5700) { 3934 check = bge_phys_check(bgep); 3935 if (check) 3936 bge_factotum_link_handler(bgep); 3937 } 3938 3939 return (check); 3940 } 3941 3942 /* 3943 * Factotum routine to check for Tx stall, using the 'watchdog' counter 3944 */ 3945 static boolean_t bge_factotum_stall_check(bge_t *bgep); 3946 #pragma no_inline(bge_factotum_stall_check) 3947 3948 static boolean_t 3949 bge_factotum_stall_check(bge_t *bgep) 3950 { 3951 uint32_t dogval; 3952 3953 ASSERT(mutex_owned(bgep->genlock)); 3954 3955 /* 3956 * Specific check for Tx stall ... 3957 * 3958 * The 'watchdog' counter is incremented whenever a packet 3959 * is queued, reset to 1 when some (but not all) buffers 3960 * are reclaimed, reset to 0 (disabled) when all buffers 3961 * are reclaimed, and shifted left here. If it exceeds the 3962 * threshold value, the chip is assumed to have stalled and 3963 * is put into the ERROR state. The factotum will then reset 3964 * it on the next pass. 3965 * 3966 * All of which should ensure that we don't get into a state 3967 * where packets are left pending indefinitely! 3968 */ 3969 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 3970 if (dogval < bge_watchdog_count) 3971 return (B_FALSE); 3972 3973 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 3974 return (B_TRUE); 3975 } 3976 3977 /* 3978 * The factotum is woken up when there's something to do that we'd rather 3979 * not do from inside a hardware interrupt handler or high-level cyclic. 3980 * Its two main tasks are: 3981 * reset & restart the chip after an error 3982 * check the link status whenever necessary 3983 */ 3984 uint_t bge_chip_factotum(caddr_t arg); 3985 #pragma no_inline(bge_chip_factotum) 3986 3987 uint_t 3988 bge_chip_factotum(caddr_t arg) 3989 { 3990 bge_t *bgep; 3991 uint_t result; 3992 boolean_t error; 3993 boolean_t linkchg; 3994 3995 bgep = (bge_t *)arg; 3996 3997 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 3998 3999 mutex_enter(bgep->softintrlock); 4000 if (bgep->factotum_flag == 0) { 4001 mutex_exit(bgep->softintrlock); 4002 return (DDI_INTR_UNCLAIMED); 4003 } 4004 mutex_exit(bgep->softintrlock); 4005 4006 bgep->factotum_flag = 0; 4007 result = DDI_INTR_CLAIMED; 4008 error = B_FALSE; 4009 linkchg = B_FALSE; 4010 4011 mutex_enter(bgep->genlock); 4012 switch (bgep->bge_chip_state) { 4013 default: 4014 break; 4015 4016 case BGE_CHIP_RUNNING: 4017 linkchg = bge_factotum_link_check(bgep); 4018 error = bge_factotum_stall_check(bgep); 4019 break; 4020 4021 case BGE_CHIP_ERROR: 4022 error = B_TRUE; 4023 break; 4024 4025 case BGE_CHIP_FAULT: 4026 /* 4027 * Fault detected, time to reset ... 4028 */ 4029 if (bge_autorecover) { 4030 BGE_REPORT((bgep, "automatic recovery activated")); 4031 bge_restart(bgep, B_FALSE); 4032 #ifdef BGE_IPMI_ASF 4033 /* 4034 * Start our ASF heartbeat counter as soon as possible. 4035 */ 4036 if (bgep->asf_enabled) { 4037 if (bgep->asf_status != ASF_STAT_RUN) { 4038 bgep->asf_timeout_id = timeout( 4039 bge_asf_heartbeat, 4040 (void *)bgep, 4041 drv_usectohz( 4042 BGE_ASF_HEARTBEAT_INTERVAL)); 4043 bgep->asf_status = ASF_STAT_RUN; 4044 } 4045 } 4046 #endif 4047 } 4048 break; 4049 } 4050 4051 /* 4052 * If an error is detected, stop the chip now, marking it as 4053 * faulty, so that it will be reset next time through ... 4054 */ 4055 if (error) { 4056 #ifdef BGE_IPMI_ASF 4057 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4058 /* 4059 * We must stop ASF heart beat before bge_chip_stop(), 4060 * otherwise some computers (ex. IBM HS20 blade server) 4061 * may crash. 4062 */ 4063 bge_asf_update_status(bgep); 4064 bge_asf_stop_timer(bgep); 4065 bgep->asf_status = ASF_STAT_STOP; 4066 4067 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4068 } 4069 #endif 4070 bge_chip_stop(bgep, B_TRUE); 4071 } 4072 mutex_exit(bgep->genlock); 4073 4074 /* 4075 * If the link state changed, tell the world about it. 4076 * Note: can't do this while still holding the mutex. 4077 */ 4078 if (linkchg) 4079 mac_link_update(bgep->macp, bgep->link_state); 4080 4081 return (result); 4082 } 4083 4084 /* 4085 * High-level cyclic handler 4086 * 4087 * This routine schedules a (low-level) softint callback to the 4088 * factotum, and prods the chip to update the status block (which 4089 * will cause a hardware interrupt when complete). 4090 */ 4091 void bge_chip_cyclic(void *arg); 4092 #pragma no_inline(bge_chip_cyclic) 4093 4094 void 4095 bge_chip_cyclic(void *arg) 4096 { 4097 bge_t *bgep; 4098 4099 bgep = arg; 4100 4101 switch (bgep->bge_chip_state) { 4102 default: 4103 return; 4104 4105 case BGE_CHIP_RUNNING: 4106 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4107 break; 4108 4109 case BGE_CHIP_FAULT: 4110 case BGE_CHIP_ERROR: 4111 break; 4112 } 4113 4114 bge_wake_factotum(bgep); 4115 } 4116 4117 4118 /* 4119 * ========== Ioctl subfunctions ========== 4120 */ 4121 4122 #undef BGE_DBG 4123 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4124 4125 #if BGE_DEBUGGING || BGE_DO_PPIO 4126 4127 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4128 #pragma no_inline(bge_chip_peek_cfg) 4129 4130 static void 4131 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4132 { 4133 uint64_t regval; 4134 uint64_t regno; 4135 4136 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4137 (void *)bgep, (void *)ppd)); 4138 4139 regno = ppd->pp_acc_offset; 4140 4141 switch (ppd->pp_acc_size) { 4142 case 1: 4143 regval = pci_config_get8(bgep->cfg_handle, regno); 4144 break; 4145 4146 case 2: 4147 regval = pci_config_get16(bgep->cfg_handle, regno); 4148 break; 4149 4150 case 4: 4151 regval = pci_config_get32(bgep->cfg_handle, regno); 4152 break; 4153 4154 case 8: 4155 regval = pci_config_get64(bgep->cfg_handle, regno); 4156 break; 4157 } 4158 4159 ppd->pp_acc_data = regval; 4160 } 4161 4162 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4163 #pragma no_inline(bge_chip_poke_cfg) 4164 4165 static void 4166 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4167 { 4168 uint64_t regval; 4169 uint64_t regno; 4170 4171 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4172 (void *)bgep, (void *)ppd)); 4173 4174 regno = ppd->pp_acc_offset; 4175 regval = ppd->pp_acc_data; 4176 4177 switch (ppd->pp_acc_size) { 4178 case 1: 4179 pci_config_put8(bgep->cfg_handle, regno, regval); 4180 break; 4181 4182 case 2: 4183 pci_config_put16(bgep->cfg_handle, regno, regval); 4184 break; 4185 4186 case 4: 4187 pci_config_put32(bgep->cfg_handle, regno, regval); 4188 break; 4189 4190 case 8: 4191 pci_config_put64(bgep->cfg_handle, regno, regval); 4192 break; 4193 } 4194 } 4195 4196 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4197 #pragma no_inline(bge_chip_peek_reg) 4198 4199 static void 4200 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4201 { 4202 uint64_t regval; 4203 void *regaddr; 4204 4205 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4206 (void *)bgep, (void *)ppd)); 4207 4208 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4209 4210 switch (ppd->pp_acc_size) { 4211 case 1: 4212 regval = ddi_get8(bgep->io_handle, regaddr); 4213 break; 4214 4215 case 2: 4216 regval = ddi_get16(bgep->io_handle, regaddr); 4217 break; 4218 4219 case 4: 4220 regval = ddi_get32(bgep->io_handle, regaddr); 4221 break; 4222 4223 case 8: 4224 regval = ddi_get64(bgep->io_handle, regaddr); 4225 break; 4226 } 4227 4228 ppd->pp_acc_data = regval; 4229 } 4230 4231 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4232 #pragma no_inline(bge_chip_peek_reg) 4233 4234 static void 4235 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4236 { 4237 uint64_t regval; 4238 void *regaddr; 4239 4240 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4241 (void *)bgep, (void *)ppd)); 4242 4243 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4244 regval = ppd->pp_acc_data; 4245 4246 switch (ppd->pp_acc_size) { 4247 case 1: 4248 ddi_put8(bgep->io_handle, regaddr, regval); 4249 break; 4250 4251 case 2: 4252 ddi_put16(bgep->io_handle, regaddr, regval); 4253 break; 4254 4255 case 4: 4256 ddi_put32(bgep->io_handle, regaddr, regval); 4257 break; 4258 4259 case 8: 4260 ddi_put64(bgep->io_handle, regaddr, regval); 4261 break; 4262 } 4263 BGE_PCICHK(bgep); 4264 } 4265 4266 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4267 #pragma no_inline(bge_chip_peek_nic) 4268 4269 static void 4270 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4271 { 4272 uint64_t regoff; 4273 uint64_t regval; 4274 void *regaddr; 4275 4276 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4277 (void *)bgep, (void *)ppd)); 4278 4279 regoff = ppd->pp_acc_offset; 4280 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4281 regoff &= MWBAR_GRANULE_MASK; 4282 regoff += NIC_MEM_WINDOW_OFFSET; 4283 regaddr = PIO_ADDR(bgep, regoff); 4284 4285 switch (ppd->pp_acc_size) { 4286 case 1: 4287 regval = ddi_get8(bgep->io_handle, regaddr); 4288 break; 4289 4290 case 2: 4291 regval = ddi_get16(bgep->io_handle, regaddr); 4292 break; 4293 4294 case 4: 4295 regval = ddi_get32(bgep->io_handle, regaddr); 4296 break; 4297 4298 case 8: 4299 regval = ddi_get64(bgep->io_handle, regaddr); 4300 break; 4301 } 4302 4303 ppd->pp_acc_data = regval; 4304 } 4305 4306 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4307 #pragma no_inline(bge_chip_poke_nic) 4308 4309 static void 4310 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4311 { 4312 uint64_t regoff; 4313 uint64_t regval; 4314 void *regaddr; 4315 4316 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4317 (void *)bgep, (void *)ppd)); 4318 4319 regoff = ppd->pp_acc_offset; 4320 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4321 regoff &= MWBAR_GRANULE_MASK; 4322 regoff += NIC_MEM_WINDOW_OFFSET; 4323 regaddr = PIO_ADDR(bgep, regoff); 4324 regval = ppd->pp_acc_data; 4325 4326 switch (ppd->pp_acc_size) { 4327 case 1: 4328 ddi_put8(bgep->io_handle, regaddr, regval); 4329 break; 4330 4331 case 2: 4332 ddi_put16(bgep->io_handle, regaddr, regval); 4333 break; 4334 4335 case 4: 4336 ddi_put32(bgep->io_handle, regaddr, regval); 4337 break; 4338 4339 case 8: 4340 ddi_put64(bgep->io_handle, regaddr, regval); 4341 break; 4342 } 4343 BGE_PCICHK(bgep); 4344 } 4345 4346 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4347 #pragma no_inline(bge_chip_peek_mii) 4348 4349 static void 4350 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4351 { 4352 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4353 (void *)bgep, (void *)ppd)); 4354 4355 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4356 } 4357 4358 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4359 #pragma no_inline(bge_chip_poke_mii) 4360 4361 static void 4362 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4363 { 4364 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4365 (void *)bgep, (void *)ppd)); 4366 4367 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4368 } 4369 4370 #if BGE_SEE_IO32 4371 4372 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4373 #pragma no_inline(bge_chip_peek_seeprom) 4374 4375 static void 4376 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4377 { 4378 uint32_t data; 4379 int err; 4380 4381 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4382 (void *)bgep, (void *)ppd)); 4383 4384 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4385 ppd->pp_acc_data = err ? ~0ull : data; 4386 } 4387 4388 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4389 #pragma no_inline(bge_chip_poke_seeprom) 4390 4391 static void 4392 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4393 { 4394 uint32_t data; 4395 4396 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4397 (void *)bgep, (void *)ppd)); 4398 4399 data = ppd->pp_acc_data; 4400 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4401 } 4402 #endif /* BGE_SEE_IO32 */ 4403 4404 #if BGE_FLASH_IO32 4405 4406 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4407 #pragma no_inline(bge_chip_peek_flash) 4408 4409 static void 4410 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4411 { 4412 uint32_t data; 4413 int err; 4414 4415 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4416 (void *)bgep, (void *)ppd)); 4417 4418 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4419 ppd->pp_acc_data = err ? ~0ull : data; 4420 } 4421 4422 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4423 #pragma no_inline(bge_chip_poke_flash) 4424 4425 static void 4426 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4427 { 4428 uint32_t data; 4429 4430 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4431 (void *)bgep, (void *)ppd)); 4432 4433 data = ppd->pp_acc_data; 4434 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4435 ppd->pp_acc_offset, &data); 4436 } 4437 #endif /* BGE_FLASH_IO32 */ 4438 4439 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4440 #pragma no_inline(bge_chip_peek_mem) 4441 4442 static void 4443 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4444 { 4445 uint64_t regval; 4446 void *vaddr; 4447 4448 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4449 (void *)bgep, (void *)ppd)); 4450 4451 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4452 4453 switch (ppd->pp_acc_size) { 4454 case 1: 4455 regval = *(uint8_t *)vaddr; 4456 break; 4457 4458 case 2: 4459 regval = *(uint16_t *)vaddr; 4460 break; 4461 4462 case 4: 4463 regval = *(uint32_t *)vaddr; 4464 break; 4465 4466 case 8: 4467 regval = *(uint64_t *)vaddr; 4468 break; 4469 } 4470 4471 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4472 (void *)bgep, (void *)ppd, regval, vaddr)); 4473 4474 ppd->pp_acc_data = regval; 4475 } 4476 4477 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4478 #pragma no_inline(bge_chip_poke_mem) 4479 4480 static void 4481 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4482 { 4483 uint64_t regval; 4484 void *vaddr; 4485 4486 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4487 (void *)bgep, (void *)ppd)); 4488 4489 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4490 regval = ppd->pp_acc_data; 4491 4492 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4493 (void *)bgep, (void *)ppd, regval, vaddr)); 4494 4495 switch (ppd->pp_acc_size) { 4496 case 1: 4497 *(uint8_t *)vaddr = (uint8_t)regval; 4498 break; 4499 4500 case 2: 4501 *(uint16_t *)vaddr = (uint16_t)regval; 4502 break; 4503 4504 case 4: 4505 *(uint32_t *)vaddr = (uint32_t)regval; 4506 break; 4507 4508 case 8: 4509 *(uint64_t *)vaddr = (uint64_t)regval; 4510 break; 4511 } 4512 } 4513 4514 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4515 struct iocblk *iocp); 4516 #pragma no_inline(bge_pp_ioctl) 4517 4518 static enum ioc_reply 4519 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4520 { 4521 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4522 bge_peekpoke_t *ppd; 4523 dma_area_t *areap; 4524 uint64_t sizemask; 4525 uint64_t mem_va; 4526 uint64_t maxoff; 4527 boolean_t peek; 4528 4529 switch (cmd) { 4530 default: 4531 /* NOTREACHED */ 4532 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4533 return (IOC_INVAL); 4534 4535 case BGE_PEEK: 4536 peek = B_TRUE; 4537 break; 4538 4539 case BGE_POKE: 4540 peek = B_FALSE; 4541 break; 4542 } 4543 4544 /* 4545 * Validate format of ioctl 4546 */ 4547 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4548 return (IOC_INVAL); 4549 if (mp->b_cont == NULL) 4550 return (IOC_INVAL); 4551 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4552 4553 /* 4554 * Validate request parameters 4555 */ 4556 switch (ppd->pp_acc_space) { 4557 default: 4558 return (IOC_INVAL); 4559 4560 case BGE_PP_SPACE_CFG: 4561 /* 4562 * Config space 4563 */ 4564 sizemask = 8|4|2|1; 4565 mem_va = 0; 4566 maxoff = PCI_CONF_HDR_SIZE; 4567 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4568 break; 4569 4570 case BGE_PP_SPACE_REG: 4571 /* 4572 * Memory-mapped I/O space 4573 */ 4574 sizemask = 8|4|2|1; 4575 mem_va = 0; 4576 maxoff = RIAAR_REGISTER_MAX; 4577 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4578 break; 4579 4580 case BGE_PP_SPACE_NIC: 4581 /* 4582 * NIC on-chip memory 4583 */ 4584 sizemask = 8|4|2|1; 4585 mem_va = 0; 4586 maxoff = MWBAR_ONCHIP_MAX; 4587 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4588 break; 4589 4590 case BGE_PP_SPACE_MII: 4591 /* 4592 * PHY's MII registers 4593 * NB: all PHY registers are two bytes, but the 4594 * addresses increment in ones (word addressing). 4595 * So we scale the address here, then undo the 4596 * transformation inside the peek/poke functions. 4597 */ 4598 ppd->pp_acc_offset *= 2; 4599 sizemask = 2; 4600 mem_va = 0; 4601 maxoff = (MII_MAXREG+1)*2; 4602 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 4603 break; 4604 4605 #if BGE_SEE_IO32 4606 case BGE_PP_SPACE_SEEPROM: 4607 /* 4608 * Attached SEEPROM(s), if any. 4609 * NB: we use the high-order bits of the 'address' as 4610 * a device select to accommodate multiple SEEPROMS, 4611 * If each one is the maximum size (64kbytes), this 4612 * makes them appear contiguous. Otherwise, there may 4613 * be holes in the mapping. ENxS doesn't have any 4614 * SEEPROMs anyway ... 4615 */ 4616 sizemask = 4; 4617 mem_va = 0; 4618 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 4619 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 4620 break; 4621 #endif /* BGE_SEE_IO32 */ 4622 4623 #if BGE_FLASH_IO32 4624 case BGE_PP_SPACE_FLASH: 4625 /* 4626 * Attached Flash device (if any); a maximum of one device 4627 * is currently supported. But it can be up to 1MB (unlike 4628 * the 64k limit on SEEPROMs) so why would you need more ;-) 4629 */ 4630 sizemask = 4; 4631 mem_va = 0; 4632 maxoff = NVM_FLASH_ADDR_MASK; 4633 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 4634 break; 4635 #endif /* BGE_FLASH_IO32 */ 4636 4637 case BGE_PP_SPACE_BGE: 4638 /* 4639 * BGE data structure! 4640 */ 4641 sizemask = 8|4|2|1; 4642 mem_va = (uintptr_t)bgep; 4643 maxoff = sizeof (*bgep); 4644 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4645 break; 4646 4647 case BGE_PP_SPACE_STATUS: 4648 case BGE_PP_SPACE_STATISTICS: 4649 case BGE_PP_SPACE_TXDESC: 4650 case BGE_PP_SPACE_TXBUFF: 4651 case BGE_PP_SPACE_RXDESC: 4652 case BGE_PP_SPACE_RXBUFF: 4653 /* 4654 * Various DMA_AREAs 4655 */ 4656 switch (ppd->pp_acc_space) { 4657 case BGE_PP_SPACE_TXDESC: 4658 areap = &bgep->tx_desc; 4659 break; 4660 case BGE_PP_SPACE_TXBUFF: 4661 areap = &bgep->tx_buff[0]; 4662 break; 4663 case BGE_PP_SPACE_RXDESC: 4664 areap = &bgep->rx_desc[0]; 4665 break; 4666 case BGE_PP_SPACE_RXBUFF: 4667 areap = &bgep->rx_buff[0]; 4668 break; 4669 case BGE_PP_SPACE_STATUS: 4670 areap = &bgep->status_block; 4671 break; 4672 case BGE_PP_SPACE_STATISTICS: 4673 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4674 areap = &bgep->statistics; 4675 break; 4676 } 4677 4678 sizemask = 8|4|2|1; 4679 mem_va = (uintptr_t)areap->mem_va; 4680 maxoff = areap->alength; 4681 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4682 break; 4683 } 4684 4685 switch (ppd->pp_acc_size) { 4686 default: 4687 return (IOC_INVAL); 4688 4689 case 8: 4690 case 4: 4691 case 2: 4692 case 1: 4693 if ((ppd->pp_acc_size & sizemask) == 0) 4694 return (IOC_INVAL); 4695 break; 4696 } 4697 4698 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4699 return (IOC_INVAL); 4700 4701 if (ppd->pp_acc_offset >= maxoff) 4702 return (IOC_INVAL); 4703 4704 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 4705 return (IOC_INVAL); 4706 4707 /* 4708 * All OK - go do it! 4709 */ 4710 ppd->pp_acc_offset += mem_va; 4711 (*ppfn)(bgep, ppd); 4712 return (peek ? IOC_REPLY : IOC_ACK); 4713 } 4714 4715 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4716 struct iocblk *iocp); 4717 #pragma no_inline(bge_diag_ioctl) 4718 4719 static enum ioc_reply 4720 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4721 { 4722 ASSERT(mutex_owned(bgep->genlock)); 4723 4724 switch (cmd) { 4725 default: 4726 /* NOTREACHED */ 4727 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 4728 return (IOC_INVAL); 4729 4730 case BGE_DIAG: 4731 /* 4732 * Currently a no-op 4733 */ 4734 return (IOC_ACK); 4735 4736 case BGE_PEEK: 4737 case BGE_POKE: 4738 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 4739 4740 case BGE_PHY_RESET: 4741 return (IOC_RESTART_ACK); 4742 4743 case BGE_SOFT_RESET: 4744 case BGE_HARD_RESET: 4745 /* 4746 * Reset and reinitialise the 570x hardware 4747 */ 4748 bge_restart(bgep, cmd == BGE_HARD_RESET); 4749 return (IOC_ACK); 4750 } 4751 4752 /* NOTREACHED */ 4753 } 4754 4755 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 4756 4757 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4758 struct iocblk *iocp); 4759 #pragma no_inline(bge_mii_ioctl) 4760 4761 static enum ioc_reply 4762 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4763 { 4764 struct bge_mii_rw *miirwp; 4765 4766 /* 4767 * Validate format of ioctl 4768 */ 4769 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 4770 return (IOC_INVAL); 4771 if (mp->b_cont == NULL) 4772 return (IOC_INVAL); 4773 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 4774 4775 /* 4776 * Validate request parameters ... 4777 */ 4778 if (miirwp->mii_reg > MII_MAXREG) 4779 return (IOC_INVAL); 4780 4781 switch (cmd) { 4782 default: 4783 /* NOTREACHED */ 4784 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 4785 return (IOC_INVAL); 4786 4787 case BGE_MII_READ: 4788 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 4789 return (IOC_REPLY); 4790 4791 case BGE_MII_WRITE: 4792 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 4793 return (IOC_ACK); 4794 } 4795 4796 /* NOTREACHED */ 4797 } 4798 4799 #if BGE_SEE_IO32 4800 4801 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4802 struct iocblk *iocp); 4803 #pragma no_inline(bge_see_ioctl) 4804 4805 static enum ioc_reply 4806 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4807 { 4808 struct bge_see_rw *seerwp; 4809 4810 /* 4811 * Validate format of ioctl 4812 */ 4813 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 4814 return (IOC_INVAL); 4815 if (mp->b_cont == NULL) 4816 return (IOC_INVAL); 4817 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 4818 4819 /* 4820 * Validate request parameters ... 4821 */ 4822 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 4823 return (IOC_INVAL); 4824 4825 switch (cmd) { 4826 default: 4827 /* NOTREACHED */ 4828 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 4829 return (IOC_INVAL); 4830 4831 case BGE_SEE_READ: 4832 case BGE_SEE_WRITE: 4833 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 4834 seerwp->see_addr, &seerwp->see_data); 4835 return (IOC_REPLY); 4836 } 4837 4838 /* NOTREACHED */ 4839 } 4840 4841 #endif /* BGE_SEE_IO32 */ 4842 4843 #if BGE_FLASH_IO32 4844 4845 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4846 struct iocblk *iocp); 4847 #pragma no_inline(bge_flash_ioctl) 4848 4849 static enum ioc_reply 4850 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4851 { 4852 struct bge_flash_rw *flashrwp; 4853 4854 /* 4855 * Validate format of ioctl 4856 */ 4857 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 4858 return (IOC_INVAL); 4859 if (mp->b_cont == NULL) 4860 return (IOC_INVAL); 4861 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 4862 4863 /* 4864 * Validate request parameters ... 4865 */ 4866 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 4867 return (IOC_INVAL); 4868 4869 switch (cmd) { 4870 default: 4871 /* NOTREACHED */ 4872 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 4873 return (IOC_INVAL); 4874 4875 case BGE_FLASH_READ: 4876 case BGE_FLASH_WRITE: 4877 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 4878 flashrwp->flash_addr, &flashrwp->flash_data); 4879 return (IOC_REPLY); 4880 } 4881 4882 /* NOTREACHED */ 4883 } 4884 4885 #endif /* BGE_FLASH_IO32 */ 4886 4887 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 4888 struct iocblk *iocp); 4889 #pragma no_inline(bge_chip_ioctl) 4890 4891 enum ioc_reply 4892 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 4893 { 4894 int cmd; 4895 4896 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 4897 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 4898 4899 ASSERT(mutex_owned(bgep->genlock)); 4900 4901 cmd = iocp->ioc_cmd; 4902 switch (cmd) { 4903 default: 4904 /* NOTREACHED */ 4905 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 4906 return (IOC_INVAL); 4907 4908 case BGE_DIAG: 4909 case BGE_PEEK: 4910 case BGE_POKE: 4911 case BGE_PHY_RESET: 4912 case BGE_SOFT_RESET: 4913 case BGE_HARD_RESET: 4914 #if BGE_DEBUGGING || BGE_DO_PPIO 4915 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 4916 #else 4917 return (IOC_INVAL); 4918 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 4919 4920 case BGE_MII_READ: 4921 case BGE_MII_WRITE: 4922 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 4923 4924 #if BGE_SEE_IO32 4925 case BGE_SEE_READ: 4926 case BGE_SEE_WRITE: 4927 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 4928 #endif /* BGE_SEE_IO32 */ 4929 4930 #if BGE_FLASH_IO32 4931 case BGE_FLASH_READ: 4932 case BGE_FLASH_WRITE: 4933 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 4934 #endif /* BGE_FLASH_IO32 */ 4935 } 4936 4937 /* NOTREACHED */ 4938 } 4939 4940 void 4941 bge_chip_blank(void *arg, time_t ticks, uint_t count) 4942 { 4943 bge_t *bgep = arg; 4944 4945 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 4946 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 4947 } 4948 4949 #ifdef BGE_IPMI_ASF 4950 4951 uint32_t 4952 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 4953 { 4954 uint32_t data; 4955 4956 if (!bgep->asf_wordswapped) { 4957 /* a workaround word swap error */ 4958 if (addr & 4) 4959 addr = addr - 4; 4960 else 4961 addr = addr + 4; 4962 } 4963 4964 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 4965 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 4966 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 4967 4968 return (data); 4969 } 4970 4971 4972 void 4973 bge_asf_update_status(bge_t *bgep) 4974 { 4975 uint32_t event; 4976 4977 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 4978 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 4979 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 4980 4981 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 4982 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 4983 } 4984 4985 4986 /* 4987 * The driver is supposed to notify ASF that the OS is still running 4988 * every three seconds, otherwise the management server may attempt 4989 * to reboot the machine. If it hasn't actually failed, this is 4990 * not a desireable result. However, this isn't running as a real-time 4991 * thread, and even if it were, it might not be able to generate the 4992 * heartbeat in a timely manner due to system load. As it isn't a 4993 * significant strain on the machine, we will set the interval to half 4994 * of the required value. 4995 */ 4996 void 4997 bge_asf_heartbeat(void *bgep) 4998 { 4999 bge_asf_update_status((bge_t *)bgep); 5000 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5001 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5002 } 5003 5004 5005 void 5006 bge_asf_stop_timer(bge_t *bgep) 5007 { 5008 timeout_id_t tmp_id = 0; 5009 5010 while ((bgep->asf_timeout_id != 0) && 5011 (tmp_id != bgep->asf_timeout_id)) { 5012 tmp_id = bgep->asf_timeout_id; 5013 (void) untimeout(tmp_id); 5014 } 5015 bgep->asf_timeout_id = 0; 5016 } 5017 5018 5019 5020 /* 5021 * This function should be placed at the earliest postion of bge_attach(). 5022 */ 5023 void 5024 bge_asf_get_config(bge_t *bgep) 5025 { 5026 uint32_t nicsig; 5027 uint32_t niccfg; 5028 5029 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5030 if (nicsig == BGE_NIC_DATA_SIG) { 5031 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5032 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5033 /* 5034 * Here, we don't consider BAXTER, because BGE haven't 5035 * supported BAXTER (that is 5752). Also, as I know, 5036 * BAXTER doesn't support ASF feature. 5037 */ 5038 bgep->asf_enabled = B_TRUE; 5039 else 5040 bgep->asf_enabled = B_FALSE; 5041 } else 5042 bgep->asf_enabled = B_FALSE; 5043 } 5044 5045 5046 void 5047 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5048 { 5049 uint32_t tries; 5050 uint32_t event; 5051 5052 ASSERT(bgep->asf_enabled); 5053 5054 /* Issues "pause firmware" command and wait for ACK */ 5055 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5056 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5057 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5058 5059 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5060 tries = 0; 5061 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5062 drv_usecwait(1); 5063 tries ++; 5064 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5065 } 5066 5067 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5068 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5069 5070 if (bgep->asf_newhandshake) { 5071 switch (mode) { 5072 case BGE_INIT_RESET: 5073 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5074 BGE_DRV_STATE_START); 5075 break; 5076 case BGE_SHUTDOWN_RESET: 5077 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5078 BGE_DRV_STATE_UNLOAD); 5079 break; 5080 case BGE_SUSPEND_RESET: 5081 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5082 BGE_DRV_STATE_SUSPEND); 5083 break; 5084 default: 5085 break; 5086 } 5087 } 5088 } 5089 5090 5091 void 5092 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5093 { 5094 switch (mode) { 5095 case BGE_INIT_RESET: 5096 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5097 BGE_DRV_STATE_START); 5098 break; 5099 case BGE_SHUTDOWN_RESET: 5100 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5101 BGE_DRV_STATE_UNLOAD); 5102 break; 5103 case BGE_SUSPEND_RESET: 5104 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5105 BGE_DRV_STATE_SUSPEND); 5106 break; 5107 default: 5108 break; 5109 } 5110 } 5111 5112 5113 void 5114 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5115 { 5116 switch (mode) { 5117 case BGE_INIT_RESET: 5118 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5119 BGE_DRV_STATE_START_DONE); 5120 break; 5121 case BGE_SHUTDOWN_RESET: 5122 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5123 BGE_DRV_STATE_UNLOAD_DONE); 5124 break; 5125 default: 5126 break; 5127 } 5128 } 5129 5130 #endif /* BGE_IPMI_ASF */ 5131