1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 /* 153 * bge_intr_max_loop controls the maximum loop number within bge_intr. 154 * When loading NIC with heavy network traffic, it is useful. 155 * Increasing this value could have positive effect to throughput, 156 * but it might also increase ticks of a bge ISR stick on CPU, which might 157 * lead to bad UI interactive experience. So tune this with caution. 158 */ 159 static int bge_intr_max_loop = 1; 160 161 /* 162 * ========== Low-level chip & ring buffer manipulation ========== 163 */ 164 165 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 166 167 168 /* 169 * Config space read-modify-write routines 170 */ 171 172 #if BGE_CFG_IO8 173 174 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 175 #pragma inline(bge_cfg_clr16) 176 177 static void 178 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 179 { 180 uint16_t regval; 181 182 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 183 (void *)bgep, regno, bits)); 184 185 regval = pci_config_get16(bgep->cfg_handle, regno); 186 187 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 188 (void *)bgep, regno, bits, regval, regval & ~bits)); 189 190 regval &= ~bits; 191 pci_config_put16(bgep->cfg_handle, regno, regval); 192 } 193 194 #endif /* BGE_CFG_IO8 */ 195 196 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 197 #pragma inline(bge_cfg_clr32) 198 199 static void 200 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 201 { 202 uint32_t regval; 203 204 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get32(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put32(bgep->cfg_handle, regno, regval); 214 } 215 216 #if BGE_IND_IO32 217 218 /* 219 * Indirect access to registers & RISC scratchpads, using config space 220 * accesses only. 221 * 222 * This isn't currently used, but someday we might want to use it for 223 * restoring the Subsystem Device/Vendor registers (which aren't directly 224 * writable in Config Space), or for downloading firmware into the RISCs 225 * 226 * In any case there are endian issues to be resolved before this code is 227 * enabled; the bizarre way that bytes get twisted by this chip AND by 228 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 229 * it's been thoroughly tested for all access sizes on all supported 230 * architectures (SPARC *and* x86!). 231 */ 232 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 233 #pragma inline(bge_ind_get32) 234 235 uint32_t 236 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 237 { 238 uint32_t val; 239 240 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 241 242 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 243 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 244 245 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 246 (void *)bgep, regno, val)); 247 248 val = LE_32(val); 249 250 return (val); 251 } 252 253 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 254 #pragma inline(bge_ind_put32) 255 256 void 257 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 258 { 259 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 260 (void *)bgep, regno, val)); 261 262 val = LE_32(val); 263 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 264 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 265 } 266 267 #endif /* BGE_IND_IO32 */ 268 269 #if BGE_DEBUGGING 270 271 static void bge_pci_check(bge_t *bgep); 272 #pragma no_inline(bge_pci_check) 273 274 static void 275 bge_pci_check(bge_t *bgep) 276 { 277 uint16_t pcistatus; 278 279 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 280 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 281 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 282 (void *)bgep, pcistatus)); 283 } 284 285 #endif /* BGE_DEBUGGING */ 286 287 /* 288 * Perform first-stage chip (re-)initialisation, using only config-space 289 * accesses: 290 * 291 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 292 * returning the data in the structure pointed to by <idp>. 293 * + Configure the target-mode endianness (swap) options. 294 * + Disable interrupts and enable Memory Space accesses. 295 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 296 * 297 * This sequence is adapted from Broadcom document 570X-PG102-R, 298 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 299 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 300 * 301 * This function MUST be called before any non-config-space accesses 302 * are made; on this first call <enable_dma> is B_FALSE, and it 303 * effectively performs steps 3-1(!) of the initialisation sequence 304 * (the rest are not required but should be harmless). 305 * 306 * It MUST also be called after a chip reset, as this disables 307 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 308 * it is effectively performing steps 6-8. 309 */ 310 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 311 #pragma no_inline(bge_chip_cfg_init) 312 313 void 314 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 315 { 316 ddi_acc_handle_t handle; 317 uint16_t command; 318 uint32_t mhcr; 319 uint16_t value16; 320 int i; 321 322 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 323 (void *)bgep, (void *)cidp, enable_dma)); 324 325 /* 326 * Step 3: save PCI cache line size and subsystem vendor ID 327 * 328 * Read all the config-space registers that characterise the 329 * chip, specifically vendor/device/revision/subsystem vendor 330 * and subsystem device id. We expect (but don't check) that 331 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 332 * 333 * Also save all bus-transaction related registers (cache-line 334 * size, bus-grant/latency parameters, etc). Some of these are 335 * cleared by reset, so we'll have to restore them later. This 336 * comes from the Broadcom document 570X-PG102-R ... 337 * 338 * Note: Broadcom document 570X-PG102-R seems to be in error 339 * here w.r.t. the offsets of the Subsystem Vendor ID and 340 * Subsystem (Device) ID registers, which are the opposite way 341 * round according to the PCI standard. For good measure, we 342 * save/restore both anyway. 343 */ 344 handle = bgep->cfg_handle; 345 346 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 347 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 348 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 349 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 350 351 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 352 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 353 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 354 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 355 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 356 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 357 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 358 359 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 360 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 361 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 362 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 363 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 364 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 365 cidp->vendor, cidp->device, cidp->revision)); 366 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 367 cidp->subven, cidp->subdev, cidp->asic_rev)); 368 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 369 cidp->clsize, cidp->latency, cidp->command)); 370 371 /* 372 * Step 2 (also step 6): disable and clear interrupts. 373 * Steps 11-13: configure PIO endianness options, and enable 374 * indirect register access. We'll also select any other 375 * options controlled by the MHCR (e.g. tagged status, mask 376 * interrupt mode) at this stage ... 377 * 378 * Note: internally, the chip is 64-bit and BIG-endian, but 379 * since it talks to the host over a (LITTLE-endian) PCI bus, 380 * it normally swaps bytes around at the PCI interface. 381 * However, the PCI host bridge on SPARC systems normally 382 * swaps the byte lanes around too, since SPARCs are also 383 * BIG-endian. So it turns out that on SPARC, the right 384 * option is to tell the chip to swap (and the host bridge 385 * will swap back again), whereas on x86 we ask the chip 386 * NOT to swap, so the natural little-endianness of the 387 * PCI bus is assumed. Then the only thing that doesn't 388 * automatically work right is access to an 8-byte register 389 * by a little-endian host; but we don't want to set the 390 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 391 * accesses don't go where expected ;-( So we live with 392 * that, and perform word-swaps in software in the few cases 393 * where a chip register is defined as an 8-byte value -- 394 * see the code below for details ... 395 * 396 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 397 * very clear in the register description in the PRM, but 398 * Broadcom document 570X-PG104-R page 248 explains a little 399 * more (under "Broadcom Mask Mode"). The bit changes the way 400 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 401 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 402 * way as the 5700 did, which isn't very convenient. Setting 403 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 404 * bit do just what its name says -- MASK the PCI #INTA output 405 * (i.e. deassert the signal at the pin) leaving all internal 406 * state unchanged. This is much more convenient for our 407 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 408 * 409 * Note: the inconvenient semantics of the interrupt mailbox 410 * (nonzero disables and acknowledges/clears the interrupt, 411 * zero enables AND CLEARS it) would make race conditions 412 * likely in the interrupt handler: 413 * 414 * (1) acknowledge & disable interrupts 415 * (2) while (more to do) 416 * process packets 417 * (3) enable interrupts -- also clears pending 418 * 419 * If the chip received more packets and internally generated 420 * an interrupt between the check at (2) and the mbox write 421 * at (3), this interrupt would be lost :-( 422 * 423 * The best way to avoid this is to use TAGGED STATUS mode, 424 * where the chip includes a unique tag in each status block 425 * update, and the host, when re-enabling interrupts, passes 426 * the last tag it saw back to the chip; then the chip can 427 * see whether the host is truly up to date, and regenerate 428 * its interrupt if not. 429 */ 430 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 431 MHCR_ENABLE_TAGGED_STATUS_MODE | 432 MHCR_MASK_INTERRUPT_MODE | 433 MHCR_CLEAR_INTERRUPT_INTA; 434 435 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 436 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 437 438 #ifdef _BIG_ENDIAN 439 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 440 #endif /* _BIG_ENDIAN */ 441 442 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 443 444 #ifdef BGE_IPMI_ASF 445 bgep->asf_wordswapped = B_FALSE; 446 #endif 447 /* 448 * Step 1 (also step 7): Enable PCI Memory Space accesses 449 * Disable Memory Write/Invalidate 450 * Enable or disable Bus Mastering 451 * 452 * Note that all other bits are taken from the original value saved 453 * the first time through here, rather than from the current register 454 * value, 'cos that will have been cleared by a soft RESET since. 455 * In this way we preserve the OBP/nexus-parent's preferred settings 456 * of the parity-error and system-error enable bits across multiple 457 * chip RESETs. 458 */ 459 command = bgep->chipid.command | PCI_COMM_MAE; 460 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 461 if (enable_dma) 462 command |= PCI_COMM_ME; 463 /* 464 * on BCM5714 revision A0, false parity error gets generated 465 * due to a logic bug. Provide a workaround by disabling parity 466 * error. 467 */ 468 if (((cidp->device == DEVICE_ID_5714C) || 469 (cidp->device == DEVICE_ID_5714S)) && 470 (cidp->revision == REVISION_ID_5714_A0)) { 471 command &= ~PCI_COMM_PARITY_DETECT; 472 } 473 pci_config_put16(handle, PCI_CONF_COMM, command); 474 475 /* 476 * On some PCI-E device, there were instances when 477 * the device was still link training. 478 */ 479 if (bgep->chipid.pci_type == BGE_PCI_E) { 480 i = 0; 481 value16 = pci_config_get16(handle, PCI_CONF_COMM); 482 while ((value16 != command) && (i < 100)) { 483 drv_usecwait(200); 484 value16 = pci_config_get16(handle, PCI_CONF_COMM); 485 ++i; 486 } 487 } 488 489 /* 490 * Clear any remaining error status bits 491 */ 492 pci_config_put16(handle, PCI_CONF_STAT, ~0); 493 494 /* 495 * Do following if and only if the device is NOT BCM5714C OR 496 * BCM5715C 497 */ 498 if (!((cidp->device == DEVICE_ID_5714C) || 499 (cidp->device == DEVICE_ID_5715C))) { 500 /* 501 * Make sure these indirect-access registers are sane 502 * rather than random after power-up or reset 503 */ 504 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 505 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 506 } 507 /* 508 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 509 */ 510 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 511 512 if (cidp->pci_type == BGE_PCI_E) { 513 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 514 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 515 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 516 } else 517 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 518 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 519 } 520 } 521 522 #ifdef __amd64 523 /* 524 * Distinguish CPU types 525 * 526 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 527 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 528 * for PCI-Express based network interface card. This is the work-around 529 * for those nics. 530 */ 531 static boolean_t bge_get_em64t_type(void); 532 #pragma inline(bge_get_em64t_type) 533 534 static boolean_t 535 bge_get_em64t_type(void) 536 { 537 538 return (x86_vendor == X86_VENDOR_Intel); 539 } 540 #endif 541 542 /* 543 * Operating register get/set access routines 544 */ 545 546 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 547 #pragma inline(bge_reg_get32) 548 549 uint32_t 550 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 551 { 552 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 553 (void *)bgep, regno)); 554 555 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 556 } 557 558 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 559 #pragma inline(bge_reg_put32) 560 561 void 562 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 563 { 564 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 565 (void *)bgep, regno, data)); 566 567 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 568 BGE_PCICHK(bgep); 569 } 570 571 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 572 #pragma inline(bge_reg_set32) 573 574 void 575 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 576 { 577 uint32_t regval; 578 579 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 580 (void *)bgep, regno, bits)); 581 582 regval = bge_reg_get32(bgep, regno); 583 regval |= bits; 584 bge_reg_put32(bgep, regno, regval); 585 } 586 587 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 588 #pragma inline(bge_reg_clr32) 589 590 void 591 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 592 { 593 uint32_t regval; 594 595 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 596 (void *)bgep, regno, bits)); 597 598 regval = bge_reg_get32(bgep, regno); 599 regval &= ~bits; 600 bge_reg_put32(bgep, regno, regval); 601 } 602 603 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 604 #pragma inline(bge_reg_get64) 605 606 static uint64_t 607 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 608 { 609 uint64_t regval; 610 611 #ifdef __amd64 612 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 613 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 614 regval <<= 32; 615 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 616 } else { 617 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 } 619 #elif defined(__sparc) 620 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 621 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 622 regval <<= 32; 623 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 624 } else { 625 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 626 } 627 #else 628 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 629 #endif 630 631 #ifdef _LITTLE_ENDIAN 632 regval = (regval >> 32) | (regval << 32); 633 #endif /* _LITTLE_ENDIAN */ 634 635 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 636 (void *)bgep, regno, regval)); 637 638 return (regval); 639 } 640 641 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 642 #pragma inline(bge_reg_put64) 643 644 static void 645 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 646 { 647 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 648 (void *)bgep, regno, data)); 649 650 #ifdef _LITTLE_ENDIAN 651 data = ((data >> 32) | (data << 32)); 652 #endif /* _LITTLE_ENDIAN */ 653 654 #ifdef __amd64 655 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 656 ddi_put32(bgep->io_handle, 657 PIO_ADDR(bgep, regno), (uint32_t)data); 658 BGE_PCICHK(bgep); 659 ddi_put32(bgep->io_handle, 660 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 661 662 } else { 663 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 664 } 665 #elif defined(__sparc) 666 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 667 ddi_put32(bgep->io_handle, 668 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 669 BGE_PCICHK(bgep); 670 ddi_put32(bgep->io_handle, 671 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 672 } else { 673 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 674 } 675 #else 676 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 677 #endif 678 679 BGE_PCICHK(bgep); 680 } 681 682 /* 683 * The DDI doesn't provide get/put functions for 128 bit data 684 * so we put RCBs out as two 64-bit chunks instead. 685 */ 686 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 687 #pragma inline(bge_reg_putrcb) 688 689 static void 690 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 691 { 692 uint64_t *p; 693 694 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 695 (void *)bgep, addr, rcbp->host_ring_addr, 696 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 697 698 ASSERT((addr % sizeof (*rcbp)) == 0); 699 700 p = (void *)rcbp; 701 bge_reg_put64(bgep, addr, *p++); 702 bge_reg_put64(bgep, addr+8, *p); 703 } 704 705 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 706 #pragma inline(bge_mbx_put) 707 708 void 709 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 710 { 711 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 712 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 713 714 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 715 (void *)bgep, regno, data)); 716 717 /* 718 * Mailbox registers are nominally 64 bits on the 5701, but 719 * the MSW isn't used. On the 5703, they're only 32 bits 720 * anyway. So here we just write the lower(!) 32 bits - 721 * remembering that the chip is big-endian, even though the 722 * PCI bus is little-endian ... 723 */ 724 #ifdef _BIG_ENDIAN 725 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 726 #else 727 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 728 #endif /* _BIG_ENDIAN */ 729 BGE_PCICHK(bgep); 730 } 731 732 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 733 #pragma inline(bge_mbx_get) 734 735 uint32_t 736 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 737 { 738 uint32_t val32; 739 740 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 741 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 742 743 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 744 (void *)bgep, regno)); 745 746 #ifdef _BIG_ENDIAN 747 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 748 #else 749 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 750 #endif /* _BIG_ENDIAN */ 751 BGE_PCICHK(bgep); 752 753 return (val32); 754 } 755 756 757 #if BGE_DEBUGGING 758 759 void bge_led_mark(bge_t *bgep); 760 #pragma no_inline(bge_led_mark) 761 762 void 763 bge_led_mark(bge_t *bgep) 764 { 765 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 766 LED_CONTROL_1000MBPS_LED | 767 LED_CONTROL_100MBPS_LED | 768 LED_CONTROL_10MBPS_LED; 769 770 /* 771 * Blink all three LINK LEDs on simultaneously, then all off, 772 * then restore to automatic hardware control. This is used 773 * in laboratory testing to trigger a logic analyser or scope. 774 */ 775 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 776 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 777 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 778 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 779 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 780 } 781 782 #endif /* BGE_DEBUGGING */ 783 784 /* 785 * NIC on-chip memory access routines 786 * 787 * Only 32K of NIC memory is visible at a time, controlled by the 788 * Memory Window Base Address Register (in PCI config space). Once 789 * this is set, the 32K region of NIC-local memory that it refers 790 * to can be directly addressed in the upper 32K of the 64K of PCI 791 * memory space used for the device. 792 */ 793 794 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 795 #pragma inline(bge_nic_setwin) 796 797 static void 798 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 799 { 800 chip_id_t *cidp; 801 802 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 803 (void *)bgep, base)); 804 805 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 806 807 /* 808 * Don't do repeated zero data writes, 809 * if the device is BCM5714C/15C. 810 */ 811 cidp = &bgep->chipid; 812 if ((cidp->device == DEVICE_ID_5714C) || 813 (cidp->device == DEVICE_ID_5715C)) { 814 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 815 return; 816 /* Adjust lastWriteZeroData */ 817 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 818 B_TRUE : B_FALSE); 819 } 820 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 821 } 822 823 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 824 #pragma inline(bge_nic_get32) 825 826 static uint32_t 827 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 828 { 829 uint32_t data; 830 831 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 832 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 833 /* workaround for word swap error */ 834 if (addr & 4) 835 addr = addr - 4; 836 else 837 addr = addr + 4; 838 } 839 #endif 840 841 #ifdef __sparc 842 data = bge_nic_read32(bgep, addr); 843 #else 844 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 845 addr &= MWBAR_GRANULE_MASK; 846 addr += NIC_MEM_WINDOW_OFFSET; 847 848 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 849 #endif 850 851 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 852 (void *)bgep, addr, data)); 853 854 return (data); 855 } 856 857 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 858 #pragma inline(bge_nic_put32) 859 860 void 861 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 862 { 863 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 864 (void *)bgep, addr, data)); 865 866 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 867 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 868 /* workaround for word swap error */ 869 if (addr & 4) 870 addr = addr - 4; 871 else 872 addr = addr + 4; 873 } 874 #endif 875 876 #ifdef __sparc 877 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 878 data = LE_32(data); 879 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 880 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 881 #else 882 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 883 addr &= MWBAR_GRANULE_MASK; 884 addr += NIC_MEM_WINDOW_OFFSET; 885 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 886 BGE_PCICHK(bgep); 887 #endif 888 } 889 890 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 891 #pragma inline(bge_nic_get64) 892 893 static uint64_t 894 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 895 { 896 uint64_t data; 897 898 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 899 addr &= MWBAR_GRANULE_MASK; 900 addr += NIC_MEM_WINDOW_OFFSET; 901 902 #ifdef __amd64 903 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 904 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 905 data <<= 32; 906 data |= ddi_get32(bgep->io_handle, 907 PIO_ADDR(bgep, addr + 4)); 908 } else { 909 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 910 } 911 #elif defined(__sparc) 912 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 913 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 914 data <<= 32; 915 data |= ddi_get32(bgep->io_handle, 916 PIO_ADDR(bgep, addr + 4)); 917 } else { 918 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 919 } 920 #else 921 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 922 #endif 923 924 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 925 (void *)bgep, addr, data)); 926 927 return (data); 928 } 929 930 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 931 #pragma inline(bge_nic_put64) 932 933 static void 934 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 935 { 936 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 937 (void *)bgep, addr, data)); 938 939 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 940 addr &= MWBAR_GRANULE_MASK; 941 addr += NIC_MEM_WINDOW_OFFSET; 942 943 #ifdef __amd64 944 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 945 ddi_put32(bgep->io_handle, 946 PIO_ADDR(bgep, addr), (uint32_t)data); 947 BGE_PCICHK(bgep); 948 ddi_put32(bgep->io_handle, 949 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 950 } else { 951 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 952 } 953 #elif defined(__sparc) 954 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 955 ddi_put32(bgep->io_handle, 956 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 957 BGE_PCICHK(bgep); 958 ddi_put32(bgep->io_handle, 959 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 960 } else { 961 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 962 } 963 #else 964 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 965 #endif 966 967 BGE_PCICHK(bgep); 968 } 969 970 /* 971 * The DDI doesn't provide get/put functions for 128 bit data 972 * so we put RCBs out as two 64-bit chunks instead. 973 */ 974 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 975 #pragma inline(bge_nic_putrcb) 976 977 static void 978 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 979 { 980 uint64_t *p; 981 982 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 983 (void *)bgep, addr, rcbp->host_ring_addr, 984 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 985 986 ASSERT((addr % sizeof (*rcbp)) == 0); 987 988 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 989 addr &= MWBAR_GRANULE_MASK; 990 addr += NIC_MEM_WINDOW_OFFSET; 991 992 p = (void *)rcbp; 993 #ifdef __amd64 994 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 995 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 996 (uint32_t)(*p)); 997 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 998 (uint32_t)(*p >> 32)); 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1000 (uint32_t)(*(p + 1))); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1002 (uint32_t)(*p >> 32)); 1003 1004 } else { 1005 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1006 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1007 } 1008 #elif defined(__sparc) 1009 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 1010 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1011 (uint32_t)(*p)); 1012 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1013 (uint32_t)(*p >> 32)); 1014 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1015 (uint32_t)(*(p + 1))); 1016 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1017 (uint32_t)(*p >> 32)); 1018 } else { 1019 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1020 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1021 } 1022 #else 1023 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1024 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1025 #endif 1026 1027 BGE_PCICHK(bgep); 1028 } 1029 1030 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1031 #pragma inline(bge_nic_zero) 1032 1033 static void 1034 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1035 { 1036 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1037 (void *)bgep, addr, nbytes)); 1038 1039 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1040 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1041 1042 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1043 addr &= MWBAR_GRANULE_MASK; 1044 addr += NIC_MEM_WINDOW_OFFSET; 1045 1046 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1047 nbytes, 1, DDI_DATA_SZ08_ACC); 1048 BGE_PCICHK(bgep); 1049 } 1050 1051 /* 1052 * MII (PHY) register get/set access routines 1053 * 1054 * These use the chip's MII auto-access method, controlled by the 1055 * MII Communication register at 0x044c, so the CPU doesn't have 1056 * to fiddle with the individual bits. 1057 */ 1058 1059 #undef BGE_DBG 1060 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1061 1062 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1063 uint16_t data, uint32_t cmd); 1064 #pragma no_inline(bge_mii_access) 1065 1066 static uint16_t 1067 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1068 { 1069 uint32_t timeout; 1070 uint32_t regval1; 1071 uint32_t regval2; 1072 1073 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1074 (void *)bgep, regno, data, cmd)); 1075 1076 ASSERT(mutex_owned(bgep->genlock)); 1077 1078 /* 1079 * Assemble the command ... 1080 */ 1081 cmd |= data << MI_COMMS_DATA_SHIFT; 1082 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1083 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1084 cmd |= MI_COMMS_START; 1085 1086 /* 1087 * Wait for any command already in progress ... 1088 * 1089 * Note: this *shouldn't* ever find that there is a command 1090 * in progress, because we already hold the <genlock> mutex. 1091 * Nonetheless, we have sometimes seen the MI_COMMS_START 1092 * bit set here -- it seems that the chip can initiate MII 1093 * accesses internally, even with polling OFF. 1094 */ 1095 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1096 for (timeout = 100; ; ) { 1097 if ((regval2 & MI_COMMS_START) == 0) { 1098 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1099 break; 1100 } 1101 if (--timeout == 0) 1102 break; 1103 drv_usecwait(10); 1104 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1105 } 1106 1107 if (timeout == 0) 1108 return ((uint16_t)~0u); 1109 1110 if (timeout != 100) 1111 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1112 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1113 cmd, 10*(100-timeout), regval1, regval2)); 1114 1115 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1116 for (timeout = 1000; ; ) { 1117 if ((regval1 & MI_COMMS_START) == 0) 1118 break; 1119 if (--timeout == 0) 1120 break; 1121 drv_usecwait(10); 1122 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1123 } 1124 1125 /* 1126 * Drop out early if the READ FAILED bit is set -- this chip 1127 * could be a 5703/4S, with a SerDes instead of a PHY! 1128 */ 1129 if (regval2 & MI_COMMS_READ_FAILED) 1130 return ((uint16_t)~0u); 1131 1132 if (timeout == 0) 1133 return ((uint16_t)~0u); 1134 1135 /* 1136 * The PRM says to wait 5us after seeing the START bit clear 1137 * and then re-read the register to get the final value of the 1138 * data field, in order to avoid a race condition where the 1139 * START bit is clear but the data field isn't yet valid. 1140 * 1141 * Note: we don't actually seem to be encounter this race; 1142 * except when the START bit is seen set again (see below), 1143 * the data field doesn't change during this 5us interval. 1144 */ 1145 drv_usecwait(5); 1146 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1147 1148 /* 1149 * Unfortunately, when following the PRMs instructions above, 1150 * we have occasionally seen the START bit set again(!) in the 1151 * value read after the 5us delay. This seems to be due to the 1152 * chip autonomously starting another MII access internally. 1153 * In such cases, the command/data/etc fields relate to the 1154 * internal command, rather than the one that we thought had 1155 * just finished. So in this case, we fall back to returning 1156 * the data from the original read that showed START clear. 1157 */ 1158 if (regval2 & MI_COMMS_START) { 1159 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1160 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1161 cmd, regval1, regval2)); 1162 regval2 = regval1; 1163 } 1164 1165 if (regval2 & MI_COMMS_START) 1166 return ((uint16_t)~0u); 1167 1168 if (regval2 & MI_COMMS_READ_FAILED) 1169 return ((uint16_t)~0u); 1170 1171 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1172 } 1173 1174 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1175 #pragma no_inline(bge_mii_get16) 1176 1177 uint16_t 1178 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1179 { 1180 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1181 (void *)bgep, regno)); 1182 1183 ASSERT(mutex_owned(bgep->genlock)); 1184 1185 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1186 (regno == MII_MSCONTROL))) 1187 return (0); 1188 1189 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1190 } 1191 1192 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1193 #pragma no_inline(bge_mii_put16) 1194 1195 void 1196 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1197 { 1198 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1199 (void *)bgep, regno, data)); 1200 1201 ASSERT(mutex_owned(bgep->genlock)); 1202 1203 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1204 (regno == MII_MSCONTROL))) 1205 return; 1206 1207 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1208 } 1209 1210 #undef BGE_DBG 1211 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1212 1213 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1214 1215 /* 1216 * Basic SEEPROM get/set access routine 1217 * 1218 * This uses the chip's SEEPROM auto-access method, controlled by the 1219 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1220 * doesn't have to fiddle with the individual bits. 1221 * 1222 * The caller should hold <genlock> and *also* have already acquired 1223 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1224 * 1225 * Return value: 1226 * 0 on success, 1227 * ENODATA on access timeout (maybe retryable: device may just be busy) 1228 * EPROTO on other h/w or s/w errors. 1229 * 1230 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1231 * from a (successful) SEEPROM_ACCESS_READ. 1232 */ 1233 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1234 uint32_t *dp); 1235 #pragma no_inline(bge_seeprom_access) 1236 1237 static int 1238 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1239 { 1240 uint32_t tries; 1241 uint32_t regval; 1242 1243 ASSERT(mutex_owned(bgep->genlock)); 1244 1245 /* 1246 * On the newer chips that support both SEEPROM & Flash, we need 1247 * to specifically enable SEEPROM access (Flash is the default). 1248 * On older chips, we don't; SEEPROM is the only NVtype supported, 1249 * and the NVM control registers don't exist ... 1250 */ 1251 switch (bgep->chipid.nvtype) { 1252 case BGE_NVTYPE_NONE: 1253 case BGE_NVTYPE_UNKNOWN: 1254 _NOTE(NOTREACHED) 1255 case BGE_NVTYPE_SEEPROM: 1256 break; 1257 1258 case BGE_NVTYPE_LEGACY_SEEPROM: 1259 case BGE_NVTYPE_UNBUFFERED_FLASH: 1260 case BGE_NVTYPE_BUFFERED_FLASH: 1261 default: 1262 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1263 NVM_CFG1_LEGACY_SEEPROM_MODE); 1264 break; 1265 } 1266 1267 /* 1268 * Check there's no command in progress. 1269 * 1270 * Note: this *shouldn't* ever find that there is a command 1271 * in progress, because we already hold the <genlock> mutex. 1272 * Also, to ensure we don't have a conflict with the chip's 1273 * internal firmware or a process accessing the same (shared) 1274 * SEEPROM through the other port of a 5704, we've already 1275 * been through the "software arbitration" protocol. 1276 * So this is just a final consistency check: we shouldn't 1277 * see EITHER the START bit (command started but not complete) 1278 * OR the COMPLETE bit (command completed but not cleared). 1279 */ 1280 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1281 if (regval & SEEPROM_ACCESS_START) 1282 return (EPROTO); 1283 if (regval & SEEPROM_ACCESS_COMPLETE) 1284 return (EPROTO); 1285 1286 /* 1287 * Assemble the command ... 1288 */ 1289 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1290 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1291 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1292 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1293 cmd |= SEEPROM_ACCESS_START; 1294 cmd |= SEEPROM_ACCESS_COMPLETE; 1295 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1296 1297 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1298 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1299 1300 /* 1301 * By observation, a successful access takes ~20us on a 5703/4, 1302 * but apparently much longer (up to 1000us) on the obsolescent 1303 * BCM5700/BCM5701. We want to be sure we don't get any false 1304 * timeouts here; but OTOH, we don't want a bogus access to lock 1305 * out interrupts for longer than necessary. So we'll allow up 1306 * to 1000us ... 1307 */ 1308 for (tries = 0; tries < 1000; ++tries) { 1309 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1310 if (regval & SEEPROM_ACCESS_COMPLETE) 1311 break; 1312 drv_usecwait(1); 1313 } 1314 1315 if (regval & SEEPROM_ACCESS_COMPLETE) { 1316 /* 1317 * All OK; read the SEEPROM data register, then write back 1318 * the value read from the address register in order to 1319 * clear the <complete> bit and leave the SEEPROM access 1320 * state machine idle, ready for the next access ... 1321 */ 1322 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1323 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1324 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1325 return (0); 1326 } 1327 1328 /* 1329 * Hmm ... what happened here? 1330 * 1331 * Most likely, the user addressed a non-existent SEEPROM. Or 1332 * maybe the SEEPROM was busy internally (e.g. processing a write) 1333 * and didn't respond to being addressed. Either way, it's left 1334 * the SEEPROM access state machine wedged. So we'll reset it 1335 * before we leave, so it's ready for next time ... 1336 */ 1337 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1338 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1339 return (ENODATA); 1340 } 1341 1342 /* 1343 * Basic Flash get/set access routine 1344 * 1345 * These use the chip's Flash auto-access method, controlled by the 1346 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1347 * fiddle with the individual bits. 1348 * 1349 * The caller should hold <genlock> and *also* have already acquired 1350 * the right to access the Flash, via bge_nvmem_acquire() above. 1351 * 1352 * Return value: 1353 * 0 on success, 1354 * ENODATA on access timeout (maybe retryable: device may just be busy) 1355 * ENODEV if the NVmem device is missing or otherwise unusable 1356 * 1357 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1358 * from a (successful) NVM_FLASH_CMD_RD. 1359 */ 1360 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1361 uint32_t *dp); 1362 #pragma no_inline(bge_flash_access) 1363 1364 static int 1365 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1366 { 1367 uint32_t tries; 1368 uint32_t regval; 1369 1370 ASSERT(mutex_owned(bgep->genlock)); 1371 1372 /* 1373 * On the newer chips that support both SEEPROM & Flash, we need 1374 * to specifically disable SEEPROM access while accessing Flash. 1375 * The older chips don't support Flash, and the NVM registers don't 1376 * exist, so we shouldn't be here at all! 1377 */ 1378 switch (bgep->chipid.nvtype) { 1379 case BGE_NVTYPE_NONE: 1380 case BGE_NVTYPE_UNKNOWN: 1381 _NOTE(NOTREACHED) 1382 case BGE_NVTYPE_SEEPROM: 1383 return (ENODEV); 1384 1385 case BGE_NVTYPE_LEGACY_SEEPROM: 1386 case BGE_NVTYPE_UNBUFFERED_FLASH: 1387 case BGE_NVTYPE_BUFFERED_FLASH: 1388 default: 1389 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1390 NVM_CFG1_LEGACY_SEEPROM_MODE); 1391 break; 1392 } 1393 1394 /* 1395 * Assemble the command ... 1396 */ 1397 addr &= NVM_FLASH_ADDR_MASK; 1398 cmd |= NVM_FLASH_CMD_DOIT; 1399 cmd |= NVM_FLASH_CMD_FIRST; 1400 cmd |= NVM_FLASH_CMD_LAST; 1401 cmd |= NVM_FLASH_CMD_DONE; 1402 1403 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1404 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1405 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1406 1407 /* 1408 * Allow up to 1000ms ... 1409 */ 1410 for (tries = 0; tries < 1000; ++tries) { 1411 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1412 if (regval & NVM_FLASH_CMD_DONE) 1413 break; 1414 drv_usecwait(1); 1415 } 1416 1417 if (regval & NVM_FLASH_CMD_DONE) { 1418 /* 1419 * All OK; read the data from the Flash read register 1420 */ 1421 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1422 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1423 return (0); 1424 } 1425 1426 /* 1427 * Hmm ... what happened here? 1428 * 1429 * Most likely, the user addressed a non-existent Flash. Or 1430 * maybe the Flash was busy internally (e.g. processing a write) 1431 * and didn't respond to being addressed. Either way, there's 1432 * nothing we can here ... 1433 */ 1434 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1435 return (ENODATA); 1436 } 1437 1438 /* 1439 * The next two functions regulate access to the NVram (if fitted). 1440 * 1441 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1442 * (SPI) interface, but they can be accessed through either port. These 1443 * are managed by different instance of this driver and have no software 1444 * state in common. 1445 * 1446 * In addition (and even on a single core chip) the chip's internal 1447 * firmware can access the SEEPROM/Flash, most notably after a RESET 1448 * when it may download code to run internally. 1449 * 1450 * So we need to arbitrate between these various software agents. For 1451 * this purpose, the chip provides the Software Arbitration Register, 1452 * which implements hardware(!) arbitration. 1453 * 1454 * This functionality didn't exist on older (5700/5701) chips, so there's 1455 * nothing we can do by way of arbitration on those; also, if there's no 1456 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1457 * nothing to do. 1458 * 1459 * The internal firmware appears to use Request 0, which is the highest 1460 * priority. So we'd like to use Request 2, leaving one higher and one 1461 * lower for any future developments ... but apparently this doesn't 1462 * always work. So for now, the code uses Request 1 ;-( 1463 */ 1464 1465 #define NVM_READ_REQ NVM_READ_REQ1 1466 #define NVM_RESET_REQ NVM_RESET_REQ1 1467 #define NVM_SET_REQ NVM_SET_REQ1 1468 1469 static void bge_nvmem_relinquish(bge_t *bgep); 1470 #pragma no_inline(bge_nvmem_relinquish) 1471 1472 static void 1473 bge_nvmem_relinquish(bge_t *bgep) 1474 { 1475 ASSERT(mutex_owned(bgep->genlock)); 1476 1477 switch (bgep->chipid.nvtype) { 1478 case BGE_NVTYPE_NONE: 1479 case BGE_NVTYPE_UNKNOWN: 1480 _NOTE(NOTREACHED) 1481 return; 1482 1483 case BGE_NVTYPE_SEEPROM: 1484 /* 1485 * No arbitration performed, no release needed 1486 */ 1487 return; 1488 1489 case BGE_NVTYPE_LEGACY_SEEPROM: 1490 case BGE_NVTYPE_UNBUFFERED_FLASH: 1491 case BGE_NVTYPE_BUFFERED_FLASH: 1492 default: 1493 break; 1494 } 1495 1496 /* 1497 * Our own request should be present (whether or not granted) ... 1498 */ 1499 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1500 1501 /* 1502 * ... this will make it go away. 1503 */ 1504 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1505 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1506 } 1507 1508 /* 1509 * Arbitrate for access to the NVmem, if necessary 1510 * 1511 * Return value: 1512 * 0 on success 1513 * EAGAIN if the device is in use (retryable) 1514 * ENODEV if the NVmem device is missing or otherwise unusable 1515 */ 1516 static int bge_nvmem_acquire(bge_t *bgep); 1517 #pragma no_inline(bge_nvmem_acquire) 1518 1519 static int 1520 bge_nvmem_acquire(bge_t *bgep) 1521 { 1522 uint32_t regval; 1523 uint32_t tries; 1524 1525 ASSERT(mutex_owned(bgep->genlock)); 1526 1527 switch (bgep->chipid.nvtype) { 1528 case BGE_NVTYPE_NONE: 1529 case BGE_NVTYPE_UNKNOWN: 1530 /* 1531 * Access denied: no (recognisable) device fitted 1532 */ 1533 return (ENODEV); 1534 1535 case BGE_NVTYPE_SEEPROM: 1536 /* 1537 * Access granted: no arbitration needed (or possible) 1538 */ 1539 return (0); 1540 1541 case BGE_NVTYPE_LEGACY_SEEPROM: 1542 case BGE_NVTYPE_UNBUFFERED_FLASH: 1543 case BGE_NVTYPE_BUFFERED_FLASH: 1544 default: 1545 /* 1546 * Access conditional: conduct arbitration protocol 1547 */ 1548 break; 1549 } 1550 1551 /* 1552 * We're holding the per-port mutex <genlock>, so no-one other 1553 * thread can be attempting to access the NVmem through *this* 1554 * port. But it could be in use by the *other* port (of a 5704), 1555 * or by the chip's internal firmware, so we have to go through 1556 * the full (hardware) arbitration protocol ... 1557 * 1558 * Note that *because* we're holding <genlock>, the interrupt handler 1559 * won't be able to progress. So we're only willing to spin for a 1560 * fairly short time. Specifically: 1561 * 1562 * We *must* wait long enough for the hardware to resolve all 1563 * requests and determine the winner. Fortunately, this is 1564 * "almost instantaneous", even as observed by GHz CPUs. 1565 * 1566 * A successful access by another Solaris thread (via either 1567 * port) typically takes ~20us. So waiting a bit longer than 1568 * that will give a good chance of success, if the other user 1569 * *is* another thread on the other port. 1570 * 1571 * However, the internal firmware can hold on to the NVmem 1572 * for *much* longer: at least 10 milliseconds just after a 1573 * RESET, and maybe even longer if the NVmem actually contains 1574 * code to download and run on the internal CPUs. 1575 * 1576 * So, we'll allow 50us; if that's not enough then it's up to the 1577 * caller to retry later (hence the choice of return code EAGAIN). 1578 */ 1579 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1580 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1581 1582 for (tries = 0; tries < 50; ++tries) { 1583 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1584 if (regval & NVM_WON_REQ1) 1585 break; 1586 drv_usecwait(1); 1587 } 1588 1589 if (regval & NVM_WON_REQ1) { 1590 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1591 return (0); 1592 } 1593 1594 /* 1595 * Somebody else must be accessing the NVmem, so abandon our 1596 * attempt take control of it. The caller can try again later ... 1597 */ 1598 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1599 bge_nvmem_relinquish(bgep); 1600 return (EAGAIN); 1601 } 1602 1603 /* 1604 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1605 * write protect line in such a way that the NVmem is protected when 1606 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1607 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1608 * 1609 * Note: there's only one set of GPIO pins on a 5704, even though they 1610 * can be accessed through either port. So the chip has to resolve what 1611 * happens if the two ports program a single pin differently ... the rule 1612 * it uses is that if the ports disagree about the *direction* of a pin, 1613 * "output" wins over "input", but if they disagree about its *value* as 1614 * an output, then the pin is TRISTATED instead! In such a case, no-one 1615 * wins, and the external signal does whatever the external circuitry 1616 * defines as the default -- which we've assumed is the PROTECTED state. 1617 * So, we always change GPIO1 back to being an *input* whenever we're not 1618 * specifically using it to unprotect the NVmem. This allows either port 1619 * to update the NVmem, although obviously only one at a time! 1620 * 1621 * The caller should hold <genlock> and *also* have already acquired the 1622 * right to access the NVmem, via bge_nvmem_acquire() above. 1623 */ 1624 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1625 #pragma inline(bge_nvmem_protect) 1626 1627 static void 1628 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1629 { 1630 uint32_t regval; 1631 1632 ASSERT(mutex_owned(bgep->genlock)); 1633 1634 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1635 if (protect) { 1636 regval |= MLCR_MISC_PINS_OUTPUT_1; 1637 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1638 } else { 1639 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1640 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1641 } 1642 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1643 } 1644 1645 /* 1646 * Now put it all together ... 1647 * 1648 * Try to acquire control of the NVmem; if successful, then: 1649 * unprotect it (if we want to write to it) 1650 * perform the requested access 1651 * reprotect it (after a write) 1652 * relinquish control 1653 * 1654 * Return value: 1655 * 0 on success, 1656 * EAGAIN if the device is in use (retryable) 1657 * ENODATA on access timeout (maybe retryable: device may just be busy) 1658 * ENODEV if the NVmem device is missing or otherwise unusable 1659 * EPROTO on other h/w or s/w errors. 1660 */ 1661 static int 1662 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1663 { 1664 int err; 1665 1666 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1667 switch (cmd) { 1668 case BGE_SEE_READ: 1669 err = bge_seeprom_access(bgep, 1670 SEEPROM_ACCESS_READ, addr, dp); 1671 break; 1672 1673 case BGE_SEE_WRITE: 1674 bge_nvmem_protect(bgep, B_FALSE); 1675 err = bge_seeprom_access(bgep, 1676 SEEPROM_ACCESS_WRITE, addr, dp); 1677 bge_nvmem_protect(bgep, B_TRUE); 1678 break; 1679 1680 case BGE_FLASH_READ: 1681 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1682 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1683 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1684 bge_reg_set32(bgep, NVM_ACCESS_REG, 1685 NVM_ACCESS_ENABLE); 1686 } 1687 err = bge_flash_access(bgep, 1688 NVM_FLASH_CMD_RD, addr, dp); 1689 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1690 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1691 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1692 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1693 NVM_ACCESS_ENABLE); 1694 } 1695 break; 1696 1697 case BGE_FLASH_WRITE: 1698 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1699 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1700 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1701 bge_reg_set32(bgep, NVM_ACCESS_REG, 1702 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1703 } 1704 bge_nvmem_protect(bgep, B_FALSE); 1705 err = bge_flash_access(bgep, 1706 NVM_FLASH_CMD_WR, addr, dp); 1707 bge_nvmem_protect(bgep, B_TRUE); 1708 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1709 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1710 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1711 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1712 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1713 } 1714 1715 break; 1716 1717 default: 1718 _NOTE(NOTREACHED) 1719 break; 1720 } 1721 bge_nvmem_relinquish(bgep); 1722 } 1723 1724 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1725 return (err); 1726 } 1727 1728 /* 1729 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1730 */ 1731 static uint64_t bge_get_nvmac(bge_t *bgep); 1732 #pragma no_inline(bge_get_nvmac) 1733 1734 static uint64_t 1735 bge_get_nvmac(bge_t *bgep) 1736 { 1737 uint32_t mac_high; 1738 uint32_t mac_low; 1739 uint32_t addr; 1740 uint32_t cmd; 1741 uint64_t mac; 1742 1743 BGE_TRACE(("bge_get_nvmac($%p)", 1744 (void *)bgep)); 1745 1746 switch (bgep->chipid.nvtype) { 1747 case BGE_NVTYPE_NONE: 1748 case BGE_NVTYPE_UNKNOWN: 1749 default: 1750 return (0ULL); 1751 1752 case BGE_NVTYPE_SEEPROM: 1753 case BGE_NVTYPE_LEGACY_SEEPROM: 1754 cmd = BGE_SEE_READ; 1755 break; 1756 1757 case BGE_NVTYPE_UNBUFFERED_FLASH: 1758 case BGE_NVTYPE_BUFFERED_FLASH: 1759 cmd = BGE_FLASH_READ; 1760 break; 1761 } 1762 1763 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1764 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1765 else 1766 addr = NVMEM_DATA_MAC_ADDRESS; 1767 1768 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1769 return (0ULL); 1770 addr += 4; 1771 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1772 return (0ULL); 1773 1774 /* 1775 * The Broadcom chip is natively BIG-endian, so that's how the 1776 * MAC address is represented in NVmem. We may need to swap it 1777 * around on a little-endian host ... 1778 */ 1779 #ifdef _BIG_ENDIAN 1780 mac = mac_high; 1781 mac = mac << 32; 1782 mac |= mac_low; 1783 #else 1784 mac = BGE_BSWAP_32(mac_high); 1785 mac = mac << 32; 1786 mac |= BGE_BSWAP_32(mac_low); 1787 #endif /* _BIG_ENDIAN */ 1788 1789 return (mac); 1790 } 1791 1792 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1793 1794 /* 1795 * Dummy version for when we're not supporting NVmem access 1796 */ 1797 static uint64_t bge_get_nvmac(bge_t *bgep); 1798 #pragma inline(bge_get_nvmac) 1799 1800 static uint64_t 1801 bge_get_nvmac(bge_t *bgep) 1802 { 1803 _NOTE(ARGUNUSED(bgep)) 1804 return (0ULL); 1805 } 1806 1807 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1808 1809 /* 1810 * Determine the type of NVmem that is (or may be) attached to this chip, 1811 */ 1812 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1813 #pragma no_inline(bge_nvmem_id) 1814 1815 static enum bge_nvmem_type 1816 bge_nvmem_id(bge_t *bgep) 1817 { 1818 enum bge_nvmem_type nvtype; 1819 uint32_t config1; 1820 1821 BGE_TRACE(("bge_nvmem_id($%p)", 1822 (void *)bgep)); 1823 1824 switch (bgep->chipid.device) { 1825 default: 1826 /* 1827 * We shouldn't get here; it means we don't recognise 1828 * the chip, which means we don't know how to determine 1829 * what sort of NVmem (if any) it has. So we'll say 1830 * NONE, to disable the NVmem access code ... 1831 */ 1832 nvtype = BGE_NVTYPE_NONE; 1833 break; 1834 1835 case DEVICE_ID_5700: 1836 case DEVICE_ID_5700x: 1837 case DEVICE_ID_5701: 1838 /* 1839 * These devices support *only* SEEPROMs 1840 */ 1841 nvtype = BGE_NVTYPE_SEEPROM; 1842 break; 1843 1844 case DEVICE_ID_5702: 1845 case DEVICE_ID_5702fe: 1846 case DEVICE_ID_5703C: 1847 case DEVICE_ID_5703S: 1848 case DEVICE_ID_5704C: 1849 case DEVICE_ID_5704S: 1850 case DEVICE_ID_5704: 1851 case DEVICE_ID_5705M: 1852 case DEVICE_ID_5705C: 1853 case DEVICE_ID_5705_2: 1854 case DEVICE_ID_5780: 1855 case DEVICE_ID_5782: 1856 case DEVICE_ID_5787: 1857 case DEVICE_ID_5787M: 1858 case DEVICE_ID_5788: 1859 case DEVICE_ID_5789: 1860 case DEVICE_ID_5751: 1861 case DEVICE_ID_5751M: 1862 case DEVICE_ID_5752: 1863 case DEVICE_ID_5752M: 1864 case DEVICE_ID_5754: 1865 case DEVICE_ID_5755: 1866 case DEVICE_ID_5755M: 1867 case DEVICE_ID_5756M: 1868 case DEVICE_ID_5721: 1869 case DEVICE_ID_5722: 1870 case DEVICE_ID_5723: 1871 case DEVICE_ID_5761: 1872 case DEVICE_ID_5761E: 1873 case DEVICE_ID_5764: 1874 case DEVICE_ID_5714C: 1875 case DEVICE_ID_5714S: 1876 case DEVICE_ID_5715C: 1877 case DEVICE_ID_5715S: 1878 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1879 if (config1 & NVM_CFG1_FLASH_MODE) 1880 if (config1 & NVM_CFG1_BUFFERED_MODE) 1881 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1882 else 1883 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1884 else 1885 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1886 break; 1887 case DEVICE_ID_5906: 1888 case DEVICE_ID_5906M: 1889 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1890 break; 1891 } 1892 1893 return (nvtype); 1894 } 1895 1896 #undef BGE_DBG 1897 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1898 1899 static void 1900 bge_init_recv_rule(bge_t *bgep) 1901 { 1902 bge_recv_rule_t *rulep = bgep->recv_rules; 1903 uint32_t i; 1904 1905 /* 1906 * Initialize receive rule registers. 1907 * Note that rules may persist across each bge_m_start/stop() call. 1908 */ 1909 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1910 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1911 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1912 } 1913 } 1914 1915 /* 1916 * Using the values captured by bge_chip_cfg_init(), and additional probes 1917 * as required, characterise the chip fully: determine the label by which 1918 * to refer to this chip, the correct settings for various registers, and 1919 * of course whether the device and/or subsystem are supported! 1920 */ 1921 int bge_chip_id_init(bge_t *bgep); 1922 #pragma no_inline(bge_chip_id_init) 1923 1924 int 1925 bge_chip_id_init(bge_t *bgep) 1926 { 1927 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1928 boolean_t sys_ok; 1929 boolean_t dev_ok; 1930 chip_id_t *cidp; 1931 uint32_t subid; 1932 char *devname; 1933 char *sysname; 1934 int *ids; 1935 int err; 1936 uint_t i; 1937 1938 sys_ok = dev_ok = B_FALSE; 1939 cidp = &bgep->chipid; 1940 1941 /* 1942 * Check the PCI device ID to determine the generic chip type and 1943 * select parameters that depend on this. 1944 * 1945 * Note: because the SPARC platforms in general don't fit the 1946 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1947 * as zero - which is why we use <asic_rev> rather than <revision> 1948 * below ... 1949 * 1950 * Note: in general we can't distinguish between the Copper/SerDes 1951 * versions by ID alone, as some Copper devices (e.g. some but not 1952 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1953 * treat them the same here, and the MII code works out the media 1954 * type later on ... 1955 */ 1956 cidp->mbuf_base = bge_mbuf_pool_base; 1957 cidp->mbuf_length = bge_mbuf_pool_len; 1958 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1959 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1960 cidp->pci_type = BGE_PCI_X; 1961 cidp->statistic_type = BGE_STAT_BLK; 1962 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1963 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1964 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1965 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1966 cidp->rx_count_norm = bge_rx_count_norm; 1967 cidp->tx_ticks_norm = bge_tx_ticks_norm; 1968 cidp->tx_count_norm = bge_tx_count_norm; 1969 1970 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1971 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1972 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1973 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1974 1975 cidp->msi_enabled = B_FALSE; 1976 1977 switch (cidp->device) { 1978 case DEVICE_ID_5700: 1979 case DEVICE_ID_5700x: 1980 cidp->chip_label = 5700; 1981 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1982 break; 1983 1984 case DEVICE_ID_5701: 1985 cidp->chip_label = 5701; 1986 dev_ok = B_TRUE; 1987 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1988 break; 1989 1990 case DEVICE_ID_5702: 1991 case DEVICE_ID_5702fe: 1992 cidp->chip_label = 5702; 1993 dev_ok = B_TRUE; 1994 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1995 cidp->pci_type = BGE_PCI; 1996 break; 1997 1998 case DEVICE_ID_5703C: 1999 case DEVICE_ID_5703S: 2000 case DEVICE_ID_5703: 2001 /* 2002 * Revision A0 of the 5703/5793 had various errata 2003 * that we can't or don't work around, so it's not 2004 * supported, but all later versions are 2005 */ 2006 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2007 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2008 dev_ok = B_TRUE; 2009 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2010 break; 2011 2012 case DEVICE_ID_5704C: 2013 case DEVICE_ID_5704S: 2014 case DEVICE_ID_5704: 2015 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2016 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2017 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2018 dev_ok = B_TRUE; 2019 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2020 break; 2021 2022 case DEVICE_ID_5705C: 2023 case DEVICE_ID_5705M: 2024 case DEVICE_ID_5705MA3: 2025 case DEVICE_ID_5705F: 2026 case DEVICE_ID_5705_2: 2027 case DEVICE_ID_5754: 2028 if (cidp->device == DEVICE_ID_5754) { 2029 cidp->chip_label = 5754; 2030 cidp->pci_type = BGE_PCI_E; 2031 } else { 2032 cidp->chip_label = 5705; 2033 cidp->pci_type = BGE_PCI; 2034 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2035 } 2036 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2037 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2038 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2039 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2040 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2041 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2042 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2043 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2044 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2045 cidp->statistic_type = BGE_STAT_REG; 2046 dev_ok = B_TRUE; 2047 break; 2048 2049 case DEVICE_ID_5906: 2050 case DEVICE_ID_5906M: 2051 cidp->chip_label = 5906; 2052 cidp->pci_type = BGE_PCI_E; 2053 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2054 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2055 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2056 cidp->mbuf_base = bge_mbuf_pool_base; 2057 cidp->mbuf_length = bge_mbuf_pool_len; 2058 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2059 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2060 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2061 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2062 cidp->statistic_type = BGE_STAT_REG; 2063 dev_ok = B_TRUE; 2064 break; 2065 2066 case DEVICE_ID_5753: 2067 cidp->chip_label = 5753; 2068 cidp->pci_type = BGE_PCI_E; 2069 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2070 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2071 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2072 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2073 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2074 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2075 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2076 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2077 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2078 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2079 cidp->statistic_type = BGE_STAT_REG; 2080 dev_ok = B_TRUE; 2081 break; 2082 2083 case DEVICE_ID_5755: 2084 case DEVICE_ID_5755M: 2085 cidp->chip_label = 5755; 2086 cidp->pci_type = BGE_PCI_E; 2087 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2088 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2089 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2090 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2091 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2092 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2093 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2094 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2095 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2096 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2097 if (cidp->device == DEVICE_ID_5755M) 2098 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2099 cidp->statistic_type = BGE_STAT_REG; 2100 dev_ok = B_TRUE; 2101 break; 2102 2103 case DEVICE_ID_5756M: 2104 /* 2105 * This is nearly identical to the 5755M. 2106 * (Actually reports the 5755 chip ID.) 2107 */ 2108 cidp->chip_label = 5756; 2109 cidp->pci_type = BGE_PCI_E; 2110 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2111 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2112 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2113 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2114 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2115 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2116 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2117 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2118 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2119 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2120 cidp->statistic_type = BGE_STAT_REG; 2121 dev_ok = B_TRUE; 2122 break; 2123 2124 case DEVICE_ID_5787: 2125 case DEVICE_ID_5787M: 2126 cidp->chip_label = 5787; 2127 cidp->pci_type = BGE_PCI_E; 2128 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2129 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2130 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2131 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2132 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2133 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2134 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2135 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2136 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2137 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2138 cidp->statistic_type = BGE_STAT_REG; 2139 dev_ok = B_TRUE; 2140 break; 2141 2142 case DEVICE_ID_5723: 2143 case DEVICE_ID_5761: 2144 case DEVICE_ID_5761E: 2145 cidp->msi_enabled = bge_enable_msi; 2146 /* 2147 * We don't use MSI for BCM5764, as the status block may 2148 * fail to update when the network traffic is heavy. 2149 */ 2150 /* FALLTHRU */ 2151 case DEVICE_ID_5764: 2152 if (cidp->device == DEVICE_ID_5723) 2153 cidp->chip_label = 5723; 2154 else if (cidp->device == DEVICE_ID_5764) 2155 cidp->chip_label = 5764; 2156 else 2157 cidp->chip_label = 5761; 2158 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2159 cidp->pci_type = BGE_PCI_E; 2160 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2161 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2162 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2163 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2164 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2165 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2166 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2167 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2168 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2169 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2170 cidp->statistic_type = BGE_STAT_REG; 2171 dev_ok = B_TRUE; 2172 break; 2173 2174 /* PCI-X device, identical to 5714 */ 2175 case DEVICE_ID_5780: 2176 cidp->chip_label = 5780; 2177 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2178 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2179 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2180 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2181 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2182 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2183 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2184 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2185 cidp->statistic_type = BGE_STAT_REG; 2186 dev_ok = B_TRUE; 2187 break; 2188 2189 case DEVICE_ID_5782: 2190 /* 2191 * Apart from the label, we treat this as a 5705(?) 2192 */ 2193 cidp->chip_label = 5782; 2194 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2195 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2196 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2197 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2198 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2199 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2200 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2201 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2202 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2203 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2204 cidp->statistic_type = BGE_STAT_REG; 2205 dev_ok = B_TRUE; 2206 break; 2207 2208 case DEVICE_ID_5788: 2209 /* 2210 * Apart from the label, we treat this as a 5705(?) 2211 */ 2212 cidp->chip_label = 5788; 2213 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2214 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2215 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2216 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2217 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2218 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2219 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2220 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2221 cidp->statistic_type = BGE_STAT_REG; 2222 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2223 dev_ok = B_TRUE; 2224 break; 2225 2226 case DEVICE_ID_5714C: 2227 if (cidp->revision >= REVISION_ID_5714_A2) 2228 cidp->msi_enabled = bge_enable_msi; 2229 /* FALLTHRU */ 2230 case DEVICE_ID_5714S: 2231 cidp->chip_label = 5714; 2232 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2233 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2234 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2235 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2236 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2237 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2238 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2239 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2240 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2241 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2242 cidp->pci_type = BGE_PCI_E; 2243 cidp->statistic_type = BGE_STAT_REG; 2244 dev_ok = B_TRUE; 2245 break; 2246 2247 case DEVICE_ID_5715C: 2248 case DEVICE_ID_5715S: 2249 cidp->chip_label = 5715; 2250 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2251 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2252 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2253 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2254 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2255 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2256 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2257 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2258 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2259 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2260 cidp->pci_type = BGE_PCI_E; 2261 cidp->statistic_type = BGE_STAT_REG; 2262 if (cidp->revision >= REVISION_ID_5715_A2) 2263 cidp->msi_enabled = bge_enable_msi; 2264 dev_ok = B_TRUE; 2265 break; 2266 2267 case DEVICE_ID_5721: 2268 cidp->chip_label = 5721; 2269 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2270 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2271 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2272 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2273 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2274 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2275 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2276 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2277 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2278 cidp->pci_type = BGE_PCI_E; 2279 cidp->statistic_type = BGE_STAT_REG; 2280 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2281 dev_ok = B_TRUE; 2282 break; 2283 2284 case DEVICE_ID_5722: 2285 cidp->chip_label = 5722; 2286 cidp->pci_type = BGE_PCI_E; 2287 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2288 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2289 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2290 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2291 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2292 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2293 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2294 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2295 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2296 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2297 cidp->statistic_type = BGE_STAT_REG; 2298 dev_ok = B_TRUE; 2299 break; 2300 2301 case DEVICE_ID_5751: 2302 case DEVICE_ID_5751M: 2303 cidp->chip_label = 5751; 2304 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2305 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2306 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2307 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2308 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2309 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2310 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2311 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2312 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2313 cidp->pci_type = BGE_PCI_E; 2314 cidp->statistic_type = BGE_STAT_REG; 2315 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2316 dev_ok = B_TRUE; 2317 break; 2318 2319 case DEVICE_ID_5752: 2320 case DEVICE_ID_5752M: 2321 cidp->chip_label = 5752; 2322 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2323 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2324 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2325 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2326 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2327 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2328 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2329 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2330 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2331 cidp->pci_type = BGE_PCI_E; 2332 cidp->statistic_type = BGE_STAT_REG; 2333 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2334 dev_ok = B_TRUE; 2335 break; 2336 2337 case DEVICE_ID_5789: 2338 cidp->chip_label = 5789; 2339 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2340 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2341 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2342 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2343 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2344 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2345 cidp->pci_type = BGE_PCI_E; 2346 cidp->statistic_type = BGE_STAT_REG; 2347 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2348 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2349 cidp->msi_enabled = B_TRUE; 2350 dev_ok = B_TRUE; 2351 break; 2352 2353 } 2354 2355 /* 2356 * Setup the default jumbo parameter. 2357 */ 2358 cidp->ethmax_size = ETHERMAX; 2359 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2360 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2361 2362 /* 2363 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2364 * setup below jumbo specific parameters. 2365 * 2366 * For BCM5714/5715, there is only one standard receive ring. So the 2367 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2368 * feature is enabled. 2369 */ 2370 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2371 (cidp->default_mtu > BGE_DEFAULT_MTU)) { 2372 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2373 cidp->mbuf_lo_water_rdma = 2374 RDMA_MBUF_LOWAT_5714_JUMBO; 2375 cidp->mbuf_lo_water_rmac = 2376 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2377 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2378 cidp->jumbo_slots = 0; 2379 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2380 } else { 2381 cidp->mbuf_lo_water_rdma = 2382 RDMA_MBUF_LOWAT_JUMBO; 2383 cidp->mbuf_lo_water_rmac = 2384 MAC_RX_MBUF_LOWAT_JUMBO; 2385 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2386 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2387 } 2388 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2389 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2390 cidp->ethmax_size = cidp->default_mtu + 2391 sizeof (struct ether_header); 2392 } 2393 2394 /* 2395 * Identify the NV memory type: SEEPROM or Flash? 2396 */ 2397 cidp->nvtype = bge_nvmem_id(bgep); 2398 2399 /* 2400 * Now, we want to check whether this device is part of a 2401 * supported subsystem (e.g., on the motherboard of a Sun 2402 * branded platform). 2403 * 2404 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2405 */ 2406 if (cidp->subven == VENDOR_ID_SUN) 2407 sys_ok = B_TRUE; 2408 2409 /* 2410 * Rule 2: If it's on the list on known subsystems, then it's OK. 2411 * Note: 0x14e41647 should *not* appear in the list, but the code 2412 * doesn't enforce that. 2413 */ 2414 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2415 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2416 if (err == DDI_PROP_SUCCESS) { 2417 /* 2418 * Got the list; scan for a matching subsystem vendor/device 2419 */ 2420 subid = (cidp->subven << 16) | cidp->subdev; 2421 while (i--) 2422 if (ids[i] == subid) 2423 sys_ok = B_TRUE; 2424 ddi_prop_free(ids); 2425 } 2426 2427 /* 2428 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2429 * 2430 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2431 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2432 * we have to check specially for the exact device paths to the 2433 * motherboard devices on those platforms ;-( 2434 * 2435 * Note: we can't just use the "supported-subsystems" mechanism 2436 * above, because the entry would have to be 0x14e41647 -- which 2437 * would then accept *any* plugin card that *didn't* contain a 2438 * (valid) SEEPROM ;-( 2439 */ 2440 sysname = ddi_node_name(ddi_root_node()); 2441 devname = ddi_pathname(bgep->devinfo, buf); 2442 ASSERT(strlen(devname) > 0); 2443 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2444 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2445 sys_ok = B_TRUE; 2446 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2447 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2448 sys_ok = B_TRUE; 2449 2450 /* 2451 * Now check what we've discovered: is this truly a supported 2452 * chip on (the motherboard of) a supported platform? 2453 * 2454 * Possible problems here: 2455 * 1) it's a completely unheard-of chip 2456 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2457 * 3) it's a chip we would support if it were on the motherboard 2458 * of a Sun platform, but this one isn't ;-( 2459 */ 2460 if (cidp->chip_label == 0) 2461 bge_problem(bgep, 2462 "Device 'pci%04x,%04x' not recognized (%d?)", 2463 cidp->vendor, cidp->device, cidp->device); 2464 else if (!dev_ok) 2465 bge_problem(bgep, 2466 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2467 cidp->vendor, cidp->device, cidp->chip_label, 2468 cidp->revision); 2469 #if BGE_DEBUGGING 2470 else if (!sys_ok) 2471 bge_problem(bgep, 2472 "%d-based subsystem 'pci%04x,%04x' not validated", 2473 cidp->chip_label, cidp->subven, cidp->subdev); 2474 #endif 2475 else 2476 cidp->flags |= CHIP_FLAG_SUPPORTED; 2477 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2478 return (EIO); 2479 return (0); 2480 } 2481 2482 void 2483 bge_chip_msi_trig(bge_t *bgep) 2484 { 2485 uint32_t regval; 2486 2487 regval = bgep->param_msi_cnt<<4; 2488 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2489 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2490 } 2491 2492 /* 2493 * Various registers that control the chip's internal engines (state 2494 * machines) have a <reset> and <enable> bits (fortunately, in the 2495 * same place in each such register :-). 2496 * 2497 * To reset the state machine, the <reset> bit must be written with 1; 2498 * it will then read back as 1 while the reset is in progress, but 2499 * self-clear to 0 when the reset completes. 2500 * 2501 * To enable a state machine, one must set the <enable> bit, which 2502 * will continue to read back as 0 until the state machine is running. 2503 * 2504 * To disable a state machine, the <enable> bit must be cleared, but 2505 * it will continue to read back as 1 until the state machine actually 2506 * stops. 2507 * 2508 * This routine implements polling for completion of a reset, enable 2509 * or disable operation, returning B_TRUE on success (bit reached the 2510 * required state) or B_FALSE on timeout (200*100us == 20ms). 2511 */ 2512 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2513 uint32_t mask, uint32_t val); 2514 #pragma no_inline(bge_chip_poll_engine) 2515 2516 static boolean_t 2517 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2518 uint32_t mask, uint32_t val) 2519 { 2520 uint32_t regval; 2521 uint32_t n; 2522 2523 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2524 (void *)bgep, regno, mask, val)); 2525 2526 for (n = 200; n; --n) { 2527 regval = bge_reg_get32(bgep, regno); 2528 if ((regval & mask) == val) 2529 return (B_TRUE); 2530 drv_usecwait(100); 2531 } 2532 2533 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2534 return (B_FALSE); 2535 } 2536 2537 /* 2538 * Various registers that control the chip's internal engines (state 2539 * machines) have a <reset> bit (fortunately, in the same place in 2540 * each such register :-). To reset the state machine, this bit must 2541 * be written with 1; it will then read back as 1 while the reset is 2542 * in progress, but self-clear to 0 when the reset completes. 2543 * 2544 * This code sets the bit, then polls for it to read back as zero. 2545 * The return value is B_TRUE on success (reset bit cleared itself), 2546 * or B_FALSE if the state machine didn't recover :( 2547 * 2548 * NOTE: the Core reset is similar to other resets, except that we 2549 * can't poll for completion, since the Core reset disables memory 2550 * access! So we just have to assume that it will all complete in 2551 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2552 */ 2553 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2554 #pragma no_inline(bge_chip_reset_engine) 2555 2556 static boolean_t 2557 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2558 { 2559 uint32_t regval; 2560 uint32_t val32; 2561 2562 regval = bge_reg_get32(bgep, regno); 2563 2564 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2565 (void *)bgep, regno)); 2566 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2567 regno, regval)); 2568 2569 regval |= STATE_MACHINE_RESET_BIT; 2570 2571 switch (regno) { 2572 case MISC_CONFIG_REG: 2573 /* 2574 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2575 * resetting PCIE block and bringing PCIE link down, bit 29 2576 * in the register needs to be set first, and then set it again 2577 * while the reset bit is written. 2578 * See:P500 of 57xx-PG102-RDS.pdf. 2579 */ 2580 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2581 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2582 DEVICE_5723_SERIES_CHIPSETS(bgep)|| 2583 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2584 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2585 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2586 if (bgep->chipid.pci_type == BGE_PCI_E) { 2587 if (bgep->chipid.asic_rev == 2588 MHCR_CHIP_REV_5751_A0 || 2589 bgep->chipid.asic_rev == 2590 MHCR_CHIP_REV_5721_A0 || 2591 bgep->chipid.asic_rev == 2592 MHCR_CHIP_REV_5755_A0) { 2593 val32 = bge_reg_get32(bgep, 2594 PHY_TEST_CTRL_REG); 2595 if (val32 == (PHY_PCIE_SCRAM_MODE | 2596 PHY_PCIE_LTASS_MODE)) 2597 bge_reg_put32(bgep, 2598 PHY_TEST_CTRL_REG, 2599 PHY_PCIE_SCRAM_MODE); 2600 val32 = pci_config_get32 2601 (bgep->cfg_handle, 2602 PCI_CONF_BGE_CLKCTL); 2603 val32 |= CLKCTL_PCIE_A0_FIX; 2604 pci_config_put32(bgep->cfg_handle, 2605 PCI_CONF_BGE_CLKCTL, val32); 2606 } 2607 bge_reg_set32(bgep, regno, 2608 MISC_CONFIG_GRC_RESET_DISABLE); 2609 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2610 } 2611 } 2612 2613 /* 2614 * Special case - causes Core reset 2615 * 2616 * On SPARC v9 we want to ensure that we don't start 2617 * timing until the I/O access has actually reached 2618 * the chip, otherwise we might make the next access 2619 * too early. And we can't just force the write out 2620 * by following it with a read (even to config space) 2621 * because that would cause the fault we're trying 2622 * to avoid. Hence the need for membar_sync() here. 2623 */ 2624 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2625 #ifdef __sparcv9 2626 membar_sync(); 2627 #endif /* __sparcv9 */ 2628 /* 2629 * On some platforms,system need about 300us for 2630 * link setup. 2631 */ 2632 drv_usecwait(300); 2633 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2634 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2635 bge_reg_clr32( 2636 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2637 } 2638 2639 if (bgep->chipid.pci_type == BGE_PCI_E) { 2640 /* PCI-E device need more reset time */ 2641 drv_usecwait(120000); 2642 2643 /* Set PCIE max payload size and clear error status. */ 2644 if ((bgep->chipid.chip_label == 5721) || 2645 (bgep->chipid.chip_label == 5751) || 2646 (bgep->chipid.chip_label == 5752) || 2647 (bgep->chipid.chip_label == 5789) || 2648 (bgep->chipid.chip_label == 5906)) { 2649 pci_config_put16(bgep->cfg_handle, 2650 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2651 pci_config_put16(bgep->cfg_handle, 2652 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2653 } 2654 2655 if ((bgep->chipid.chip_label == 5723) || 2656 (bgep->chipid.chip_label == 5761)) { 2657 pci_config_put16(bgep->cfg_handle, 2658 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 2659 pci_config_put16(bgep->cfg_handle, 2660 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 2661 } 2662 } 2663 2664 BGE_PCICHK(bgep); 2665 return (B_TRUE); 2666 2667 default: 2668 bge_reg_put32(bgep, regno, regval); 2669 return (bge_chip_poll_engine(bgep, regno, 2670 STATE_MACHINE_RESET_BIT, 0)); 2671 } 2672 } 2673 2674 /* 2675 * Various registers that control the chip's internal engines (state 2676 * machines) have an <enable> bit (fortunately, in the same place in 2677 * each such register :-). To stop the state machine, this bit must 2678 * be written with 0, then polled to see when the state machine has 2679 * actually stopped. 2680 * 2681 * The return value is B_TRUE on success (enable bit cleared), or 2682 * B_FALSE if the state machine didn't stop :( 2683 */ 2684 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2685 uint32_t morebits); 2686 #pragma no_inline(bge_chip_disable_engine) 2687 2688 static boolean_t 2689 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2690 { 2691 uint32_t regval; 2692 2693 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2694 (void *)bgep, regno, morebits)); 2695 2696 switch (regno) { 2697 case FTQ_RESET_REG: 2698 /* 2699 * For Schumacher's bugfix CR6490108 2700 */ 2701 #ifdef BGE_IPMI_ASF 2702 #ifdef BGE_NETCONSOLE 2703 if (bgep->asf_enabled) 2704 return (B_TRUE); 2705 #endif 2706 #endif 2707 /* 2708 * Not quite like the others; it doesn't 2709 * have an <enable> bit, but instead we 2710 * have to set and then clear all the bits 2711 */ 2712 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2713 drv_usecwait(100); 2714 bge_reg_put32(bgep, regno, 0); 2715 return (B_TRUE); 2716 2717 default: 2718 regval = bge_reg_get32(bgep, regno); 2719 regval &= ~STATE_MACHINE_ENABLE_BIT; 2720 regval &= ~morebits; 2721 bge_reg_put32(bgep, regno, regval); 2722 return (bge_chip_poll_engine(bgep, regno, 2723 STATE_MACHINE_ENABLE_BIT, 0)); 2724 } 2725 } 2726 2727 /* 2728 * Various registers that control the chip's internal engines (state 2729 * machines) have an <enable> bit (fortunately, in the same place in 2730 * each such register :-). To start the state machine, this bit must 2731 * be written with 1, then polled to see when the state machine has 2732 * actually started. 2733 * 2734 * The return value is B_TRUE on success (enable bit set), or 2735 * B_FALSE if the state machine didn't start :( 2736 */ 2737 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2738 uint32_t morebits); 2739 #pragma no_inline(bge_chip_enable_engine) 2740 2741 static boolean_t 2742 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2743 { 2744 uint32_t regval; 2745 2746 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2747 (void *)bgep, regno, morebits)); 2748 2749 switch (regno) { 2750 case FTQ_RESET_REG: 2751 #ifdef BGE_IPMI_ASF 2752 #ifdef BGE_NETCONSOLE 2753 if (bgep->asf_enabled) 2754 return (B_TRUE); 2755 #endif 2756 #endif 2757 /* 2758 * Not quite like the others; it doesn't 2759 * have an <enable> bit, but instead we 2760 * have to set and then clear all the bits 2761 */ 2762 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2763 drv_usecwait(100); 2764 bge_reg_put32(bgep, regno, 0); 2765 return (B_TRUE); 2766 2767 default: 2768 regval = bge_reg_get32(bgep, regno); 2769 regval |= STATE_MACHINE_ENABLE_BIT; 2770 regval |= morebits; 2771 bge_reg_put32(bgep, regno, regval); 2772 return (bge_chip_poll_engine(bgep, regno, 2773 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2774 } 2775 } 2776 2777 /* 2778 * Reprogram the Ethernet, Transmit, and Receive MAC 2779 * modes to match the param_* variables 2780 */ 2781 void bge_sync_mac_modes(bge_t *bgep); 2782 #pragma no_inline(bge_sync_mac_modes) 2783 2784 void 2785 bge_sync_mac_modes(bge_t *bgep) 2786 { 2787 uint32_t macmode; 2788 uint32_t regval; 2789 2790 ASSERT(mutex_owned(bgep->genlock)); 2791 2792 /* 2793 * Reprogram the Ethernet MAC mode ... 2794 */ 2795 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2796 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2797 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2798 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2799 macmode |= ETHERNET_MODE_LINK_POLARITY; 2800 else 2801 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2802 else 2803 macmode |= ETHERNET_MODE_LINK_POLARITY; 2804 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2805 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2806 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2807 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2808 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2809 else 2810 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2811 } else if (bgep->param_link_speed == 10 || 2812 bgep->param_link_speed == 100) 2813 macmode |= ETHERNET_MODE_PORTMODE_MII; 2814 else 2815 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2816 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2817 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2818 else 2819 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2820 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2821 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2822 else 2823 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2824 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2825 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2826 (void *)bgep, regval, macmode)); 2827 2828 /* 2829 * ... the Transmit MAC mode ... 2830 */ 2831 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2832 if (bgep->param_link_tx_pause) 2833 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2834 else 2835 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2836 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2837 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2838 (void *)bgep, regval, macmode)); 2839 2840 /* 2841 * ... and the Receive MAC mode 2842 */ 2843 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2844 if (bgep->param_link_rx_pause) 2845 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2846 else 2847 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2848 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2849 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2850 (void *)bgep, regval, macmode)); 2851 } 2852 2853 /* 2854 * bge_chip_sync() -- program the chip with the unicast MAC address, 2855 * the multicast hash table, the required level of promiscuity, and 2856 * the current loopback mode ... 2857 */ 2858 #ifdef BGE_IPMI_ASF 2859 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2860 #else 2861 int bge_chip_sync(bge_t *bgep); 2862 #endif 2863 #pragma no_inline(bge_chip_sync) 2864 2865 int 2866 #ifdef BGE_IPMI_ASF 2867 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2868 #else 2869 bge_chip_sync(bge_t *bgep) 2870 #endif 2871 { 2872 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2873 boolean_t promisc; 2874 uint64_t macaddr; 2875 uint32_t fill = 0; 2876 int i, j; 2877 int retval = DDI_SUCCESS; 2878 2879 BGE_TRACE(("bge_chip_sync($%p)", 2880 (void *)bgep)); 2881 2882 ASSERT(mutex_owned(bgep->genlock)); 2883 2884 promisc = B_FALSE; 2885 fill = ~(uint32_t)0; 2886 2887 if (bgep->promisc) 2888 promisc = B_TRUE; 2889 else 2890 fill = (uint32_t)0; 2891 2892 /* 2893 * If the TX/RX MAC engines are already running, we should stop 2894 * them (and reset the RX engine) before changing the parameters. 2895 * If they're not running, this will have no effect ... 2896 * 2897 * NOTE: this is currently disabled by default because stopping 2898 * and restarting the Tx engine may cause an outgoing packet in 2899 * transit to be truncated. Also, stopping and restarting the 2900 * Rx engine seems to not work correctly on the 5705. Testing 2901 * has not (yet!) revealed any problems with NOT stopping and 2902 * restarting these engines (and Broadcom say their drivers don't 2903 * do this), but if it is found to cause problems, this variable 2904 * can be patched to re-enable the old behaviour ... 2905 */ 2906 if (bge_stop_start_on_sync) { 2907 #ifdef BGE_IPMI_ASF 2908 if (!bgep->asf_enabled) { 2909 if (!bge_chip_disable_engine(bgep, 2910 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2911 retval = DDI_FAILURE; 2912 } else { 2913 if (!bge_chip_disable_engine(bgep, 2914 RECEIVE_MAC_MODE_REG, 0)) 2915 retval = DDI_FAILURE; 2916 } 2917 #else 2918 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2919 RECEIVE_MODE_KEEP_VLAN_TAG)) 2920 retval = DDI_FAILURE; 2921 #endif 2922 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2923 retval = DDI_FAILURE; 2924 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2925 retval = DDI_FAILURE; 2926 } 2927 2928 /* 2929 * Reprogram the hashed multicast address table ... 2930 */ 2931 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2932 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2933 2934 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2935 bge_reg_put32(bgep, MAC_HASH_REG(i), 2936 bgep->mcast_hash[i] | fill); 2937 2938 #ifdef BGE_IPMI_ASF 2939 if (!bgep->asf_enabled || !asf_keeplive) { 2940 #endif 2941 /* 2942 * Transform the MAC address(es) from host to chip format, then 2943 * reprogram the transmit random backoff seed and the unicast 2944 * MAC address(es) ... 2945 */ 2946 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2947 for (i = 0, macaddr = 0ull; 2948 i < ETHERADDRL; ++i) { 2949 macaddr <<= 8; 2950 macaddr |= bgep->curr_addr[j].addr[i]; 2951 } 2952 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 2953 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2954 2955 BGE_DEBUG(("bge_chip_sync($%p) " 2956 "setting MAC address %012llx", 2957 (void *)bgep, macaddr)); 2958 } 2959 #ifdef BGE_IPMI_ASF 2960 } 2961 #endif 2962 /* 2963 * Set random seed of backoff interval 2964 * - Writing zero means no backoff interval 2965 */ 2966 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 2967 if (fill == 0) 2968 fill = 1; 2969 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2970 2971 /* 2972 * Set or clear the PROMISCUOUS mode bit 2973 */ 2974 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2975 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2976 2977 /* 2978 * Sync the rest of the MAC modes too ... 2979 */ 2980 bge_sync_mac_modes(bgep); 2981 2982 /* 2983 * Restart RX/TX MAC engines if required ... 2984 */ 2985 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2986 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2987 retval = DDI_FAILURE; 2988 #ifdef BGE_IPMI_ASF 2989 if (!bgep->asf_enabled) { 2990 if (!bge_chip_enable_engine(bgep, 2991 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2992 retval = DDI_FAILURE; 2993 } else { 2994 if (!bge_chip_enable_engine(bgep, 2995 RECEIVE_MAC_MODE_REG, 0)) 2996 retval = DDI_FAILURE; 2997 } 2998 #else 2999 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3000 RECEIVE_MODE_KEEP_VLAN_TAG)) 3001 retval = DDI_FAILURE; 3002 #endif 3003 } 3004 return (retval); 3005 } 3006 3007 /* 3008 * This array defines the sequence of state machine control registers 3009 * in which the <enable> bit must be cleared to bring the chip to a 3010 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 3011 */ 3012 static bge_regno_t shutdown_engine_regs[] = { 3013 RECEIVE_MAC_MODE_REG, 3014 RCV_BD_INITIATOR_MODE_REG, 3015 RCV_LIST_PLACEMENT_MODE_REG, 3016 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 3017 RCV_DATA_BD_INITIATOR_MODE_REG, 3018 RCV_DATA_COMPLETION_MODE_REG, 3019 RCV_BD_COMPLETION_MODE_REG, 3020 3021 SEND_BD_SELECTOR_MODE_REG, 3022 SEND_BD_INITIATOR_MODE_REG, 3023 SEND_DATA_INITIATOR_MODE_REG, 3024 READ_DMA_MODE_REG, 3025 SEND_DATA_COMPLETION_MODE_REG, 3026 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 3027 SEND_BD_COMPLETION_MODE_REG, 3028 TRANSMIT_MAC_MODE_REG, 3029 3030 HOST_COALESCE_MODE_REG, 3031 WRITE_DMA_MODE_REG, 3032 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 3033 FTQ_RESET_REG, /* special - see code */ 3034 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 3035 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 3036 BGE_REGNO_NONE /* terminator */ 3037 }; 3038 3039 #ifndef __sparc 3040 static bge_regno_t quiesce_regs[] = { 3041 READ_DMA_MODE_REG, 3042 DMA_COMPLETION_MODE_REG, 3043 WRITE_DMA_MODE_REG, 3044 BGE_REGNO_NONE 3045 }; 3046 3047 void bge_chip_stop_nonblocking(bge_t *bgep); 3048 #pragma no_inline(bge_chip_stop_nonblocking) 3049 3050 /* 3051 * This function is called by bge_quiesce(). We 3052 * turn off all the DMA engines here. 3053 */ 3054 void 3055 bge_chip_stop_nonblocking(bge_t *bgep) 3056 { 3057 bge_regno_t *rbp; 3058 3059 /* 3060 * Flag that no more activity may be initiated 3061 */ 3062 bgep->progress &= ~PROGRESS_READY; 3063 3064 rbp = quiesce_regs; 3065 while (*rbp != BGE_REGNO_NONE) { 3066 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3067 ++rbp; 3068 } 3069 3070 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3071 } 3072 3073 #endif 3074 3075 /* 3076 * bge_chip_stop() -- stop all chip processing 3077 * 3078 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3079 * we've detected a problem internally; otherwise, this is a normal 3080 * (clean) stop (at user request i.e. the last STREAM has been closed). 3081 */ 3082 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3083 #pragma no_inline(bge_chip_stop) 3084 3085 void 3086 bge_chip_stop(bge_t *bgep, boolean_t fault) 3087 { 3088 bge_regno_t regno; 3089 bge_regno_t *rbp; 3090 boolean_t ok; 3091 3092 BGE_TRACE(("bge_chip_stop($%p)", 3093 (void *)bgep)); 3094 3095 ASSERT(mutex_owned(bgep->genlock)); 3096 3097 rbp = shutdown_engine_regs; 3098 /* 3099 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3100 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3101 * -ory arbiter should not be disabled. 3102 */ 3103 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3104 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3105 ok &= bge_chip_disable_engine(bgep, regno, 0); 3106 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3107 (regno != DMA_COMPLETION_MODE_REG) && 3108 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3109 (regno != BUFFER_MANAGER_MODE_REG) && 3110 (regno != MEMORY_ARBITER_MODE_REG)) 3111 ok &= bge_chip_disable_engine(bgep, 3112 regno, 0); 3113 } 3114 3115 if (!ok && !fault) 3116 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3117 3118 /* 3119 * Finally, disable (all) MAC events & clear the MAC status 3120 */ 3121 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3122 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3123 3124 /* 3125 * if we're stopping the chip because of a detected fault then do 3126 * appropriate actions 3127 */ 3128 if (fault) { 3129 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3130 bgep->bge_chip_state = BGE_CHIP_FAULT; 3131 if (!bgep->manual_reset) 3132 ddi_fm_service_impact(bgep->devinfo, 3133 DDI_SERVICE_LOST); 3134 if (bgep->bge_dma_error) { 3135 /* 3136 * need to free buffers in case the fault was 3137 * due to a memory error in a buffer - got to 3138 * do a fair bit of tidying first 3139 */ 3140 if (bgep->progress & PROGRESS_KSTATS) { 3141 bge_fini_kstats(bgep); 3142 bgep->progress &= ~PROGRESS_KSTATS; 3143 } 3144 if (bgep->progress & PROGRESS_INTR) { 3145 bge_intr_disable(bgep); 3146 rw_enter(bgep->errlock, RW_WRITER); 3147 bge_fini_rings(bgep); 3148 rw_exit(bgep->errlock); 3149 bgep->progress &= ~PROGRESS_INTR; 3150 } 3151 if (bgep->progress & PROGRESS_BUFS) { 3152 bge_free_bufs(bgep); 3153 bgep->progress &= ~PROGRESS_BUFS; 3154 } 3155 bgep->bge_dma_error = B_FALSE; 3156 } 3157 } 3158 } else 3159 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3160 } 3161 3162 /* 3163 * Poll for completion of chip's ROM firmware; also, at least on the 3164 * first time through, find and return the hardware MAC address, if any. 3165 */ 3166 static uint64_t bge_poll_firmware(bge_t *bgep); 3167 #pragma no_inline(bge_poll_firmware) 3168 3169 static uint64_t 3170 bge_poll_firmware(bge_t *bgep) 3171 { 3172 uint64_t magic; 3173 uint64_t mac; 3174 uint32_t gen, val; 3175 uint32_t i; 3176 3177 /* 3178 * Step 19: poll for firmware completion (GENCOMM port set 3179 * to the ones complement of T3_MAGIC_NUMBER). 3180 * 3181 * While we're at it, we also read the MAC address register; 3182 * at some stage the firmware will load this with the 3183 * factory-set value. 3184 * 3185 * When both the magic number and the MAC address are set, 3186 * we're done; but we impose a time limit of one second 3187 * (1000*1000us) in case the firmware fails in some fashion 3188 * or the SEEPROM that provides that MAC address isn't fitted. 3189 * 3190 * After the first time through (chip state != INITIAL), we 3191 * don't need the MAC address to be set (we've already got it 3192 * or not, from the first time), so we don't wait for it, but 3193 * we still have to wait for the T3_MAGIC_NUMBER. 3194 * 3195 * Note: the magic number is only a 32-bit quantity, but the NIC 3196 * memory is 64-bit (and big-endian) internally. Addressing the 3197 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3198 * it work correctly on both big- and little-endian hosts. 3199 */ 3200 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3201 MHCR_CHIP_ASIC_REV_5906) { 3202 for (i = 0; i < 1000; ++i) { 3203 drv_usecwait(1000); 3204 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3205 if (val & VCPU_INIT_DONE) 3206 break; 3207 } 3208 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3209 (void *)bgep, i)); 3210 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3211 } else { 3212 for (i = 0; i < 1000; ++i) { 3213 drv_usecwait(1000); 3214 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3215 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3216 drv_usecwait(100000); 3217 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3218 #ifdef BGE_IPMI_ASF 3219 if (!bgep->asf_enabled) { 3220 #endif 3221 if (gen != ~T3_MAGIC_NUMBER) 3222 continue; 3223 #ifdef BGE_IPMI_ASF 3224 } 3225 #endif 3226 if (mac != 0ULL) 3227 break; 3228 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3229 break; 3230 } 3231 } 3232 3233 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3234 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3235 (void *)bgep, gen, i)); 3236 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3237 mac, magic)); 3238 3239 return (mac); 3240 } 3241 3242 /* 3243 * Maximum times of trying to get the NVRAM access lock 3244 * by calling bge_nvmem_acquire() 3245 */ 3246 #define MAX_TRY_NVMEM_ACQUIRE 10000 3247 3248 #ifdef BGE_IPMI_ASF 3249 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3250 #else 3251 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3252 #endif 3253 #pragma no_inline(bge_chip_reset) 3254 3255 int 3256 #ifdef BGE_IPMI_ASF 3257 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3258 #else 3259 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3260 #endif 3261 { 3262 chip_id_t chipid; 3263 uint64_t mac; 3264 uint64_t magic; 3265 uint32_t modeflags; 3266 uint32_t mhcr; 3267 uint32_t sx0; 3268 uint32_t i, tries; 3269 #ifdef BGE_IPMI_ASF 3270 uint32_t mailbox; 3271 #endif 3272 int retval = DDI_SUCCESS; 3273 3274 BGE_TRACE(("bge_chip_reset($%p, %d)", 3275 (void *)bgep, enable_dma)); 3276 3277 ASSERT(mutex_owned(bgep->genlock)); 3278 3279 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3280 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3281 3282 /* 3283 * Do we need to stop the chip cleanly before resetting? 3284 */ 3285 switch (bgep->bge_chip_state) { 3286 default: 3287 _NOTE(NOTREACHED) 3288 return (DDI_FAILURE); 3289 3290 case BGE_CHIP_INITIAL: 3291 case BGE_CHIP_STOPPED: 3292 case BGE_CHIP_RESET: 3293 break; 3294 3295 case BGE_CHIP_RUNNING: 3296 case BGE_CHIP_ERROR: 3297 case BGE_CHIP_FAULT: 3298 bge_chip_stop(bgep, B_FALSE); 3299 break; 3300 } 3301 3302 #ifdef BGE_IPMI_ASF 3303 if (bgep->asf_enabled) { 3304 #ifdef __sparc 3305 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3306 MHCR_ENABLE_TAGGED_STATUS_MODE | 3307 MHCR_MASK_INTERRUPT_MODE | 3308 MHCR_MASK_PCI_INT_OUTPUT | 3309 MHCR_CLEAR_INTERRUPT_INTA | 3310 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3311 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3312 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3313 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3314 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3315 MEMORY_ARBITER_ENABLE); 3316 #endif 3317 if (asf_mode == ASF_MODE_INIT) { 3318 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3319 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3320 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3321 } 3322 } 3323 #endif 3324 /* 3325 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3326 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3327 * 3328 * Before reset Core clock,it is 3329 * also required to initialize the Memory Arbiter as specified in step9 3330 * and Misc Host Control Register as specified in step-13 3331 * Step 4-5: reset Core clock & wait for completion 3332 * Steps 6-8: are done by bge_chip_cfg_init() 3333 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3334 */ 3335 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3336 retval = DDI_FAILURE; 3337 3338 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3339 MHCR_ENABLE_TAGGED_STATUS_MODE | 3340 MHCR_MASK_INTERRUPT_MODE | 3341 MHCR_MASK_PCI_INT_OUTPUT | 3342 MHCR_CLEAR_INTERRUPT_INTA; 3343 #ifdef _BIG_ENDIAN 3344 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3345 #endif /* _BIG_ENDIAN */ 3346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3347 #ifdef BGE_IPMI_ASF 3348 if (bgep->asf_enabled) 3349 bgep->asf_wordswapped = B_FALSE; 3350 #endif 3351 /* 3352 * NVRAM Corruption Workaround 3353 */ 3354 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3355 if (bge_nvmem_acquire(bgep) != EAGAIN) 3356 break; 3357 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3358 BGE_DEBUG(("%s: fail to acquire nvram lock", 3359 bgep->ifname)); 3360 3361 #ifdef BGE_IPMI_ASF 3362 if (!bgep->asf_enabled) { 3363 #endif 3364 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3365 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3366 #ifdef BGE_IPMI_ASF 3367 } 3368 #endif 3369 3370 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3371 retval = DDI_FAILURE; 3372 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3373 3374 /* 3375 * Step 8a: This may belong elsewhere, but BCM5721 needs 3376 * a bit set to avoid a fifo overflow/underflow bug. 3377 */ 3378 if ((bgep->chipid.chip_label == 5721) || 3379 (bgep->chipid.chip_label == 5751) || 3380 (bgep->chipid.chip_label == 5752) || 3381 (bgep->chipid.chip_label == 5755) || 3382 (bgep->chipid.chip_label == 5756) || 3383 (bgep->chipid.chip_label == 5789) || 3384 (bgep->chipid.chip_label == 5906)) 3385 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3386 3387 3388 /* 3389 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3390 * not be changed. 3391 */ 3392 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3393 retval = DDI_FAILURE; 3394 3395 /* 3396 * Steps 10-11: configure PIO endianness options and 3397 * enable indirect register access -- already done 3398 * Steps 12-13: enable writing to the PCI state & clock 3399 * control registers -- not required; we aren't going to 3400 * use those features. 3401 * Steps 14-15: Configure DMA endianness options. See 3402 * the comments on the setting of the MHCR above. 3403 */ 3404 #ifdef _BIG_ENDIAN 3405 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3406 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3407 #else 3408 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3409 #endif /* _BIG_ENDIAN */ 3410 #ifdef BGE_IPMI_ASF 3411 if (bgep->asf_enabled) 3412 modeflags |= MODE_HOST_STACK_UP; 3413 #endif 3414 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3415 3416 #ifdef BGE_IPMI_ASF 3417 if (bgep->asf_enabled) { 3418 #ifdef __sparc 3419 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3420 MEMORY_ARBITER_ENABLE | 3421 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3422 #endif 3423 3424 #ifdef BGE_NETCONSOLE 3425 if (!bgep->asf_newhandshake) { 3426 if ((asf_mode == ASF_MODE_INIT) || 3427 (asf_mode == ASF_MODE_POST_INIT)) { 3428 bge_asf_post_reset_old_mode(bgep, 3429 BGE_INIT_RESET); 3430 } else { 3431 bge_asf_post_reset_old_mode(bgep, 3432 BGE_SHUTDOWN_RESET); 3433 } 3434 } 3435 #endif 3436 3437 /* Wait for NVRAM init */ 3438 i = 0; 3439 drv_usecwait(5000); 3440 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3441 3442 while ((mailbox != (uint32_t) 3443 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3444 (i < 10000)) { 3445 drv_usecwait(100); 3446 mailbox = bge_nic_get32(bgep, 3447 BGE_FIRMWARE_MAILBOX); 3448 i++; 3449 } 3450 3451 #ifndef BGE_NETCONSOLE 3452 if (!bgep->asf_newhandshake) { 3453 if ((asf_mode == ASF_MODE_INIT) || 3454 (asf_mode == ASF_MODE_POST_INIT)) { 3455 3456 bge_asf_post_reset_old_mode(bgep, 3457 BGE_INIT_RESET); 3458 } else { 3459 bge_asf_post_reset_old_mode(bgep, 3460 BGE_SHUTDOWN_RESET); 3461 } 3462 } 3463 #endif 3464 } 3465 #endif 3466 /* 3467 * Steps 16-17: poll for firmware completion 3468 */ 3469 mac = bge_poll_firmware(bgep); 3470 3471 /* 3472 * Step 18: enable external memory -- doesn't apply. 3473 * 3474 * However we take the opportunity to set the MLCR anyway, as 3475 * this register also controls the SEEPROM auto-access method 3476 * which we may want to use later ... 3477 * 3478 * The proper value here depends on the way the chip is wired 3479 * into the circuit board, as this register *also* controls which 3480 * of the "Miscellaneous I/O" pins are driven as outputs and the 3481 * values driven onto those pins! 3482 * 3483 * See also step 74 in the PRM ... 3484 */ 3485 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3486 bgep->chipid.bge_mlcr_default); 3487 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3488 3489 /* 3490 * Step 20: clear the Ethernet MAC mode register 3491 */ 3492 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3493 3494 /* 3495 * Step 21: restore cache-line-size, latency timer, and 3496 * subsystem ID registers to their original values (not 3497 * those read into the local structure <chipid>, 'cos 3498 * that was after they were cleared by the RESET). 3499 * 3500 * Note: the Subsystem Vendor/Device ID registers are not 3501 * directly writable in config space, so we use the shadow 3502 * copy in "Page Zero" of register space to restore them 3503 * both in one go ... 3504 */ 3505 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3506 bgep->chipid.clsize); 3507 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3508 bgep->chipid.latency); 3509 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3510 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3511 3512 /* 3513 * The SEND INDEX registers should be reset to zero by the 3514 * global chip reset; if they're not, there'll be trouble 3515 * later on. 3516 */ 3517 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3518 if (sx0 != 0) { 3519 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3520 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3521 retval = DDI_FAILURE; 3522 } 3523 3524 /* Enable MSI code */ 3525 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3526 bge_reg_set32(bgep, MSI_MODE_REG, 3527 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3528 3529 /* 3530 * On the first time through, save the factory-set MAC address 3531 * (if any). If bge_poll_firmware() above didn't return one 3532 * (from a chip register) consider looking in the attached NV 3533 * memory device, if any. Once we have it, we save it in both 3534 * register-image (64-bit) and byte-array forms. All-zero and 3535 * all-one addresses are not valid, and we refuse to stash those. 3536 */ 3537 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3538 if (mac == 0ULL) 3539 mac = bge_get_nvmac(bgep); 3540 if (mac != 0ULL && mac != ~0ULL) { 3541 bgep->chipid.hw_mac_addr = mac; 3542 for (i = ETHERADDRL; i-- != 0; ) { 3543 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3544 mac >>= 8; 3545 } 3546 bgep->chipid.vendor_addr.set = B_TRUE; 3547 } 3548 } 3549 3550 #ifdef BGE_IPMI_ASF 3551 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3552 if (asf_mode != ASF_MODE_NONE) { 3553 if ((asf_mode == ASF_MODE_INIT) || 3554 (asf_mode == ASF_MODE_POST_INIT)) { 3555 3556 bge_asf_post_reset_new_mode(bgep, 3557 BGE_INIT_RESET); 3558 } else { 3559 bge_asf_post_reset_new_mode(bgep, 3560 BGE_SHUTDOWN_RESET); 3561 } 3562 } 3563 } 3564 #endif 3565 3566 /* 3567 * Record the new state 3568 */ 3569 bgep->chip_resets += 1; 3570 bgep->bge_chip_state = BGE_CHIP_RESET; 3571 return (retval); 3572 } 3573 3574 /* 3575 * bge_chip_start() -- start the chip transmitting and/or receiving, 3576 * including enabling interrupts 3577 */ 3578 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3579 #pragma no_inline(bge_chip_start) 3580 3581 void 3582 bge_chip_coalesce_update(bge_t *bgep) 3583 { 3584 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, 3585 bgep->chipid.tx_count_norm); 3586 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, 3587 bgep->chipid.tx_ticks_norm); 3588 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, 3589 bgep->chipid.rx_count_norm); 3590 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, 3591 bgep->chipid.rx_ticks_norm); 3592 } 3593 3594 int 3595 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3596 { 3597 uint32_t coalmode; 3598 uint32_t ledctl; 3599 uint32_t mtu; 3600 uint32_t maxring; 3601 uint32_t stats_mask; 3602 uint32_t dma_wrprio; 3603 uint64_t ring; 3604 int retval = DDI_SUCCESS; 3605 3606 BGE_TRACE(("bge_chip_start($%p)", 3607 (void *)bgep)); 3608 3609 ASSERT(mutex_owned(bgep->genlock)); 3610 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3611 3612 /* 3613 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3614 * The document specifies 95 separate steps to fully 3615 * initialise the chip!!!! 3616 * 3617 * The reset code above has already got us as far as step 3618 * 21, so we continue with ... 3619 * 3620 * Step 22: clear the MAC statistics block 3621 * (0x0300-0x0aff in NIC-local memory) 3622 */ 3623 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3624 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3625 NIC_MEM_STATISTICS_SIZE); 3626 3627 /* 3628 * Step 23: clear the status block (in host memory) 3629 */ 3630 DMA_ZERO(bgep->status_block); 3631 3632 /* 3633 * Step 24: set DMA read/write control register 3634 */ 3635 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3636 bgep->chipid.bge_dma_rwctrl); 3637 3638 /* 3639 * Step 25: Configure DMA endianness -- already done (16/17) 3640 * Step 26: Configure Host-Based Send Rings 3641 * Step 27: Indicate Host Stack Up 3642 */ 3643 bge_reg_set32(bgep, MODE_CONTROL_REG, 3644 MODE_HOST_SEND_BDS | 3645 MODE_HOST_STACK_UP); 3646 3647 /* 3648 * Step 28: Configure checksum options: 3649 * Solaris supports the hardware default checksum options. 3650 * 3651 * Workaround for Incorrect pseudo-header checksum calculation. 3652 */ 3653 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3654 bge_reg_set32(bgep, MODE_CONTROL_REG, 3655 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3656 3657 /* 3658 * Step 29: configure Timer Prescaler. The value is always the 3659 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3660 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3661 * for the whole chip! 3662 */ 3663 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3664 3665 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3666 drv_usecwait(40); 3667 /* put PHY into ready state */ 3668 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3669 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3670 drv_usecwait(40); 3671 } 3672 3673 /* 3674 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3675 * 3676 * If the mbuf_length is specified as 0, we just leave these at 3677 * their hardware defaults, rather than explicitly setting them. 3678 * As the Broadcom HRM,driver better not change the parameters 3679 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3680 */ 3681 if ((bgep->chipid.mbuf_length != 0) && 3682 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3683 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3684 bgep->chipid.mbuf_base); 3685 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3686 bgep->chipid.mbuf_length); 3687 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3688 DMAD_POOL_BASE_DEFAULT); 3689 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3690 DMAD_POOL_LENGTH_DEFAULT); 3691 } 3692 3693 /* 3694 * Step 32: configure MAC memory pool watermarks 3695 */ 3696 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3697 bgep->chipid.mbuf_lo_water_rdma); 3698 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3699 bgep->chipid.mbuf_lo_water_rmac); 3700 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3701 bgep->chipid.mbuf_hi_water); 3702 3703 /* 3704 * Step 33: configure DMA resource watermarks 3705 */ 3706 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3707 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3708 bge_dmad_lo_water); 3709 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3710 bge_dmad_hi_water); 3711 } 3712 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3713 3714 /* 3715 * Steps 34-36: enable buffer manager & internal h/w queues 3716 */ 3717 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3718 STATE_MACHINE_ATTN_ENABLE_BIT)) 3719 retval = DDI_FAILURE; 3720 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3721 retval = DDI_FAILURE; 3722 3723 /* 3724 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3725 */ 3726 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3727 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3728 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3729 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3730 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3731 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3732 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3733 } 3734 3735 /* 3736 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3737 */ 3738 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3739 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3740 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3741 bge_replenish_jumbo); 3742 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3743 bge_replenish_mini); 3744 } 3745 3746 /* 3747 * Steps 41-43: clear Send Ring Producer Indices and initialise 3748 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3749 */ 3750 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3751 maxring = BGE_SEND_RINGS_MAX; 3752 else 3753 maxring = BGE_SEND_RINGS_MAX_5705; 3754 for (ring = 0; ring < maxring; ++ring) { 3755 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3756 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3757 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3758 &bgep->send[ring].hw_rcb); 3759 } 3760 3761 /* 3762 * Steps 44-45: initialise Receive Return Rings 3763 * (0x0200-0x02ff in NIC-local memory) 3764 */ 3765 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3766 maxring = BGE_RECV_RINGS_MAX; 3767 else 3768 maxring = BGE_RECV_RINGS_MAX_5705; 3769 for (ring = 0; ring < maxring; ++ring) 3770 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3771 &bgep->recv[ring].hw_rcb); 3772 3773 /* 3774 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3775 */ 3776 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3777 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3778 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3779 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3780 } 3781 /* 3782 * Step 47: configure the MAC unicast address 3783 * Step 48: configure the random backoff seed 3784 * Step 96: set up multicast filters 3785 */ 3786 #ifdef BGE_IPMI_ASF 3787 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3788 #else 3789 if (bge_chip_sync(bgep) == DDI_FAILURE) 3790 #endif 3791 retval = DDI_FAILURE; 3792 3793 /* 3794 * Step 49: configure the MTU 3795 */ 3796 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3797 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3798 3799 /* 3800 * Step 50: configure the IPG et al 3801 */ 3802 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3803 3804 /* 3805 * Step 51: configure the default Rx Return Ring 3806 */ 3807 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3808 3809 /* 3810 * Steps 52-54: configure Receive List Placement, 3811 * and enable Receive List Placement Statistics 3812 */ 3813 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3814 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3815 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3816 case MHCR_CHIP_ASIC_REV_5700: 3817 case MHCR_CHIP_ASIC_REV_5701: 3818 case MHCR_CHIP_ASIC_REV_5703: 3819 case MHCR_CHIP_ASIC_REV_5704: 3820 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3821 break; 3822 case MHCR_CHIP_ASIC_REV_5705: 3823 break; 3824 default: 3825 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3826 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3827 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3828 break; 3829 } 3830 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3831 3832 if (bgep->chipid.rx_rings > 1) 3833 bge_init_recv_rule(bgep); 3834 3835 /* 3836 * Steps 55-56: enable Send Data Initiator Statistics 3837 */ 3838 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3839 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3840 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3841 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3842 } else { 3843 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3844 SEND_INIT_STATS_ENABLE); 3845 } 3846 /* 3847 * Steps 57-58: stop (?) the Host Coalescing Engine 3848 */ 3849 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3850 retval = DDI_FAILURE; 3851 3852 /* 3853 * Steps 59-62: initialise Host Coalescing parameters 3854 */ 3855 bge_chip_coalesce_update(bgep); 3856 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3857 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3858 bge_tx_count_intr); 3859 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3860 bge_tx_ticks_intr); 3861 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3862 bge_rx_count_intr); 3863 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3864 bge_rx_ticks_intr); 3865 } 3866 3867 /* 3868 * Steps 63-64: initialise status block & statistics 3869 * host memory addresses 3870 * The statistic block does not exist in some chipsets 3871 * Step 65: initialise Statistics Coalescing Tick Counter 3872 */ 3873 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3874 bgep->status_block.cookie.dmac_laddress); 3875 3876 /* 3877 * Steps 66-67: initialise status block & statistics 3878 * NIC-local memory addresses 3879 */ 3880 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3881 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3882 bgep->statistics.cookie.dmac_laddress); 3883 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3884 STATISTICS_TICKS_DEFAULT); 3885 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3886 NIC_MEM_STATUS_BLOCK); 3887 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3888 NIC_MEM_STATISTICS); 3889 } 3890 3891 /* 3892 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3893 * Completion Engine, the Receive List Placement Engine, and the 3894 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3895 * and BCM5715. 3896 */ 3897 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3898 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3899 coalmode = COALESCE_64_BYTE_STATUS; 3900 else 3901 coalmode = 0; 3902 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3903 retval = DDI_FAILURE; 3904 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3905 STATE_MACHINE_ATTN_ENABLE_BIT)) 3906 retval = DDI_FAILURE; 3907 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3908 retval = DDI_FAILURE; 3909 3910 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3911 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3912 STATE_MACHINE_ATTN_ENABLE_BIT)) 3913 retval = DDI_FAILURE; 3914 3915 /* 3916 * Step 72: Enable MAC DMA engines 3917 * Step 73: Clear & enable MAC statistics 3918 */ 3919 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3920 ETHERNET_MODE_ENABLE_FHDE | 3921 ETHERNET_MODE_ENABLE_RDE | 3922 ETHERNET_MODE_ENABLE_TDE); 3923 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3924 ETHERNET_MODE_ENABLE_TX_STATS | 3925 ETHERNET_MODE_ENABLE_RX_STATS | 3926 ETHERNET_MODE_CLEAR_TX_STATS | 3927 ETHERNET_MODE_CLEAR_RX_STATS); 3928 3929 /* 3930 * Step 74: configure the MLCR (Miscellaneous Local Control 3931 * Register); not required, as we set up the MLCR in step 10 3932 * (part of the reset code) above. 3933 * 3934 * Step 75: clear Interrupt Mailbox 0 3935 */ 3936 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3937 3938 /* 3939 * Steps 76-87: Gentlemen, start your engines ... 3940 * 3941 * Enable the DMA Completion Engine, the Write DMA Engine, 3942 * the Read DMA Engine, Receive Data Completion Engine, 3943 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3944 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3945 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3946 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3947 * 3948 * Beware exhaust fumes? 3949 */ 3950 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3951 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3952 retval = DDI_FAILURE; 3953 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3954 ALL_DMA_ATTN_BITS; 3955 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3956 MHCR_CHIP_ASIC_REV_5755) || 3957 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3958 MHCR_CHIP_ASIC_REV_5906)) { 3959 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3960 } 3961 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3962 dma_wrprio)) 3963 retval = DDI_FAILURE; 3964 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3965 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3966 retval = DDI_FAILURE; 3967 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3968 STATE_MACHINE_ATTN_ENABLE_BIT)) 3969 retval = DDI_FAILURE; 3970 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3971 if (!bge_chip_enable_engine(bgep, 3972 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3973 retval = DDI_FAILURE; 3974 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3975 retval = DDI_FAILURE; 3976 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3977 STATE_MACHINE_ATTN_ENABLE_BIT)) 3978 retval = DDI_FAILURE; 3979 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3980 RCV_BD_DISABLED_RING_ATTN)) 3981 retval = DDI_FAILURE; 3982 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3983 RCV_DATA_BD_ILL_RING_ATTN)) 3984 retval = DDI_FAILURE; 3985 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3986 retval = DDI_FAILURE; 3987 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3988 STATE_MACHINE_ATTN_ENABLE_BIT)) 3989 retval = DDI_FAILURE; 3990 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3991 STATE_MACHINE_ATTN_ENABLE_BIT)) 3992 retval = DDI_FAILURE; 3993 3994 /* 3995 * Step 88: download firmware -- doesn't apply 3996 * Steps 89-90: enable Transmit & Receive MAC Engines 3997 */ 3998 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3999 retval = DDI_FAILURE; 4000 #ifdef BGE_IPMI_ASF 4001 if (!bgep->asf_enabled) { 4002 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4003 RECEIVE_MODE_KEEP_VLAN_TAG)) 4004 retval = DDI_FAILURE; 4005 } else { 4006 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 4007 retval = DDI_FAILURE; 4008 } 4009 #else 4010 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4011 RECEIVE_MODE_KEEP_VLAN_TAG)) 4012 retval = DDI_FAILURE; 4013 #endif 4014 4015 /* 4016 * Step 91: disable auto-polling of PHY status 4017 */ 4018 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 4019 4020 /* 4021 * Step 92: configure D0 power state (not required) 4022 * Step 93: initialise LED control register () 4023 */ 4024 ledctl = LED_CONTROL_DEFAULT; 4025 switch (bgep->chipid.device) { 4026 case DEVICE_ID_5700: 4027 case DEVICE_ID_5700x: 4028 case DEVICE_ID_5701: 4029 /* 4030 * Switch to 5700 (MAC) mode on these older chips 4031 */ 4032 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4033 ledctl |= LED_CONTROL_LED_MODE_5700; 4034 break; 4035 4036 default: 4037 break; 4038 } 4039 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4040 4041 /* 4042 * Step 94: activate link 4043 */ 4044 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4045 4046 /* 4047 * Step 95: set up physical layer (PHY/SerDes) 4048 * restart autoneg (if required) 4049 */ 4050 if (reset_phys) 4051 if (bge_phys_update(bgep) == DDI_FAILURE) 4052 retval = DDI_FAILURE; 4053 4054 /* 4055 * Extra step (DSG): hand over all the Receive Buffers to the chip 4056 */ 4057 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4058 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4059 bgep->buff[ring].rf_next); 4060 4061 /* 4062 * MSI bits:The least significant MSI 16-bit word. 4063 * ISR will be triggered different. 4064 */ 4065 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4066 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4067 4068 /* 4069 * Extra step (DSG): select which interrupts are enabled 4070 * 4071 * Program the Ethernet MAC engine to signal attention on 4072 * Link Change events, then enable interrupts on MAC, DMA, 4073 * and FLOW attention signals. 4074 */ 4075 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4076 ETHERNET_EVENT_LINK_INT | 4077 ETHERNET_STATUS_PCS_ERROR_INT); 4078 #ifdef BGE_IPMI_ASF 4079 if (bgep->asf_enabled) { 4080 bge_reg_set32(bgep, MODE_CONTROL_REG, 4081 MODE_INT_ON_FLOW_ATTN | 4082 MODE_INT_ON_DMA_ATTN | 4083 MODE_HOST_STACK_UP| 4084 MODE_INT_ON_MAC_ATTN); 4085 } else { 4086 #endif 4087 bge_reg_set32(bgep, MODE_CONTROL_REG, 4088 MODE_INT_ON_FLOW_ATTN | 4089 MODE_INT_ON_DMA_ATTN | 4090 MODE_INT_ON_MAC_ATTN); 4091 #ifdef BGE_IPMI_ASF 4092 } 4093 #endif 4094 4095 /* 4096 * Step 97: enable PCI interrupts!!! 4097 */ 4098 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4099 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4100 MHCR_MASK_PCI_INT_OUTPUT); 4101 4102 /* 4103 * All done! 4104 */ 4105 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4106 return (retval); 4107 } 4108 4109 4110 /* 4111 * ========== Hardware interrupt handler ========== 4112 */ 4113 4114 #undef BGE_DBG 4115 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4116 4117 /* 4118 * Sync the status block, then atomically clear the specified bits in 4119 * the <flags-and-tag> field of the status block. 4120 * the <flags> word of the status block, returning the value of the 4121 * <tag> and the <flags> before the bits were cleared. 4122 */ 4123 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4124 #pragma inline(bge_status_sync) 4125 4126 static int 4127 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4128 { 4129 bge_status_t *bsp; 4130 int retval; 4131 4132 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4133 (void *)bgep, bits)); 4134 4135 ASSERT(bgep->bge_guard == BGE_GUARD); 4136 4137 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4138 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4139 if (retval != DDI_FM_OK) 4140 return (retval); 4141 4142 bsp = DMA_VPTR(bgep->status_block); 4143 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4144 4145 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4146 (void *)bgep, bits, *flags)); 4147 4148 return (retval); 4149 } 4150 4151 void bge_wake_factotum(bge_t *bgep); 4152 #pragma inline(bge_wake_factotum) 4153 4154 void 4155 bge_wake_factotum(bge_t *bgep) 4156 { 4157 mutex_enter(bgep->softintrlock); 4158 if (bgep->factotum_flag == 0) { 4159 bgep->factotum_flag = 1; 4160 ddi_trigger_softintr(bgep->factotum_id); 4161 } 4162 mutex_exit(bgep->softintrlock); 4163 } 4164 4165 /* 4166 * bge_intr() -- handle chip interrupts 4167 */ 4168 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4169 #pragma no_inline(bge_intr) 4170 4171 uint_t 4172 bge_intr(caddr_t arg1, caddr_t arg2) 4173 { 4174 bge_t *bgep = (void *)arg1; /* private device info */ 4175 bge_status_t *bsp; 4176 uint64_t flags; 4177 uint32_t regval; 4178 uint_t result; 4179 int retval, loop_cnt = 0; 4180 4181 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4182 4183 /* 4184 * GLD v2 checks that s/w setup is complete before passing 4185 * interrupts to this routine, thus eliminating the old 4186 * (and well-known) race condition around ddi_add_intr() 4187 */ 4188 ASSERT(bgep->progress & PROGRESS_HWINT); 4189 4190 result = DDI_INTR_UNCLAIMED; 4191 mutex_enter(bgep->genlock); 4192 4193 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4194 /* 4195 * Check whether chip's says it's asserting #INTA; 4196 * if not, don't process or claim the interrupt. 4197 * 4198 * Note that the PCI signal is active low, so the 4199 * bit is *zero* when the interrupt is asserted. 4200 */ 4201 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4202 if (regval & MLCR_INTA_STATE) { 4203 if (bge_check_acc_handle(bgep, bgep->io_handle) 4204 != DDI_FM_OK) 4205 goto chip_stop; 4206 mutex_exit(bgep->genlock); 4207 return (result); 4208 } 4209 4210 /* 4211 * Block further PCI interrupts ... 4212 */ 4213 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4214 MHCR_MASK_PCI_INT_OUTPUT); 4215 4216 } else { 4217 /* 4218 * Check MSI status 4219 */ 4220 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4221 if (regval & MSI_ERROR_ATTENTION) { 4222 BGE_REPORT((bgep, "msi error attention," 4223 " status=0x%x", regval)); 4224 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4225 } 4226 } 4227 4228 result = DDI_INTR_CLAIMED; 4229 4230 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4231 4232 /* 4233 * Sync the status block and grab the flags-n-tag from it. 4234 * We count the number of interrupts where there doesn't 4235 * seem to have been a DMA update of the status block; if 4236 * it *has* been updated, the counter will be cleared in 4237 * the while() loop below ... 4238 */ 4239 bgep->missed_dmas += 1; 4240 bsp = DMA_VPTR(bgep->status_block); 4241 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4242 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4243 /* 4244 * bge_chip_stop() may have freed dma area etc 4245 * while we were in this interrupt handler - 4246 * better not call bge_status_sync() 4247 */ 4248 (void) bge_check_acc_handle(bgep, 4249 bgep->io_handle); 4250 mutex_exit(bgep->genlock); 4251 return (DDI_INTR_CLAIMED); 4252 } 4253 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4254 &flags); 4255 if (retval != DDI_FM_OK) { 4256 bgep->bge_dma_error = B_TRUE; 4257 goto chip_stop; 4258 } 4259 4260 if (!(flags & STATUS_FLAG_UPDATED)) 4261 break; 4262 4263 /* 4264 * Tell the chip that we're processing the interrupt 4265 */ 4266 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4267 INTERRUPT_MBOX_DISABLE(flags)); 4268 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4269 DDI_FM_OK) 4270 goto chip_stop; 4271 4272 /* 4273 * Drop the mutex while we: 4274 * Receive any newly-arrived packets 4275 * Recycle any newly-finished send buffers 4276 */ 4277 bgep->bge_intr_running = B_TRUE; 4278 mutex_exit(bgep->genlock); 4279 bge_receive(bgep, bsp); 4280 bge_recycle(bgep, bsp); 4281 mutex_enter(bgep->genlock); 4282 bgep->bge_intr_running = B_FALSE; 4283 4284 /* 4285 * Tell the chip we've finished processing, and 4286 * give it the tag that we got from the status 4287 * block earlier, so that it knows just how far 4288 * we've gone. If it's got more for us to do, 4289 * it will now update the status block and try 4290 * to assert an interrupt (but we've got the 4291 * #INTA blocked at present). If we see the 4292 * update, we'll loop around to do some more. 4293 * Eventually we'll get out of here ... 4294 */ 4295 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4296 INTERRUPT_MBOX_ENABLE(flags)); 4297 if (bgep->chipid.pci_type == BGE_PCI_E) 4298 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4299 bgep->missed_dmas = 0; 4300 } 4301 4302 /* 4303 * Check for exceptional conditions that we need to handle 4304 * 4305 * Link status changed 4306 * Status block not updated 4307 */ 4308 if (flags & STATUS_FLAG_LINK_CHANGED) 4309 bge_wake_factotum(bgep); 4310 4311 if (bgep->missed_dmas) { 4312 /* 4313 * Probably due to the internal status tag not 4314 * being reset. Force a status block update now; 4315 * this should ensure that we get an update and 4316 * a new interrupt. After that, we should be in 4317 * sync again ... 4318 */ 4319 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4320 "not updated?", flags)); 4321 bgep->missed_updates++; 4322 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4323 COALESCE_NOW); 4324 4325 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4326 /* 4327 * If this happens multiple times in a row, 4328 * it means DMA is just not working. Maybe 4329 * the chip's failed, or maybe there's a 4330 * problem on the PCI bus or in the host-PCI 4331 * bridge (Tomatillo). 4332 * 4333 * At all events, we want to stop further 4334 * interrupts and let the recovery code take 4335 * over to see whether anything can be done 4336 * about it ... 4337 */ 4338 bge_fm_ereport(bgep, 4339 DDI_FM_DEVICE_BADINT_LIMIT); 4340 goto chip_stop; 4341 } 4342 } 4343 4344 /* 4345 * Reenable assertion of #INTA, unless there's a DMA fault 4346 */ 4347 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4348 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4349 MHCR_MASK_PCI_INT_OUTPUT); 4350 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4351 DDI_FM_OK) 4352 goto chip_stop; 4353 } 4354 4355 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4356 goto chip_stop; 4357 4358 mutex_exit(bgep->genlock); 4359 return (result); 4360 4361 chip_stop: 4362 #ifdef BGE_IPMI_ASF 4363 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4364 /* 4365 * We must stop ASF heart beat before 4366 * bge_chip_stop(), otherwise some 4367 * computers (ex. IBM HS20 blade 4368 * server) may crash. 4369 */ 4370 bge_asf_update_status(bgep); 4371 bge_asf_stop_timer(bgep); 4372 bgep->asf_status = ASF_STAT_STOP; 4373 4374 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4375 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4376 } 4377 #endif 4378 bge_chip_stop(bgep, B_TRUE); 4379 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4380 mutex_exit(bgep->genlock); 4381 return (result); 4382 } 4383 4384 /* 4385 * ========== Factotum, implemented as a softint handler ========== 4386 */ 4387 4388 #undef BGE_DBG 4389 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4390 4391 static void bge_factotum_error_handler(bge_t *bgep); 4392 #pragma no_inline(bge_factotum_error_handler) 4393 4394 static void 4395 bge_factotum_error_handler(bge_t *bgep) 4396 { 4397 uint32_t flow; 4398 uint32_t rdma; 4399 uint32_t wdma; 4400 uint32_t tmac; 4401 uint32_t rmac; 4402 uint32_t rxrs; 4403 uint32_t txrs = 0; 4404 4405 ASSERT(mutex_owned(bgep->genlock)); 4406 4407 /* 4408 * Read all the registers that show the possible 4409 * reasons for the ERROR bit to be asserted 4410 */ 4411 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4412 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4413 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4414 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4415 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4416 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4417 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4418 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4419 4420 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4421 (void *)bgep, flow, rdma, wdma)); 4422 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4423 (void *)bgep, tmac, rmac, rxrs, txrs)); 4424 4425 /* 4426 * For now, just clear all the errors ... 4427 */ 4428 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4429 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4430 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4431 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4432 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4433 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4434 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4435 } 4436 4437 /* 4438 * Handler for hardware link state change. 4439 * 4440 * When this routine is called, the hardware link state has changed 4441 * and the new state is reflected in the param_* variables. Here 4442 * we must update the softstate and reprogram the MAC to match. 4443 */ 4444 static void bge_factotum_link_handler(bge_t *bgep); 4445 #pragma no_inline(bge_factotum_link_handler) 4446 4447 static void 4448 bge_factotum_link_handler(bge_t *bgep) 4449 { 4450 ASSERT(mutex_owned(bgep->genlock)); 4451 4452 /* 4453 * Update the s/w link_state 4454 */ 4455 if (bgep->param_link_up) 4456 bgep->link_state = LINK_STATE_UP; 4457 else 4458 bgep->link_state = LINK_STATE_DOWN; 4459 4460 /* 4461 * Reprogram the MAC modes to match 4462 */ 4463 bge_sync_mac_modes(bgep); 4464 } 4465 4466 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4467 #pragma no_inline(bge_factotum_link_check) 4468 4469 static boolean_t 4470 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4471 { 4472 boolean_t check; 4473 uint64_t flags; 4474 uint32_t tmac_status; 4475 4476 ASSERT(mutex_owned(bgep->genlock)); 4477 4478 /* 4479 * Get & clear the writable status bits in the Tx status register 4480 * (some bits are write-1-to-clear, others are just readonly). 4481 */ 4482 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4483 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4484 4485 /* 4486 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4487 */ 4488 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4489 STATUS_FLAG_LINK_CHANGED, &flags); 4490 if (*dma_state != DDI_FM_OK) 4491 return (B_FALSE); 4492 4493 /* 4494 * Clear any errors flagged in the status block ... 4495 */ 4496 if (flags & STATUS_FLAG_ERROR) 4497 bge_factotum_error_handler(bgep); 4498 4499 /* 4500 * We need to check the link status if: 4501 * the status block says there's been a link change 4502 * or there's any discrepancy between the various 4503 * flags indicating the link state (link_state, 4504 * param_link_up, and the LINK STATE bit in the 4505 * Transmit MAC status register). 4506 */ 4507 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4508 switch (bgep->link_state) { 4509 case LINK_STATE_UP: 4510 check |= (bgep->param_link_up == B_FALSE); 4511 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4512 break; 4513 4514 case LINK_STATE_DOWN: 4515 check |= (bgep->param_link_up != B_FALSE); 4516 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4517 break; 4518 4519 default: 4520 check = B_TRUE; 4521 break; 4522 } 4523 4524 /* 4525 * If <check> is false, we're sure the link hasn't changed. 4526 * If true, however, it's not yet definitive; we have to call 4527 * bge_phys_check() to determine whether the link has settled 4528 * into a new state yet ... and if it has, then call the link 4529 * state change handler.But when the chip is 5700 in Dell 6650 4530 * ,even if check is false, the link may have changed.So we 4531 * have to call bge_phys_check() to determine the link state. 4532 */ 4533 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4534 check = bge_phys_check(bgep); 4535 if (check) 4536 bge_factotum_link_handler(bgep); 4537 } 4538 4539 return (check); 4540 } 4541 4542 /* 4543 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4544 */ 4545 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4546 #pragma no_inline(bge_factotum_stall_check) 4547 4548 static boolean_t 4549 bge_factotum_stall_check(bge_t *bgep) 4550 { 4551 uint32_t dogval; 4552 4553 ASSERT(mutex_owned(bgep->genlock)); 4554 4555 /* 4556 * Specific check for Tx stall ... 4557 * 4558 * The 'watchdog' counter is incremented whenever a packet 4559 * is queued, reset to 1 when some (but not all) buffers 4560 * are reclaimed, reset to 0 (disabled) when all buffers 4561 * are reclaimed, and shifted left here. If it exceeds the 4562 * threshold value, the chip is assumed to have stalled and 4563 * is put into the ERROR state. The factotum will then reset 4564 * it on the next pass. 4565 * 4566 * All of which should ensure that we don't get into a state 4567 * where packets are left pending indefinitely! 4568 */ 4569 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4570 if (dogval < bge_watchdog_count) 4571 return (B_FALSE); 4572 4573 #if !defined(BGE_NETCONSOLE) 4574 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4575 #endif 4576 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4577 return (B_TRUE); 4578 } 4579 4580 /* 4581 * The factotum is woken up when there's something to do that we'd rather 4582 * not do from inside a hardware interrupt handler or high-level cyclic. 4583 * Its two main tasks are: 4584 * reset & restart the chip after an error 4585 * check the link status whenever necessary 4586 */ 4587 uint_t bge_chip_factotum(caddr_t arg); 4588 #pragma no_inline(bge_chip_factotum) 4589 4590 uint_t 4591 bge_chip_factotum(caddr_t arg) 4592 { 4593 bge_t *bgep; 4594 uint_t result; 4595 boolean_t error; 4596 boolean_t linkchg; 4597 int dma_state; 4598 4599 bgep = (void *)arg; 4600 4601 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4602 4603 mutex_enter(bgep->softintrlock); 4604 if (bgep->factotum_flag == 0) { 4605 mutex_exit(bgep->softintrlock); 4606 return (DDI_INTR_UNCLAIMED); 4607 } 4608 bgep->factotum_flag = 0; 4609 mutex_exit(bgep->softintrlock); 4610 4611 result = DDI_INTR_CLAIMED; 4612 error = B_FALSE; 4613 linkchg = B_FALSE; 4614 4615 mutex_enter(bgep->genlock); 4616 switch (bgep->bge_chip_state) { 4617 default: 4618 break; 4619 4620 case BGE_CHIP_RUNNING: 4621 linkchg = bge_factotum_link_check(bgep, &dma_state); 4622 error = bge_factotum_stall_check(bgep); 4623 if (dma_state != DDI_FM_OK) { 4624 bgep->bge_dma_error = B_TRUE; 4625 error = B_TRUE; 4626 } 4627 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4628 error = B_TRUE; 4629 if (error) 4630 bgep->bge_chip_state = BGE_CHIP_ERROR; 4631 break; 4632 4633 case BGE_CHIP_ERROR: 4634 error = B_TRUE; 4635 break; 4636 4637 case BGE_CHIP_FAULT: 4638 /* 4639 * Fault detected, time to reset ... 4640 */ 4641 if (bge_autorecover) { 4642 if (!(bgep->progress & PROGRESS_BUFS)) { 4643 /* 4644 * if we can't allocate the ring buffers, 4645 * try later 4646 */ 4647 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4648 mutex_exit(bgep->genlock); 4649 return (result); 4650 } 4651 bgep->progress |= PROGRESS_BUFS; 4652 } 4653 if (!(bgep->progress & PROGRESS_INTR)) { 4654 bge_init_rings(bgep); 4655 bge_intr_enable(bgep); 4656 bgep->progress |= PROGRESS_INTR; 4657 } 4658 if (!(bgep->progress & PROGRESS_KSTATS)) { 4659 bge_init_kstats(bgep, 4660 ddi_get_instance(bgep->devinfo)); 4661 bgep->progress |= PROGRESS_KSTATS; 4662 } 4663 4664 BGE_REPORT((bgep, "automatic recovery activated")); 4665 4666 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4667 bgep->bge_chip_state = BGE_CHIP_ERROR; 4668 error = B_TRUE; 4669 } 4670 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4671 DDI_FM_OK) { 4672 bgep->bge_chip_state = BGE_CHIP_ERROR; 4673 error = B_TRUE; 4674 } 4675 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4676 DDI_FM_OK) { 4677 bgep->bge_chip_state = BGE_CHIP_ERROR; 4678 error = B_TRUE; 4679 } 4680 if (error == B_FALSE) { 4681 #ifdef BGE_IPMI_ASF 4682 if (bgep->asf_enabled && 4683 bgep->asf_status != ASF_STAT_RUN) { 4684 bgep->asf_timeout_id = timeout( 4685 bge_asf_heartbeat, (void *)bgep, 4686 drv_usectohz( 4687 BGE_ASF_HEARTBEAT_INTERVAL)); 4688 bgep->asf_status = ASF_STAT_RUN; 4689 } 4690 #endif 4691 if (!bgep->manual_reset) { 4692 ddi_fm_service_impact(bgep->devinfo, 4693 DDI_SERVICE_RESTORED); 4694 } 4695 } 4696 } 4697 break; 4698 } 4699 4700 4701 /* 4702 * If an error is detected, stop the chip now, marking it as 4703 * faulty, so that it will be reset next time through ... 4704 * 4705 * Note that if intr_running is set, then bge_intr() has dropped 4706 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4707 * this point so have to wait until the next time the factotum runs. 4708 */ 4709 if (error && !bgep->bge_intr_running) { 4710 #ifdef BGE_IPMI_ASF 4711 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4712 /* 4713 * We must stop ASF heart beat before bge_chip_stop(), 4714 * otherwise some computers (ex. IBM HS20 blade server) 4715 * may crash. 4716 */ 4717 bge_asf_update_status(bgep); 4718 bge_asf_stop_timer(bgep); 4719 bgep->asf_status = ASF_STAT_STOP; 4720 4721 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4722 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4723 } 4724 #endif 4725 bge_chip_stop(bgep, B_TRUE); 4726 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4727 } 4728 mutex_exit(bgep->genlock); 4729 4730 /* 4731 * If the link state changed, tell the world about it. 4732 * Note: can't do this while still holding the mutex. 4733 */ 4734 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4735 bgep->link_state != LINK_STATE_UNKNOWN) 4736 linkchg = B_TRUE; 4737 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4738 bgep->link_state == LINK_STATE_DOWN) 4739 linkchg = B_FALSE; 4740 4741 if (linkchg) { 4742 mac_link_update(bgep->mh, bgep->link_state); 4743 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4744 } 4745 if (bgep->manual_reset) { 4746 bgep->manual_reset = B_FALSE; 4747 } 4748 4749 return (result); 4750 } 4751 4752 /* 4753 * High-level cyclic handler 4754 * 4755 * This routine schedules a (low-level) softint callback to the 4756 * factotum, and prods the chip to update the status block (which 4757 * will cause a hardware interrupt when complete). 4758 */ 4759 void bge_chip_cyclic(void *arg); 4760 #pragma no_inline(bge_chip_cyclic) 4761 4762 void 4763 bge_chip_cyclic(void *arg) 4764 { 4765 bge_t *bgep; 4766 4767 bgep = arg; 4768 4769 switch (bgep->bge_chip_state) { 4770 default: 4771 return; 4772 4773 case BGE_CHIP_RUNNING: 4774 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4775 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4776 ddi_fm_service_impact(bgep->devinfo, 4777 DDI_SERVICE_UNAFFECTED); 4778 4779 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4780 bgep->link_update_timer++; 4781 4782 break; 4783 4784 case BGE_CHIP_FAULT: 4785 case BGE_CHIP_ERROR: 4786 break; 4787 } 4788 4789 bge_wake_factotum(bgep); 4790 } 4791 4792 4793 /* 4794 * ========== Ioctl subfunctions ========== 4795 */ 4796 4797 #undef BGE_DBG 4798 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4799 4800 #if BGE_DEBUGGING || BGE_DO_PPIO 4801 4802 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4803 #pragma no_inline(bge_chip_peek_cfg) 4804 4805 static void 4806 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4807 { 4808 uint64_t regval; 4809 uint64_t regno; 4810 4811 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4812 (void *)bgep, (void *)ppd)); 4813 4814 regno = ppd->pp_acc_offset; 4815 4816 switch (ppd->pp_acc_size) { 4817 case 1: 4818 regval = pci_config_get8(bgep->cfg_handle, regno); 4819 break; 4820 4821 case 2: 4822 regval = pci_config_get16(bgep->cfg_handle, regno); 4823 break; 4824 4825 case 4: 4826 regval = pci_config_get32(bgep->cfg_handle, regno); 4827 break; 4828 4829 case 8: 4830 regval = pci_config_get64(bgep->cfg_handle, regno); 4831 break; 4832 } 4833 4834 ppd->pp_acc_data = regval; 4835 } 4836 4837 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4838 #pragma no_inline(bge_chip_poke_cfg) 4839 4840 static void 4841 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4842 { 4843 uint64_t regval; 4844 uint64_t regno; 4845 4846 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4847 (void *)bgep, (void *)ppd)); 4848 4849 regno = ppd->pp_acc_offset; 4850 regval = ppd->pp_acc_data; 4851 4852 switch (ppd->pp_acc_size) { 4853 case 1: 4854 pci_config_put8(bgep->cfg_handle, regno, regval); 4855 break; 4856 4857 case 2: 4858 pci_config_put16(bgep->cfg_handle, regno, regval); 4859 break; 4860 4861 case 4: 4862 pci_config_put32(bgep->cfg_handle, regno, regval); 4863 break; 4864 4865 case 8: 4866 pci_config_put64(bgep->cfg_handle, regno, regval); 4867 break; 4868 } 4869 } 4870 4871 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4872 #pragma no_inline(bge_chip_peek_reg) 4873 4874 static void 4875 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4876 { 4877 uint64_t regval; 4878 void *regaddr; 4879 4880 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4881 (void *)bgep, (void *)ppd)); 4882 4883 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4884 4885 switch (ppd->pp_acc_size) { 4886 case 1: 4887 regval = ddi_get8(bgep->io_handle, regaddr); 4888 break; 4889 4890 case 2: 4891 regval = ddi_get16(bgep->io_handle, regaddr); 4892 break; 4893 4894 case 4: 4895 regval = ddi_get32(bgep->io_handle, regaddr); 4896 break; 4897 4898 case 8: 4899 regval = ddi_get64(bgep->io_handle, regaddr); 4900 break; 4901 } 4902 4903 ppd->pp_acc_data = regval; 4904 } 4905 4906 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4907 #pragma no_inline(bge_chip_peek_reg) 4908 4909 static void 4910 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4911 { 4912 uint64_t regval; 4913 void *regaddr; 4914 4915 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4916 (void *)bgep, (void *)ppd)); 4917 4918 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4919 regval = ppd->pp_acc_data; 4920 4921 switch (ppd->pp_acc_size) { 4922 case 1: 4923 ddi_put8(bgep->io_handle, regaddr, regval); 4924 break; 4925 4926 case 2: 4927 ddi_put16(bgep->io_handle, regaddr, regval); 4928 break; 4929 4930 case 4: 4931 ddi_put32(bgep->io_handle, regaddr, regval); 4932 break; 4933 4934 case 8: 4935 ddi_put64(bgep->io_handle, regaddr, regval); 4936 break; 4937 } 4938 BGE_PCICHK(bgep); 4939 } 4940 4941 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4942 #pragma no_inline(bge_chip_peek_nic) 4943 4944 static void 4945 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4946 { 4947 uint64_t regoff; 4948 uint64_t regval; 4949 void *regaddr; 4950 4951 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4952 (void *)bgep, (void *)ppd)); 4953 4954 regoff = ppd->pp_acc_offset; 4955 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4956 regoff &= MWBAR_GRANULE_MASK; 4957 regoff += NIC_MEM_WINDOW_OFFSET; 4958 regaddr = PIO_ADDR(bgep, regoff); 4959 4960 switch (ppd->pp_acc_size) { 4961 case 1: 4962 regval = ddi_get8(bgep->io_handle, regaddr); 4963 break; 4964 4965 case 2: 4966 regval = ddi_get16(bgep->io_handle, regaddr); 4967 break; 4968 4969 case 4: 4970 regval = ddi_get32(bgep->io_handle, regaddr); 4971 break; 4972 4973 case 8: 4974 regval = ddi_get64(bgep->io_handle, regaddr); 4975 break; 4976 } 4977 4978 ppd->pp_acc_data = regval; 4979 } 4980 4981 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4982 #pragma no_inline(bge_chip_poke_nic) 4983 4984 static void 4985 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4986 { 4987 uint64_t regoff; 4988 uint64_t regval; 4989 void *regaddr; 4990 4991 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4992 (void *)bgep, (void *)ppd)); 4993 4994 regoff = ppd->pp_acc_offset; 4995 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4996 regoff &= MWBAR_GRANULE_MASK; 4997 regoff += NIC_MEM_WINDOW_OFFSET; 4998 regaddr = PIO_ADDR(bgep, regoff); 4999 regval = ppd->pp_acc_data; 5000 5001 switch (ppd->pp_acc_size) { 5002 case 1: 5003 ddi_put8(bgep->io_handle, regaddr, regval); 5004 break; 5005 5006 case 2: 5007 ddi_put16(bgep->io_handle, regaddr, regval); 5008 break; 5009 5010 case 4: 5011 ddi_put32(bgep->io_handle, regaddr, regval); 5012 break; 5013 5014 case 8: 5015 ddi_put64(bgep->io_handle, regaddr, regval); 5016 break; 5017 } 5018 BGE_PCICHK(bgep); 5019 } 5020 5021 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5022 #pragma no_inline(bge_chip_peek_mii) 5023 5024 static void 5025 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5026 { 5027 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5028 (void *)bgep, (void *)ppd)); 5029 5030 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5031 } 5032 5033 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5034 #pragma no_inline(bge_chip_poke_mii) 5035 5036 static void 5037 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5038 { 5039 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5040 (void *)bgep, (void *)ppd)); 5041 5042 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5043 } 5044 5045 #if BGE_SEE_IO32 5046 5047 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5048 #pragma no_inline(bge_chip_peek_seeprom) 5049 5050 static void 5051 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5052 { 5053 uint32_t data; 5054 int err; 5055 5056 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5057 (void *)bgep, (void *)ppd)); 5058 5059 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5060 ppd->pp_acc_data = err ? ~0ull : data; 5061 } 5062 5063 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5064 #pragma no_inline(bge_chip_poke_seeprom) 5065 5066 static void 5067 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5068 { 5069 uint32_t data; 5070 5071 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5072 (void *)bgep, (void *)ppd)); 5073 5074 data = ppd->pp_acc_data; 5075 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5076 } 5077 #endif /* BGE_SEE_IO32 */ 5078 5079 #if BGE_FLASH_IO32 5080 5081 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5082 #pragma no_inline(bge_chip_peek_flash) 5083 5084 static void 5085 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5086 { 5087 uint32_t data; 5088 int err; 5089 5090 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5091 (void *)bgep, (void *)ppd)); 5092 5093 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5094 ppd->pp_acc_data = err ? ~0ull : data; 5095 } 5096 5097 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5098 #pragma no_inline(bge_chip_poke_flash) 5099 5100 static void 5101 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5102 { 5103 uint32_t data; 5104 5105 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5106 (void *)bgep, (void *)ppd)); 5107 5108 data = ppd->pp_acc_data; 5109 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5110 ppd->pp_acc_offset, &data); 5111 } 5112 #endif /* BGE_FLASH_IO32 */ 5113 5114 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5115 #pragma no_inline(bge_chip_peek_mem) 5116 5117 static void 5118 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5119 { 5120 uint64_t regval; 5121 void *vaddr; 5122 5123 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5124 (void *)bgep, (void *)ppd)); 5125 5126 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5127 5128 switch (ppd->pp_acc_size) { 5129 case 1: 5130 regval = *(uint8_t *)vaddr; 5131 break; 5132 5133 case 2: 5134 regval = *(uint16_t *)vaddr; 5135 break; 5136 5137 case 4: 5138 regval = *(uint32_t *)vaddr; 5139 break; 5140 5141 case 8: 5142 regval = *(uint64_t *)vaddr; 5143 break; 5144 } 5145 5146 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5147 (void *)bgep, (void *)ppd, regval, vaddr)); 5148 5149 ppd->pp_acc_data = regval; 5150 } 5151 5152 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5153 #pragma no_inline(bge_chip_poke_mem) 5154 5155 static void 5156 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5157 { 5158 uint64_t regval; 5159 void *vaddr; 5160 5161 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5162 (void *)bgep, (void *)ppd)); 5163 5164 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5165 regval = ppd->pp_acc_data; 5166 5167 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5168 (void *)bgep, (void *)ppd, regval, vaddr)); 5169 5170 switch (ppd->pp_acc_size) { 5171 case 1: 5172 *(uint8_t *)vaddr = (uint8_t)regval; 5173 break; 5174 5175 case 2: 5176 *(uint16_t *)vaddr = (uint16_t)regval; 5177 break; 5178 5179 case 4: 5180 *(uint32_t *)vaddr = (uint32_t)regval; 5181 break; 5182 5183 case 8: 5184 *(uint64_t *)vaddr = (uint64_t)regval; 5185 break; 5186 } 5187 } 5188 5189 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5190 struct iocblk *iocp); 5191 #pragma no_inline(bge_pp_ioctl) 5192 5193 static enum ioc_reply 5194 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5195 { 5196 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5197 bge_peekpoke_t *ppd; 5198 dma_area_t *areap; 5199 uint64_t sizemask; 5200 uint64_t mem_va; 5201 uint64_t maxoff; 5202 boolean_t peek; 5203 5204 switch (cmd) { 5205 default: 5206 /* NOTREACHED */ 5207 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5208 return (IOC_INVAL); 5209 5210 case BGE_PEEK: 5211 peek = B_TRUE; 5212 break; 5213 5214 case BGE_POKE: 5215 peek = B_FALSE; 5216 break; 5217 } 5218 5219 /* 5220 * Validate format of ioctl 5221 */ 5222 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5223 return (IOC_INVAL); 5224 if (mp->b_cont == NULL) 5225 return (IOC_INVAL); 5226 ppd = (void *)mp->b_cont->b_rptr; 5227 5228 /* 5229 * Validate request parameters 5230 */ 5231 switch (ppd->pp_acc_space) { 5232 default: 5233 return (IOC_INVAL); 5234 5235 case BGE_PP_SPACE_CFG: 5236 /* 5237 * Config space 5238 */ 5239 sizemask = 8|4|2|1; 5240 mem_va = 0; 5241 maxoff = PCI_CONF_HDR_SIZE; 5242 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5243 break; 5244 5245 case BGE_PP_SPACE_REG: 5246 /* 5247 * Memory-mapped I/O space 5248 */ 5249 sizemask = 8|4|2|1; 5250 mem_va = 0; 5251 maxoff = RIAAR_REGISTER_MAX; 5252 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5253 break; 5254 5255 case BGE_PP_SPACE_NIC: 5256 /* 5257 * NIC on-chip memory 5258 */ 5259 sizemask = 8|4|2|1; 5260 mem_va = 0; 5261 maxoff = MWBAR_ONCHIP_MAX; 5262 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5263 break; 5264 5265 case BGE_PP_SPACE_MII: 5266 /* 5267 * PHY's MII registers 5268 * NB: all PHY registers are two bytes, but the 5269 * addresses increment in ones (word addressing). 5270 * So we scale the address here, then undo the 5271 * transformation inside the peek/poke functions. 5272 */ 5273 ppd->pp_acc_offset *= 2; 5274 sizemask = 2; 5275 mem_va = 0; 5276 maxoff = (MII_MAXREG+1)*2; 5277 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5278 break; 5279 5280 #if BGE_SEE_IO32 5281 case BGE_PP_SPACE_SEEPROM: 5282 /* 5283 * Attached SEEPROM(s), if any. 5284 * NB: we use the high-order bits of the 'address' as 5285 * a device select to accommodate multiple SEEPROMS, 5286 * If each one is the maximum size (64kbytes), this 5287 * makes them appear contiguous. Otherwise, there may 5288 * be holes in the mapping. ENxS doesn't have any 5289 * SEEPROMs anyway ... 5290 */ 5291 sizemask = 4; 5292 mem_va = 0; 5293 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5294 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5295 break; 5296 #endif /* BGE_SEE_IO32 */ 5297 5298 #if BGE_FLASH_IO32 5299 case BGE_PP_SPACE_FLASH: 5300 /* 5301 * Attached Flash device (if any); a maximum of one device 5302 * is currently supported. But it can be up to 1MB (unlike 5303 * the 64k limit on SEEPROMs) so why would you need more ;-) 5304 */ 5305 sizemask = 4; 5306 mem_va = 0; 5307 maxoff = NVM_FLASH_ADDR_MASK; 5308 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5309 break; 5310 #endif /* BGE_FLASH_IO32 */ 5311 5312 case BGE_PP_SPACE_BGE: 5313 /* 5314 * BGE data structure! 5315 */ 5316 sizemask = 8|4|2|1; 5317 mem_va = (uintptr_t)bgep; 5318 maxoff = sizeof (*bgep); 5319 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5320 break; 5321 5322 case BGE_PP_SPACE_STATUS: 5323 case BGE_PP_SPACE_STATISTICS: 5324 case BGE_PP_SPACE_TXDESC: 5325 case BGE_PP_SPACE_TXBUFF: 5326 case BGE_PP_SPACE_RXDESC: 5327 case BGE_PP_SPACE_RXBUFF: 5328 /* 5329 * Various DMA_AREAs 5330 */ 5331 switch (ppd->pp_acc_space) { 5332 case BGE_PP_SPACE_TXDESC: 5333 areap = &bgep->tx_desc; 5334 break; 5335 case BGE_PP_SPACE_TXBUFF: 5336 areap = &bgep->tx_buff[0]; 5337 break; 5338 case BGE_PP_SPACE_RXDESC: 5339 areap = &bgep->rx_desc[0]; 5340 break; 5341 case BGE_PP_SPACE_RXBUFF: 5342 areap = &bgep->rx_buff[0]; 5343 break; 5344 case BGE_PP_SPACE_STATUS: 5345 areap = &bgep->status_block; 5346 break; 5347 case BGE_PP_SPACE_STATISTICS: 5348 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5349 areap = &bgep->statistics; 5350 break; 5351 } 5352 5353 sizemask = 8|4|2|1; 5354 mem_va = (uintptr_t)areap->mem_va; 5355 maxoff = areap->alength; 5356 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5357 break; 5358 } 5359 5360 switch (ppd->pp_acc_size) { 5361 default: 5362 return (IOC_INVAL); 5363 5364 case 8: 5365 case 4: 5366 case 2: 5367 case 1: 5368 if ((ppd->pp_acc_size & sizemask) == 0) 5369 return (IOC_INVAL); 5370 break; 5371 } 5372 5373 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5374 return (IOC_INVAL); 5375 5376 if (ppd->pp_acc_offset >= maxoff) 5377 return (IOC_INVAL); 5378 5379 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5380 return (IOC_INVAL); 5381 5382 /* 5383 * All OK - go do it! 5384 */ 5385 ppd->pp_acc_offset += mem_va; 5386 (*ppfn)(bgep, ppd); 5387 return (peek ? IOC_REPLY : IOC_ACK); 5388 } 5389 5390 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5391 struct iocblk *iocp); 5392 #pragma no_inline(bge_diag_ioctl) 5393 5394 static enum ioc_reply 5395 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5396 { 5397 ASSERT(mutex_owned(bgep->genlock)); 5398 5399 switch (cmd) { 5400 default: 5401 /* NOTREACHED */ 5402 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5403 return (IOC_INVAL); 5404 5405 case BGE_DIAG: 5406 /* 5407 * Currently a no-op 5408 */ 5409 return (IOC_ACK); 5410 5411 case BGE_PEEK: 5412 case BGE_POKE: 5413 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5414 5415 case BGE_PHY_RESET: 5416 return (IOC_RESTART_ACK); 5417 5418 case BGE_SOFT_RESET: 5419 case BGE_HARD_RESET: 5420 /* 5421 * Reset and reinitialise the 570x hardware 5422 */ 5423 bgep->bge_chip_state = BGE_CHIP_FAULT; 5424 ddi_trigger_softintr(bgep->factotum_id); 5425 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5426 return (IOC_ACK); 5427 } 5428 5429 /* NOTREACHED */ 5430 } 5431 5432 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5433 5434 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5435 struct iocblk *iocp); 5436 #pragma no_inline(bge_mii_ioctl) 5437 5438 static enum ioc_reply 5439 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5440 { 5441 struct bge_mii_rw *miirwp; 5442 5443 /* 5444 * Validate format of ioctl 5445 */ 5446 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5447 return (IOC_INVAL); 5448 if (mp->b_cont == NULL) 5449 return (IOC_INVAL); 5450 miirwp = (void *)mp->b_cont->b_rptr; 5451 5452 /* 5453 * Validate request parameters ... 5454 */ 5455 if (miirwp->mii_reg > MII_MAXREG) 5456 return (IOC_INVAL); 5457 5458 switch (cmd) { 5459 default: 5460 /* NOTREACHED */ 5461 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5462 return (IOC_INVAL); 5463 5464 case BGE_MII_READ: 5465 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5466 return (IOC_REPLY); 5467 5468 case BGE_MII_WRITE: 5469 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5470 return (IOC_ACK); 5471 } 5472 5473 /* NOTREACHED */ 5474 } 5475 5476 #if BGE_SEE_IO32 5477 5478 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5479 struct iocblk *iocp); 5480 #pragma no_inline(bge_see_ioctl) 5481 5482 static enum ioc_reply 5483 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5484 { 5485 struct bge_see_rw *seerwp; 5486 5487 /* 5488 * Validate format of ioctl 5489 */ 5490 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5491 return (IOC_INVAL); 5492 if (mp->b_cont == NULL) 5493 return (IOC_INVAL); 5494 seerwp = (void *)mp->b_cont->b_rptr; 5495 5496 /* 5497 * Validate request parameters ... 5498 */ 5499 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5500 return (IOC_INVAL); 5501 5502 switch (cmd) { 5503 default: 5504 /* NOTREACHED */ 5505 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5506 return (IOC_INVAL); 5507 5508 case BGE_SEE_READ: 5509 case BGE_SEE_WRITE: 5510 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5511 seerwp->see_addr, &seerwp->see_data); 5512 return (IOC_REPLY); 5513 } 5514 5515 /* NOTREACHED */ 5516 } 5517 5518 #endif /* BGE_SEE_IO32 */ 5519 5520 #if BGE_FLASH_IO32 5521 5522 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5523 struct iocblk *iocp); 5524 #pragma no_inline(bge_flash_ioctl) 5525 5526 static enum ioc_reply 5527 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5528 { 5529 struct bge_flash_rw *flashrwp; 5530 5531 /* 5532 * Validate format of ioctl 5533 */ 5534 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5535 return (IOC_INVAL); 5536 if (mp->b_cont == NULL) 5537 return (IOC_INVAL); 5538 flashrwp = (void *)mp->b_cont->b_rptr; 5539 5540 /* 5541 * Validate request parameters ... 5542 */ 5543 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5544 return (IOC_INVAL); 5545 5546 switch (cmd) { 5547 default: 5548 /* NOTREACHED */ 5549 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5550 return (IOC_INVAL); 5551 5552 case BGE_FLASH_READ: 5553 case BGE_FLASH_WRITE: 5554 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5555 flashrwp->flash_addr, &flashrwp->flash_data); 5556 return (IOC_REPLY); 5557 } 5558 5559 /* NOTREACHED */ 5560 } 5561 5562 #endif /* BGE_FLASH_IO32 */ 5563 5564 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5565 struct iocblk *iocp); 5566 #pragma no_inline(bge_chip_ioctl) 5567 5568 enum ioc_reply 5569 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5570 { 5571 int cmd; 5572 5573 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5574 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5575 5576 ASSERT(mutex_owned(bgep->genlock)); 5577 5578 cmd = iocp->ioc_cmd; 5579 switch (cmd) { 5580 default: 5581 /* NOTREACHED */ 5582 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5583 return (IOC_INVAL); 5584 5585 case BGE_DIAG: 5586 case BGE_PEEK: 5587 case BGE_POKE: 5588 case BGE_PHY_RESET: 5589 case BGE_SOFT_RESET: 5590 case BGE_HARD_RESET: 5591 #if BGE_DEBUGGING || BGE_DO_PPIO 5592 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5593 #else 5594 return (IOC_INVAL); 5595 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5596 5597 case BGE_MII_READ: 5598 case BGE_MII_WRITE: 5599 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5600 5601 #if BGE_SEE_IO32 5602 case BGE_SEE_READ: 5603 case BGE_SEE_WRITE: 5604 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5605 #endif /* BGE_SEE_IO32 */ 5606 5607 #if BGE_FLASH_IO32 5608 case BGE_FLASH_READ: 5609 case BGE_FLASH_WRITE: 5610 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5611 #endif /* BGE_FLASH_IO32 */ 5612 } 5613 5614 /* NOTREACHED */ 5615 } 5616 5617 /* ARGSUSED */ 5618 void 5619 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5620 { 5621 recv_ring_t *rrp = arg; 5622 bge_t *bgep = rrp->bgep; 5623 5624 mutex_enter(bgep->genlock); 5625 rrp->poll_flag = flag; 5626 #ifdef NOT_YET 5627 /* 5628 * XXX-Sunay: Since most broadcom cards support only one 5629 * interrupt but multiple rx rings, we can't disable the 5630 * physical interrupt. This need to be done via capability 5631 * negotiation depending on the NIC. 5632 */ 5633 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5634 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5635 #endif 5636 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5637 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5638 mutex_exit(bgep->genlock); 5639 } 5640 5641 #ifdef BGE_IPMI_ASF 5642 5643 uint32_t 5644 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5645 { 5646 uint32_t data; 5647 5648 #ifndef __sparc 5649 if (!bgep->asf_wordswapped) { 5650 /* a workaround word swap error */ 5651 if (addr & 4) 5652 addr = addr - 4; 5653 else 5654 addr = addr + 4; 5655 } 5656 #endif 5657 5658 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5659 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5660 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5661 5662 data = LE_32(data); 5663 return (data); 5664 } 5665 5666 void 5667 bge_asf_update_status(bge_t *bgep) 5668 { 5669 uint32_t event; 5670 5671 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5672 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5673 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5674 5675 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5676 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5677 } 5678 5679 5680 /* 5681 * The driver is supposed to notify ASF that the OS is still running 5682 * every three seconds, otherwise the management server may attempt 5683 * to reboot the machine. If it hasn't actually failed, this is 5684 * not a desirable result. However, this isn't running as a real-time 5685 * thread, and even if it were, it might not be able to generate the 5686 * heartbeat in a timely manner due to system load. As it isn't a 5687 * significant strain on the machine, we will set the interval to half 5688 * of the required value. 5689 */ 5690 void 5691 bge_asf_heartbeat(void *arg) 5692 { 5693 bge_t *bgep = (bge_t *)arg; 5694 5695 mutex_enter(bgep->genlock); 5696 bge_asf_update_status((bge_t *)bgep); 5697 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5698 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5699 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5700 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5701 mutex_exit(bgep->genlock); 5702 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5703 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5704 } 5705 5706 5707 void 5708 bge_asf_stop_timer(bge_t *bgep) 5709 { 5710 timeout_id_t tmp_id = 0; 5711 5712 while ((bgep->asf_timeout_id != 0) && 5713 (tmp_id != bgep->asf_timeout_id)) { 5714 tmp_id = bgep->asf_timeout_id; 5715 (void) untimeout(tmp_id); 5716 } 5717 bgep->asf_timeout_id = 0; 5718 } 5719 5720 5721 5722 /* 5723 * This function should be placed at the earliest position of bge_attach(). 5724 */ 5725 void 5726 bge_asf_get_config(bge_t *bgep) 5727 { 5728 uint32_t nicsig; 5729 uint32_t niccfg; 5730 5731 bgep->asf_enabled = B_FALSE; 5732 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5733 if (nicsig == BGE_NIC_DATA_SIG) { 5734 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5735 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5736 /* 5737 * Here, we don't consider BAXTER, because BGE haven't 5738 * supported BAXTER (that is 5752). Also, as I know, 5739 * BAXTER doesn't support ASF feature. 5740 */ 5741 bgep->asf_enabled = B_TRUE; 5742 else 5743 bgep->asf_enabled = B_FALSE; 5744 } else 5745 bgep->asf_enabled = B_FALSE; 5746 } 5747 5748 5749 void 5750 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5751 { 5752 uint32_t tries; 5753 uint32_t event; 5754 5755 ASSERT(bgep->asf_enabled); 5756 5757 /* Issues "pause firmware" command and wait for ACK */ 5758 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5759 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5760 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5761 5762 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5763 tries = 0; 5764 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5765 drv_usecwait(1); 5766 tries ++; 5767 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5768 } 5769 5770 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5771 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5772 5773 if (bgep->asf_newhandshake) { 5774 switch (mode) { 5775 case BGE_INIT_RESET: 5776 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5777 BGE_DRV_STATE_START); 5778 break; 5779 case BGE_SHUTDOWN_RESET: 5780 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5781 BGE_DRV_STATE_UNLOAD); 5782 break; 5783 case BGE_SUSPEND_RESET: 5784 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5785 BGE_DRV_STATE_SUSPEND); 5786 break; 5787 default: 5788 break; 5789 } 5790 } 5791 } 5792 5793 5794 void 5795 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5796 { 5797 switch (mode) { 5798 case BGE_INIT_RESET: 5799 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5800 BGE_DRV_STATE_START); 5801 break; 5802 case BGE_SHUTDOWN_RESET: 5803 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5804 BGE_DRV_STATE_UNLOAD); 5805 break; 5806 case BGE_SUSPEND_RESET: 5807 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5808 BGE_DRV_STATE_SUSPEND); 5809 break; 5810 default: 5811 break; 5812 } 5813 } 5814 5815 5816 void 5817 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5818 { 5819 switch (mode) { 5820 case BGE_INIT_RESET: 5821 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5822 BGE_DRV_STATE_START_DONE); 5823 break; 5824 case BGE_SHUTDOWN_RESET: 5825 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5826 BGE_DRV_STATE_UNLOAD_DONE); 5827 break; 5828 default: 5829 break; 5830 } 5831 } 5832 5833 #endif /* BGE_IPMI_ASF */ 5834