1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 1 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 56 */ 57 boolean_t bge_relaxed_ordering = B_TRUE; 58 59 /* 60 * Property names 61 */ 62 static char knownids_propname[] = "bge-known-subsystems"; 63 64 /* 65 * Patchable globals: 66 * 67 * bge_autorecover 68 * Enables/disables automatic recovery after fault detection 69 * 70 * bge_mlcr_default 71 * Value to program into the MLCR; controls the chip's GPIO pins 72 * 73 * bge_dma_{rd,wr}prio 74 * Relative priorities of DMA reads & DMA writes respectively. 75 * These may each be patched to any value 0-3. Equal values 76 * will give "fair" (round-robin) arbitration for PCI access. 77 * Unequal values will give one or the other function priority. 78 * 79 * bge_dma_rwctrl 80 * Value to put in the Read/Write DMA control register. See 81 * the Broadcom PRM for things you can fiddle with in this 82 * register ... 83 * 84 * bge_{tx,rx}_{count,ticks}_{norm,intr} 85 * Send/receive interrupt coalescing parameters. Counts are 86 * #s of descriptors, ticks are in microseconds. *norm* values 87 * apply between status updates/interrupts; the *intr* values 88 * refer to the 'during-interrupt' versions - see the PRM. 89 * 90 * NOTE: these values have been determined by measurement. They 91 * differ significantly from the values recommended in the PRM. 92 */ 93 static uint32_t bge_autorecover = 1; 94 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 95 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 96 97 static uint32_t bge_dma_rdprio = 1; 98 static uint32_t bge_dma_wrprio = 0; 99 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 100 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 101 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 102 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 103 104 uint32_t bge_rx_ticks_norm = 128; 105 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 106 uint32_t bge_rx_count_norm = 8; 107 uint32_t bge_tx_count_norm = 128; 108 109 static uint32_t bge_rx_ticks_intr = 128; 110 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 111 static uint32_t bge_rx_count_intr = 2; 112 static uint32_t bge_tx_count_intr = 0; 113 114 /* 115 * Memory pool configuration parameters. 116 * 117 * These are generally specific to each member of the chip family, since 118 * each one may have a different memory size/configuration. 119 * 120 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 121 * the driver from programming the various registers; instead they are left 122 * at their hardware defaults. This is the preferred option for later chips 123 * (5705+), whereas the older chips *required* these registers to be set, 124 * since the h/w default was 0 ;-( 125 */ 126 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 127 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 128 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 129 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 130 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 131 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 132 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 133 static uint32_t bge_mbuf_pool_len_5721 = 0; 134 135 /* 136 * Various high and low water marks, thresholds, etc ... 137 * 138 * Note: these are taken from revision 7 of the PRM, and some are different 139 * from both the values in earlier PRMs *and* those determined experimentally 140 * and used in earlier versions of this driver ... 141 */ 142 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 143 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 144 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 145 146 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 147 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 148 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 149 150 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 151 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 152 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 153 154 static uint32_t bge_watchdog_count = 1 << 16; 155 static uint16_t bge_dma_miss_limit = 20; 156 157 static uint32_t bge_stop_start_on_sync = 0; 158 159 boolean_t bge_jumbo_enable = B_TRUE; 160 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 161 162 /* 163 * bge_intr_max_loop controls the maximum loop number within bge_intr. 164 * When loading NIC with heavy network traffic, it is useful. 165 * Increasing this value could have positive effect to throughput, 166 * but it might also increase ticks of a bge ISR stick on CPU, which might 167 * lead to bad UI interactive experience. So tune this with caution. 168 */ 169 static int bge_intr_max_loop = 1; 170 171 /* 172 * ========== Low-level chip & ring buffer manipulation ========== 173 */ 174 175 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 176 177 178 /* 179 * Config space read-modify-write routines 180 */ 181 182 #if BGE_CFG_IO8 183 184 /* 185 * 8- and 16-bit set/clr operations are not used; all the config registers 186 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 187 * code here, though, in case we ever find that we do want it after all ... 188 */ 189 190 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 191 #pragma inline(bge_cfg_set8) 192 193 static void 194 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 195 { 196 uint8_t regval; 197 198 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 199 (void *)bgep, regno, bits)); 200 201 regval = pci_config_get8(bgep->cfg_handle, regno); 202 203 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 204 (void *)bgep, regno, bits, regval, regval | bits)); 205 206 regval |= bits; 207 pci_config_put8(bgep->cfg_handle, regno, regval); 208 } 209 210 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 211 #pragma inline(bge_cfg_clr8) 212 213 static void 214 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 215 { 216 uint8_t regval; 217 218 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 219 (void *)bgep, regno, bits)); 220 221 regval = pci_config_get8(bgep->cfg_handle, regno); 222 223 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 224 (void *)bgep, regno, bits, regval, regval & ~bits)); 225 226 regval &= ~bits; 227 pci_config_put8(bgep->cfg_handle, regno, regval); 228 } 229 230 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 231 #pragma inline(bge_cfg_set16) 232 233 static void 234 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 235 { 236 uint16_t regval; 237 238 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 239 (void *)bgep, regno, bits)); 240 241 regval = pci_config_get16(bgep->cfg_handle, regno); 242 243 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 244 (void *)bgep, regno, bits, regval, regval | bits)); 245 246 regval |= bits; 247 pci_config_put16(bgep->cfg_handle, regno, regval); 248 } 249 250 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 251 #pragma inline(bge_cfg_clr16) 252 253 static void 254 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 255 { 256 uint16_t regval; 257 258 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 259 (void *)bgep, regno, bits)); 260 261 regval = pci_config_get16(bgep->cfg_handle, regno); 262 263 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 264 (void *)bgep, regno, bits, regval, regval & ~bits)); 265 266 regval &= ~bits; 267 pci_config_put16(bgep->cfg_handle, regno, regval); 268 } 269 270 #endif /* BGE_CFG_IO8 */ 271 272 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 273 #pragma inline(bge_cfg_set32) 274 275 static void 276 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 277 { 278 uint32_t regval; 279 280 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 281 (void *)bgep, regno, bits)); 282 283 regval = pci_config_get32(bgep->cfg_handle, regno); 284 285 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 286 (void *)bgep, regno, bits, regval, regval | bits)); 287 288 regval |= bits; 289 pci_config_put32(bgep->cfg_handle, regno, regval); 290 } 291 292 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 293 #pragma inline(bge_cfg_clr32) 294 295 static void 296 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 297 { 298 uint32_t regval; 299 300 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 301 (void *)bgep, regno, bits)); 302 303 regval = pci_config_get32(bgep->cfg_handle, regno); 304 305 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 306 (void *)bgep, regno, bits, regval, regval & ~bits)); 307 308 regval &= ~bits; 309 pci_config_put32(bgep->cfg_handle, regno, regval); 310 } 311 312 #if BGE_IND_IO32 313 314 /* 315 * Indirect access to registers & RISC scratchpads, using config space 316 * accesses only. 317 * 318 * This isn't currently used, but someday we might want to use it for 319 * restoring the Subsystem Device/Vendor registers (which aren't directly 320 * writable in Config Space), or for downloading firmware into the RISCs 321 * 322 * In any case there are endian issues to be resolved before this code is 323 * enabled; the bizarre way that bytes get twisted by this chip AND by 324 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 325 * it's been thoroughly tested for all access sizes on all supported 326 * architectures (SPARC *and* x86!). 327 */ 328 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 329 #pragma inline(bge_ind_get32) 330 331 uint32_t 332 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 333 { 334 uint32_t val; 335 336 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 337 338 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 339 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 340 341 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 342 (void *)bgep, regno, val)); 343 344 val = LE_32(val); 345 346 return (val); 347 } 348 349 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 350 #pragma inline(bge_ind_put32) 351 352 void 353 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 354 { 355 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 356 (void *)bgep, regno, val)); 357 358 val = LE_32(val); 359 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 360 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 361 } 362 363 #endif /* BGE_IND_IO32 */ 364 365 #if BGE_DEBUGGING 366 367 static void bge_pci_check(bge_t *bgep); 368 #pragma no_inline(bge_pci_check) 369 370 static void 371 bge_pci_check(bge_t *bgep) 372 { 373 uint16_t pcistatus; 374 375 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 376 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 377 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 378 (void *)bgep, pcistatus)); 379 } 380 381 #endif /* BGE_DEBUGGING */ 382 383 /* 384 * Perform first-stage chip (re-)initialisation, using only config-space 385 * accesses: 386 * 387 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 388 * returning the data in the structure pointed to by <idp>. 389 * + Configure the target-mode endianness (swap) options. 390 * + Disable interrupts and enable Memory Space accesses. 391 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 392 * 393 * This sequence is adapted from Broadcom document 570X-PG102-R, 394 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 395 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 396 * 397 * This function MUST be called before any non-config-space accesses 398 * are made; on this first call <enable_dma> is B_FALSE, and it 399 * effectively performs steps 3-1(!) of the initialisation sequence 400 * (the rest are not required but should be harmless). 401 * 402 * It MUST also be called after a chip reset, as this disables 403 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 404 * it is effectively performing steps 6-8. 405 */ 406 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 407 #pragma no_inline(bge_chip_cfg_init) 408 409 void 410 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 411 { 412 ddi_acc_handle_t handle; 413 uint16_t command; 414 uint32_t mhcr; 415 uint16_t value16; 416 int i; 417 418 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 419 (void *)bgep, (void *)cidp, enable_dma)); 420 421 /* 422 * Step 3: save PCI cache line size and subsystem vendor ID 423 * 424 * Read all the config-space registers that characterise the 425 * chip, specifically vendor/device/revision/subsystem vendor 426 * and subsystem device id. We expect (but don't check) that 427 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 428 * 429 * Also save all bus-transaction related registers (cache-line 430 * size, bus-grant/latency parameters, etc). Some of these are 431 * cleared by reset, so we'll have to restore them later. This 432 * comes from the Broadcom document 570X-PG102-R ... 433 * 434 * Note: Broadcom document 570X-PG102-R seems to be in error 435 * here w.r.t. the offsets of the Subsystem Vendor ID and 436 * Subsystem (Device) ID registers, which are the opposite way 437 * round according to the PCI standard. For good measure, we 438 * save/restore both anyway. 439 */ 440 handle = bgep->cfg_handle; 441 442 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 443 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 444 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 445 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 446 447 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 448 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 449 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 450 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 451 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 452 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 453 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 454 455 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 456 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 457 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 458 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 459 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 460 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 461 cidp->vendor, cidp->device, cidp->revision)); 462 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 463 cidp->subven, cidp->subdev, cidp->asic_rev)); 464 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 465 cidp->clsize, cidp->latency, cidp->command)); 466 467 /* 468 * Step 2 (also step 6): disable and clear interrupts. 469 * Steps 11-13: configure PIO endianness options, and enable 470 * indirect register access. We'll also select any other 471 * options controlled by the MHCR (e.g. tagged status, mask 472 * interrupt mode) at this stage ... 473 * 474 * Note: internally, the chip is 64-bit and BIG-endian, but 475 * since it talks to the host over a (LITTLE-endian) PCI bus, 476 * it normally swaps bytes around at the PCI interface. 477 * However, the PCI host bridge on SPARC systems normally 478 * swaps the byte lanes around too, since SPARCs are also 479 * BIG-endian. So it turns out that on SPARC, the right 480 * option is to tell the chip to swap (and the host bridge 481 * will swap back again), whereas on x86 we ask the chip 482 * NOT to swap, so the natural little-endianness of the 483 * PCI bus is assumed. Then the only thing that doesn't 484 * automatically work right is access to an 8-byte register 485 * by a little-endian host; but we don't want to set the 486 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 487 * accesses don't go where expected ;-( So we live with 488 * that, and perform word-swaps in software in the few cases 489 * where a chip register is defined as an 8-byte value -- 490 * see the code below for details ... 491 * 492 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 493 * very clear in the register description in the PRM, but 494 * Broadcom document 570X-PG104-R page 248 explains a little 495 * more (under "Broadcom Mask Mode"). The bit changes the way 496 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 497 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 498 * way as the 5700 did, which isn't very convenient. Setting 499 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 500 * bit do just what its name says -- MASK the PCI #INTA output 501 * (i.e. deassert the signal at the pin) leaving all internal 502 * state unchanged. This is much more convenient for our 503 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 504 * 505 * Note: the inconvenient semantics of the interrupt mailbox 506 * (nonzero disables and acknowledges/clears the interrupt, 507 * zero enables AND CLEARS it) would make race conditions 508 * likely in the interrupt handler: 509 * 510 * (1) acknowledge & disable interrupts 511 * (2) while (more to do) 512 * process packets 513 * (3) enable interrupts -- also clears pending 514 * 515 * If the chip received more packets and internally generated 516 * an interrupt between the check at (2) and the mbox write 517 * at (3), this interrupt would be lost :-( 518 * 519 * The best way to avoid this is to use TAGGED STATUS mode, 520 * where the chip includes a unique tag in each status block 521 * update, and the host, when re-enabling interrupts, passes 522 * the last tag it saw back to the chip; then the chip can 523 * see whether the host is truly up to date, and regenerate 524 * its interrupt if not. 525 */ 526 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 527 MHCR_ENABLE_TAGGED_STATUS_MODE | 528 MHCR_MASK_INTERRUPT_MODE | 529 MHCR_CLEAR_INTERRUPT_INTA; 530 531 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 532 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 533 534 #ifdef _BIG_ENDIAN 535 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 536 #endif /* _BIG_ENDIAN */ 537 538 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 539 540 #ifdef BGE_IPMI_ASF 541 bgep->asf_wordswapped = B_FALSE; 542 #endif 543 /* 544 * Step 1 (also step 7): Enable PCI Memory Space accesses 545 * Disable Memory Write/Invalidate 546 * Enable or disable Bus Mastering 547 * 548 * Note that all other bits are taken from the original value saved 549 * the first time through here, rather than from the current register 550 * value, 'cos that will have been cleared by a soft RESET since. 551 * In this way we preserve the OBP/nexus-parent's preferred settings 552 * of the parity-error and system-error enable bits across multiple 553 * chip RESETs. 554 */ 555 command = bgep->chipid.command | PCI_COMM_MAE; 556 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 557 if (enable_dma) 558 command |= PCI_COMM_ME; 559 /* 560 * on BCM5714 revision A0, false parity error gets generated 561 * due to a logic bug. Provide a workaround by disabling parity 562 * error. 563 */ 564 if (((cidp->device == DEVICE_ID_5714C) || 565 (cidp->device == DEVICE_ID_5714S)) && 566 (cidp->revision == REVISION_ID_5714_A0)) { 567 command &= ~PCI_COMM_PARITY_DETECT; 568 } 569 pci_config_put16(handle, PCI_CONF_COMM, command); 570 571 /* 572 * On some PCI-E device, there were instances when 573 * the device was still link training. 574 */ 575 if (bgep->chipid.pci_type == BGE_PCI_E) { 576 i = 0; 577 value16 = pci_config_get16(handle, PCI_CONF_COMM); 578 while ((value16 != command) && (i < 100)) { 579 drv_usecwait(200); 580 value16 = pci_config_get16(handle, PCI_CONF_COMM); 581 ++i; 582 } 583 } 584 585 /* 586 * Clear any remaining error status bits 587 */ 588 pci_config_put16(handle, PCI_CONF_STAT, ~0); 589 590 /* 591 * Do following if and only if the device is NOT BCM5714C OR 592 * BCM5715C 593 */ 594 if (!((cidp->device == DEVICE_ID_5714C) || 595 (cidp->device == DEVICE_ID_5715C))) { 596 /* 597 * Make sure these indirect-access registers are sane 598 * rather than random after power-up or reset 599 */ 600 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 601 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 602 } 603 /* 604 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 605 */ 606 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 607 608 if (cidp->pci_type == BGE_PCI_E) 609 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 610 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 611 } 612 613 #ifdef __amd64 614 /* 615 * Distinguish CPU types 616 * 617 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 618 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 619 * for PCI-Express based network interface card. This is the work-around 620 * for those nics. 621 */ 622 static boolean_t bge_get_em64t_type(void); 623 #pragma inline(bge_get_em64t_type) 624 625 static boolean_t 626 bge_get_em64t_type(void) 627 { 628 629 return (x86_vendor == X86_VENDOR_Intel); 630 } 631 #endif 632 633 /* 634 * Operating register get/set access routines 635 */ 636 637 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 638 #pragma inline(bge_reg_get32) 639 640 uint32_t 641 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 642 { 643 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 644 (void *)bgep, regno)); 645 646 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 647 } 648 649 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 650 #pragma inline(bge_reg_put32) 651 652 void 653 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 654 { 655 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 656 (void *)bgep, regno, data)); 657 658 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 659 BGE_PCICHK(bgep); 660 } 661 662 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 663 #pragma inline(bge_reg_set32) 664 665 void 666 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 667 { 668 uint32_t regval; 669 670 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 671 (void *)bgep, regno, bits)); 672 673 regval = bge_reg_get32(bgep, regno); 674 regval |= bits; 675 bge_reg_put32(bgep, regno, regval); 676 } 677 678 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 679 #pragma inline(bge_reg_clr32) 680 681 void 682 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 683 { 684 uint32_t regval; 685 686 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 687 (void *)bgep, regno, bits)); 688 689 regval = bge_reg_get32(bgep, regno); 690 regval &= ~bits; 691 bge_reg_put32(bgep, regno, regval); 692 } 693 694 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 695 #pragma inline(bge_reg_get64) 696 697 static uint64_t 698 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 699 { 700 uint64_t regval; 701 702 #ifdef __amd64 703 if (bge_get_em64t_type()) { 704 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 705 regval <<= 32; 706 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 707 } else { 708 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 709 } 710 #else 711 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 712 #endif 713 714 #ifdef _LITTLE_ENDIAN 715 regval = (regval >> 32) | (regval << 32); 716 #endif /* _LITTLE_ENDIAN */ 717 718 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 719 (void *)bgep, regno, regval)); 720 721 return (regval); 722 } 723 724 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 725 #pragma inline(bge_reg_put64) 726 727 static void 728 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 729 { 730 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 731 (void *)bgep, regno, data)); 732 733 #ifdef _LITTLE_ENDIAN 734 data = ((data >> 32) | (data << 32)); 735 #endif /* _LITTLE_ENDIAN */ 736 737 #ifdef __amd64 738 if (bge_get_em64t_type()) { 739 ddi_put32(bgep->io_handle, 740 PIO_ADDR(bgep, regno), (uint32_t)data); 741 BGE_PCICHK(bgep); 742 ddi_put32(bgep->io_handle, 743 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 744 745 } else { 746 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 747 } 748 #else 749 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 750 #endif 751 752 BGE_PCICHK(bgep); 753 } 754 755 /* 756 * The DDI doesn't provide get/put functions for 128 bit data 757 * so we put RCBs out as two 64-bit chunks instead. 758 */ 759 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 760 #pragma inline(bge_reg_putrcb) 761 762 static void 763 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 764 { 765 uint64_t *p; 766 767 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 768 (void *)bgep, addr, rcbp->host_ring_addr, 769 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 770 771 ASSERT((addr % sizeof (*rcbp)) == 0); 772 773 p = (void *)rcbp; 774 bge_reg_put64(bgep, addr, *p++); 775 bge_reg_put64(bgep, addr+8, *p); 776 } 777 778 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 779 #pragma inline(bge_mbx_put) 780 781 void 782 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 783 { 784 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 785 (void *)bgep, regno, data)); 786 787 /* 788 * Mailbox registers are nominally 64 bits on the 5701, but 789 * the MSW isn't used. On the 5703, they're only 32 bits 790 * anyway. So here we just write the lower(!) 32 bits - 791 * remembering that the chip is big-endian, even though the 792 * PCI bus is little-endian ... 793 */ 794 #ifdef _BIG_ENDIAN 795 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 796 #else 797 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 798 #endif /* _BIG_ENDIAN */ 799 BGE_PCICHK(bgep); 800 } 801 802 #if BGE_DEBUGGING 803 804 void bge_led_mark(bge_t *bgep); 805 #pragma no_inline(bge_led_mark) 806 807 void 808 bge_led_mark(bge_t *bgep) 809 { 810 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 811 LED_CONTROL_1000MBPS_LED | 812 LED_CONTROL_100MBPS_LED | 813 LED_CONTROL_10MBPS_LED; 814 815 /* 816 * Blink all three LINK LEDs on simultaneously, then all off, 817 * then restore to automatic hardware control. This is used 818 * in laboratory testing to trigger a logic analyser or scope. 819 */ 820 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 821 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 822 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 823 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 824 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 825 } 826 827 #endif /* BGE_DEBUGGING */ 828 829 /* 830 * NIC on-chip memory access routines 831 * 832 * Only 32K of NIC memory is visible at a time, controlled by the 833 * Memory Window Base Address Register (in PCI config space). Once 834 * this is set, the 32K region of NIC-local memory that it refers 835 * to can be directly addressed in the upper 32K of the 64K of PCI 836 * memory space used for the device. 837 */ 838 839 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 840 #pragma inline(bge_nic_setwin) 841 842 static void 843 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 844 { 845 chip_id_t *cidp; 846 847 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 848 (void *)bgep, base)); 849 850 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 851 852 /* 853 * Don't do repeated zero data writes, 854 * if the device is BCM5714C/15C. 855 */ 856 cidp = &bgep->chipid; 857 if ((cidp->device == DEVICE_ID_5714C) || 858 (cidp->device == DEVICE_ID_5715C)) { 859 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 860 return; 861 /* Adjust lastWriteZeroData */ 862 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 863 B_TRUE : B_FALSE); 864 } 865 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 866 } 867 868 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 869 #pragma inline(bge_nic_get32) 870 871 static uint32_t 872 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 873 { 874 uint32_t data; 875 876 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 877 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 878 /* workaround for word swap error */ 879 if (addr & 4) 880 addr = addr - 4; 881 else 882 addr = addr + 4; 883 } 884 #endif 885 886 #ifdef __sparc 887 data = bge_nic_read32(bgep, addr); 888 #else 889 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 890 addr &= MWBAR_GRANULE_MASK; 891 addr += NIC_MEM_WINDOW_OFFSET; 892 893 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 894 #endif 895 896 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 897 (void *)bgep, addr, data)); 898 899 return (data); 900 } 901 902 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 903 #pragma inline(bge_nic_put32) 904 905 void 906 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 907 { 908 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 909 (void *)bgep, addr, data)); 910 911 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 912 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 913 /* workaround for word swap error */ 914 if (addr & 4) 915 addr = addr - 4; 916 else 917 addr = addr + 4; 918 } 919 #endif 920 921 #ifdef __sparc 922 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 923 data = LE_32(data); 924 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 925 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 926 #else 927 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 928 addr &= MWBAR_GRANULE_MASK; 929 addr += NIC_MEM_WINDOW_OFFSET; 930 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 931 BGE_PCICHK(bgep); 932 #endif 933 } 934 935 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 936 #pragma inline(bge_nic_get64) 937 938 static uint64_t 939 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 940 { 941 uint64_t data; 942 943 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 944 addr &= MWBAR_GRANULE_MASK; 945 addr += NIC_MEM_WINDOW_OFFSET; 946 947 #ifdef __amd64 948 if (bge_get_em64t_type()) { 949 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 950 data <<= 32; 951 data |= ddi_get32(bgep->io_handle, 952 PIO_ADDR(bgep, addr + 4)); 953 } else { 954 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 955 } 956 #else 957 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 958 #endif 959 960 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 961 (void *)bgep, addr, data)); 962 963 return (data); 964 } 965 966 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 967 #pragma inline(bge_nic_put64) 968 969 static void 970 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 971 { 972 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 973 (void *)bgep, addr, data)); 974 975 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 976 addr &= MWBAR_GRANULE_MASK; 977 addr += NIC_MEM_WINDOW_OFFSET; 978 979 #ifdef __amd64 980 if (bge_get_em64t_type()) { 981 ddi_put32(bgep->io_handle, 982 PIO_ADDR(bgep, addr), (uint32_t)data); 983 BGE_PCICHK(bgep); 984 ddi_put32(bgep->io_handle, 985 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 986 } else { 987 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 988 } 989 #else 990 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 991 #endif 992 993 BGE_PCICHK(bgep); 994 } 995 996 /* 997 * The DDI doesn't provide get/put functions for 128 bit data 998 * so we put RCBs out as two 64-bit chunks instead. 999 */ 1000 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1001 #pragma inline(bge_nic_putrcb) 1002 1003 static void 1004 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1005 { 1006 uint64_t *p; 1007 1008 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1009 (void *)bgep, addr, rcbp->host_ring_addr, 1010 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1011 1012 ASSERT((addr % sizeof (*rcbp)) == 0); 1013 1014 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1015 addr &= MWBAR_GRANULE_MASK; 1016 addr += NIC_MEM_WINDOW_OFFSET; 1017 1018 p = (void *)rcbp; 1019 #ifdef __amd64 1020 if (bge_get_em64t_type()) { 1021 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1022 (uint32_t)(*p)); 1023 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1024 (uint32_t)(*p >> 32)); 1025 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1026 (uint32_t)(*(p + 1))); 1027 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1028 (uint32_t)(*p >> 32)); 1029 1030 } else { 1031 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1032 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1033 } 1034 #else 1035 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1036 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1037 #endif 1038 1039 BGE_PCICHK(bgep); 1040 } 1041 1042 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1043 #pragma inline(bge_nic_zero) 1044 1045 static void 1046 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1047 { 1048 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1049 (void *)bgep, addr, nbytes)); 1050 1051 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1052 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1053 1054 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1055 addr &= MWBAR_GRANULE_MASK; 1056 addr += NIC_MEM_WINDOW_OFFSET; 1057 1058 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1059 nbytes, 1, DDI_DATA_SZ08_ACC); 1060 BGE_PCICHK(bgep); 1061 } 1062 1063 /* 1064 * MII (PHY) register get/set access routines 1065 * 1066 * These use the chip's MII auto-access method, controlled by the 1067 * MII Communication register at 0x044c, so the CPU doesn't have 1068 * to fiddle with the individual bits. 1069 */ 1070 1071 #undef BGE_DBG 1072 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1073 1074 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1075 uint16_t data, uint32_t cmd); 1076 #pragma no_inline(bge_mii_access) 1077 1078 static uint16_t 1079 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1080 { 1081 uint32_t timeout; 1082 uint32_t regval1; 1083 uint32_t regval2; 1084 1085 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1086 (void *)bgep, regno, data, cmd)); 1087 1088 ASSERT(mutex_owned(bgep->genlock)); 1089 1090 /* 1091 * Assemble the command ... 1092 */ 1093 cmd |= data << MI_COMMS_DATA_SHIFT; 1094 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1095 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1096 cmd |= MI_COMMS_START; 1097 1098 /* 1099 * Wait for any command already in progress ... 1100 * 1101 * Note: this *shouldn't* ever find that there is a command 1102 * in progress, because we already hold the <genlock> mutex. 1103 * Nonetheless, we have sometimes seen the MI_COMMS_START 1104 * bit set here -- it seems that the chip can initiate MII 1105 * accesses internally, even with polling OFF. 1106 */ 1107 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1108 for (timeout = 100; ; ) { 1109 if ((regval2 & MI_COMMS_START) == 0) { 1110 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1111 break; 1112 } 1113 if (--timeout == 0) 1114 break; 1115 drv_usecwait(10); 1116 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1117 } 1118 1119 if (timeout == 0) 1120 return ((uint16_t)~0u); 1121 1122 if (timeout != 100) 1123 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1124 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1125 cmd, 10*(100-timeout), regval1, regval2)); 1126 1127 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1128 for (timeout = 1000; ; ) { 1129 if ((regval1 & MI_COMMS_START) == 0) 1130 break; 1131 if (--timeout == 0) 1132 break; 1133 drv_usecwait(10); 1134 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1135 } 1136 1137 /* 1138 * Drop out early if the READ FAILED bit is set -- this chip 1139 * could be a 5703/4S, with a SerDes instead of a PHY! 1140 */ 1141 if (regval2 & MI_COMMS_READ_FAILED) 1142 return ((uint16_t)~0u); 1143 1144 if (timeout == 0) 1145 return ((uint16_t)~0u); 1146 1147 /* 1148 * The PRM says to wait 5us after seeing the START bit clear 1149 * and then re-read the register to get the final value of the 1150 * data field, in order to avoid a race condition where the 1151 * START bit is clear but the data field isn't yet valid. 1152 * 1153 * Note: we don't actually seem to be encounter this race; 1154 * except when the START bit is seen set again (see below), 1155 * the data field doesn't change during this 5us interval. 1156 */ 1157 drv_usecwait(5); 1158 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1159 1160 /* 1161 * Unfortunately, when following the PRMs instructions above, 1162 * we have occasionally seen the START bit set again(!) in the 1163 * value read after the 5us delay. This seems to be due to the 1164 * chip autonomously starting another MII access internally. 1165 * In such cases, the command/data/etc fields relate to the 1166 * internal command, rather than the one that we thought had 1167 * just finished. So in this case, we fall back to returning 1168 * the data from the original read that showed START clear. 1169 */ 1170 if (regval2 & MI_COMMS_START) { 1171 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1172 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1173 cmd, regval1, regval2)); 1174 regval2 = regval1; 1175 } 1176 1177 if (regval2 & MI_COMMS_START) 1178 return ((uint16_t)~0u); 1179 1180 if (regval2 & MI_COMMS_READ_FAILED) 1181 return ((uint16_t)~0u); 1182 1183 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1184 } 1185 1186 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1187 #pragma no_inline(bge_mii_get16) 1188 1189 uint16_t 1190 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1191 { 1192 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1193 (void *)bgep, regno)); 1194 1195 ASSERT(mutex_owned(bgep->genlock)); 1196 1197 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1198 } 1199 1200 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1201 #pragma no_inline(bge_mii_put16) 1202 1203 void 1204 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1205 { 1206 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1207 (void *)bgep, regno, data)); 1208 1209 ASSERT(mutex_owned(bgep->genlock)); 1210 1211 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1212 } 1213 1214 #undef BGE_DBG 1215 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1216 1217 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1218 1219 /* 1220 * Basic SEEPROM get/set access routine 1221 * 1222 * This uses the chip's SEEPROM auto-access method, controlled by the 1223 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1224 * doesn't have to fiddle with the individual bits. 1225 * 1226 * The caller should hold <genlock> and *also* have already acquired 1227 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1228 * 1229 * Return value: 1230 * 0 on success, 1231 * ENODATA on access timeout (maybe retryable: device may just be busy) 1232 * EPROTO on other h/w or s/w errors. 1233 * 1234 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1235 * from a (successful) SEEPROM_ACCESS_READ. 1236 */ 1237 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1238 uint32_t *dp); 1239 #pragma no_inline(bge_seeprom_access) 1240 1241 static int 1242 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1243 { 1244 uint32_t tries; 1245 uint32_t regval; 1246 1247 ASSERT(mutex_owned(bgep->genlock)); 1248 1249 /* 1250 * On the newer chips that support both SEEPROM & Flash, we need 1251 * to specifically enable SEEPROM access (Flash is the default). 1252 * On older chips, we don't; SEEPROM is the only NVtype supported, 1253 * and the NVM control registers don't exist ... 1254 */ 1255 switch (bgep->chipid.nvtype) { 1256 case BGE_NVTYPE_NONE: 1257 case BGE_NVTYPE_UNKNOWN: 1258 _NOTE(NOTREACHED) 1259 case BGE_NVTYPE_SEEPROM: 1260 break; 1261 1262 case BGE_NVTYPE_LEGACY_SEEPROM: 1263 case BGE_NVTYPE_UNBUFFERED_FLASH: 1264 case BGE_NVTYPE_BUFFERED_FLASH: 1265 default: 1266 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1267 NVM_CFG1_LEGACY_SEEPROM_MODE); 1268 break; 1269 } 1270 1271 /* 1272 * Check there's no command in progress. 1273 * 1274 * Note: this *shouldn't* ever find that there is a command 1275 * in progress, because we already hold the <genlock> mutex. 1276 * Also, to ensure we don't have a conflict with the chip's 1277 * internal firmware or a process accessing the same (shared) 1278 * SEEPROM through the other port of a 5704, we've already 1279 * been through the "software arbitration" protocol. 1280 * So this is just a final consistency check: we shouldn't 1281 * see EITHER the START bit (command started but not complete) 1282 * OR the COMPLETE bit (command completed but not cleared). 1283 */ 1284 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1285 if (regval & SEEPROM_ACCESS_START) 1286 return (EPROTO); 1287 if (regval & SEEPROM_ACCESS_COMPLETE) 1288 return (EPROTO); 1289 1290 /* 1291 * Assemble the command ... 1292 */ 1293 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1294 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1295 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1296 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1297 cmd |= SEEPROM_ACCESS_START; 1298 cmd |= SEEPROM_ACCESS_COMPLETE; 1299 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1300 1301 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1302 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1303 1304 /* 1305 * By observation, a successful access takes ~20us on a 5703/4, 1306 * but apparently much longer (up to 1000us) on the obsolescent 1307 * BCM5700/BCM5701. We want to be sure we don't get any false 1308 * timeouts here; but OTOH, we don't want a bogus access to lock 1309 * out interrupts for longer than necessary. So we'll allow up 1310 * to 1000us ... 1311 */ 1312 for (tries = 0; tries < 1000; ++tries) { 1313 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1314 if (regval & SEEPROM_ACCESS_COMPLETE) 1315 break; 1316 drv_usecwait(1); 1317 } 1318 1319 if (regval & SEEPROM_ACCESS_COMPLETE) { 1320 /* 1321 * All OK; read the SEEPROM data register, then write back 1322 * the value read from the address register in order to 1323 * clear the <complete> bit and leave the SEEPROM access 1324 * state machine idle, ready for the next access ... 1325 */ 1326 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1327 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1328 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1329 return (0); 1330 } 1331 1332 /* 1333 * Hmm ... what happened here? 1334 * 1335 * Most likely, the user addressed a non-existent SEEPROM. Or 1336 * maybe the SEEPROM was busy internally (e.g. processing a write) 1337 * and didn't respond to being addressed. Either way, it's left 1338 * the SEEPROM access state machine wedged. So we'll reset it 1339 * before we leave, so it's ready for next time ... 1340 */ 1341 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1342 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1343 return (ENODATA); 1344 } 1345 1346 /* 1347 * Basic Flash get/set access routine 1348 * 1349 * These use the chip's Flash auto-access method, controlled by the 1350 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1351 * fiddle with the individual bits. 1352 * 1353 * The caller should hold <genlock> and *also* have already acquired 1354 * the right to access the Flash, via bge_nvmem_acquire() above. 1355 * 1356 * Return value: 1357 * 0 on success, 1358 * ENODATA on access timeout (maybe retryable: device may just be busy) 1359 * ENODEV if the NVmem device is missing or otherwise unusable 1360 * 1361 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1362 * from a (successful) NVM_FLASH_CMD_RD. 1363 */ 1364 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1365 uint32_t *dp); 1366 #pragma no_inline(bge_flash_access) 1367 1368 static int 1369 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1370 { 1371 uint32_t tries; 1372 uint32_t regval; 1373 1374 ASSERT(mutex_owned(bgep->genlock)); 1375 1376 /* 1377 * On the newer chips that support both SEEPROM & Flash, we need 1378 * to specifically disable SEEPROM access while accessing Flash. 1379 * The older chips don't support Flash, and the NVM registers don't 1380 * exist, so we shouldn't be here at all! 1381 */ 1382 switch (bgep->chipid.nvtype) { 1383 case BGE_NVTYPE_NONE: 1384 case BGE_NVTYPE_UNKNOWN: 1385 _NOTE(NOTREACHED) 1386 case BGE_NVTYPE_SEEPROM: 1387 return (ENODEV); 1388 1389 case BGE_NVTYPE_LEGACY_SEEPROM: 1390 case BGE_NVTYPE_UNBUFFERED_FLASH: 1391 case BGE_NVTYPE_BUFFERED_FLASH: 1392 default: 1393 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1394 NVM_CFG1_LEGACY_SEEPROM_MODE); 1395 break; 1396 } 1397 1398 /* 1399 * Assemble the command ... 1400 */ 1401 addr &= NVM_FLASH_ADDR_MASK; 1402 cmd |= NVM_FLASH_CMD_DOIT; 1403 cmd |= NVM_FLASH_CMD_FIRST; 1404 cmd |= NVM_FLASH_CMD_LAST; 1405 cmd |= NVM_FLASH_CMD_DONE; 1406 1407 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1408 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1409 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1410 1411 /* 1412 * Allow up to 1000ms ... 1413 */ 1414 for (tries = 0; tries < 1000; ++tries) { 1415 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1416 if (regval & NVM_FLASH_CMD_DONE) 1417 break; 1418 drv_usecwait(1); 1419 } 1420 1421 if (regval & NVM_FLASH_CMD_DONE) { 1422 /* 1423 * All OK; read the data from the Flash read register 1424 */ 1425 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1426 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1427 return (0); 1428 } 1429 1430 /* 1431 * Hmm ... what happened here? 1432 * 1433 * Most likely, the user addressed a non-existent Flash. Or 1434 * maybe the Flash was busy internally (e.g. processing a write) 1435 * and didn't respond to being addressed. Either way, there's 1436 * nothing we can here ... 1437 */ 1438 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1439 return (ENODATA); 1440 } 1441 1442 /* 1443 * The next two functions regulate access to the NVram (if fitted). 1444 * 1445 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1446 * (SPI) interface, but they can be accessed through either port. These 1447 * are managed by different instance of this driver and have no software 1448 * state in common. 1449 * 1450 * In addition (and even on a single core chip) the chip's internal 1451 * firmware can access the SEEPROM/Flash, most notably after a RESET 1452 * when it may download code to run internally. 1453 * 1454 * So we need to arbitrate between these various software agents. For 1455 * this purpose, the chip provides the Software Arbitration Register, 1456 * which implements hardware(!) arbitration. 1457 * 1458 * This functionality didn't exist on older (5700/5701) chips, so there's 1459 * nothing we can do by way of arbitration on those; also, if there's no 1460 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1461 * nothing to do. 1462 * 1463 * The internal firmware appears to use Request 0, which is the highest 1464 * priority. So we'd like to use Request 2, leaving one higher and one 1465 * lower for any future developments ... but apparently this doesn't 1466 * always work. So for now, the code uses Request 1 ;-( 1467 */ 1468 1469 #define NVM_READ_REQ NVM_READ_REQ1 1470 #define NVM_RESET_REQ NVM_RESET_REQ1 1471 #define NVM_SET_REQ NVM_SET_REQ1 1472 1473 static void bge_nvmem_relinquish(bge_t *bgep); 1474 #pragma no_inline(bge_nvmem_relinquish) 1475 1476 static void 1477 bge_nvmem_relinquish(bge_t *bgep) 1478 { 1479 ASSERT(mutex_owned(bgep->genlock)); 1480 1481 switch (bgep->chipid.nvtype) { 1482 case BGE_NVTYPE_NONE: 1483 case BGE_NVTYPE_UNKNOWN: 1484 _NOTE(NOTREACHED) 1485 return; 1486 1487 case BGE_NVTYPE_SEEPROM: 1488 /* 1489 * No arbitration performed, no release needed 1490 */ 1491 return; 1492 1493 case BGE_NVTYPE_LEGACY_SEEPROM: 1494 case BGE_NVTYPE_UNBUFFERED_FLASH: 1495 case BGE_NVTYPE_BUFFERED_FLASH: 1496 default: 1497 break; 1498 } 1499 1500 /* 1501 * Our own request should be present (whether or not granted) ... 1502 */ 1503 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1504 1505 /* 1506 * ... this will make it go away. 1507 */ 1508 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1509 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1510 } 1511 1512 /* 1513 * Arbitrate for access to the NVmem, if necessary 1514 * 1515 * Return value: 1516 * 0 on success 1517 * EAGAIN if the device is in use (retryable) 1518 * ENODEV if the NVmem device is missing or otherwise unusable 1519 */ 1520 static int bge_nvmem_acquire(bge_t *bgep); 1521 #pragma no_inline(bge_nvmem_acquire) 1522 1523 static int 1524 bge_nvmem_acquire(bge_t *bgep) 1525 { 1526 uint32_t regval; 1527 uint32_t tries; 1528 1529 ASSERT(mutex_owned(bgep->genlock)); 1530 1531 switch (bgep->chipid.nvtype) { 1532 case BGE_NVTYPE_NONE: 1533 case BGE_NVTYPE_UNKNOWN: 1534 /* 1535 * Access denied: no (recognisable) device fitted 1536 */ 1537 return (ENODEV); 1538 1539 case BGE_NVTYPE_SEEPROM: 1540 /* 1541 * Access granted: no arbitration needed (or possible) 1542 */ 1543 return (0); 1544 1545 case BGE_NVTYPE_LEGACY_SEEPROM: 1546 case BGE_NVTYPE_UNBUFFERED_FLASH: 1547 case BGE_NVTYPE_BUFFERED_FLASH: 1548 default: 1549 /* 1550 * Access conditional: conduct arbitration protocol 1551 */ 1552 break; 1553 } 1554 1555 /* 1556 * We're holding the per-port mutex <genlock>, so no-one other 1557 * thread can be attempting to access the NVmem through *this* 1558 * port. But it could be in use by the *other* port (of a 5704), 1559 * or by the chip's internal firmware, so we have to go through 1560 * the full (hardware) arbitration protocol ... 1561 * 1562 * Note that *because* we're holding <genlock>, the interrupt handler 1563 * won't be able to progress. So we're only willing to spin for a 1564 * fairly short time. Specifically: 1565 * 1566 * We *must* wait long enough for the hardware to resolve all 1567 * requests and determine the winner. Fortunately, this is 1568 * "almost instantaneous", even as observed by GHz CPUs. 1569 * 1570 * A successful access by another Solaris thread (via either 1571 * port) typically takes ~20us. So waiting a bit longer than 1572 * that will give a good chance of success, if the other user 1573 * *is* another thread on the other port. 1574 * 1575 * However, the internal firmware can hold on to the NVmem 1576 * for *much* longer: at least 10 milliseconds just after a 1577 * RESET, and maybe even longer if the NVmem actually contains 1578 * code to download and run on the internal CPUs. 1579 * 1580 * So, we'll allow 50us; if that's not enough then it's up to the 1581 * caller to retry later (hence the choice of return code EAGAIN). 1582 */ 1583 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1584 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1585 1586 for (tries = 0; tries < 50; ++tries) { 1587 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1588 if (regval & NVM_WON_REQ1) 1589 break; 1590 drv_usecwait(1); 1591 } 1592 1593 if (regval & NVM_WON_REQ1) { 1594 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1595 return (0); 1596 } 1597 1598 /* 1599 * Somebody else must be accessing the NVmem, so abandon our 1600 * attempt take control of it. The caller can try again later ... 1601 */ 1602 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1603 bge_nvmem_relinquish(bgep); 1604 return (EAGAIN); 1605 } 1606 1607 /* 1608 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1609 * write protect line in such a way that the NVmem is protected when 1610 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1611 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1612 * 1613 * Note: there's only one set of GPIO pins on a 5704, even though they 1614 * can be accessed through either port. So the chip has to resolve what 1615 * happens if the two ports program a single pin differently ... the rule 1616 * it uses is that if the ports disagree about the *direction* of a pin, 1617 * "output" wins over "input", but if they disagree about its *value* as 1618 * an output, then the pin is TRISTATED instead! In such a case, no-one 1619 * wins, and the external signal does whatever the external circuitry 1620 * defines as the default -- which we've assumed is the PROTECTED state. 1621 * So, we always change GPIO1 back to being an *input* whenever we're not 1622 * specifically using it to unprotect the NVmem. This allows either port 1623 * to update the NVmem, although obviously only one at a time! 1624 * 1625 * The caller should hold <genlock> and *also* have already acquired the 1626 * right to access the NVmem, via bge_nvmem_acquire() above. 1627 */ 1628 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1629 #pragma inline(bge_nvmem_protect) 1630 1631 static void 1632 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1633 { 1634 uint32_t regval; 1635 1636 ASSERT(mutex_owned(bgep->genlock)); 1637 1638 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1639 if (protect) { 1640 regval |= MLCR_MISC_PINS_OUTPUT_1; 1641 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1642 } else { 1643 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1644 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1645 } 1646 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1647 } 1648 1649 /* 1650 * Now put it all together ... 1651 * 1652 * Try to acquire control of the NVmem; if successful, then: 1653 * unprotect it (if we want to write to it) 1654 * perform the requested access 1655 * reprotect it (after a write) 1656 * relinquish control 1657 * 1658 * Return value: 1659 * 0 on success, 1660 * EAGAIN if the device is in use (retryable) 1661 * ENODATA on access timeout (maybe retryable: device may just be busy) 1662 * ENODEV if the NVmem device is missing or otherwise unusable 1663 * EPROTO on other h/w or s/w errors. 1664 */ 1665 static int 1666 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1667 { 1668 int err; 1669 1670 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1671 switch (cmd) { 1672 case BGE_SEE_READ: 1673 err = bge_seeprom_access(bgep, 1674 SEEPROM_ACCESS_READ, addr, dp); 1675 break; 1676 1677 case BGE_SEE_WRITE: 1678 bge_nvmem_protect(bgep, B_FALSE); 1679 err = bge_seeprom_access(bgep, 1680 SEEPROM_ACCESS_WRITE, addr, dp); 1681 bge_nvmem_protect(bgep, B_TRUE); 1682 break; 1683 1684 case BGE_FLASH_READ: 1685 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1686 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1687 bge_reg_set32(bgep, NVM_ACCESS_REG, 1688 NVM_ACCESS_ENABLE); 1689 } 1690 err = bge_flash_access(bgep, 1691 NVM_FLASH_CMD_RD, addr, dp); 1692 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_ACCESS_ENABLE); 1696 } 1697 break; 1698 1699 case BGE_FLASH_WRITE: 1700 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1701 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1702 bge_reg_set32(bgep, NVM_ACCESS_REG, 1703 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1704 } 1705 bge_nvmem_protect(bgep, B_FALSE); 1706 err = bge_flash_access(bgep, 1707 NVM_FLASH_CMD_WR, addr, dp); 1708 bge_nvmem_protect(bgep, B_TRUE); 1709 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1710 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1711 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1712 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1713 } 1714 1715 break; 1716 1717 default: 1718 _NOTE(NOTREACHED) 1719 break; 1720 } 1721 bge_nvmem_relinquish(bgep); 1722 } 1723 1724 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1725 return (err); 1726 } 1727 1728 /* 1729 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1730 */ 1731 static uint64_t bge_get_nvmac(bge_t *bgep); 1732 #pragma no_inline(bge_get_nvmac) 1733 1734 static uint64_t 1735 bge_get_nvmac(bge_t *bgep) 1736 { 1737 uint32_t mac_high; 1738 uint32_t mac_low; 1739 uint32_t addr; 1740 uint32_t cmd; 1741 uint64_t mac; 1742 1743 BGE_TRACE(("bge_get_nvmac($%p)", 1744 (void *)bgep)); 1745 1746 switch (bgep->chipid.nvtype) { 1747 case BGE_NVTYPE_NONE: 1748 case BGE_NVTYPE_UNKNOWN: 1749 default: 1750 return (0ULL); 1751 1752 case BGE_NVTYPE_SEEPROM: 1753 case BGE_NVTYPE_LEGACY_SEEPROM: 1754 cmd = BGE_SEE_READ; 1755 break; 1756 1757 case BGE_NVTYPE_UNBUFFERED_FLASH: 1758 case BGE_NVTYPE_BUFFERED_FLASH: 1759 cmd = BGE_FLASH_READ; 1760 break; 1761 } 1762 1763 addr = NVMEM_DATA_MAC_ADDRESS; 1764 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1765 return (0ULL); 1766 addr += 4; 1767 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1768 return (0ULL); 1769 1770 /* 1771 * The Broadcom chip is natively BIG-endian, so that's how the 1772 * MAC address is represented in NVmem. We may need to swap it 1773 * around on a little-endian host ... 1774 */ 1775 #ifdef _BIG_ENDIAN 1776 mac = mac_high; 1777 mac = mac << 32; 1778 mac |= mac_low; 1779 #else 1780 mac = BGE_BSWAP_32(mac_high); 1781 mac = mac << 32; 1782 mac |= BGE_BSWAP_32(mac_low); 1783 #endif /* _BIG_ENDIAN */ 1784 1785 return (mac); 1786 } 1787 1788 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1789 1790 /* 1791 * Dummy version for when we're not supporting NVmem access 1792 */ 1793 static uint64_t bge_get_nvmac(bge_t *bgep); 1794 #pragma inline(bge_get_nvmac) 1795 1796 static uint64_t 1797 bge_get_nvmac(bge_t *bgep) 1798 { 1799 _NOTE(ARGUNUSED(bgep)) 1800 return (0ULL); 1801 } 1802 1803 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1804 1805 /* 1806 * Determine the type of NVmem that is (or may be) attached to this chip, 1807 */ 1808 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1809 #pragma no_inline(bge_nvmem_id) 1810 1811 static enum bge_nvmem_type 1812 bge_nvmem_id(bge_t *bgep) 1813 { 1814 enum bge_nvmem_type nvtype; 1815 uint32_t config1; 1816 1817 BGE_TRACE(("bge_nvmem_id($%p)", 1818 (void *)bgep)); 1819 1820 switch (bgep->chipid.device) { 1821 default: 1822 /* 1823 * We shouldn't get here; it means we don't recognise 1824 * the chip, which means we don't know how to determine 1825 * what sort of NVmem (if any) it has. So we'll say 1826 * NONE, to disable the NVmem access code ... 1827 */ 1828 nvtype = BGE_NVTYPE_NONE; 1829 break; 1830 1831 case DEVICE_ID_5700: 1832 case DEVICE_ID_5700x: 1833 case DEVICE_ID_5701: 1834 /* 1835 * These devices support *only* SEEPROMs 1836 */ 1837 nvtype = BGE_NVTYPE_SEEPROM; 1838 break; 1839 1840 case DEVICE_ID_5702: 1841 case DEVICE_ID_5702fe: 1842 case DEVICE_ID_5703C: 1843 case DEVICE_ID_5703S: 1844 case DEVICE_ID_5704C: 1845 case DEVICE_ID_5704S: 1846 case DEVICE_ID_5704: 1847 case DEVICE_ID_5705M: 1848 case DEVICE_ID_5705C: 1849 case DEVICE_ID_5705_2: 1850 case DEVICE_ID_5706: 1851 case DEVICE_ID_5782: 1852 case DEVICE_ID_5788: 1853 case DEVICE_ID_5789: 1854 case DEVICE_ID_5751: 1855 case DEVICE_ID_5751M: 1856 case DEVICE_ID_5752: 1857 case DEVICE_ID_5752M: 1858 case DEVICE_ID_5754: 1859 case DEVICE_ID_5755: 1860 case DEVICE_ID_5721: 1861 case DEVICE_ID_5714C: 1862 case DEVICE_ID_5714S: 1863 case DEVICE_ID_5715C: 1864 case DEVICE_ID_5715S: 1865 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1866 if (config1 & NVM_CFG1_FLASH_MODE) 1867 if (config1 & NVM_CFG1_BUFFERED_MODE) 1868 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1869 else 1870 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1871 else 1872 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1873 break; 1874 } 1875 1876 return (nvtype); 1877 } 1878 1879 #undef BGE_DBG 1880 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1881 1882 static void 1883 bge_init_recv_rule(bge_t *bgep) 1884 { 1885 bge_recv_rule_t *rulep; 1886 uint32_t i; 1887 1888 /* 1889 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1890 * 1. to direct UDP traffic, set: 1891 * rulep->control = RULE_PROTO_CONTROL; 1892 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1893 * 2. to direct ICMP traffic, set: 1894 * rulep->control = RULE_PROTO_CONTROL; 1895 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1896 * 3. to direct traffic by source ip, set: 1897 * rulep->control = RULE_SIP_CONTROL; 1898 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1899 */ 1900 rulep = bgep->recv_rules; 1901 rulep->control = RULE_PROTO_CONTROL; 1902 rulep->mask_value = RULE_TCP_MASK_VALUE; 1903 1904 /* 1905 * set receive rule registers 1906 */ 1907 rulep = bgep->recv_rules; 1908 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1909 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1910 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1911 } 1912 } 1913 1914 /* 1915 * Using the values captured by bge_chip_cfg_init(), and additional probes 1916 * as required, characterise the chip fully: determine the label by which 1917 * to refer to this chip, the correct settings for various registers, and 1918 * of course whether the device and/or subsystem are supported! 1919 */ 1920 int bge_chip_id_init(bge_t *bgep); 1921 #pragma no_inline(bge_chip_id_init) 1922 1923 int 1924 bge_chip_id_init(bge_t *bgep) 1925 { 1926 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1927 boolean_t sys_ok; 1928 boolean_t dev_ok; 1929 chip_id_t *cidp; 1930 uint32_t subid; 1931 char *devname; 1932 char *sysname; 1933 int *ids; 1934 int err; 1935 uint_t i; 1936 1937 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1938 1939 sys_ok = dev_ok = B_FALSE; 1940 cidp = &bgep->chipid; 1941 1942 /* 1943 * Check the PCI device ID to determine the generic chip type and 1944 * select parameters that depend on this. 1945 * 1946 * Note: because the SPARC platforms in general don't fit the 1947 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1948 * as zero - which is why we use <asic_rev> rather than <revision> 1949 * below ... 1950 * 1951 * Note: in general we can't distinguish between the Copper/SerDes 1952 * versions by ID alone, as some Copper devices (e.g. some but not 1953 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1954 * treat them the same here, and the MII code works out the media 1955 * type later on ... 1956 */ 1957 cidp->mbuf_base = bge_mbuf_pool_base; 1958 cidp->mbuf_length = bge_mbuf_pool_len; 1959 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1960 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1961 cidp->pci_type = BGE_PCI_X; 1962 cidp->statistic_type = BGE_STAT_BLK; 1963 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1964 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1965 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1966 1967 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1968 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1969 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1970 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1971 1972 cidp->msi_enabled = B_FALSE; 1973 1974 switch (cidp->device) { 1975 case DEVICE_ID_5700: 1976 case DEVICE_ID_5700x: 1977 cidp->chip_label = 5700; 1978 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1979 break; 1980 1981 case DEVICE_ID_5701: 1982 cidp->chip_label = 5701; 1983 dev_ok = B_TRUE; 1984 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1985 break; 1986 1987 case DEVICE_ID_5702: 1988 case DEVICE_ID_5702fe: 1989 cidp->chip_label = 5702; 1990 dev_ok = B_TRUE; 1991 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1992 cidp->pci_type = BGE_PCI; 1993 break; 1994 1995 case DEVICE_ID_5703C: 1996 case DEVICE_ID_5703S: 1997 case DEVICE_ID_5703: 1998 /* 1999 * Revision A0 of the 5703/5793 had various errata 2000 * that we can't or don't work around, so it's not 2001 * supported, but all later versions are 2002 */ 2003 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2004 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2005 dev_ok = B_TRUE; 2006 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2007 break; 2008 2009 case DEVICE_ID_5704C: 2010 case DEVICE_ID_5704S: 2011 case DEVICE_ID_5704: 2012 /* 2013 * Revision A0 of the 5704/5794 had various errata 2014 * but we have workarounds, so it *is* supported. 2015 */ 2016 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2017 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2018 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2019 dev_ok = B_TRUE; 2020 if (cidp->asic_rev < MHCR_CHIP_REV_5704_B0) 2021 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2022 break; 2023 2024 case DEVICE_ID_5705C: 2025 case DEVICE_ID_5705M: 2026 case DEVICE_ID_5705MA3: 2027 case DEVICE_ID_5705F: 2028 case DEVICE_ID_5705_2: 2029 case DEVICE_ID_5754: 2030 if (cidp->device == DEVICE_ID_5754) { 2031 cidp->chip_label = 5754; 2032 cidp->pci_type = BGE_PCI_E; 2033 } else { 2034 cidp->chip_label = 5705; 2035 cidp->pci_type = BGE_PCI; 2036 } 2037 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2038 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2039 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2040 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2041 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2042 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2043 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2044 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2045 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2046 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2047 cidp->statistic_type = BGE_STAT_REG; 2048 dev_ok = B_TRUE; 2049 break; 2050 2051 case DEVICE_ID_5753: 2052 cidp->chip_label = 5753; 2053 cidp->pci_type = BGE_PCI_E; 2054 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2055 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2056 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2057 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2058 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2059 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2060 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2061 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2062 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2063 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2064 cidp->statistic_type = BGE_STAT_REG; 2065 dev_ok = B_TRUE; 2066 break; 2067 2068 case DEVICE_ID_5755: 2069 cidp->chip_label = 5755; 2070 cidp->pci_type = BGE_PCI_E; 2071 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2072 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2073 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2074 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2075 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2076 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2077 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2078 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2079 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2080 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2081 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2082 cidp->statistic_type = BGE_STAT_REG; 2083 dev_ok = B_TRUE; 2084 break; 2085 2086 case DEVICE_ID_5706: 2087 cidp->chip_label = 5706; 2088 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2089 break; 2090 2091 case DEVICE_ID_5782: 2092 /* 2093 * Apart from the label, we treat this as a 5705(?) 2094 */ 2095 cidp->chip_label = 5782; 2096 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2097 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2098 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2099 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2100 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2101 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2102 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2103 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2104 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2105 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2106 cidp->statistic_type = BGE_STAT_REG; 2107 dev_ok = B_TRUE; 2108 break; 2109 2110 case DEVICE_ID_5788: 2111 /* 2112 * Apart from the label, we treat this as a 5705(?) 2113 */ 2114 cidp->chip_label = 5788; 2115 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2116 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2117 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2118 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2119 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2120 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2121 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2122 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2123 cidp->statistic_type = BGE_STAT_REG; 2124 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2125 dev_ok = B_TRUE; 2126 break; 2127 2128 case DEVICE_ID_5714C: 2129 if (cidp->revision >= REVISION_ID_5714_A2) 2130 cidp->msi_enabled = bge_enable_msi; 2131 /* FALLTHRU */ 2132 case DEVICE_ID_5714S: 2133 cidp->chip_label = 5714; 2134 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2135 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2136 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2137 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2138 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2139 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2140 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2141 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2142 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2143 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2144 cidp->pci_type = BGE_PCI_E; 2145 cidp->statistic_type = BGE_STAT_REG; 2146 dev_ok = B_TRUE; 2147 break; 2148 2149 case DEVICE_ID_5715C: 2150 case DEVICE_ID_5715S: 2151 cidp->chip_label = 5715; 2152 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2153 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2154 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2155 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2156 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2157 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2158 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2159 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2160 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2161 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2162 cidp->pci_type = BGE_PCI_E; 2163 cidp->statistic_type = BGE_STAT_REG; 2164 if (cidp->revision >= REVISION_ID_5715_A2) 2165 cidp->msi_enabled = bge_enable_msi; 2166 dev_ok = B_TRUE; 2167 break; 2168 2169 case DEVICE_ID_5721: 2170 cidp->chip_label = 5721; 2171 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2172 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2173 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2174 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2175 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2176 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2177 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2178 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2179 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2180 cidp->pci_type = BGE_PCI_E; 2181 cidp->statistic_type = BGE_STAT_REG; 2182 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2183 dev_ok = B_TRUE; 2184 break; 2185 2186 case DEVICE_ID_5751: 2187 case DEVICE_ID_5751M: 2188 cidp->chip_label = 5751; 2189 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2190 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2191 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2192 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2193 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2194 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2195 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2196 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2197 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2198 cidp->pci_type = BGE_PCI_E; 2199 cidp->statistic_type = BGE_STAT_REG; 2200 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2201 dev_ok = B_TRUE; 2202 break; 2203 2204 case DEVICE_ID_5752: 2205 case DEVICE_ID_5752M: 2206 cidp->chip_label = 5752; 2207 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2208 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2209 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2210 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2211 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2212 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2213 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2214 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2215 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2216 cidp->pci_type = BGE_PCI_E; 2217 cidp->statistic_type = BGE_STAT_REG; 2218 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2219 dev_ok = B_TRUE; 2220 break; 2221 2222 case DEVICE_ID_5789: 2223 cidp->chip_label = 5789; 2224 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2225 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2226 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2227 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2228 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2229 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2230 cidp->pci_type = BGE_PCI_E; 2231 cidp->statistic_type = BGE_STAT_REG; 2232 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2233 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2234 cidp->msi_enabled = B_TRUE; 2235 dev_ok = B_TRUE; 2236 break; 2237 2238 } 2239 2240 /* 2241 * Setup the default jumbo parameter. 2242 */ 2243 cidp->ethmax_size = ETHERMAX; 2244 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2245 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2246 2247 /* 2248 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2249 * setup below jumbo specific parameters. 2250 * 2251 * For BCM5714/5715, there is only one standard receive ring. So the 2252 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2253 * feature is enabled. 2254 */ 2255 if (bge_jumbo_enable && 2256 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2257 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2258 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2259 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2260 cidp->mbuf_lo_water_rdma = 2261 RDMA_MBUF_LOWAT_5714_JUMBO; 2262 cidp->mbuf_lo_water_rmac = 2263 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2264 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2265 cidp->jumbo_slots = 0; 2266 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2267 } else { 2268 cidp->mbuf_lo_water_rdma = 2269 RDMA_MBUF_LOWAT_JUMBO; 2270 cidp->mbuf_lo_water_rmac = 2271 MAC_RX_MBUF_LOWAT_JUMBO; 2272 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2273 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2274 } 2275 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2276 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2277 cidp->ethmax_size = cidp->default_mtu + 2278 sizeof (struct ether_header); 2279 } 2280 2281 /* 2282 * Identify the NV memory type: SEEPROM or Flash? 2283 */ 2284 cidp->nvtype = bge_nvmem_id(bgep); 2285 2286 /* 2287 * Now, we want to check whether this device is part of a 2288 * supported subsystem (e.g., on the motherboard of a Sun 2289 * branded platform). 2290 * 2291 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2292 */ 2293 if (cidp->subven == VENDOR_ID_SUN) 2294 sys_ok = B_TRUE; 2295 2296 /* 2297 * Rule 2: If it's on the list on known subsystems, then it's OK. 2298 * Note: 0x14e41647 should *not* appear in the list, but the code 2299 * doesn't enforce that. 2300 */ 2301 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2302 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2303 if (err == DDI_PROP_SUCCESS) { 2304 /* 2305 * Got the list; scan for a matching subsystem vendor/device 2306 */ 2307 subid = (cidp->subven << 16) | cidp->subdev; 2308 while (i--) 2309 if (ids[i] == subid) 2310 sys_ok = B_TRUE; 2311 ddi_prop_free(ids); 2312 } 2313 2314 /* 2315 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2316 * 2317 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2318 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2319 * we have to check specially for the exact device paths to the 2320 * motherboard devices on those platforms ;-( 2321 * 2322 * Note: we can't just use the "supported-subsystems" mechanism 2323 * above, because the entry would have to be 0x14e41647 -- which 2324 * would then accept *any* plugin card that *didn't* contain a 2325 * (valid) SEEPROM ;-( 2326 */ 2327 sysname = ddi_node_name(ddi_root_node()); 2328 devname = ddi_pathname(bgep->devinfo, buf); 2329 ASSERT(strlen(devname) > 0); 2330 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2331 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2332 sys_ok = B_TRUE; 2333 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2334 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2335 sys_ok = B_TRUE; 2336 2337 /* 2338 * Now check what we've discovered: is this truly a supported 2339 * chip on (the motherboard of) a supported platform? 2340 * 2341 * Possible problems here: 2342 * 1) it's a completely unheard-of chip (e.g. 5761) 2343 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2344 * 3) it's a chip we would support if it were on the motherboard 2345 * of a Sun platform, but this one isn't ;-( 2346 */ 2347 if (cidp->chip_label == 0) 2348 bge_problem(bgep, 2349 "Device 'pci%04x,%04x' not recognized (%d?)", 2350 cidp->vendor, cidp->device, cidp->device); 2351 else if (!dev_ok) 2352 bge_problem(bgep, 2353 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2354 cidp->vendor, cidp->device, cidp->chip_label, 2355 cidp->revision); 2356 #if BGE_DEBUGGING 2357 else if (!sys_ok) 2358 bge_problem(bgep, 2359 "%d-based subsystem 'pci%04x,%04x' not validated", 2360 cidp->chip_label, cidp->subven, cidp->subdev); 2361 #endif 2362 else 2363 cidp->flags |= CHIP_FLAG_SUPPORTED; 2364 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2365 return (EIO); 2366 return (0); 2367 } 2368 2369 void 2370 bge_chip_msi_trig(bge_t *bgep) 2371 { 2372 uint32_t regval; 2373 2374 regval = bgep->param_msi_cnt<<4; 2375 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2376 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2377 } 2378 2379 /* 2380 * Various registers that control the chip's internal engines (state 2381 * machines) have a <reset> and <enable> bits (fortunately, in the 2382 * same place in each such register :-). 2383 * 2384 * To reset the state machine, the <reset> bit must be written with 1; 2385 * it will then read back as 1 while the reset is in progress, but 2386 * self-clear to 0 when the reset completes. 2387 * 2388 * To enable a state machine, one must set the <enable> bit, which 2389 * will continue to read back as 0 until the state machine is running. 2390 * 2391 * To disable a state machine, the <enable> bit must be cleared, but 2392 * it will continue to read back as 1 until the state machine actually 2393 * stops. 2394 * 2395 * This routine implements polling for completion of a reset, enable 2396 * or disable operation, returning B_TRUE on success (bit reached the 2397 * required state) or B_FALSE on timeout (200*100us == 20ms). 2398 */ 2399 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2400 uint32_t mask, uint32_t val); 2401 #pragma no_inline(bge_chip_poll_engine) 2402 2403 static boolean_t 2404 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2405 uint32_t mask, uint32_t val) 2406 { 2407 uint32_t regval; 2408 uint32_t n; 2409 2410 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2411 (void *)bgep, regno, mask, val)); 2412 2413 for (n = 200; n; --n) { 2414 regval = bge_reg_get32(bgep, regno); 2415 if ((regval & mask) == val) 2416 return (B_TRUE); 2417 drv_usecwait(100); 2418 } 2419 2420 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2421 return (B_FALSE); 2422 } 2423 2424 /* 2425 * Various registers that control the chip's internal engines (state 2426 * machines) have a <reset> bit (fortunately, in the same place in 2427 * each such register :-). To reset the state machine, this bit must 2428 * be written with 1; it will then read back as 1 while the reset is 2429 * in progress, but self-clear to 0 when the reset completes. 2430 * 2431 * This code sets the bit, then polls for it to read back as zero. 2432 * The return value is B_TRUE on success (reset bit cleared itself), 2433 * or B_FALSE if the state machine didn't recover :( 2434 * 2435 * NOTE: the Core reset is similar to other resets, except that we 2436 * can't poll for completion, since the Core reset disables memory 2437 * access! So we just have to assume that it will all complete in 2438 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2439 */ 2440 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2441 #pragma no_inline(bge_chip_reset_engine) 2442 2443 static boolean_t 2444 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2445 { 2446 uint32_t regval; 2447 uint32_t val32; 2448 2449 regval = bge_reg_get32(bgep, regno); 2450 2451 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2452 (void *)bgep, regno)); 2453 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2454 regno, regval)); 2455 2456 regval |= STATE_MACHINE_RESET_BIT; 2457 2458 switch (regno) { 2459 case MISC_CONFIG_REG: 2460 /* 2461 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2462 * resetting PCIE block and bringing PCIE link down, bit 29 2463 * in the register needs to be set first, and then set it again 2464 * while the reset bit is written. 2465 * See:P500 of 57xx-PG102-RDS.pdf. 2466 */ 2467 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2468 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2469 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2470 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2471 if (bgep->chipid.pci_type == BGE_PCI_E) { 2472 if (bgep->chipid.asic_rev == 2473 MHCR_CHIP_REV_5751_A0 || 2474 bgep->chipid.asic_rev == 2475 MHCR_CHIP_REV_5721_A0 || 2476 bgep->chipid.asic_rev == 2477 MHCR_CHIP_REV_5755_A0) { 2478 val32 = bge_reg_get32(bgep, 2479 PHY_TEST_CTRL_REG); 2480 if (val32 == (PHY_PCIE_SCRAM_MODE | 2481 PHY_PCIE_LTASS_MODE)) 2482 bge_reg_put32(bgep, 2483 PHY_TEST_CTRL_REG, 2484 PHY_PCIE_SCRAM_MODE); 2485 val32 = pci_config_get32 2486 (bgep->cfg_handle, 2487 PCI_CONF_BGE_CLKCTL); 2488 val32 |= CLKCTL_PCIE_A0_FIX; 2489 pci_config_put32(bgep->cfg_handle, 2490 PCI_CONF_BGE_CLKCTL, val32); 2491 } 2492 bge_reg_set32(bgep, regno, 2493 MISC_CONFIG_GRC_RESET_DISABLE); 2494 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2495 } 2496 } 2497 2498 /* 2499 * Special case - causes Core reset 2500 * 2501 * On SPARC v9 we want to ensure that we don't start 2502 * timing until the I/O access has actually reached 2503 * the chip, otherwise we might make the next access 2504 * too early. And we can't just force the write out 2505 * by following it with a read (even to config space) 2506 * because that would cause the fault we're trying 2507 * to avoid. Hence the need for membar_sync() here. 2508 */ 2509 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2510 #ifdef __sparcv9 2511 membar_sync(); 2512 #endif /* __sparcv9 */ 2513 /* 2514 * On some platforms,system need about 300us for 2515 * link setup. 2516 */ 2517 drv_usecwait(300); 2518 2519 if (bgep->chipid.pci_type == BGE_PCI_E) { 2520 /* PCI-E device need more reset time */ 2521 drv_usecwait(120000); 2522 2523 /* Set PCIE max payload size and clear error status. */ 2524 if ((bgep->chipid.chip_label == 5721) || 2525 (bgep->chipid.chip_label == 5751) || 2526 (bgep->chipid.chip_label == 5752) || 2527 (bgep->chipid.chip_label == 5789)) { 2528 pci_config_put16(bgep->cfg_handle, 2529 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2530 pci_config_put16(bgep->cfg_handle, 2531 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2532 } 2533 } 2534 2535 BGE_PCICHK(bgep); 2536 return (B_TRUE); 2537 2538 default: 2539 bge_reg_put32(bgep, regno, regval); 2540 return (bge_chip_poll_engine(bgep, regno, 2541 STATE_MACHINE_RESET_BIT, 0)); 2542 } 2543 } 2544 2545 /* 2546 * Various registers that control the chip's internal engines (state 2547 * machines) have an <enable> bit (fortunately, in the same place in 2548 * each such register :-). To stop the state machine, this bit must 2549 * be written with 0, then polled to see when the state machine has 2550 * actually stopped. 2551 * 2552 * The return value is B_TRUE on success (enable bit cleared), or 2553 * B_FALSE if the state machine didn't stop :( 2554 */ 2555 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2556 uint32_t morebits); 2557 #pragma no_inline(bge_chip_disable_engine) 2558 2559 static boolean_t 2560 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2561 { 2562 uint32_t regval; 2563 2564 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2565 (void *)bgep, regno, morebits)); 2566 2567 switch (regno) { 2568 case FTQ_RESET_REG: 2569 /* 2570 * For Schumacher's bugfix CR6490108 2571 */ 2572 #ifdef BGE_IPMI_ASF 2573 #ifdef BGE_NETCONSOLE 2574 if (bgep->asf_enabled) 2575 return (B_TRUE); 2576 #endif 2577 #endif 2578 /* 2579 * Not quite like the others; it doesn't 2580 * have an <enable> bit, but instead we 2581 * have to set and then clear all the bits 2582 */ 2583 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2584 drv_usecwait(100); 2585 bge_reg_put32(bgep, regno, 0); 2586 return (B_TRUE); 2587 2588 default: 2589 regval = bge_reg_get32(bgep, regno); 2590 regval &= ~STATE_MACHINE_ENABLE_BIT; 2591 regval &= ~morebits; 2592 bge_reg_put32(bgep, regno, regval); 2593 return (bge_chip_poll_engine(bgep, regno, 2594 STATE_MACHINE_ENABLE_BIT, 0)); 2595 } 2596 } 2597 2598 /* 2599 * Various registers that control the chip's internal engines (state 2600 * machines) have an <enable> bit (fortunately, in the same place in 2601 * each such register :-). To start the state machine, this bit must 2602 * be written with 1, then polled to see when the state machine has 2603 * actually started. 2604 * 2605 * The return value is B_TRUE on success (enable bit set), or 2606 * B_FALSE if the state machine didn't start :( 2607 */ 2608 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2609 uint32_t morebits); 2610 #pragma no_inline(bge_chip_enable_engine) 2611 2612 static boolean_t 2613 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2614 { 2615 uint32_t regval; 2616 2617 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2618 (void *)bgep, regno, morebits)); 2619 2620 switch (regno) { 2621 case FTQ_RESET_REG: 2622 #ifdef BGE_IPMI_ASF 2623 #ifdef BGE_NETCONSOLE 2624 if (bgep->asf_enabled) 2625 return (B_TRUE); 2626 #endif 2627 #endif 2628 /* 2629 * Not quite like the others; it doesn't 2630 * have an <enable> bit, but instead we 2631 * have to set and then clear all the bits 2632 */ 2633 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2634 drv_usecwait(100); 2635 bge_reg_put32(bgep, regno, 0); 2636 return (B_TRUE); 2637 2638 default: 2639 regval = bge_reg_get32(bgep, regno); 2640 regval |= STATE_MACHINE_ENABLE_BIT; 2641 regval |= morebits; 2642 bge_reg_put32(bgep, regno, regval); 2643 return (bge_chip_poll_engine(bgep, regno, 2644 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2645 } 2646 } 2647 2648 /* 2649 * Reprogram the Ethernet, Transmit, and Receive MAC 2650 * modes to match the param_* variables 2651 */ 2652 static void bge_sync_mac_modes(bge_t *bgep); 2653 #pragma no_inline(bge_sync_mac_modes) 2654 2655 static void 2656 bge_sync_mac_modes(bge_t *bgep) 2657 { 2658 uint32_t macmode; 2659 uint32_t regval; 2660 2661 ASSERT(mutex_owned(bgep->genlock)); 2662 2663 /* 2664 * Reprogram the Ethernet MAC mode ... 2665 */ 2666 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2667 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2668 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2669 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2670 else 2671 macmode |= ETHERNET_MODE_LINK_POLARITY; 2672 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2673 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2674 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2675 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2676 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2677 macmode |= ETHERNET_MODE_PORTMODE_MII; 2678 else 2679 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2680 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2681 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2682 else 2683 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2684 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2685 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2686 else 2687 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2688 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2689 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2690 (void *)bgep, regval, macmode)); 2691 2692 /* 2693 * ... the Transmit MAC mode ... 2694 */ 2695 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2696 if (bgep->param_link_tx_pause) 2697 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2698 else 2699 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2700 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2701 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2702 (void *)bgep, regval, macmode)); 2703 2704 /* 2705 * ... and the Receive MAC mode 2706 */ 2707 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2708 if (bgep->param_link_rx_pause) 2709 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2710 else 2711 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2712 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2713 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2714 (void *)bgep, regval, macmode)); 2715 } 2716 2717 /* 2718 * bge_chip_sync() -- program the chip with the unicast MAC address, 2719 * the multicast hash table, the required level of promiscuity, and 2720 * the current loopback mode ... 2721 */ 2722 #ifdef BGE_IPMI_ASF 2723 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2724 #else 2725 int bge_chip_sync(bge_t *bgep); 2726 #endif 2727 #pragma no_inline(bge_chip_sync) 2728 2729 int 2730 #ifdef BGE_IPMI_ASF 2731 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2732 #else 2733 bge_chip_sync(bge_t *bgep) 2734 #endif 2735 { 2736 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2737 boolean_t promisc; 2738 uint64_t macaddr; 2739 uint32_t fill; 2740 int i, j; 2741 int retval = DDI_SUCCESS; 2742 2743 BGE_TRACE(("bge_chip_sync($%p)", 2744 (void *)bgep)); 2745 2746 ASSERT(mutex_owned(bgep->genlock)); 2747 2748 promisc = B_FALSE; 2749 fill = ~(uint32_t)0; 2750 2751 if (bgep->promisc) 2752 promisc = B_TRUE; 2753 else 2754 fill = (uint32_t)0; 2755 2756 /* 2757 * If the TX/RX MAC engines are already running, we should stop 2758 * them (and reset the RX engine) before changing the parameters. 2759 * If they're not running, this will have no effect ... 2760 * 2761 * NOTE: this is currently disabled by default because stopping 2762 * and restarting the Tx engine may cause an outgoing packet in 2763 * transit to be truncated. Also, stopping and restarting the 2764 * Rx engine seems to not work correctly on the 5705. Testing 2765 * has not (yet!) revealed any problems with NOT stopping and 2766 * restarting these engines (and Broadcom say their drivers don't 2767 * do this), but if it is found to cause problems, this variable 2768 * can be patched to re-enable the old behaviour ... 2769 */ 2770 if (bge_stop_start_on_sync) { 2771 #ifdef BGE_IPMI_ASF 2772 if (!bgep->asf_enabled) { 2773 if (!bge_chip_disable_engine(bgep, 2774 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2775 retval = DDI_FAILURE; 2776 } else { 2777 if (!bge_chip_disable_engine(bgep, 2778 RECEIVE_MAC_MODE_REG, 0)) 2779 retval = DDI_FAILURE; 2780 } 2781 #else 2782 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2783 RECEIVE_MODE_KEEP_VLAN_TAG)) 2784 retval = DDI_FAILURE; 2785 #endif 2786 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2787 retval = DDI_FAILURE; 2788 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2789 retval = DDI_FAILURE; 2790 } 2791 2792 /* 2793 * Reprogram the hashed multicast address table ... 2794 */ 2795 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2796 bge_reg_put32(bgep, MAC_HASH_REG(i), 2797 bgep->mcast_hash[i] | fill); 2798 2799 #ifdef BGE_IPMI_ASF 2800 if (!bgep->asf_enabled || !asf_keeplive) { 2801 #endif 2802 /* 2803 * Transform the MAC address(es) from host to chip format, then 2804 * reprogram the transmit random backoff seed and the unicast 2805 * MAC address(es) ... 2806 */ 2807 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2808 for (i = 0, fill = 0, macaddr = 0ull; 2809 i < ETHERADDRL; ++i) { 2810 macaddr <<= 8; 2811 macaddr |= bgep->curr_addr[j].addr[i]; 2812 fill += bgep->curr_addr[j].addr[i]; 2813 } 2814 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2815 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2816 } 2817 2818 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2819 (void *)bgep, macaddr)); 2820 #ifdef BGE_IPMI_ASF 2821 } 2822 #endif 2823 2824 /* 2825 * Set or clear the PROMISCUOUS mode bit 2826 */ 2827 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2828 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2829 2830 /* 2831 * Sync the rest of the MAC modes too ... 2832 */ 2833 bge_sync_mac_modes(bgep); 2834 2835 /* 2836 * Restart RX/TX MAC engines if required ... 2837 */ 2838 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2839 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2840 retval = DDI_FAILURE; 2841 #ifdef BGE_IPMI_ASF 2842 if (!bgep->asf_enabled) { 2843 if (!bge_chip_enable_engine(bgep, 2844 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2845 retval = DDI_FAILURE; 2846 } else { 2847 if (!bge_chip_enable_engine(bgep, 2848 RECEIVE_MAC_MODE_REG, 0)) 2849 retval = DDI_FAILURE; 2850 } 2851 #else 2852 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2853 RECEIVE_MODE_KEEP_VLAN_TAG)) 2854 retval = DDI_FAILURE; 2855 #endif 2856 } 2857 return (retval); 2858 } 2859 2860 /* 2861 * This array defines the sequence of state machine control registers 2862 * in which the <enable> bit must be cleared to bring the chip to a 2863 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2864 */ 2865 static bge_regno_t shutdown_engine_regs[] = { 2866 RECEIVE_MAC_MODE_REG, 2867 RCV_BD_INITIATOR_MODE_REG, 2868 RCV_LIST_PLACEMENT_MODE_REG, 2869 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2870 RCV_DATA_BD_INITIATOR_MODE_REG, 2871 RCV_DATA_COMPLETION_MODE_REG, 2872 RCV_BD_COMPLETION_MODE_REG, 2873 2874 SEND_BD_SELECTOR_MODE_REG, 2875 SEND_BD_INITIATOR_MODE_REG, 2876 SEND_DATA_INITIATOR_MODE_REG, 2877 READ_DMA_MODE_REG, 2878 SEND_DATA_COMPLETION_MODE_REG, 2879 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2880 SEND_BD_COMPLETION_MODE_REG, 2881 TRANSMIT_MAC_MODE_REG, 2882 2883 HOST_COALESCE_MODE_REG, 2884 WRITE_DMA_MODE_REG, 2885 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2886 FTQ_RESET_REG, /* special - see code */ 2887 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2888 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2889 BGE_REGNO_NONE /* terminator */ 2890 }; 2891 2892 /* 2893 * bge_chip_stop() -- stop all chip processing 2894 * 2895 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2896 * we've detected a problem internally; otherwise, this is a normal 2897 * (clean) stop (at user request i.e. the last STREAM has been closed). 2898 */ 2899 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2900 #pragma no_inline(bge_chip_stop) 2901 2902 void 2903 bge_chip_stop(bge_t *bgep, boolean_t fault) 2904 { 2905 bge_regno_t regno; 2906 bge_regno_t *rbp; 2907 boolean_t ok; 2908 2909 BGE_TRACE(("bge_chip_stop($%p)", 2910 (void *)bgep)); 2911 2912 ASSERT(mutex_owned(bgep->genlock)); 2913 2914 rbp = shutdown_engine_regs; 2915 /* 2916 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2917 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2918 * -ory arbiter should not be disabled. 2919 */ 2920 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2921 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2922 ok &= bge_chip_disable_engine(bgep, regno, 0); 2923 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2924 (regno != DMA_COMPLETION_MODE_REG) && 2925 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2926 (regno != BUFFER_MANAGER_MODE_REG) && 2927 (regno != MEMORY_ARBITER_MODE_REG)) 2928 ok &= bge_chip_disable_engine(bgep, 2929 regno, 0); 2930 } 2931 2932 if (!ok && !fault) 2933 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2934 2935 /* 2936 * Finally, disable (all) MAC events & clear the MAC status 2937 */ 2938 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2939 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2940 2941 /* 2942 * if we're stopping the chip because of a detected fault then do 2943 * appropriate actions 2944 */ 2945 if (fault) { 2946 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2947 bgep->bge_chip_state = BGE_CHIP_FAULT; 2948 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2949 if (bgep->bge_dma_error) { 2950 /* 2951 * need to free buffers in case the fault was 2952 * due to a memory error in a buffer - got to 2953 * do a fair bit of tidying first 2954 */ 2955 if (bgep->progress & PROGRESS_KSTATS) { 2956 bge_fini_kstats(bgep); 2957 bgep->progress &= ~PROGRESS_KSTATS; 2958 } 2959 if (bgep->progress & PROGRESS_INTR) { 2960 bge_intr_disable(bgep); 2961 rw_enter(bgep->errlock, RW_WRITER); 2962 bge_fini_rings(bgep); 2963 rw_exit(bgep->errlock); 2964 bgep->progress &= ~PROGRESS_INTR; 2965 } 2966 if (bgep->progress & PROGRESS_BUFS) { 2967 bge_free_bufs(bgep); 2968 bgep->progress &= ~PROGRESS_BUFS; 2969 } 2970 bgep->bge_dma_error = B_FALSE; 2971 } 2972 } 2973 } else 2974 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2975 } 2976 2977 /* 2978 * Poll for completion of chip's ROM firmware; also, at least on the 2979 * first time through, find and return the hardware MAC address, if any. 2980 */ 2981 static uint64_t bge_poll_firmware(bge_t *bgep); 2982 #pragma no_inline(bge_poll_firmware) 2983 2984 static uint64_t 2985 bge_poll_firmware(bge_t *bgep) 2986 { 2987 uint64_t magic; 2988 uint64_t mac; 2989 uint32_t gen; 2990 uint32_t i; 2991 2992 /* 2993 * Step 19: poll for firmware completion (GENCOMM port set 2994 * to the ones complement of T3_MAGIC_NUMBER). 2995 * 2996 * While we're at it, we also read the MAC address register; 2997 * at some stage the firmware will load this with the 2998 * factory-set value. 2999 * 3000 * When both the magic number and the MAC address are set, 3001 * we're done; but we impose a time limit of one second 3002 * (1000*1000us) in case the firmware fails in some fashion 3003 * or the SEEPROM that provides that MAC address isn't fitted. 3004 * 3005 * After the first time through (chip state != INITIAL), we 3006 * don't need the MAC address to be set (we've already got it 3007 * or not, from the first time), so we don't wait for it, but 3008 * we still have to wait for the T3_MAGIC_NUMBER. 3009 * 3010 * Note: the magic number is only a 32-bit quantity, but the NIC 3011 * memory is 64-bit (and big-endian) internally. Addressing the 3012 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3013 * it work correctly on both big- and little-endian hosts. 3014 */ 3015 for (i = 0; i < 1000; ++i) { 3016 drv_usecwait(1000); 3017 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3018 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3019 #ifdef BGE_IPMI_ASF 3020 if (!bgep->asf_enabled) { 3021 #endif 3022 if (gen != ~T3_MAGIC_NUMBER) 3023 continue; 3024 #ifdef BGE_IPMI_ASF 3025 } 3026 #endif 3027 if (mac != 0ULL) 3028 break; 3029 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3030 break; 3031 } 3032 3033 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3034 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3035 (void *)bgep, gen, i)); 3036 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3037 mac, magic)); 3038 3039 return (mac); 3040 } 3041 3042 /* 3043 * Maximum times of trying to get the NVRAM access lock 3044 * by calling bge_nvmem_acquire() 3045 */ 3046 #define MAX_TRY_NVMEM_ACQUIRE 10000 3047 3048 #ifdef BGE_IPMI_ASF 3049 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3050 #else 3051 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3052 #endif 3053 #pragma no_inline(bge_chip_reset) 3054 3055 int 3056 #ifdef BGE_IPMI_ASF 3057 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3058 #else 3059 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3060 #endif 3061 { 3062 chip_id_t chipid; 3063 uint64_t mac; 3064 uint64_t magic; 3065 uint32_t modeflags; 3066 uint32_t mhcr; 3067 uint32_t sx0; 3068 uint32_t i, tries; 3069 #ifdef BGE_IPMI_ASF 3070 uint32_t mailbox; 3071 #endif 3072 int retval = DDI_SUCCESS; 3073 3074 BGE_TRACE(("bge_chip_reset($%p, %d)", 3075 (void *)bgep, enable_dma)); 3076 3077 ASSERT(mutex_owned(bgep->genlock)); 3078 3079 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3080 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3081 3082 /* 3083 * Do we need to stop the chip cleanly before resetting? 3084 */ 3085 switch (bgep->bge_chip_state) { 3086 default: 3087 _NOTE(NOTREACHED) 3088 return (DDI_FAILURE); 3089 3090 case BGE_CHIP_INITIAL: 3091 case BGE_CHIP_STOPPED: 3092 case BGE_CHIP_RESET: 3093 break; 3094 3095 case BGE_CHIP_RUNNING: 3096 case BGE_CHIP_ERROR: 3097 case BGE_CHIP_FAULT: 3098 bge_chip_stop(bgep, B_FALSE); 3099 break; 3100 } 3101 3102 #ifdef BGE_IPMI_ASF 3103 if (bgep->asf_enabled) { 3104 #ifdef __sparc 3105 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3106 MHCR_ENABLE_TAGGED_STATUS_MODE | 3107 MHCR_MASK_INTERRUPT_MODE | 3108 MHCR_MASK_PCI_INT_OUTPUT | 3109 MHCR_CLEAR_INTERRUPT_INTA | 3110 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3111 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3112 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3113 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3114 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3115 MEMORY_ARBITER_ENABLE); 3116 #endif 3117 if (asf_mode == ASF_MODE_INIT) { 3118 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3119 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3120 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3121 } 3122 } 3123 #endif 3124 /* 3125 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3126 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3127 * 3128 * Before reset Core clock,it is 3129 * also required to initialize the Memory Arbiter as specified in step9 3130 * and Misc Host Control Register as specified in step-13 3131 * Step 4-5: reset Core clock & wait for completion 3132 * Steps 6-8: are done by bge_chip_cfg_init() 3133 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3134 */ 3135 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3136 retval = DDI_FAILURE; 3137 3138 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3139 MHCR_ENABLE_TAGGED_STATUS_MODE | 3140 MHCR_MASK_INTERRUPT_MODE | 3141 MHCR_MASK_PCI_INT_OUTPUT | 3142 MHCR_CLEAR_INTERRUPT_INTA; 3143 #ifdef _BIG_ENDIAN 3144 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3145 #endif /* _BIG_ENDIAN */ 3146 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3147 #ifdef BGE_IPMI_ASF 3148 if (bgep->asf_enabled) 3149 bgep->asf_wordswapped = B_FALSE; 3150 #endif 3151 /* 3152 * NVRAM Corruption Workaround 3153 */ 3154 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3155 if (bge_nvmem_acquire(bgep) != EAGAIN) 3156 break; 3157 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3158 BGE_DEBUG(("%s: fail to acquire nvram lock", 3159 bgep->ifname)); 3160 3161 #ifdef BGE_IPMI_ASF 3162 if (!bgep->asf_enabled) { 3163 #endif 3164 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3165 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3166 #ifdef BGE_IPMI_ASF 3167 } 3168 #endif 3169 3170 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3171 retval = DDI_FAILURE; 3172 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3173 3174 /* 3175 * Step 8a: This may belong elsewhere, but BCM5721 needs 3176 * a bit set to avoid a fifo overflow/underflow bug. 3177 */ 3178 if ((bgep->chipid.chip_label == 5721) || 3179 (bgep->chipid.chip_label == 5751) || 3180 (bgep->chipid.chip_label == 5752) || 3181 (bgep->chipid.chip_label == 5755) || 3182 (bgep->chipid.chip_label == 5789)) 3183 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3184 3185 3186 /* 3187 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3188 * not be changed. 3189 */ 3190 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3191 retval = DDI_FAILURE; 3192 3193 /* 3194 * Steps 10-11: configure PIO endianness options and 3195 * enable indirect register access -- already done 3196 * Steps 12-13: enable writing to the PCI state & clock 3197 * control registers -- not required; we aren't going to 3198 * use those features. 3199 * Steps 14-15: Configure DMA endianness options. See 3200 * the comments on the setting of the MHCR above. 3201 */ 3202 #ifdef _BIG_ENDIAN 3203 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3204 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3205 #else 3206 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3207 #endif /* _BIG_ENDIAN */ 3208 #ifdef BGE_IPMI_ASF 3209 if (bgep->asf_enabled) 3210 modeflags |= MODE_HOST_STACK_UP; 3211 #endif 3212 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3213 3214 #ifdef BGE_IPMI_ASF 3215 if (bgep->asf_enabled) { 3216 #ifdef __sparc 3217 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3218 MEMORY_ARBITER_ENABLE | 3219 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3220 #endif 3221 3222 #ifdef BGE_NETCONSOLE 3223 if (!bgep->asf_newhandshake) { 3224 if ((asf_mode == ASF_MODE_INIT) || 3225 (asf_mode == ASF_MODE_POST_INIT)) { 3226 bge_asf_post_reset_old_mode(bgep, 3227 BGE_INIT_RESET); 3228 } else { 3229 bge_asf_post_reset_old_mode(bgep, 3230 BGE_SHUTDOWN_RESET); 3231 } 3232 } 3233 #endif 3234 3235 /* Wait for NVRAM init */ 3236 i = 0; 3237 drv_usecwait(5000); 3238 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3239 3240 while ((mailbox != (uint32_t) 3241 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3242 (i < 10000)) { 3243 drv_usecwait(100); 3244 mailbox = bge_nic_get32(bgep, 3245 BGE_FIRMWARE_MAILBOX); 3246 i++; 3247 } 3248 3249 #ifndef BGE_NETCONSOLE 3250 if (!bgep->asf_newhandshake) { 3251 if ((asf_mode == ASF_MODE_INIT) || 3252 (asf_mode == ASF_MODE_POST_INIT)) { 3253 3254 bge_asf_post_reset_old_mode(bgep, 3255 BGE_INIT_RESET); 3256 } else { 3257 bge_asf_post_reset_old_mode(bgep, 3258 BGE_SHUTDOWN_RESET); 3259 } 3260 } 3261 #endif 3262 } 3263 #endif 3264 /* 3265 * Steps 16-17: poll for firmware completion 3266 */ 3267 mac = bge_poll_firmware(bgep); 3268 3269 /* 3270 * Step 18: enable external memory -- doesn't apply. 3271 * 3272 * However we take the opportunity to set the MLCR anyway, as 3273 * this register also controls the SEEPROM auto-access method 3274 * which we may want to use later ... 3275 * 3276 * The proper value here depends on the way the chip is wired 3277 * into the circuit board, as this register *also* controls which 3278 * of the "Miscellaneous I/O" pins are driven as outputs and the 3279 * values driven onto those pins! 3280 * 3281 * See also step 74 in the PRM ... 3282 */ 3283 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3284 bgep->chipid.bge_mlcr_default); 3285 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3286 3287 /* 3288 * Step 20: clear the Ethernet MAC mode register 3289 */ 3290 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3291 3292 /* 3293 * Step 21: restore cache-line-size, latency timer, and 3294 * subsystem ID registers to their original values (not 3295 * those read into the local structure <chipid>, 'cos 3296 * that was after they were cleared by the RESET). 3297 * 3298 * Note: the Subsystem Vendor/Device ID registers are not 3299 * directly writable in config space, so we use the shadow 3300 * copy in "Page Zero" of register space to restore them 3301 * both in one go ... 3302 */ 3303 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3304 bgep->chipid.clsize); 3305 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3306 bgep->chipid.latency); 3307 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3308 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3309 3310 /* 3311 * The SEND INDEX registers should be reset to zero by the 3312 * global chip reset; if they're not, there'll be trouble 3313 * later on. 3314 */ 3315 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3316 if (sx0 != 0) { 3317 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3318 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3319 retval = DDI_FAILURE; 3320 } 3321 3322 /* Enable MSI code */ 3323 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3324 bge_reg_set32(bgep, MSI_MODE_REG, 3325 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3326 3327 /* 3328 * On the first time through, save the factory-set MAC address 3329 * (if any). If bge_poll_firmware() above didn't return one 3330 * (from a chip register) consider looking in the attached NV 3331 * memory device, if any. Once we have it, we save it in both 3332 * register-image (64-bit) and byte-array forms. All-zero and 3333 * all-one addresses are not valid, and we refuse to stash those. 3334 */ 3335 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3336 if (mac == 0ULL) 3337 mac = bge_get_nvmac(bgep); 3338 if (mac != 0ULL && mac != ~0ULL) { 3339 bgep->chipid.hw_mac_addr = mac; 3340 for (i = ETHERADDRL; i-- != 0; ) { 3341 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3342 mac >>= 8; 3343 } 3344 bgep->chipid.vendor_addr.set = B_TRUE; 3345 } 3346 } 3347 3348 #ifdef BGE_IPMI_ASF 3349 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3350 if (asf_mode != ASF_MODE_NONE) { 3351 if ((asf_mode == ASF_MODE_INIT) || 3352 (asf_mode == ASF_MODE_POST_INIT)) { 3353 3354 bge_asf_post_reset_new_mode(bgep, 3355 BGE_INIT_RESET); 3356 } else { 3357 bge_asf_post_reset_new_mode(bgep, 3358 BGE_SHUTDOWN_RESET); 3359 } 3360 } 3361 } 3362 #endif 3363 3364 /* 3365 * Record the new state 3366 */ 3367 bgep->chip_resets += 1; 3368 bgep->bge_chip_state = BGE_CHIP_RESET; 3369 return (retval); 3370 } 3371 3372 /* 3373 * bge_chip_start() -- start the chip transmitting and/or receiving, 3374 * including enabling interrupts 3375 */ 3376 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3377 #pragma no_inline(bge_chip_start) 3378 3379 int 3380 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3381 { 3382 uint32_t coalmode; 3383 uint32_t ledctl; 3384 uint32_t mtu; 3385 uint32_t maxring; 3386 uint32_t stats_mask; 3387 uint32_t dma_wrprio; 3388 uint64_t ring; 3389 int retval = DDI_SUCCESS; 3390 3391 BGE_TRACE(("bge_chip_start($%p)", 3392 (void *)bgep)); 3393 3394 ASSERT(mutex_owned(bgep->genlock)); 3395 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3396 3397 /* 3398 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3399 * The document specifies 95 separate steps to fully 3400 * initialise the chip!!!! 3401 * 3402 * The reset code above has already got us as far as step 3403 * 21, so we continue with ... 3404 * 3405 * Step 22: clear the MAC statistics block 3406 * (0x0300-0x0aff in NIC-local memory) 3407 */ 3408 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3409 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3410 NIC_MEM_STATISTICS_SIZE); 3411 3412 /* 3413 * Step 23: clear the status block (in host memory) 3414 */ 3415 DMA_ZERO(bgep->status_block); 3416 3417 /* 3418 * Step 24: set DMA read/write control register 3419 */ 3420 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3421 bgep->chipid.bge_dma_rwctrl); 3422 3423 /* 3424 * Step 25: Configure DMA endianness -- already done (16/17) 3425 * Step 26: Configure Host-Based Send Rings 3426 * Step 27: Indicate Host Stack Up 3427 */ 3428 bge_reg_set32(bgep, MODE_CONTROL_REG, 3429 MODE_HOST_SEND_BDS | 3430 MODE_HOST_STACK_UP); 3431 3432 /* 3433 * Step 28: Configure checksum options: 3434 * Solaris supports the hardware default checksum options. 3435 * 3436 * Workaround for Incorrect pseudo-header checksum calculation. 3437 */ 3438 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3439 bge_reg_set32(bgep, MODE_CONTROL_REG, 3440 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3441 3442 /* 3443 * Step 29: configure Timer Prescaler. The value is always the 3444 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3445 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3446 * for the whole chip! 3447 */ 3448 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3449 3450 /* 3451 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3452 * 3453 * If the mbuf_length is specified as 0, we just leave these at 3454 * their hardware defaults, rather than explicitly setting them. 3455 * As the Broadcom HRM,driver better not change the parameters 3456 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3457 */ 3458 if ((bgep->chipid.mbuf_length != 0) && 3459 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3460 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3461 bgep->chipid.mbuf_base); 3462 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3463 bgep->chipid.mbuf_length); 3464 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3465 DMAD_POOL_BASE_DEFAULT); 3466 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3467 DMAD_POOL_LENGTH_DEFAULT); 3468 } 3469 3470 /* 3471 * Step 32: configure MAC memory pool watermarks 3472 */ 3473 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3474 bgep->chipid.mbuf_lo_water_rdma); 3475 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3476 bgep->chipid.mbuf_lo_water_rmac); 3477 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3478 bgep->chipid.mbuf_hi_water); 3479 3480 /* 3481 * Step 33: configure DMA resource watermarks 3482 */ 3483 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3484 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3485 bge_dmad_lo_water); 3486 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3487 bge_dmad_hi_water); 3488 } 3489 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3490 3491 /* 3492 * Steps 34-36: enable buffer manager & internal h/w queues 3493 */ 3494 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3495 STATE_MACHINE_ATTN_ENABLE_BIT)) 3496 retval = DDI_FAILURE; 3497 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3498 retval = DDI_FAILURE; 3499 3500 /* 3501 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3502 */ 3503 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3504 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3505 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3506 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3507 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3508 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3509 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3510 } 3511 3512 /* 3513 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3514 */ 3515 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3516 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3517 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3518 bge_replenish_jumbo); 3519 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3520 bge_replenish_mini); 3521 } 3522 3523 /* 3524 * Steps 41-43: clear Send Ring Producer Indices and initialise 3525 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3526 */ 3527 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3528 maxring = BGE_SEND_RINGS_MAX; 3529 else 3530 maxring = BGE_SEND_RINGS_MAX_5705; 3531 for (ring = 0; ring < maxring; ++ring) { 3532 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3533 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3534 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3535 &bgep->send[ring].hw_rcb); 3536 } 3537 3538 /* 3539 * Steps 44-45: initialise Receive Return Rings 3540 * (0x0200-0x02ff in NIC-local memory) 3541 */ 3542 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3543 maxring = BGE_RECV_RINGS_MAX; 3544 else 3545 maxring = BGE_RECV_RINGS_MAX_5705; 3546 for (ring = 0; ring < maxring; ++ring) 3547 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3548 &bgep->recv[ring].hw_rcb); 3549 3550 /* 3551 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3552 */ 3553 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3554 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3555 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3556 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3557 } 3558 /* 3559 * Step 47: configure the MAC unicast address 3560 * Step 48: configure the random backoff seed 3561 * Step 96: set up multicast filters 3562 */ 3563 #ifdef BGE_IPMI_ASF 3564 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3565 #else 3566 if (bge_chip_sync(bgep) == DDI_FAILURE) 3567 #endif 3568 retval = DDI_FAILURE; 3569 3570 /* 3571 * Step 49: configure the MTU 3572 */ 3573 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3574 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3575 3576 /* 3577 * Step 50: configure the IPG et al 3578 */ 3579 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3580 3581 /* 3582 * Step 51: configure the default Rx Return Ring 3583 */ 3584 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3585 3586 /* 3587 * Steps 52-54: configure Receive List Placement, 3588 * and enable Receive List Placement Statistics 3589 */ 3590 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3591 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3592 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3593 case MHCR_CHIP_ASIC_REV_5700: 3594 case MHCR_CHIP_ASIC_REV_5701: 3595 case MHCR_CHIP_ASIC_REV_5703: 3596 case MHCR_CHIP_ASIC_REV_5704: 3597 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3598 break; 3599 case MHCR_CHIP_ASIC_REV_5705: 3600 break; 3601 default: 3602 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3603 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3604 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3605 break; 3606 } 3607 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3608 3609 if (bgep->chipid.rx_rings > 1) 3610 bge_init_recv_rule(bgep); 3611 3612 /* 3613 * Steps 55-56: enable Send Data Initiator Statistics 3614 */ 3615 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3616 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3617 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3618 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3619 } else { 3620 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3621 SEND_INIT_STATS_ENABLE); 3622 } 3623 /* 3624 * Steps 57-58: stop (?) the Host Coalescing Engine 3625 */ 3626 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3627 retval = DDI_FAILURE; 3628 3629 /* 3630 * Steps 59-62: initialise Host Coalescing parameters 3631 */ 3632 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3633 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3634 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3635 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3636 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3637 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3638 bge_tx_count_intr); 3639 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3640 bge_tx_ticks_intr); 3641 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3642 bge_rx_count_intr); 3643 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3644 bge_rx_ticks_intr); 3645 } 3646 3647 /* 3648 * Steps 63-64: initialise status block & statistics 3649 * host memory addresses 3650 * The statistic block does not exist in some chipsets 3651 * Step 65: initialise Statistics Coalescing Tick Counter 3652 */ 3653 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3654 bgep->status_block.cookie.dmac_laddress); 3655 3656 /* 3657 * Steps 66-67: initialise status block & statistics 3658 * NIC-local memory addresses 3659 */ 3660 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3661 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3662 bgep->statistics.cookie.dmac_laddress); 3663 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3664 STATISTICS_TICKS_DEFAULT); 3665 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3666 NIC_MEM_STATUS_BLOCK); 3667 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3668 NIC_MEM_STATISTICS); 3669 } 3670 3671 /* 3672 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3673 * Completion Engine, the Receive List Placement Engine, and the 3674 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3675 * and BCM5715. 3676 */ 3677 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3678 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3679 coalmode = COALESCE_64_BYTE_STATUS; 3680 else 3681 coalmode = 0; 3682 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3683 retval = DDI_FAILURE; 3684 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3685 STATE_MACHINE_ATTN_ENABLE_BIT)) 3686 retval = DDI_FAILURE; 3687 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3688 retval = DDI_FAILURE; 3689 3690 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3691 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3692 STATE_MACHINE_ATTN_ENABLE_BIT)) 3693 retval = DDI_FAILURE; 3694 3695 /* 3696 * Step 72: Enable MAC DMA engines 3697 * Step 73: Clear & enable MAC statistics 3698 */ 3699 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3700 ETHERNET_MODE_ENABLE_FHDE | 3701 ETHERNET_MODE_ENABLE_RDE | 3702 ETHERNET_MODE_ENABLE_TDE); 3703 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3704 ETHERNET_MODE_ENABLE_TX_STATS | 3705 ETHERNET_MODE_ENABLE_RX_STATS | 3706 ETHERNET_MODE_CLEAR_TX_STATS | 3707 ETHERNET_MODE_CLEAR_RX_STATS); 3708 3709 /* 3710 * Step 74: configure the MLCR (Miscellaneous Local Control 3711 * Register); not required, as we set up the MLCR in step 10 3712 * (part of the reset code) above. 3713 * 3714 * Step 75: clear Interrupt Mailbox 0 3715 */ 3716 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3717 3718 /* 3719 * Steps 76-87: Gentlemen, start your engines ... 3720 * 3721 * Enable the DMA Completion Engine, the Write DMA Engine, 3722 * the Read DMA Engine, Receive Data Completion Engine, 3723 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3724 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3725 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3726 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3727 * 3728 * Beware exhaust fumes? 3729 */ 3730 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3731 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3732 retval = DDI_FAILURE; 3733 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3734 ALL_DMA_ATTN_BITS; 3735 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3736 MHCR_CHIP_ASIC_REV_5755) { 3737 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3738 } 3739 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3740 dma_wrprio)) 3741 retval = DDI_FAILURE; 3742 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3743 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3744 retval = DDI_FAILURE; 3745 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3746 STATE_MACHINE_ATTN_ENABLE_BIT)) 3747 retval = DDI_FAILURE; 3748 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3749 if (!bge_chip_enable_engine(bgep, 3750 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3751 retval = DDI_FAILURE; 3752 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3753 retval = DDI_FAILURE; 3754 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3755 STATE_MACHINE_ATTN_ENABLE_BIT)) 3756 retval = DDI_FAILURE; 3757 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3758 RCV_BD_DISABLED_RING_ATTN)) 3759 retval = DDI_FAILURE; 3760 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3761 RCV_DATA_BD_ILL_RING_ATTN)) 3762 retval = DDI_FAILURE; 3763 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3764 retval = DDI_FAILURE; 3765 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3766 STATE_MACHINE_ATTN_ENABLE_BIT)) 3767 retval = DDI_FAILURE; 3768 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3769 STATE_MACHINE_ATTN_ENABLE_BIT)) 3770 retval = DDI_FAILURE; 3771 3772 /* 3773 * Step 88: download firmware -- doesn't apply 3774 * Steps 89-90: enable Transmit & Receive MAC Engines 3775 */ 3776 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3777 retval = DDI_FAILURE; 3778 #ifdef BGE_IPMI_ASF 3779 if (!bgep->asf_enabled) { 3780 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3781 RECEIVE_MODE_KEEP_VLAN_TAG)) 3782 retval = DDI_FAILURE; 3783 } else { 3784 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3785 retval = DDI_FAILURE; 3786 } 3787 #else 3788 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3789 RECEIVE_MODE_KEEP_VLAN_TAG)) 3790 retval = DDI_FAILURE; 3791 #endif 3792 3793 /* 3794 * Step 91: disable auto-polling of PHY status 3795 */ 3796 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3797 3798 /* 3799 * Step 92: configure D0 power state (not required) 3800 * Step 93: initialise LED control register () 3801 */ 3802 ledctl = LED_CONTROL_DEFAULT; 3803 switch (bgep->chipid.device) { 3804 case DEVICE_ID_5700: 3805 case DEVICE_ID_5700x: 3806 case DEVICE_ID_5701: 3807 /* 3808 * Switch to 5700 (MAC) mode on these older chips 3809 */ 3810 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3811 ledctl |= LED_CONTROL_LED_MODE_5700; 3812 break; 3813 3814 default: 3815 break; 3816 } 3817 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3818 3819 /* 3820 * Step 94: activate link 3821 */ 3822 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3823 3824 /* 3825 * Step 95: set up physical layer (PHY/SerDes) 3826 * restart autoneg (if required) 3827 */ 3828 if (reset_phys) 3829 if (bge_phys_update(bgep) == DDI_FAILURE) 3830 retval = DDI_FAILURE; 3831 3832 /* 3833 * Extra step (DSG): hand over all the Receive Buffers to the chip 3834 */ 3835 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3836 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3837 bgep->buff[ring].rf_next); 3838 3839 /* 3840 * MSI bits:The least significant MSI 16-bit word. 3841 * ISR will be triggered different. 3842 */ 3843 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3844 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3845 3846 /* 3847 * Extra step (DSG): select which interrupts are enabled 3848 * 3849 * Program the Ethernet MAC engine to signal attention on 3850 * Link Change events, then enable interrupts on MAC, DMA, 3851 * and FLOW attention signals. 3852 */ 3853 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3854 ETHERNET_EVENT_LINK_INT | 3855 ETHERNET_STATUS_PCS_ERROR_INT); 3856 #ifdef BGE_IPMI_ASF 3857 if (bgep->asf_enabled) { 3858 bge_reg_set32(bgep, MODE_CONTROL_REG, 3859 MODE_INT_ON_FLOW_ATTN | 3860 MODE_INT_ON_DMA_ATTN | 3861 MODE_HOST_STACK_UP| 3862 MODE_INT_ON_MAC_ATTN); 3863 } else { 3864 #endif 3865 bge_reg_set32(bgep, MODE_CONTROL_REG, 3866 MODE_INT_ON_FLOW_ATTN | 3867 MODE_INT_ON_DMA_ATTN | 3868 MODE_INT_ON_MAC_ATTN); 3869 #ifdef BGE_IPMI_ASF 3870 } 3871 #endif 3872 3873 /* 3874 * Step 97: enable PCI interrupts!!! 3875 */ 3876 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3877 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3878 MHCR_MASK_PCI_INT_OUTPUT); 3879 3880 /* 3881 * All done! 3882 */ 3883 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3884 return (retval); 3885 } 3886 3887 3888 /* 3889 * ========== Hardware interrupt handler ========== 3890 */ 3891 3892 #undef BGE_DBG 3893 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3894 3895 /* 3896 * Sync the status block, then atomically clear the specified bits in 3897 * the <flags-and-tag> field of the status block. 3898 * the <flags> word of the status block, returning the value of the 3899 * <tag> and the <flags> before the bits were cleared. 3900 */ 3901 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3902 #pragma inline(bge_status_sync) 3903 3904 static int 3905 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3906 { 3907 bge_status_t *bsp; 3908 int retval; 3909 3910 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3911 (void *)bgep, bits)); 3912 3913 ASSERT(bgep->bge_guard == BGE_GUARD); 3914 3915 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3916 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3917 if (retval != DDI_FM_OK) 3918 return (retval); 3919 3920 bsp = DMA_VPTR(bgep->status_block); 3921 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3922 3923 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3924 (void *)bgep, bits, *flags)); 3925 3926 return (retval); 3927 } 3928 3929 static void bge_wake_factotum(bge_t *bgep); 3930 #pragma inline(bge_wake_factotum) 3931 3932 static void 3933 bge_wake_factotum(bge_t *bgep) 3934 { 3935 mutex_enter(bgep->softintrlock); 3936 if (bgep->factotum_flag == 0) { 3937 bgep->factotum_flag = 1; 3938 ddi_trigger_softintr(bgep->factotum_id); 3939 } 3940 mutex_exit(bgep->softintrlock); 3941 } 3942 3943 /* 3944 * bge_intr() -- handle chip interrupts 3945 */ 3946 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3947 #pragma no_inline(bge_intr) 3948 3949 uint_t 3950 bge_intr(caddr_t arg1, caddr_t arg2) 3951 { 3952 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3953 bge_status_t *bsp; 3954 uint64_t flags; 3955 uint32_t regval; 3956 uint_t result; 3957 int retval, loop_cnt = 0; 3958 3959 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3960 3961 /* 3962 * GLD v2 checks that s/w setup is complete before passing 3963 * interrupts to this routine, thus eliminating the old 3964 * (and well-known) race condition around ddi_add_intr() 3965 */ 3966 ASSERT(bgep->progress & PROGRESS_HWINT); 3967 3968 result = DDI_INTR_UNCLAIMED; 3969 mutex_enter(bgep->genlock); 3970 3971 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3972 /* 3973 * Check whether chip's says it's asserting #INTA; 3974 * if not, don't process or claim the interrupt. 3975 * 3976 * Note that the PCI signal is active low, so the 3977 * bit is *zero* when the interrupt is asserted. 3978 */ 3979 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3980 if (regval & MLCR_INTA_STATE) { 3981 if (bge_check_acc_handle(bgep, bgep->io_handle) 3982 != DDI_FM_OK) 3983 goto chip_stop; 3984 mutex_exit(bgep->genlock); 3985 return (result); 3986 } 3987 3988 /* 3989 * Block further PCI interrupts ... 3990 */ 3991 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3992 MHCR_MASK_PCI_INT_OUTPUT); 3993 3994 } else { 3995 /* 3996 * Check MSI status 3997 */ 3998 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 3999 if (regval & MSI_ERROR_ATTENTION) { 4000 BGE_REPORT((bgep, "msi error attention," 4001 " status=0x%x", regval)); 4002 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4003 } 4004 } 4005 4006 result = DDI_INTR_CLAIMED; 4007 4008 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4009 4010 /* 4011 * Sync the status block and grab the flags-n-tag from it. 4012 * We count the number of interrupts where there doesn't 4013 * seem to have been a DMA update of the status block; if 4014 * it *has* been updated, the counter will be cleared in 4015 * the while() loop below ... 4016 */ 4017 bgep->missed_dmas += 1; 4018 bsp = DMA_VPTR(bgep->status_block); 4019 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4020 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4021 /* 4022 * bge_chip_stop() may have freed dma area etc 4023 * while we were in this interrupt handler - 4024 * better not call bge_status_sync() 4025 */ 4026 (void) bge_check_acc_handle(bgep, 4027 bgep->io_handle); 4028 mutex_exit(bgep->genlock); 4029 return (DDI_INTR_CLAIMED); 4030 } 4031 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4032 &flags); 4033 if (retval != DDI_FM_OK) { 4034 bgep->bge_dma_error = B_TRUE; 4035 goto chip_stop; 4036 } 4037 4038 if (!(flags & STATUS_FLAG_UPDATED)) 4039 break; 4040 4041 /* 4042 * Tell the chip that we're processing the interrupt 4043 */ 4044 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4045 INTERRUPT_MBOX_DISABLE(flags)); 4046 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4047 DDI_FM_OK) 4048 goto chip_stop; 4049 4050 /* 4051 * Drop the mutex while we: 4052 * Receive any newly-arrived packets 4053 * Recycle any newly-finished send buffers 4054 */ 4055 bgep->bge_intr_running = B_TRUE; 4056 mutex_exit(bgep->genlock); 4057 bge_receive(bgep, bsp); 4058 bge_recycle(bgep, bsp); 4059 mutex_enter(bgep->genlock); 4060 bgep->bge_intr_running = B_FALSE; 4061 4062 /* 4063 * Tell the chip we've finished processing, and 4064 * give it the tag that we got from the status 4065 * block earlier, so that it knows just how far 4066 * we've gone. If it's got more for us to do, 4067 * it will now update the status block and try 4068 * to assert an interrupt (but we've got the 4069 * #INTA blocked at present). If we see the 4070 * update, we'll loop around to do some more. 4071 * Eventually we'll get out of here ... 4072 */ 4073 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4074 INTERRUPT_MBOX_ENABLE(flags)); 4075 bgep->missed_dmas = 0; 4076 } 4077 4078 /* 4079 * Check for exceptional conditions that we need to handle 4080 * 4081 * Link status changed 4082 * Status block not updated 4083 */ 4084 if (flags & STATUS_FLAG_LINK_CHANGED) 4085 bge_wake_factotum(bgep); 4086 4087 if (bgep->missed_dmas) { 4088 /* 4089 * Probably due to the internal status tag not 4090 * being reset. Force a status block update now; 4091 * this should ensure that we get an update and 4092 * a new interrupt. After that, we should be in 4093 * sync again ... 4094 */ 4095 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4096 "not updated?", flags)); 4097 bgep->missed_updates++; 4098 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4099 COALESCE_NOW); 4100 4101 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4102 /* 4103 * If this happens multiple times in a row, 4104 * it means DMA is just not working. Maybe 4105 * the chip's failed, or maybe there's a 4106 * problem on the PCI bus or in the host-PCI 4107 * bridge (Tomatillo). 4108 * 4109 * At all events, we want to stop further 4110 * interrupts and let the recovery code take 4111 * over to see whether anything can be done 4112 * about it ... 4113 */ 4114 bge_fm_ereport(bgep, 4115 DDI_FM_DEVICE_BADINT_LIMIT); 4116 goto chip_stop; 4117 } 4118 } 4119 4120 /* 4121 * Reenable assertion of #INTA, unless there's a DMA fault 4122 */ 4123 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4124 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4125 MHCR_MASK_PCI_INT_OUTPUT); 4126 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4127 DDI_FM_OK) 4128 goto chip_stop; 4129 } 4130 4131 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4132 goto chip_stop; 4133 4134 mutex_exit(bgep->genlock); 4135 return (result); 4136 4137 chip_stop: 4138 #ifdef BGE_IPMI_ASF 4139 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4140 /* 4141 * We must stop ASF heart beat before 4142 * bge_chip_stop(), otherwise some 4143 * computers (ex. IBM HS20 blade 4144 * server) may crash. 4145 */ 4146 bge_asf_update_status(bgep); 4147 bge_asf_stop_timer(bgep); 4148 bgep->asf_status = ASF_STAT_STOP; 4149 4150 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4151 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4152 } 4153 #endif 4154 bge_chip_stop(bgep, B_TRUE); 4155 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4156 mutex_exit(bgep->genlock); 4157 return (result); 4158 } 4159 4160 /* 4161 * ========== Factotum, implemented as a softint handler ========== 4162 */ 4163 4164 #undef BGE_DBG 4165 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4166 4167 static void bge_factotum_error_handler(bge_t *bgep); 4168 #pragma no_inline(bge_factotum_error_handler) 4169 4170 static void 4171 bge_factotum_error_handler(bge_t *bgep) 4172 { 4173 uint32_t flow; 4174 uint32_t rdma; 4175 uint32_t wdma; 4176 uint32_t tmac; 4177 uint32_t rmac; 4178 uint32_t rxrs; 4179 uint32_t txrs = 0; 4180 4181 ASSERT(mutex_owned(bgep->genlock)); 4182 4183 /* 4184 * Read all the registers that show the possible 4185 * reasons for the ERROR bit to be asserted 4186 */ 4187 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4188 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4189 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4190 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4191 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4192 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4193 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4194 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4195 4196 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4197 (void *)bgep, flow, rdma, wdma)); 4198 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4199 (void *)bgep, tmac, rmac, rxrs, txrs)); 4200 4201 /* 4202 * For now, just clear all the errors ... 4203 */ 4204 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4205 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4206 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4207 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4208 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4209 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4210 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4211 } 4212 4213 /* 4214 * Handler for hardware link state change. 4215 * 4216 * When this routine is called, the hardware link state has changed 4217 * and the new state is reflected in the param_* variables. Here 4218 * we must update the softstate and reprogram the MAC to match. 4219 */ 4220 static void bge_factotum_link_handler(bge_t *bgep); 4221 #pragma no_inline(bge_factotum_link_handler) 4222 4223 static void 4224 bge_factotum_link_handler(bge_t *bgep) 4225 { 4226 ASSERT(mutex_owned(bgep->genlock)); 4227 4228 /* 4229 * Update the s/w link_state 4230 */ 4231 if (bgep->param_link_up) 4232 bgep->link_state = LINK_STATE_UP; 4233 else 4234 bgep->link_state = LINK_STATE_DOWN; 4235 4236 /* 4237 * Reprogram the MAC modes to match 4238 */ 4239 bge_sync_mac_modes(bgep); 4240 } 4241 4242 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4243 #pragma no_inline(bge_factotum_link_check) 4244 4245 static boolean_t 4246 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4247 { 4248 boolean_t check; 4249 uint64_t flags; 4250 uint32_t tmac_status; 4251 4252 ASSERT(mutex_owned(bgep->genlock)); 4253 4254 /* 4255 * Get & clear the writable status bits in the Tx status register 4256 * (some bits are write-1-to-clear, others are just readonly). 4257 */ 4258 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4259 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4260 4261 /* 4262 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4263 */ 4264 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4265 STATUS_FLAG_LINK_CHANGED, &flags); 4266 if (*dma_state != DDI_FM_OK) 4267 return (B_FALSE); 4268 4269 /* 4270 * Clear any errors flagged in the status block ... 4271 */ 4272 if (flags & STATUS_FLAG_ERROR) 4273 bge_factotum_error_handler(bgep); 4274 4275 /* 4276 * We need to check the link status if: 4277 * the status block says there's been a link change 4278 * or there's any discrepancy between the various 4279 * flags indicating the link state (link_state, 4280 * param_link_up, and the LINK STATE bit in the 4281 * Transmit MAC status register). 4282 */ 4283 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4284 switch (bgep->link_state) { 4285 case LINK_STATE_UP: 4286 check |= (bgep->param_link_up == B_FALSE); 4287 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4288 break; 4289 4290 case LINK_STATE_DOWN: 4291 check |= (bgep->param_link_up != B_FALSE); 4292 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4293 break; 4294 4295 default: 4296 check = B_TRUE; 4297 break; 4298 } 4299 4300 /* 4301 * If <check> is false, we're sure the link hasn't changed. 4302 * If true, however, it's not yet definitive; we have to call 4303 * bge_phys_check() to determine whether the link has settled 4304 * into a new state yet ... and if it has, then call the link 4305 * state change handler.But when the chip is 5700 in Dell 6650 4306 * ,even if check is false, the link may have changed.So we 4307 * have to call bge_phys_check() to determine the link state. 4308 */ 4309 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4310 check = bge_phys_check(bgep); 4311 if (check) 4312 bge_factotum_link_handler(bgep); 4313 } 4314 4315 return (check); 4316 } 4317 4318 /* 4319 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4320 */ 4321 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4322 #pragma no_inline(bge_factotum_stall_check) 4323 4324 static boolean_t 4325 bge_factotum_stall_check(bge_t *bgep) 4326 { 4327 uint32_t dogval; 4328 4329 ASSERT(mutex_owned(bgep->genlock)); 4330 4331 /* 4332 * Specific check for Tx stall ... 4333 * 4334 * The 'watchdog' counter is incremented whenever a packet 4335 * is queued, reset to 1 when some (but not all) buffers 4336 * are reclaimed, reset to 0 (disabled) when all buffers 4337 * are reclaimed, and shifted left here. If it exceeds the 4338 * threshold value, the chip is assumed to have stalled and 4339 * is put into the ERROR state. The factotum will then reset 4340 * it on the next pass. 4341 * 4342 * All of which should ensure that we don't get into a state 4343 * where packets are left pending indefinitely! 4344 */ 4345 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4346 if (dogval < bge_watchdog_count) 4347 return (B_FALSE); 4348 4349 #if !defined(BGE_NETCONSOLE) 4350 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4351 #endif 4352 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4353 return (B_TRUE); 4354 } 4355 4356 /* 4357 * The factotum is woken up when there's something to do that we'd rather 4358 * not do from inside a hardware interrupt handler or high-level cyclic. 4359 * Its two main tasks are: 4360 * reset & restart the chip after an error 4361 * check the link status whenever necessary 4362 */ 4363 uint_t bge_chip_factotum(caddr_t arg); 4364 #pragma no_inline(bge_chip_factotum) 4365 4366 uint_t 4367 bge_chip_factotum(caddr_t arg) 4368 { 4369 bge_t *bgep; 4370 uint_t result; 4371 boolean_t error; 4372 boolean_t linkchg; 4373 int dma_state; 4374 4375 bgep = (bge_t *)arg; 4376 4377 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4378 4379 mutex_enter(bgep->softintrlock); 4380 if (bgep->factotum_flag == 0) { 4381 mutex_exit(bgep->softintrlock); 4382 return (DDI_INTR_UNCLAIMED); 4383 } 4384 bgep->factotum_flag = 0; 4385 mutex_exit(bgep->softintrlock); 4386 4387 result = DDI_INTR_CLAIMED; 4388 error = B_FALSE; 4389 linkchg = B_FALSE; 4390 4391 mutex_enter(bgep->genlock); 4392 switch (bgep->bge_chip_state) { 4393 default: 4394 break; 4395 4396 case BGE_CHIP_RUNNING: 4397 linkchg = bge_factotum_link_check(bgep, &dma_state); 4398 error = bge_factotum_stall_check(bgep); 4399 if (dma_state != DDI_FM_OK) { 4400 bgep->bge_dma_error = B_TRUE; 4401 error = B_TRUE; 4402 } 4403 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4404 error = B_TRUE; 4405 if (error) 4406 bgep->bge_chip_state = BGE_CHIP_ERROR; 4407 break; 4408 4409 case BGE_CHIP_ERROR: 4410 error = B_TRUE; 4411 break; 4412 4413 case BGE_CHIP_FAULT: 4414 /* 4415 * Fault detected, time to reset ... 4416 */ 4417 if (bge_autorecover) { 4418 if (!(bgep->progress & PROGRESS_BUFS)) { 4419 /* 4420 * if we can't allocate the ring buffers, 4421 * try later 4422 */ 4423 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4424 mutex_exit(bgep->genlock); 4425 return (result); 4426 } 4427 bgep->progress |= PROGRESS_BUFS; 4428 } 4429 if (!(bgep->progress & PROGRESS_INTR)) { 4430 bge_init_rings(bgep); 4431 bge_intr_enable(bgep); 4432 bgep->progress |= PROGRESS_INTR; 4433 } 4434 if (!(bgep->progress & PROGRESS_KSTATS)) { 4435 bge_init_kstats(bgep, 4436 ddi_get_instance(bgep->devinfo)); 4437 bgep->progress |= PROGRESS_KSTATS; 4438 } 4439 4440 BGE_REPORT((bgep, "automatic recovery activated")); 4441 4442 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4443 bgep->bge_chip_state = BGE_CHIP_ERROR; 4444 error = B_TRUE; 4445 } 4446 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4447 DDI_FM_OK) { 4448 bgep->bge_chip_state = BGE_CHIP_ERROR; 4449 error = B_TRUE; 4450 } 4451 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4452 DDI_FM_OK) { 4453 bgep->bge_chip_state = BGE_CHIP_ERROR; 4454 error = B_TRUE; 4455 } 4456 if (error == B_FALSE) { 4457 #ifdef BGE_IPMI_ASF 4458 if (bgep->asf_enabled && 4459 bgep->asf_status != ASF_STAT_RUN) { 4460 bgep->asf_timeout_id = timeout( 4461 bge_asf_heartbeat, (void *)bgep, 4462 drv_usectohz( 4463 BGE_ASF_HEARTBEAT_INTERVAL)); 4464 bgep->asf_status = ASF_STAT_RUN; 4465 } 4466 #endif 4467 ddi_fm_service_impact(bgep->devinfo, 4468 DDI_SERVICE_RESTORED); 4469 } 4470 } 4471 break; 4472 } 4473 4474 4475 /* 4476 * If an error is detected, stop the chip now, marking it as 4477 * faulty, so that it will be reset next time through ... 4478 * 4479 * Note that if intr_running is set, then bge_intr() has dropped 4480 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4481 * this point so have to wait until the next time the factotum runs. 4482 */ 4483 if (error && !bgep->bge_intr_running) { 4484 #ifdef BGE_IPMI_ASF 4485 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4486 /* 4487 * We must stop ASF heart beat before bge_chip_stop(), 4488 * otherwise some computers (ex. IBM HS20 blade server) 4489 * may crash. 4490 */ 4491 bge_asf_update_status(bgep); 4492 bge_asf_stop_timer(bgep); 4493 bgep->asf_status = ASF_STAT_STOP; 4494 4495 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4496 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4497 } 4498 #endif 4499 bge_chip_stop(bgep, B_TRUE); 4500 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4501 } 4502 mutex_exit(bgep->genlock); 4503 4504 /* 4505 * If the link state changed, tell the world about it. 4506 * Note: can't do this while still holding the mutex. 4507 */ 4508 if (linkchg) 4509 mac_link_update(bgep->mh, bgep->link_state); 4510 4511 return (result); 4512 } 4513 4514 /* 4515 * High-level cyclic handler 4516 * 4517 * This routine schedules a (low-level) softint callback to the 4518 * factotum, and prods the chip to update the status block (which 4519 * will cause a hardware interrupt when complete). 4520 */ 4521 void bge_chip_cyclic(void *arg); 4522 #pragma no_inline(bge_chip_cyclic) 4523 4524 void 4525 bge_chip_cyclic(void *arg) 4526 { 4527 bge_t *bgep; 4528 4529 bgep = arg; 4530 4531 switch (bgep->bge_chip_state) { 4532 default: 4533 return; 4534 4535 case BGE_CHIP_RUNNING: 4536 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4537 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4538 ddi_fm_service_impact(bgep->devinfo, 4539 DDI_SERVICE_UNAFFECTED); 4540 break; 4541 4542 case BGE_CHIP_FAULT: 4543 case BGE_CHIP_ERROR: 4544 break; 4545 } 4546 4547 bge_wake_factotum(bgep); 4548 } 4549 4550 4551 /* 4552 * ========== Ioctl subfunctions ========== 4553 */ 4554 4555 #undef BGE_DBG 4556 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4557 4558 #if BGE_DEBUGGING || BGE_DO_PPIO 4559 4560 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4561 #pragma no_inline(bge_chip_peek_cfg) 4562 4563 static void 4564 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4565 { 4566 uint64_t regval; 4567 uint64_t regno; 4568 4569 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4570 (void *)bgep, (void *)ppd)); 4571 4572 regno = ppd->pp_acc_offset; 4573 4574 switch (ppd->pp_acc_size) { 4575 case 1: 4576 regval = pci_config_get8(bgep->cfg_handle, regno); 4577 break; 4578 4579 case 2: 4580 regval = pci_config_get16(bgep->cfg_handle, regno); 4581 break; 4582 4583 case 4: 4584 regval = pci_config_get32(bgep->cfg_handle, regno); 4585 break; 4586 4587 case 8: 4588 regval = pci_config_get64(bgep->cfg_handle, regno); 4589 break; 4590 } 4591 4592 ppd->pp_acc_data = regval; 4593 } 4594 4595 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4596 #pragma no_inline(bge_chip_poke_cfg) 4597 4598 static void 4599 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4600 { 4601 uint64_t regval; 4602 uint64_t regno; 4603 4604 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4605 (void *)bgep, (void *)ppd)); 4606 4607 regno = ppd->pp_acc_offset; 4608 regval = ppd->pp_acc_data; 4609 4610 switch (ppd->pp_acc_size) { 4611 case 1: 4612 pci_config_put8(bgep->cfg_handle, regno, regval); 4613 break; 4614 4615 case 2: 4616 pci_config_put16(bgep->cfg_handle, regno, regval); 4617 break; 4618 4619 case 4: 4620 pci_config_put32(bgep->cfg_handle, regno, regval); 4621 break; 4622 4623 case 8: 4624 pci_config_put64(bgep->cfg_handle, regno, regval); 4625 break; 4626 } 4627 } 4628 4629 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4630 #pragma no_inline(bge_chip_peek_reg) 4631 4632 static void 4633 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4634 { 4635 uint64_t regval; 4636 void *regaddr; 4637 4638 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4639 (void *)bgep, (void *)ppd)); 4640 4641 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4642 4643 switch (ppd->pp_acc_size) { 4644 case 1: 4645 regval = ddi_get8(bgep->io_handle, regaddr); 4646 break; 4647 4648 case 2: 4649 regval = ddi_get16(bgep->io_handle, regaddr); 4650 break; 4651 4652 case 4: 4653 regval = ddi_get32(bgep->io_handle, regaddr); 4654 break; 4655 4656 case 8: 4657 regval = ddi_get64(bgep->io_handle, regaddr); 4658 break; 4659 } 4660 4661 ppd->pp_acc_data = regval; 4662 } 4663 4664 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4665 #pragma no_inline(bge_chip_peek_reg) 4666 4667 static void 4668 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4669 { 4670 uint64_t regval; 4671 void *regaddr; 4672 4673 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4674 (void *)bgep, (void *)ppd)); 4675 4676 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4677 regval = ppd->pp_acc_data; 4678 4679 switch (ppd->pp_acc_size) { 4680 case 1: 4681 ddi_put8(bgep->io_handle, regaddr, regval); 4682 break; 4683 4684 case 2: 4685 ddi_put16(bgep->io_handle, regaddr, regval); 4686 break; 4687 4688 case 4: 4689 ddi_put32(bgep->io_handle, regaddr, regval); 4690 break; 4691 4692 case 8: 4693 ddi_put64(bgep->io_handle, regaddr, regval); 4694 break; 4695 } 4696 BGE_PCICHK(bgep); 4697 } 4698 4699 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4700 #pragma no_inline(bge_chip_peek_nic) 4701 4702 static void 4703 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4704 { 4705 uint64_t regoff; 4706 uint64_t regval; 4707 void *regaddr; 4708 4709 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4710 (void *)bgep, (void *)ppd)); 4711 4712 regoff = ppd->pp_acc_offset; 4713 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4714 regoff &= MWBAR_GRANULE_MASK; 4715 regoff += NIC_MEM_WINDOW_OFFSET; 4716 regaddr = PIO_ADDR(bgep, regoff); 4717 4718 switch (ppd->pp_acc_size) { 4719 case 1: 4720 regval = ddi_get8(bgep->io_handle, regaddr); 4721 break; 4722 4723 case 2: 4724 regval = ddi_get16(bgep->io_handle, regaddr); 4725 break; 4726 4727 case 4: 4728 regval = ddi_get32(bgep->io_handle, regaddr); 4729 break; 4730 4731 case 8: 4732 regval = ddi_get64(bgep->io_handle, regaddr); 4733 break; 4734 } 4735 4736 ppd->pp_acc_data = regval; 4737 } 4738 4739 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4740 #pragma no_inline(bge_chip_poke_nic) 4741 4742 static void 4743 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4744 { 4745 uint64_t regoff; 4746 uint64_t regval; 4747 void *regaddr; 4748 4749 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4750 (void *)bgep, (void *)ppd)); 4751 4752 regoff = ppd->pp_acc_offset; 4753 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4754 regoff &= MWBAR_GRANULE_MASK; 4755 regoff += NIC_MEM_WINDOW_OFFSET; 4756 regaddr = PIO_ADDR(bgep, regoff); 4757 regval = ppd->pp_acc_data; 4758 4759 switch (ppd->pp_acc_size) { 4760 case 1: 4761 ddi_put8(bgep->io_handle, regaddr, regval); 4762 break; 4763 4764 case 2: 4765 ddi_put16(bgep->io_handle, regaddr, regval); 4766 break; 4767 4768 case 4: 4769 ddi_put32(bgep->io_handle, regaddr, regval); 4770 break; 4771 4772 case 8: 4773 ddi_put64(bgep->io_handle, regaddr, regval); 4774 break; 4775 } 4776 BGE_PCICHK(bgep); 4777 } 4778 4779 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4780 #pragma no_inline(bge_chip_peek_mii) 4781 4782 static void 4783 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4784 { 4785 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4786 (void *)bgep, (void *)ppd)); 4787 4788 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4789 } 4790 4791 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4792 #pragma no_inline(bge_chip_poke_mii) 4793 4794 static void 4795 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4796 { 4797 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4798 (void *)bgep, (void *)ppd)); 4799 4800 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4801 } 4802 4803 #if BGE_SEE_IO32 4804 4805 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4806 #pragma no_inline(bge_chip_peek_seeprom) 4807 4808 static void 4809 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4810 { 4811 uint32_t data; 4812 int err; 4813 4814 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4815 (void *)bgep, (void *)ppd)); 4816 4817 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4818 ppd->pp_acc_data = err ? ~0ull : data; 4819 } 4820 4821 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4822 #pragma no_inline(bge_chip_poke_seeprom) 4823 4824 static void 4825 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4826 { 4827 uint32_t data; 4828 4829 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4830 (void *)bgep, (void *)ppd)); 4831 4832 data = ppd->pp_acc_data; 4833 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4834 } 4835 #endif /* BGE_SEE_IO32 */ 4836 4837 #if BGE_FLASH_IO32 4838 4839 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4840 #pragma no_inline(bge_chip_peek_flash) 4841 4842 static void 4843 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4844 { 4845 uint32_t data; 4846 int err; 4847 4848 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4849 (void *)bgep, (void *)ppd)); 4850 4851 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4852 ppd->pp_acc_data = err ? ~0ull : data; 4853 } 4854 4855 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4856 #pragma no_inline(bge_chip_poke_flash) 4857 4858 static void 4859 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4860 { 4861 uint32_t data; 4862 4863 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4864 (void *)bgep, (void *)ppd)); 4865 4866 data = ppd->pp_acc_data; 4867 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4868 ppd->pp_acc_offset, &data); 4869 } 4870 #endif /* BGE_FLASH_IO32 */ 4871 4872 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4873 #pragma no_inline(bge_chip_peek_mem) 4874 4875 static void 4876 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4877 { 4878 uint64_t regval; 4879 void *vaddr; 4880 4881 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4882 (void *)bgep, (void *)ppd)); 4883 4884 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4885 4886 switch (ppd->pp_acc_size) { 4887 case 1: 4888 regval = *(uint8_t *)vaddr; 4889 break; 4890 4891 case 2: 4892 regval = *(uint16_t *)vaddr; 4893 break; 4894 4895 case 4: 4896 regval = *(uint32_t *)vaddr; 4897 break; 4898 4899 case 8: 4900 regval = *(uint64_t *)vaddr; 4901 break; 4902 } 4903 4904 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4905 (void *)bgep, (void *)ppd, regval, vaddr)); 4906 4907 ppd->pp_acc_data = regval; 4908 } 4909 4910 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4911 #pragma no_inline(bge_chip_poke_mem) 4912 4913 static void 4914 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4915 { 4916 uint64_t regval; 4917 void *vaddr; 4918 4919 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4920 (void *)bgep, (void *)ppd)); 4921 4922 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4923 regval = ppd->pp_acc_data; 4924 4925 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4926 (void *)bgep, (void *)ppd, regval, vaddr)); 4927 4928 switch (ppd->pp_acc_size) { 4929 case 1: 4930 *(uint8_t *)vaddr = (uint8_t)regval; 4931 break; 4932 4933 case 2: 4934 *(uint16_t *)vaddr = (uint16_t)regval; 4935 break; 4936 4937 case 4: 4938 *(uint32_t *)vaddr = (uint32_t)regval; 4939 break; 4940 4941 case 8: 4942 *(uint64_t *)vaddr = (uint64_t)regval; 4943 break; 4944 } 4945 } 4946 4947 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4948 struct iocblk *iocp); 4949 #pragma no_inline(bge_pp_ioctl) 4950 4951 static enum ioc_reply 4952 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4953 { 4954 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4955 bge_peekpoke_t *ppd; 4956 dma_area_t *areap; 4957 uint64_t sizemask; 4958 uint64_t mem_va; 4959 uint64_t maxoff; 4960 boolean_t peek; 4961 4962 switch (cmd) { 4963 default: 4964 /* NOTREACHED */ 4965 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4966 return (IOC_INVAL); 4967 4968 case BGE_PEEK: 4969 peek = B_TRUE; 4970 break; 4971 4972 case BGE_POKE: 4973 peek = B_FALSE; 4974 break; 4975 } 4976 4977 /* 4978 * Validate format of ioctl 4979 */ 4980 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4981 return (IOC_INVAL); 4982 if (mp->b_cont == NULL) 4983 return (IOC_INVAL); 4984 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4985 4986 /* 4987 * Validate request parameters 4988 */ 4989 switch (ppd->pp_acc_space) { 4990 default: 4991 return (IOC_INVAL); 4992 4993 case BGE_PP_SPACE_CFG: 4994 /* 4995 * Config space 4996 */ 4997 sizemask = 8|4|2|1; 4998 mem_va = 0; 4999 maxoff = PCI_CONF_HDR_SIZE; 5000 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5001 break; 5002 5003 case BGE_PP_SPACE_REG: 5004 /* 5005 * Memory-mapped I/O space 5006 */ 5007 sizemask = 8|4|2|1; 5008 mem_va = 0; 5009 maxoff = RIAAR_REGISTER_MAX; 5010 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5011 break; 5012 5013 case BGE_PP_SPACE_NIC: 5014 /* 5015 * NIC on-chip memory 5016 */ 5017 sizemask = 8|4|2|1; 5018 mem_va = 0; 5019 maxoff = MWBAR_ONCHIP_MAX; 5020 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5021 break; 5022 5023 case BGE_PP_SPACE_MII: 5024 /* 5025 * PHY's MII registers 5026 * NB: all PHY registers are two bytes, but the 5027 * addresses increment in ones (word addressing). 5028 * So we scale the address here, then undo the 5029 * transformation inside the peek/poke functions. 5030 */ 5031 ppd->pp_acc_offset *= 2; 5032 sizemask = 2; 5033 mem_va = 0; 5034 maxoff = (MII_MAXREG+1)*2; 5035 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5036 break; 5037 5038 #if BGE_SEE_IO32 5039 case BGE_PP_SPACE_SEEPROM: 5040 /* 5041 * Attached SEEPROM(s), if any. 5042 * NB: we use the high-order bits of the 'address' as 5043 * a device select to accommodate multiple SEEPROMS, 5044 * If each one is the maximum size (64kbytes), this 5045 * makes them appear contiguous. Otherwise, there may 5046 * be holes in the mapping. ENxS doesn't have any 5047 * SEEPROMs anyway ... 5048 */ 5049 sizemask = 4; 5050 mem_va = 0; 5051 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5052 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5053 break; 5054 #endif /* BGE_SEE_IO32 */ 5055 5056 #if BGE_FLASH_IO32 5057 case BGE_PP_SPACE_FLASH: 5058 /* 5059 * Attached Flash device (if any); a maximum of one device 5060 * is currently supported. But it can be up to 1MB (unlike 5061 * the 64k limit on SEEPROMs) so why would you need more ;-) 5062 */ 5063 sizemask = 4; 5064 mem_va = 0; 5065 maxoff = NVM_FLASH_ADDR_MASK; 5066 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5067 break; 5068 #endif /* BGE_FLASH_IO32 */ 5069 5070 case BGE_PP_SPACE_BGE: 5071 /* 5072 * BGE data structure! 5073 */ 5074 sizemask = 8|4|2|1; 5075 mem_va = (uintptr_t)bgep; 5076 maxoff = sizeof (*bgep); 5077 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5078 break; 5079 5080 case BGE_PP_SPACE_STATUS: 5081 case BGE_PP_SPACE_STATISTICS: 5082 case BGE_PP_SPACE_TXDESC: 5083 case BGE_PP_SPACE_TXBUFF: 5084 case BGE_PP_SPACE_RXDESC: 5085 case BGE_PP_SPACE_RXBUFF: 5086 /* 5087 * Various DMA_AREAs 5088 */ 5089 switch (ppd->pp_acc_space) { 5090 case BGE_PP_SPACE_TXDESC: 5091 areap = &bgep->tx_desc; 5092 break; 5093 case BGE_PP_SPACE_TXBUFF: 5094 areap = &bgep->tx_buff[0]; 5095 break; 5096 case BGE_PP_SPACE_RXDESC: 5097 areap = &bgep->rx_desc[0]; 5098 break; 5099 case BGE_PP_SPACE_RXBUFF: 5100 areap = &bgep->rx_buff[0]; 5101 break; 5102 case BGE_PP_SPACE_STATUS: 5103 areap = &bgep->status_block; 5104 break; 5105 case BGE_PP_SPACE_STATISTICS: 5106 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5107 areap = &bgep->statistics; 5108 break; 5109 } 5110 5111 sizemask = 8|4|2|1; 5112 mem_va = (uintptr_t)areap->mem_va; 5113 maxoff = areap->alength; 5114 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5115 break; 5116 } 5117 5118 switch (ppd->pp_acc_size) { 5119 default: 5120 return (IOC_INVAL); 5121 5122 case 8: 5123 case 4: 5124 case 2: 5125 case 1: 5126 if ((ppd->pp_acc_size & sizemask) == 0) 5127 return (IOC_INVAL); 5128 break; 5129 } 5130 5131 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5132 return (IOC_INVAL); 5133 5134 if (ppd->pp_acc_offset >= maxoff) 5135 return (IOC_INVAL); 5136 5137 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5138 return (IOC_INVAL); 5139 5140 /* 5141 * All OK - go do it! 5142 */ 5143 ppd->pp_acc_offset += mem_va; 5144 (*ppfn)(bgep, ppd); 5145 return (peek ? IOC_REPLY : IOC_ACK); 5146 } 5147 5148 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5149 struct iocblk *iocp); 5150 #pragma no_inline(bge_diag_ioctl) 5151 5152 static enum ioc_reply 5153 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5154 { 5155 ASSERT(mutex_owned(bgep->genlock)); 5156 5157 switch (cmd) { 5158 default: 5159 /* NOTREACHED */ 5160 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5161 return (IOC_INVAL); 5162 5163 case BGE_DIAG: 5164 /* 5165 * Currently a no-op 5166 */ 5167 return (IOC_ACK); 5168 5169 case BGE_PEEK: 5170 case BGE_POKE: 5171 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5172 5173 case BGE_PHY_RESET: 5174 return (IOC_RESTART_ACK); 5175 5176 case BGE_SOFT_RESET: 5177 case BGE_HARD_RESET: 5178 /* 5179 * Reset and reinitialise the 570x hardware 5180 */ 5181 bgep->bge_chip_state = BGE_CHIP_FAULT; 5182 ddi_trigger_softintr(bgep->factotum_id); 5183 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5184 return (IOC_ACK); 5185 } 5186 5187 /* NOTREACHED */ 5188 } 5189 5190 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5191 5192 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5193 struct iocblk *iocp); 5194 #pragma no_inline(bge_mii_ioctl) 5195 5196 static enum ioc_reply 5197 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5198 { 5199 struct bge_mii_rw *miirwp; 5200 5201 /* 5202 * Validate format of ioctl 5203 */ 5204 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5205 return (IOC_INVAL); 5206 if (mp->b_cont == NULL) 5207 return (IOC_INVAL); 5208 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5209 5210 /* 5211 * Validate request parameters ... 5212 */ 5213 if (miirwp->mii_reg > MII_MAXREG) 5214 return (IOC_INVAL); 5215 5216 switch (cmd) { 5217 default: 5218 /* NOTREACHED */ 5219 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5220 return (IOC_INVAL); 5221 5222 case BGE_MII_READ: 5223 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5224 return (IOC_REPLY); 5225 5226 case BGE_MII_WRITE: 5227 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5228 return (IOC_ACK); 5229 } 5230 5231 /* NOTREACHED */ 5232 } 5233 5234 #if BGE_SEE_IO32 5235 5236 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5237 struct iocblk *iocp); 5238 #pragma no_inline(bge_see_ioctl) 5239 5240 static enum ioc_reply 5241 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5242 { 5243 struct bge_see_rw *seerwp; 5244 5245 /* 5246 * Validate format of ioctl 5247 */ 5248 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5249 return (IOC_INVAL); 5250 if (mp->b_cont == NULL) 5251 return (IOC_INVAL); 5252 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5253 5254 /* 5255 * Validate request parameters ... 5256 */ 5257 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5258 return (IOC_INVAL); 5259 5260 switch (cmd) { 5261 default: 5262 /* NOTREACHED */ 5263 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5264 return (IOC_INVAL); 5265 5266 case BGE_SEE_READ: 5267 case BGE_SEE_WRITE: 5268 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5269 seerwp->see_addr, &seerwp->see_data); 5270 return (IOC_REPLY); 5271 } 5272 5273 /* NOTREACHED */ 5274 } 5275 5276 #endif /* BGE_SEE_IO32 */ 5277 5278 #if BGE_FLASH_IO32 5279 5280 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5281 struct iocblk *iocp); 5282 #pragma no_inline(bge_flash_ioctl) 5283 5284 static enum ioc_reply 5285 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5286 { 5287 struct bge_flash_rw *flashrwp; 5288 5289 /* 5290 * Validate format of ioctl 5291 */ 5292 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5293 return (IOC_INVAL); 5294 if (mp->b_cont == NULL) 5295 return (IOC_INVAL); 5296 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5297 5298 /* 5299 * Validate request parameters ... 5300 */ 5301 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5302 return (IOC_INVAL); 5303 5304 switch (cmd) { 5305 default: 5306 /* NOTREACHED */ 5307 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5308 return (IOC_INVAL); 5309 5310 case BGE_FLASH_READ: 5311 case BGE_FLASH_WRITE: 5312 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5313 flashrwp->flash_addr, &flashrwp->flash_data); 5314 return (IOC_REPLY); 5315 } 5316 5317 /* NOTREACHED */ 5318 } 5319 5320 #endif /* BGE_FLASH_IO32 */ 5321 5322 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5323 struct iocblk *iocp); 5324 #pragma no_inline(bge_chip_ioctl) 5325 5326 enum ioc_reply 5327 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5328 { 5329 int cmd; 5330 5331 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5332 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5333 5334 ASSERT(mutex_owned(bgep->genlock)); 5335 5336 cmd = iocp->ioc_cmd; 5337 switch (cmd) { 5338 default: 5339 /* NOTREACHED */ 5340 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5341 return (IOC_INVAL); 5342 5343 case BGE_DIAG: 5344 case BGE_PEEK: 5345 case BGE_POKE: 5346 case BGE_PHY_RESET: 5347 case BGE_SOFT_RESET: 5348 case BGE_HARD_RESET: 5349 #if BGE_DEBUGGING || BGE_DO_PPIO 5350 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5351 #else 5352 return (IOC_INVAL); 5353 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5354 5355 case BGE_MII_READ: 5356 case BGE_MII_WRITE: 5357 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5358 5359 #if BGE_SEE_IO32 5360 case BGE_SEE_READ: 5361 case BGE_SEE_WRITE: 5362 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5363 #endif /* BGE_SEE_IO32 */ 5364 5365 #if BGE_FLASH_IO32 5366 case BGE_FLASH_READ: 5367 case BGE_FLASH_WRITE: 5368 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5369 #endif /* BGE_FLASH_IO32 */ 5370 } 5371 5372 /* NOTREACHED */ 5373 } 5374 5375 void 5376 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5377 { 5378 bge_t *bgep = arg; 5379 5380 mutex_enter(bgep->genlock); 5381 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5382 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5383 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5384 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5385 mutex_exit(bgep->genlock); 5386 } 5387 5388 #ifdef BGE_IPMI_ASF 5389 5390 uint32_t 5391 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5392 { 5393 uint32_t data; 5394 5395 #ifndef __sparc 5396 if (!bgep->asf_wordswapped) { 5397 /* a workaround word swap error */ 5398 if (addr & 4) 5399 addr = addr - 4; 5400 else 5401 addr = addr + 4; 5402 } 5403 #endif 5404 5405 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5406 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5407 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5408 5409 data = LE_32(data); 5410 return (data); 5411 } 5412 5413 void 5414 bge_asf_update_status(bge_t *bgep) 5415 { 5416 uint32_t event; 5417 5418 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5419 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5420 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5421 5422 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5423 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5424 } 5425 5426 5427 /* 5428 * The driver is supposed to notify ASF that the OS is still running 5429 * every three seconds, otherwise the management server may attempt 5430 * to reboot the machine. If it hasn't actually failed, this is 5431 * not a desirable result. However, this isn't running as a real-time 5432 * thread, and even if it were, it might not be able to generate the 5433 * heartbeat in a timely manner due to system load. As it isn't a 5434 * significant strain on the machine, we will set the interval to half 5435 * of the required value. 5436 */ 5437 void 5438 bge_asf_heartbeat(void *arg) 5439 { 5440 bge_t *bgep = (bge_t *)arg; 5441 5442 mutex_enter(bgep->genlock); 5443 bge_asf_update_status((bge_t *)bgep); 5444 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5445 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5446 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5447 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5448 mutex_exit(bgep->genlock); 5449 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5450 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5451 } 5452 5453 5454 void 5455 bge_asf_stop_timer(bge_t *bgep) 5456 { 5457 timeout_id_t tmp_id = 0; 5458 5459 while ((bgep->asf_timeout_id != 0) && 5460 (tmp_id != bgep->asf_timeout_id)) { 5461 tmp_id = bgep->asf_timeout_id; 5462 (void) untimeout(tmp_id); 5463 } 5464 bgep->asf_timeout_id = 0; 5465 } 5466 5467 5468 5469 /* 5470 * This function should be placed at the earliest position of bge_attach(). 5471 */ 5472 void 5473 bge_asf_get_config(bge_t *bgep) 5474 { 5475 uint32_t nicsig; 5476 uint32_t niccfg; 5477 5478 bgep->asf_enabled = B_FALSE; 5479 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5480 if (nicsig == BGE_NIC_DATA_SIG) { 5481 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5482 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5483 /* 5484 * Here, we don't consider BAXTER, because BGE haven't 5485 * supported BAXTER (that is 5752). Also, as I know, 5486 * BAXTER doesn't support ASF feature. 5487 */ 5488 bgep->asf_enabled = B_TRUE; 5489 else 5490 bgep->asf_enabled = B_FALSE; 5491 } else 5492 bgep->asf_enabled = B_FALSE; 5493 } 5494 5495 5496 void 5497 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5498 { 5499 uint32_t tries; 5500 uint32_t event; 5501 5502 ASSERT(bgep->asf_enabled); 5503 5504 /* Issues "pause firmware" command and wait for ACK */ 5505 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5506 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5507 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5508 5509 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5510 tries = 0; 5511 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5512 drv_usecwait(1); 5513 tries ++; 5514 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5515 } 5516 5517 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5518 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5519 5520 if (bgep->asf_newhandshake) { 5521 switch (mode) { 5522 case BGE_INIT_RESET: 5523 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5524 BGE_DRV_STATE_START); 5525 break; 5526 case BGE_SHUTDOWN_RESET: 5527 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5528 BGE_DRV_STATE_UNLOAD); 5529 break; 5530 case BGE_SUSPEND_RESET: 5531 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5532 BGE_DRV_STATE_SUSPEND); 5533 break; 5534 default: 5535 break; 5536 } 5537 } 5538 } 5539 5540 5541 void 5542 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5543 { 5544 switch (mode) { 5545 case BGE_INIT_RESET: 5546 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5547 BGE_DRV_STATE_START); 5548 break; 5549 case BGE_SHUTDOWN_RESET: 5550 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5551 BGE_DRV_STATE_UNLOAD); 5552 break; 5553 case BGE_SUSPEND_RESET: 5554 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5555 BGE_DRV_STATE_SUSPEND); 5556 break; 5557 default: 5558 break; 5559 } 5560 } 5561 5562 5563 void 5564 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5565 { 5566 switch (mode) { 5567 case BGE_INIT_RESET: 5568 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5569 BGE_DRV_STATE_START_DONE); 5570 break; 5571 case BGE_SHUTDOWN_RESET: 5572 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5573 BGE_DRV_STATE_UNLOAD_DONE); 5574 break; 5575 default: 5576 break; 5577 } 5578 } 5579 5580 #endif /* BGE_IPMI_ASF */ 5581