1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * NO WARRANTY 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 28 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 29 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 30 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 33 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGES. 36 * 37 */ 38 39 #pragma ident "%Z%%M% %I% %E% SMI" 40 41 /* 42 * Driver for the Atheros Wireless LAN controller. 43 * 44 * The Atheros driver calls into net80211 module for IEEE80211 protocol 45 * management functionalities. The driver includes a LLD(Low Level Driver) 46 * part to implement H/W related operations. 47 * The following is the high level structure of ath driver. 48 * (The arrows between modules indicate function call direction.) 49 * 50 * 51 * | 52 * | GLD thread 53 * V 54 * ================== ========================================= 55 * | | |[1] | 56 * | | | GLDv3 Callback functions registered | 57 * | Net80211 | ========================= by | 58 * | module | | | driver | 59 * | | V | | 60 * | |======================== | | 61 * | Functions exported by net80211 | | | 62 * | | | | 63 * ========================================== ================= 64 * | | 65 * V | 66 * +----------------------------------+ | 67 * |[2] | | 68 * | Net80211 Callback functions | | 69 * | registered by LLD | | 70 * +----------------------------------+ | 71 * | | 72 * V v 73 * +-----------------------------------------------------------+ 74 * |[3] | 75 * | LLD Internal functions | 76 * | | 77 * +-----------------------------------------------------------+ 78 * ^ 79 * | Software interrupt thread 80 * | 81 * 82 * The short description of each module is as below: 83 * Module 1: GLD callback functions, which are intercepting the calls from 84 * GLD to LLD. 85 * Module 2: Net80211 callback functions registered by LLD, which 86 * calls into LLD for H/W related functions needed by net80211. 87 * Module 3: LLD Internal functions, which are responsible for allocing 88 * descriptor/buffer, handling interrupt and other H/W 89 * operations. 90 * 91 * All functions are running in 3 types of thread: 92 * 1. GLD callbacks threads, such as ioctl, intr, etc. 93 * 2. Clock interruptt thread which is responsible for scan, rate control and 94 * calibration. 95 * 3. Software Interrupt thread originated in LLD. 96 * 97 * The lock strategy is as below: 98 * There have 4 queues for tx, each queue has one asc_txqlock[i] to 99 * prevent conflicts access to queue resource from different thread. 100 * 101 * All the transmit buffers are contained in asc_txbuf which are 102 * protected by asc_txbuflock. 103 * 104 * Each receive buffers are contained in asc_rxbuf which are protected 105 * by asc_rxbuflock. 106 * 107 * In ath struct, asc_genlock is a general lock, protecting most other 108 * operational data in ath_softc struct and HAL accesses. 109 * It is acquired by the interupt handler and most "mode-ctrl" routines. 110 * 111 * Any of the locks can be acquired singly, but where multiple 112 * locks are acquired, they *must* be in the order: 113 * asc_genlock >> asc_txqlock[i] >> asc_txbuflock >> asc_rxbuflock 114 */ 115 116 #include <sys/param.h> 117 #include <sys/types.h> 118 #include <sys/signal.h> 119 #include <sys/stream.h> 120 #include <sys/termio.h> 121 #include <sys/errno.h> 122 #include <sys/file.h> 123 #include <sys/cmn_err.h> 124 #include <sys/stropts.h> 125 #include <sys/strsubr.h> 126 #include <sys/strtty.h> 127 #include <sys/kbio.h> 128 #include <sys/cred.h> 129 #include <sys/stat.h> 130 #include <sys/consdev.h> 131 #include <sys/kmem.h> 132 #include <sys/modctl.h> 133 #include <sys/ddi.h> 134 #include <sys/sunddi.h> 135 #include <sys/pci.h> 136 #include <sys/errno.h> 137 #include <sys/mac.h> 138 #include <sys/dlpi.h> 139 #include <sys/ethernet.h> 140 #include <sys/list.h> 141 #include <sys/byteorder.h> 142 #include <sys/strsun.h> 143 #include <sys/policy.h> 144 #include <inet/common.h> 145 #include <inet/nd.h> 146 #include <inet/mi.h> 147 #include <inet/wifi_ioctl.h> 148 #include <sys/mac_wifi.h> 149 #include "ath_hal.h" 150 #include "ath_impl.h" 151 #include "ath_aux.h" 152 #include "ath_rate.h" 153 154 #define ATH_MAX_RSSI 63 /* max rssi */ 155 156 extern void ath_halfix_init(void); 157 extern void ath_halfix_finit(void); 158 extern int32_t ath_getset(ath_t *asc, mblk_t *mp, uint32_t cmd); 159 160 /* 161 * PIO access attributes for registers 162 */ 163 static ddi_device_acc_attr_t ath_reg_accattr = { 164 DDI_DEVICE_ATTR_V0, 165 DDI_STRUCTURE_LE_ACC, 166 DDI_STRICTORDER_ACC 167 }; 168 169 /* 170 * DMA access attributes for descriptors: NOT to be byte swapped. 171 */ 172 static ddi_device_acc_attr_t ath_desc_accattr = { 173 DDI_DEVICE_ATTR_V0, 174 DDI_STRUCTURE_LE_ACC, 175 DDI_STRICTORDER_ACC 176 }; 177 178 /* 179 * Describes the chip's DMA engine 180 */ 181 static ddi_dma_attr_t ath_dma_attr = { 182 DMA_ATTR_V0, /* version number */ 183 0, /* low address */ 184 0xffffffffU, /* high address */ 185 0x3ffffU, /* counter register max */ 186 1, /* alignment */ 187 0xFFF, /* burst sizes */ 188 1, /* minimum transfer size */ 189 0x3ffffU, /* max transfer size */ 190 0xffffffffU, /* address register max */ 191 1, /* no scatter-gather */ 192 1, /* granularity of device */ 193 0, /* DMA flags */ 194 }; 195 196 static ddi_dma_attr_t ath_desc_dma_attr = { 197 DMA_ATTR_V0, /* version number */ 198 0, /* low address */ 199 0xffffffffU, /* high address */ 200 0xffffffffU, /* counter register max */ 201 0x1000, /* alignment */ 202 0xFFF, /* burst sizes */ 203 1, /* minimum transfer size */ 204 0xffffffffU, /* max transfer size */ 205 0xffffffffU, /* address register max */ 206 1, /* no scatter-gather */ 207 1, /* granularity of device */ 208 0, /* DMA flags */ 209 }; 210 211 static kmutex_t ath_loglock; 212 static void *ath_soft_state_p = NULL; 213 static int ath_dwelltime = 150; /* scan interval, ms */ 214 215 static int ath_m_stat(void *, uint_t, uint64_t *); 216 static int ath_m_start(void *); 217 static void ath_m_stop(void *); 218 static int ath_m_promisc(void *, boolean_t); 219 static int ath_m_multicst(void *, boolean_t, const uint8_t *); 220 static int ath_m_unicst(void *, const uint8_t *); 221 static mblk_t *ath_m_tx(void *, mblk_t *); 222 static void ath_m_ioctl(void *, queue_t *, mblk_t *); 223 static mac_callbacks_t ath_m_callbacks = { 224 MC_IOCTL, 225 ath_m_stat, 226 ath_m_start, 227 ath_m_stop, 228 ath_m_promisc, 229 ath_m_multicst, 230 ath_m_unicst, 231 ath_m_tx, 232 NULL, /* mc_resources; */ 233 ath_m_ioctl, 234 NULL /* mc_getcapab */ 235 }; 236 237 /* 238 * Available debug flags: 239 * ATH_DBG_INIT, ATH_DBG_GLD, ATH_DBG_HAL, ATH_DBG_INT, ATH_DBG_ATTACH, 240 * ATH_DBG_DETACH, ATH_DBG_AUX, ATH_DBG_WIFICFG, ATH_DBG_OSDEP 241 */ 242 uint32_t ath_dbg_flags = 0; 243 244 /* 245 * Exception/warning cases not leading to panic. 246 */ 247 void 248 ath_problem(const int8_t *fmt, ...) 249 { 250 va_list args; 251 252 mutex_enter(&ath_loglock); 253 254 va_start(args, fmt); 255 vcmn_err(CE_WARN, fmt, args); 256 va_end(args); 257 258 mutex_exit(&ath_loglock); 259 } 260 261 /* 262 * Normal log information independent of debug. 263 */ 264 void 265 ath_log(const int8_t *fmt, ...) 266 { 267 va_list args; 268 269 mutex_enter(&ath_loglock); 270 271 va_start(args, fmt); 272 vcmn_err(CE_CONT, fmt, args); 273 va_end(args); 274 275 mutex_exit(&ath_loglock); 276 } 277 278 void 279 ath_dbg(uint32_t dbg_flags, const int8_t *fmt, ...) 280 { 281 va_list args; 282 283 if (dbg_flags & ath_dbg_flags) { 284 mutex_enter(&ath_loglock); 285 va_start(args, fmt); 286 vcmn_err(CE_CONT, fmt, args); 287 va_end(args); 288 mutex_exit(&ath_loglock); 289 } 290 } 291 292 void 293 ath_setup_desc(ath_t *asc, struct ath_buf *bf) 294 { 295 struct ath_desc *ds; 296 297 ds = bf->bf_desc; 298 ds->ds_link = bf->bf_daddr; 299 ds->ds_data = bf->bf_dma.cookie.dmac_address; 300 ds->ds_vdata = bf->bf_dma.mem_va; 301 ATH_HAL_SETUPRXDESC(asc->asc_ah, ds, 302 bf->bf_dma.alength, /* buffer size */ 303 0); 304 305 if (asc->asc_rxlink != NULL) 306 *asc->asc_rxlink = bf->bf_daddr; 307 asc->asc_rxlink = &ds->ds_link; 308 } 309 310 311 /* 312 * Allocate an area of memory and a DMA handle for accessing it 313 */ 314 static int 315 ath_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr, size_t memsize, 316 ddi_device_acc_attr_t *attr_p, uint_t alloc_flags, 317 uint_t bind_flags, dma_area_t *dma_p) 318 { 319 int err; 320 321 /* 322 * Allocate handle 323 */ 324 err = ddi_dma_alloc_handle(devinfo, dma_attr, 325 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 326 if (err != DDI_SUCCESS) 327 return (DDI_FAILURE); 328 329 /* 330 * Allocate memory 331 */ 332 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 333 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va, 334 &dma_p->alength, &dma_p->acc_hdl); 335 if (err != DDI_SUCCESS) 336 return (DDI_FAILURE); 337 338 /* 339 * Bind the two together 340 */ 341 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 342 dma_p->mem_va, dma_p->alength, bind_flags, 343 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies); 344 if (err != DDI_DMA_MAPPED) 345 return (DDI_FAILURE); 346 347 dma_p->nslots = ~0U; 348 dma_p->size = ~0U; 349 dma_p->token = ~0U; 350 dma_p->offset = 0; 351 return (DDI_SUCCESS); 352 } 353 354 /* 355 * Free one allocated area of DMAable memory 356 */ 357 static void 358 ath_free_dma_mem(dma_area_t *dma_p) 359 { 360 if (dma_p->dma_hdl != NULL) { 361 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 362 if (dma_p->acc_hdl != NULL) { 363 ddi_dma_mem_free(&dma_p->acc_hdl); 364 dma_p->acc_hdl = NULL; 365 } 366 ddi_dma_free_handle(&dma_p->dma_hdl); 367 dma_p->ncookies = 0; 368 dma_p->dma_hdl = NULL; 369 } 370 } 371 372 373 static int 374 ath_desc_alloc(dev_info_t *devinfo, ath_t *asc) 375 { 376 int i, err; 377 size_t size; 378 struct ath_desc *ds; 379 struct ath_buf *bf; 380 381 size = sizeof (struct ath_desc) * (ATH_TXBUF + ATH_RXBUF); 382 383 err = ath_alloc_dma_mem(devinfo, &ath_desc_dma_attr, size, 384 &ath_desc_accattr, DDI_DMA_CONSISTENT, 385 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &asc->asc_desc_dma); 386 387 /* virtual address of the first descriptor */ 388 asc->asc_desc = (struct ath_desc *)asc->asc_desc_dma.mem_va; 389 390 ds = asc->asc_desc; 391 ATH_DEBUG((ATH_DBG_INIT, "ath: ath_desc_alloc(): DMA map: " 392 "%p (%d) -> %p\n", 393 asc->asc_desc, asc->asc_desc_dma.alength, 394 asc->asc_desc_dma.cookie.dmac_address)); 395 396 /* allocate data structures to describe TX/RX DMA buffers */ 397 asc->asc_vbuflen = sizeof (struct ath_buf) * (ATH_TXBUF + ATH_RXBUF); 398 bf = (struct ath_buf *)kmem_zalloc(asc->asc_vbuflen, KM_SLEEP); 399 asc->asc_vbufptr = bf; 400 401 /* DMA buffer size for each TX/RX packet */ 402 asc->asc_dmabuf_size = roundup(1000 + sizeof (struct ieee80211_frame) + 403 IEEE80211_MTU + IEEE80211_CRC_LEN + 404 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 405 IEEE80211_WEP_CRCLEN), asc->asc_cachelsz); 406 407 /* create RX buffer list and allocate DMA memory */ 408 list_create(&asc->asc_rxbuf_list, sizeof (struct ath_buf), 409 offsetof(struct ath_buf, bf_node)); 410 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++) { 411 bf->bf_desc = ds; 412 bf->bf_daddr = asc->asc_desc_dma.cookie.dmac_address + 413 ((uintptr_t)ds - (uintptr_t)asc->asc_desc); 414 list_insert_tail(&asc->asc_rxbuf_list, bf); 415 416 /* alloc DMA memory */ 417 err = ath_alloc_dma_mem(devinfo, &ath_dma_attr, 418 asc->asc_dmabuf_size, &ath_desc_accattr, 419 DDI_DMA_STREAMING, DDI_DMA_READ | DDI_DMA_STREAMING, 420 &bf->bf_dma); 421 if (err != DDI_SUCCESS) 422 return (err); 423 } 424 425 /* create TX buffer list and allocate DMA memory */ 426 list_create(&asc->asc_txbuf_list, sizeof (struct ath_buf), 427 offsetof(struct ath_buf, bf_node)); 428 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++) { 429 bf->bf_desc = ds; 430 bf->bf_daddr = asc->asc_desc_dma.cookie.dmac_address + 431 ((uintptr_t)ds - (uintptr_t)asc->asc_desc); 432 list_insert_tail(&asc->asc_txbuf_list, bf); 433 434 /* alloc DMA memory */ 435 err = ath_alloc_dma_mem(devinfo, &ath_dma_attr, 436 asc->asc_dmabuf_size, &ath_desc_accattr, 437 DDI_DMA_STREAMING, DDI_DMA_STREAMING, &bf->bf_dma); 438 if (err != DDI_SUCCESS) 439 return (err); 440 } 441 442 return (DDI_SUCCESS); 443 } 444 445 static void 446 ath_desc_free(ath_t *asc) 447 { 448 struct ath_buf *bf; 449 450 /* Free TX DMA buffer */ 451 bf = list_head(&asc->asc_txbuf_list); 452 while (bf != NULL) { 453 ath_free_dma_mem(&bf->bf_dma); 454 list_remove(&asc->asc_txbuf_list, bf); 455 bf = list_head(&asc->asc_txbuf_list); 456 } 457 list_destroy(&asc->asc_txbuf_list); 458 459 /* Free RX DMA uffer */ 460 bf = list_head(&asc->asc_rxbuf_list); 461 while (bf != NULL) { 462 ath_free_dma_mem(&bf->bf_dma); 463 list_remove(&asc->asc_rxbuf_list, bf); 464 bf = list_head(&asc->asc_rxbuf_list); 465 } 466 list_destroy(&asc->asc_rxbuf_list); 467 468 /* Free descriptor DMA buffer */ 469 ath_free_dma_mem(&asc->asc_desc_dma); 470 471 kmem_free((void *)asc->asc_vbufptr, asc->asc_vbuflen); 472 asc->asc_vbufptr = NULL; 473 } 474 475 static void 476 ath_printrxbuf(struct ath_buf *bf, int32_t done) 477 { 478 struct ath_desc *ds = bf->bf_desc; 479 480 ATH_DEBUG((ATH_DBG_RECV, "ath: R (%p %p) %08x %08x %08x " 481 "%08x %08x %08x %c\n", 482 ds, bf->bf_daddr, 483 ds->ds_link, ds->ds_data, 484 ds->ds_ctl0, ds->ds_ctl1, 485 ds->ds_hw[0], ds->ds_hw[1], 486 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!')); 487 } 488 489 static void 490 ath_rx_handler(ath_t *asc) 491 { 492 ieee80211com_t *ic = (ieee80211com_t *)asc; 493 struct ath_buf *bf; 494 struct ath_hal *ah = asc->asc_ah; 495 struct ath_desc *ds; 496 mblk_t *rx_mp; 497 struct ieee80211_frame *wh; 498 int32_t len, loop = 1; 499 uint8_t phyerr; 500 HAL_STATUS status; 501 HAL_NODE_STATS hal_node_stats; 502 struct ieee80211_node *in; 503 504 do { 505 mutex_enter(&asc->asc_rxbuflock); 506 bf = list_head(&asc->asc_rxbuf_list); 507 if (bf == NULL) { 508 ATH_DEBUG((ATH_DBG_RECV, "ath: ath_rx_handler(): " 509 "no buffer\n")); 510 mutex_exit(&asc->asc_rxbuflock); 511 break; 512 } 513 ASSERT(bf->bf_dma.cookie.dmac_address != NULL); 514 ds = bf->bf_desc; 515 if (ds->ds_link == bf->bf_daddr) { 516 /* 517 * Never process the self-linked entry at the end, 518 * this may be met at heavy load. 519 */ 520 mutex_exit(&asc->asc_rxbuflock); 521 break; 522 } 523 524 status = ATH_HAL_RXPROCDESC(ah, ds, 525 bf->bf_daddr, 526 ATH_PA2DESC(asc, ds->ds_link)); 527 if (status == HAL_EINPROGRESS) { 528 mutex_exit(&asc->asc_rxbuflock); 529 break; 530 } 531 list_remove(&asc->asc_rxbuf_list, bf); 532 mutex_exit(&asc->asc_rxbuflock); 533 534 if (ds->ds_rxstat.rs_status != 0) { 535 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 536 asc->asc_stats.ast_rx_crcerr++; 537 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 538 asc->asc_stats.ast_rx_fifoerr++; 539 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) 540 asc->asc_stats.ast_rx_badcrypt++; 541 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 542 asc->asc_stats.ast_rx_phyerr++; 543 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 544 asc->asc_stats.ast_rx_phy[phyerr]++; 545 } 546 goto rx_next; 547 } 548 len = ds->ds_rxstat.rs_datalen; 549 550 /* less than sizeof(struct ieee80211_frame) */ 551 if (len < 20) { 552 asc->asc_stats.ast_rx_tooshort++; 553 goto rx_next; 554 } 555 556 if ((rx_mp = allocb(asc->asc_dmabuf_size, BPRI_MED)) == NULL) { 557 ath_problem("ath: ath_rx_handler(): " 558 "allocing mblk buffer failed.\n"); 559 return; 560 } 561 562 ATH_DMA_SYNC(bf->bf_dma, DDI_DMA_SYNC_FORCPU); 563 bcopy(bf->bf_dma.mem_va, rx_mp->b_rptr, len); 564 565 rx_mp->b_wptr += len; 566 wh = (struct ieee80211_frame *)rx_mp->b_rptr; 567 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 568 IEEE80211_FC0_TYPE_CTL) { 569 /* 570 * Ignore control frame received in promisc mode. 571 */ 572 freemsg(rx_mp); 573 goto rx_next; 574 } 575 /* Remove the CRC at the end of IEEE80211 frame */ 576 rx_mp->b_wptr -= IEEE80211_CRC_LEN; 577 #ifdef DEBUG 578 ath_printrxbuf(bf, status == HAL_OK); 579 #endif /* DEBUG */ 580 /* 581 * Locate the node for sender, track state, and then 582 * pass the (referenced) node up to the 802.11 layer 583 * for its use. 584 */ 585 in = ieee80211_find_rxnode(ic, wh); 586 587 /* 588 * Send frame up for processing. 589 */ 590 (void) ieee80211_input(ic, rx_mp, in, 591 ds->ds_rxstat.rs_rssi, 592 ds->ds_rxstat.rs_tstamp); 593 594 ieee80211_free_node(in); 595 596 rx_next: 597 mutex_enter(&asc->asc_rxbuflock); 598 list_insert_tail(&asc->asc_rxbuf_list, bf); 599 mutex_exit(&asc->asc_rxbuflock); 600 ath_setup_desc(asc, bf); 601 } while (loop); 602 603 /* rx signal state monitoring */ 604 ATH_HAL_RXMONITOR(ah, &hal_node_stats, &asc->asc_curchan); 605 } 606 607 static void 608 ath_printtxbuf(struct ath_buf *bf, int done) 609 { 610 struct ath_desc *ds = bf->bf_desc; 611 612 ATH_DEBUG((ATH_DBG_SEND, "ath: T(%p %p) %08x %08x %08x %08x %08x" 613 " %08x %08x %08x %c\n", 614 ds, bf->bf_daddr, 615 ds->ds_link, ds->ds_data, 616 ds->ds_ctl0, ds->ds_ctl1, 617 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 618 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!')); 619 } 620 621 /* 622 * The input parameter mp has following assumption: 623 * For data packets, GLDv3 mac_wifi plugin allocates and fills the 624 * ieee80211 header. For management packets, net80211 allocates and 625 * fills the ieee80211 header. In both cases, enough spaces in the 626 * header are left for encryption option. 627 */ 628 static int32_t 629 ath_tx_start(ath_t *asc, struct ieee80211_node *in, struct ath_buf *bf, 630 mblk_t *mp) 631 { 632 ieee80211com_t *ic = (ieee80211com_t *)asc; 633 struct ieee80211_frame *wh; 634 struct ath_hal *ah = asc->asc_ah; 635 uint32_t subtype, flags, ctsduration; 636 int32_t keyix, iswep, hdrlen, pktlen, mblen, mbslen, try0; 637 uint8_t rix, cix, txrate, ctsrate; 638 struct ath_desc *ds; 639 struct ath_txq *txq; 640 HAL_PKT_TYPE atype; 641 const HAL_RATE_TABLE *rt; 642 HAL_BOOL shortPreamble; 643 struct ath_node *an; 644 caddr_t dest; 645 646 /* 647 * CRC are added by H/W, not encaped by driver, 648 * but we must count it in pkt length. 649 */ 650 pktlen = IEEE80211_CRC_LEN; 651 652 wh = (struct ieee80211_frame *)mp->b_rptr; 653 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 654 keyix = HAL_TXKEYIX_INVALID; 655 hdrlen = sizeof (struct ieee80211_frame); 656 if (iswep != 0) { 657 const struct ieee80211_cipher *cip; 658 struct ieee80211_key *k; 659 660 /* 661 * Construct the 802.11 header+trailer for an encrypted 662 * frame. The only reason this can fail is because of an 663 * unknown or unsupported cipher/key type. 664 */ 665 k = ieee80211_crypto_encap(ic, mp); 666 if (k == NULL) { 667 ATH_DEBUG((ATH_DBG_AUX, "crypto_encap failed\n")); 668 /* 669 * This can happen when the key is yanked after the 670 * frame was queued. Just discard the frame; the 671 * 802.11 layer counts failures and provides 672 * debugging/diagnostics. 673 */ 674 return (EIO); 675 } 676 cip = k->wk_cipher; 677 /* 678 * Adjust the packet + header lengths for the crypto 679 * additions and calculate the h/w key index. When 680 * a s/w mic is done the frame will have had any mic 681 * added to it prior to entry so m0->m_pkthdr.len above will 682 * account for it. Otherwise we need to add it to the 683 * packet length. 684 */ 685 hdrlen += cip->ic_header; 686 pktlen += cip->ic_trailer; 687 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 688 pktlen += cip->ic_miclen; 689 keyix = k->wk_keyix; 690 691 /* packet header may have moved, reset our local pointer */ 692 wh = (struct ieee80211_frame *)mp->b_rptr; 693 } 694 695 dest = bf->bf_dma.mem_va; 696 for (; mp != NULL; mp = mp->b_cont) { 697 mblen = MBLKL(mp); 698 bcopy(mp->b_rptr, dest, mblen); 699 dest += mblen; 700 } 701 mbslen = (uintptr_t)dest - (uintptr_t)bf->bf_dma.mem_va; 702 pktlen += mbslen; 703 704 bf->bf_in = in; 705 706 /* setup descriptors */ 707 ds = bf->bf_desc; 708 rt = asc->asc_currates; 709 ASSERT(rt != NULL); 710 711 /* 712 * The 802.11 layer marks whether or not we should 713 * use short preamble based on the current mode and 714 * negotiated parameters. 715 */ 716 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 717 (in->in_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 718 shortPreamble = AH_TRUE; 719 asc->asc_stats.ast_tx_shortpre++; 720 } else { 721 shortPreamble = AH_FALSE; 722 } 723 724 an = ATH_NODE(in); 725 726 /* 727 * Calculate Atheros packet type from IEEE80211 packet header 728 * and setup for rate calculations. 729 */ 730 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 731 case IEEE80211_FC0_TYPE_MGT: 732 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 733 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 734 atype = HAL_PKT_TYPE_BEACON; 735 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 736 atype = HAL_PKT_TYPE_PROBE_RESP; 737 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 738 atype = HAL_PKT_TYPE_ATIM; 739 else 740 atype = HAL_PKT_TYPE_NORMAL; 741 rix = 0; /* lowest rate */ 742 try0 = ATH_TXMAXTRY; 743 if (shortPreamble) 744 txrate = an->an_tx_mgtratesp; 745 else 746 txrate = an->an_tx_mgtrate; 747 /* force all ctl frames to highest queue */ 748 txq = asc->asc_ac2q[WME_AC_VO]; 749 break; 750 case IEEE80211_FC0_TYPE_CTL: 751 atype = HAL_PKT_TYPE_PSPOLL; 752 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 753 rix = 0; /* lowest rate */ 754 try0 = ATH_TXMAXTRY; 755 if (shortPreamble) 756 txrate = an->an_tx_mgtratesp; 757 else 758 txrate = an->an_tx_mgtrate; 759 /* force all ctl frames to highest queue */ 760 txq = asc->asc_ac2q[WME_AC_VO]; 761 break; 762 case IEEE80211_FC0_TYPE_DATA: 763 atype = HAL_PKT_TYPE_NORMAL; 764 rix = an->an_tx_rix0; 765 try0 = an->an_tx_try0; 766 if (shortPreamble) 767 txrate = an->an_tx_rate0sp; 768 else 769 txrate = an->an_tx_rate0; 770 /* Always use background queue */ 771 txq = asc->asc_ac2q[WME_AC_BK]; 772 break; 773 default: 774 /* Unknown 802.11 frame */ 775 asc->asc_stats.ast_tx_invalid++; 776 return (1); 777 } 778 /* 779 * Calculate miscellaneous flags. 780 */ 781 flags = HAL_TXDESC_CLRDMASK; 782 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 783 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 784 asc->asc_stats.ast_tx_noack++; 785 } else if (pktlen > ic->ic_rtsthreshold) { 786 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 787 asc->asc_stats.ast_tx_rts++; 788 } 789 790 /* 791 * Calculate duration. This logically belongs in the 802.11 792 * layer but it lacks sufficient information to calculate it. 793 */ 794 if ((flags & HAL_TXDESC_NOACK) == 0 && 795 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 796 IEEE80211_FC0_TYPE_CTL) { 797 uint16_t dur; 798 dur = ath_hal_computetxtime(ah, rt, IEEE80211_ACK_SIZE, 799 rix, shortPreamble); 800 *(uint16_t *)wh->i_dur = LE_16(dur); 801 } 802 803 /* 804 * Calculate RTS/CTS rate and duration if needed. 805 */ 806 ctsduration = 0; 807 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 808 /* 809 * CTS transmit rate is derived from the transmit rate 810 * by looking in the h/w rate table. We must also factor 811 * in whether or not a short preamble is to be used. 812 */ 813 cix = rt->info[rix].controlRate; 814 ctsrate = rt->info[cix].rateCode; 815 if (shortPreamble) 816 ctsrate |= rt->info[cix].shortPreamble; 817 /* 818 * Compute the transmit duration based on the size 819 * of an ACK frame. We call into the HAL to do the 820 * computation since it depends on the characteristics 821 * of the actual PHY being used. 822 */ 823 if (flags & HAL_TXDESC_RTSENA) { /* SIFS + CTS */ 824 ctsduration += ath_hal_computetxtime(ah, 825 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 826 } 827 /* SIFS + data */ 828 ctsduration += ath_hal_computetxtime(ah, 829 rt, pktlen, rix, shortPreamble); 830 if ((flags & HAL_TXDESC_NOACK) == 0) { /* SIFS + ACK */ 831 ctsduration += ath_hal_computetxtime(ah, 832 rt, IEEE80211_ACK_SIZE, cix, shortPreamble); 833 } 834 } else 835 ctsrate = 0; 836 837 if (++txq->axq_intrcnt >= ATH_TXINTR_PERIOD) { 838 flags |= HAL_TXDESC_INTREQ; 839 txq->axq_intrcnt = 0; 840 } 841 842 /* 843 * Formulate first tx descriptor with tx controls. 844 */ 845 ATH_HAL_SETUPTXDESC(ah, ds, 846 pktlen, /* packet length */ 847 hdrlen, /* header length */ 848 atype, /* Atheros packet type */ 849 MIN(in->in_txpower, 60), /* txpower */ 850 txrate, try0, /* series 0 rate/tries */ 851 keyix, /* key cache index */ 852 an->an_tx_antenna, /* antenna mode */ 853 flags, /* flags */ 854 ctsrate, /* rts/cts rate */ 855 ctsduration); /* rts/cts duration */ 856 bf->bf_flags = flags; 857 858 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_xmit(): to %s totlen=%d " 859 "an->an_tx_rate1sp=%d tx_rate2sp=%d tx_rate3sp=%d " 860 "qnum=%d rix=%d sht=%d dur = %d\n", 861 ieee80211_macaddr_sprintf(wh->i_addr1), mbslen, an->an_tx_rate1sp, 862 an->an_tx_rate2sp, an->an_tx_rate3sp, 863 txq->axq_qnum, rix, shortPreamble, *(uint16_t *)wh->i_dur)); 864 865 /* 866 * Setup the multi-rate retry state only when we're 867 * going to use it. This assumes ath_hal_setuptxdesc 868 * initializes the descriptors (so we don't have to) 869 * when the hardware supports multi-rate retry and 870 * we don't use it. 871 */ 872 if (try0 != ATH_TXMAXTRY) 873 ATH_HAL_SETUPXTXDESC(ah, ds, 874 an->an_tx_rate1sp, 2, /* series 1 */ 875 an->an_tx_rate2sp, 2, /* series 2 */ 876 an->an_tx_rate3sp, 2); /* series 3 */ 877 878 ds->ds_link = 0; 879 ds->ds_data = bf->bf_dma.cookie.dmac_address; 880 ATH_HAL_FILLTXDESC(ah, ds, 881 mbslen, /* segment length */ 882 AH_TRUE, /* first segment */ 883 AH_TRUE, /* last segment */ 884 ds); /* first descriptor */ 885 886 ATH_DMA_SYNC(bf->bf_dma, DDI_DMA_SYNC_FORDEV); 887 888 mutex_enter(&txq->axq_lock); 889 list_insert_tail(&txq->axq_list, bf); 890 if (txq->axq_link == NULL) { 891 ATH_HAL_PUTTXBUF(ah, txq->axq_qnum, bf->bf_daddr); 892 } else { 893 *txq->axq_link = bf->bf_daddr; 894 } 895 txq->axq_link = &ds->ds_link; 896 mutex_exit(&txq->axq_lock); 897 898 ATH_HAL_TXSTART(ah, txq->axq_qnum); 899 900 ic->ic_stats.is_tx_frags++; 901 ic->ic_stats.is_tx_bytes += pktlen; 902 903 return (0); 904 } 905 906 /* 907 * Transmit a management frame. On failure we reclaim the skbuff. 908 * Note that management frames come directly from the 802.11 layer 909 * and do not honor the send queue flow control. Need to investigate 910 * using priority queueing so management frames can bypass data. 911 */ 912 static int 913 ath_xmit(ieee80211com_t *ic, mblk_t *mp, uint8_t type) 914 { 915 ath_t *asc = (ath_t *)ic; 916 struct ath_hal *ah = asc->asc_ah; 917 struct ieee80211_node *in = NULL; 918 struct ath_buf *bf = NULL; 919 struct ieee80211_frame *wh; 920 int error = 0; 921 922 ASSERT(mp->b_next == NULL); 923 924 if (!ATH_IS_RUNNING(asc)) { 925 if ((type & IEEE80211_FC0_TYPE_MASK) != 926 IEEE80211_FC0_TYPE_DATA) { 927 freemsg(mp); 928 } 929 return (ENXIO); 930 } 931 932 /* Grab a TX buffer */ 933 mutex_enter(&asc->asc_txbuflock); 934 bf = list_head(&asc->asc_txbuf_list); 935 if (bf != NULL) 936 list_remove(&asc->asc_txbuf_list, bf); 937 if (list_empty(&asc->asc_txbuf_list)) { 938 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_mgmt_send(): " 939 "stop queue\n")); 940 asc->asc_stats.ast_tx_qstop++; 941 } 942 mutex_exit(&asc->asc_txbuflock); 943 if (bf == NULL) { 944 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_mgmt_send(): discard, " 945 "no xmit buf\n")); 946 ic->ic_stats.is_tx_nobuf++; 947 if ((type & IEEE80211_FC0_TYPE_MASK) == 948 IEEE80211_FC0_TYPE_DATA) { 949 asc->asc_stats.ast_tx_nobuf++; 950 mutex_enter(&asc->asc_resched_lock); 951 asc->asc_resched_needed = B_TRUE; 952 mutex_exit(&asc->asc_resched_lock); 953 } else { 954 asc->asc_stats.ast_tx_nobufmgt++; 955 freemsg(mp); 956 } 957 return (ENOMEM); 958 } 959 960 wh = (struct ieee80211_frame *)mp->b_rptr; 961 962 /* Locate node */ 963 in = ieee80211_find_txnode(ic, wh->i_addr1); 964 if (in == NULL) { 965 error = EIO; 966 goto bad; 967 } 968 969 in->in_inact = 0; 970 switch (type & IEEE80211_FC0_TYPE_MASK) { 971 case IEEE80211_FC0_TYPE_DATA: 972 (void) ieee80211_encap(ic, mp, in); 973 break; 974 default: 975 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 976 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 977 /* fill time stamp */ 978 uint64_t tsf; 979 uint32_t *tstamp; 980 981 tsf = ATH_HAL_GETTSF64(ah); 982 /* adjust 100us delay to xmit */ 983 tsf += 100; 984 tstamp = (uint32_t *)&wh[1]; 985 tstamp[0] = LE_32(tsf & 0xffffffff); 986 tstamp[1] = LE_32(tsf >> 32); 987 } 988 asc->asc_stats.ast_tx_mgmt++; 989 break; 990 } 991 992 error = ath_tx_start(asc, in, bf, mp); 993 if (error != 0) { 994 bad: 995 ic->ic_stats.is_tx_failed++; 996 if (bf != NULL) { 997 mutex_enter(&asc->asc_txbuflock); 998 list_insert_tail(&asc->asc_txbuf_list, bf); 999 mutex_exit(&asc->asc_txbuflock); 1000 } 1001 } 1002 if (in != NULL) 1003 ieee80211_free_node(in); 1004 if ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA || 1005 error == 0) { 1006 freemsg(mp); 1007 } 1008 1009 return (error); 1010 } 1011 1012 static mblk_t * 1013 ath_m_tx(void *arg, mblk_t *mp) 1014 { 1015 ath_t *asc = arg; 1016 ieee80211com_t *ic = (ieee80211com_t *)asc; 1017 mblk_t *next; 1018 int error = 0; 1019 1020 /* 1021 * No data frames go out unless we're associated; this 1022 * should not happen as the 802.11 layer does not enable 1023 * the xmit queue until we enter the RUN state. 1024 */ 1025 if (ic->ic_state != IEEE80211_S_RUN) { 1026 ATH_DEBUG((ATH_DBG_SEND, "ath: ath_m_tx(): " 1027 "discard, state %u\n", ic->ic_state)); 1028 asc->asc_stats.ast_tx_discard++; 1029 freemsgchain(mp); 1030 return (NULL); 1031 } 1032 1033 while (mp != NULL) { 1034 next = mp->b_next; 1035 mp->b_next = NULL; 1036 error = ath_xmit(ic, mp, IEEE80211_FC0_TYPE_DATA); 1037 if (error != 0) { 1038 mp->b_next = next; 1039 if (error == ENOMEM) { 1040 break; 1041 } else { 1042 freemsgchain(mp); /* CR6501759 issues */ 1043 return (NULL); 1044 } 1045 } 1046 mp = next; 1047 } 1048 1049 return (mp); 1050 1051 } 1052 1053 static int 1054 ath_tx_processq(ath_t *asc, struct ath_txq *txq) 1055 { 1056 ieee80211com_t *ic = (ieee80211com_t *)asc; 1057 struct ath_hal *ah = asc->asc_ah; 1058 struct ath_buf *bf; 1059 struct ath_desc *ds; 1060 struct ieee80211_node *in; 1061 int32_t sr, lr, nacked = 0; 1062 HAL_STATUS status; 1063 struct ath_node *an; 1064 1065 for (;;) { 1066 mutex_enter(&txq->axq_lock); 1067 bf = list_head(&txq->axq_list); 1068 if (bf == NULL) { 1069 txq->axq_link = NULL; 1070 mutex_exit(&txq->axq_lock); 1071 break; 1072 } 1073 ds = bf->bf_desc; /* last decriptor */ 1074 status = ATH_HAL_TXPROCDESC(ah, ds); 1075 #ifdef DEBUG 1076 ath_printtxbuf(bf, status == HAL_OK); 1077 #endif 1078 if (status == HAL_EINPROGRESS) { 1079 mutex_exit(&txq->axq_lock); 1080 break; 1081 } 1082 list_remove(&txq->axq_list, bf); 1083 mutex_exit(&txq->axq_lock); 1084 in = bf->bf_in; 1085 if (in != NULL) { 1086 an = ATH_NODE(in); 1087 /* Successful transmition */ 1088 if (ds->ds_txstat.ts_status == 0) { 1089 an->an_tx_ok++; 1090 an->an_tx_antenna = 1091 ds->ds_txstat.ts_antenna; 1092 if (ds->ds_txstat.ts_rate & 1093 HAL_TXSTAT_ALTRATE) 1094 asc->asc_stats.ast_tx_altrate++; 1095 asc->asc_stats.ast_tx_rssidelta = 1096 ds->ds_txstat.ts_rssi - 1097 asc->asc_stats.ast_tx_rssi; 1098 asc->asc_stats.ast_tx_rssi = 1099 ds->ds_txstat.ts_rssi; 1100 } else { 1101 an->an_tx_err++; 1102 if (ds->ds_txstat.ts_status & 1103 HAL_TXERR_XRETRY) 1104 asc->asc_stats. 1105 ast_tx_xretries++; 1106 if (ds->ds_txstat.ts_status & 1107 HAL_TXERR_FIFO) 1108 asc->asc_stats.ast_tx_fifoerr++; 1109 if (ds->ds_txstat.ts_status & 1110 HAL_TXERR_FILT) 1111 asc->asc_stats. 1112 ast_tx_filtered++; 1113 an->an_tx_antenna = 0; /* invalidate */ 1114 } 1115 sr = ds->ds_txstat.ts_shortretry; 1116 lr = ds->ds_txstat.ts_longretry; 1117 asc->asc_stats.ast_tx_shortretry += sr; 1118 asc->asc_stats.ast_tx_longretry += lr; 1119 /* 1120 * Hand the descriptor to the rate control algorithm. 1121 */ 1122 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 1123 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { 1124 /* 1125 * If frame was ack'd update the last rx time 1126 * used to workaround phantom bmiss interrupts. 1127 */ 1128 if (ds->ds_txstat.ts_status == 0) { 1129 nacked++; 1130 an->an_tx_ok++; 1131 } else { 1132 an->an_tx_err++; 1133 } 1134 an->an_tx_retr += sr + lr; 1135 } 1136 } 1137 bf->bf_in = NULL; 1138 mutex_enter(&asc->asc_txbuflock); 1139 list_insert_tail(&asc->asc_txbuf_list, bf); 1140 mutex_exit(&asc->asc_txbuflock); 1141 /* 1142 * Reschedule stalled outbound packets 1143 */ 1144 mutex_enter(&asc->asc_resched_lock); 1145 if (asc->asc_resched_needed) { 1146 asc->asc_resched_needed = B_FALSE; 1147 mac_tx_update(ic->ic_mach); 1148 } 1149 mutex_exit(&asc->asc_resched_lock); 1150 } 1151 return (nacked); 1152 } 1153 1154 1155 static void 1156 ath_tx_handler(ath_t *asc) 1157 { 1158 int i; 1159 1160 /* 1161 * Process each active queue. 1162 */ 1163 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 1164 if (ATH_TXQ_SETUP(asc, i)) { 1165 (void) ath_tx_processq(asc, &asc->asc_txq[i]); 1166 } 1167 } 1168 } 1169 1170 static struct ieee80211_node * 1171 ath_node_alloc(ieee80211com_t *ic) 1172 { 1173 struct ath_node *an; 1174 ath_t *asc = (ath_t *)ic; 1175 1176 an = kmem_zalloc(sizeof (struct ath_node), KM_SLEEP); 1177 ath_rate_update(asc, &an->an_node, 0); 1178 return (&an->an_node); 1179 } 1180 1181 static void 1182 ath_node_free(struct ieee80211_node *in) 1183 { 1184 ieee80211com_t *ic = in->in_ic; 1185 ath_t *asc = (ath_t *)ic; 1186 struct ath_buf *bf; 1187 struct ath_txq *txq; 1188 int32_t i; 1189 1190 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 1191 if (ATH_TXQ_SETUP(asc, i)) { 1192 txq = &asc->asc_txq[i]; 1193 mutex_enter(&txq->axq_lock); 1194 bf = list_head(&txq->axq_list); 1195 while (bf != NULL) { 1196 if (bf->bf_in == in) { 1197 bf->bf_in = NULL; 1198 } 1199 bf = list_next(&txq->axq_list, bf); 1200 } 1201 mutex_exit(&txq->axq_lock); 1202 } 1203 } 1204 ic->ic_node_cleanup(in); 1205 if (in->in_wpa_ie != NULL) 1206 ieee80211_free(in->in_wpa_ie); 1207 kmem_free(in, sizeof (struct ath_node)); 1208 } 1209 1210 static void 1211 ath_next_scan(void *arg) 1212 { 1213 ieee80211com_t *ic = arg; 1214 ath_t *asc = (ath_t *)ic; 1215 1216 asc->asc_scan_timer = 0; 1217 if (ic->ic_state == IEEE80211_S_SCAN) { 1218 asc->asc_scan_timer = timeout(ath_next_scan, (void *)asc, 1219 drv_usectohz(ath_dwelltime * 1000)); 1220 ieee80211_next_scan(ic); 1221 } 1222 } 1223 1224 static void 1225 ath_stop_scantimer(ath_t *asc) 1226 { 1227 timeout_id_t tmp_id = 0; 1228 1229 while ((asc->asc_scan_timer != 0) && (tmp_id != asc->asc_scan_timer)) { 1230 tmp_id = asc->asc_scan_timer; 1231 (void) untimeout(tmp_id); 1232 } 1233 asc->asc_scan_timer = 0; 1234 } 1235 1236 static int32_t 1237 ath_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg) 1238 { 1239 ath_t *asc = (ath_t *)ic; 1240 struct ath_hal *ah = asc->asc_ah; 1241 struct ieee80211_node *in; 1242 int32_t i, error; 1243 uint8_t *bssid; 1244 uint32_t rfilt; 1245 enum ieee80211_state ostate; 1246 1247 static const HAL_LED_STATE leds[] = { 1248 HAL_LED_INIT, /* IEEE80211_S_INIT */ 1249 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 1250 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 1251 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 1252 HAL_LED_RUN, /* IEEE80211_S_RUN */ 1253 }; 1254 if (!ATH_IS_RUNNING(asc)) 1255 return (0); 1256 1257 ostate = ic->ic_state; 1258 if (nstate != IEEE80211_S_SCAN) 1259 ath_stop_scantimer(asc); 1260 1261 ATH_LOCK(asc); 1262 ATH_HAL_SETLEDSTATE(ah, leds[nstate]); /* set LED */ 1263 1264 if (nstate == IEEE80211_S_INIT) { 1265 asc->asc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 1266 ATH_HAL_INTRSET(ah, asc->asc_imask &~ HAL_INT_GLOBAL); 1267 ATH_UNLOCK(asc); 1268 goto done; 1269 } 1270 in = ic->ic_bss; 1271 error = ath_chan_set(asc, ic->ic_curchan); 1272 if (error != 0) { 1273 if (nstate != IEEE80211_S_SCAN) { 1274 ATH_UNLOCK(asc); 1275 ieee80211_reset_chan(ic); 1276 goto bad; 1277 } 1278 } 1279 1280 rfilt = ath_calcrxfilter(asc); 1281 if (nstate == IEEE80211_S_SCAN) 1282 bssid = ic->ic_macaddr; 1283 else 1284 bssid = in->in_bssid; 1285 ATH_HAL_SETRXFILTER(ah, rfilt); 1286 1287 if (nstate == IEEE80211_S_RUN && ic->ic_opmode != IEEE80211_M_IBSS) 1288 ATH_HAL_SETASSOCID(ah, bssid, in->in_associd); 1289 else 1290 ATH_HAL_SETASSOCID(ah, bssid, 0); 1291 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1292 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1293 if (ATH_HAL_KEYISVALID(ah, i)) 1294 ATH_HAL_KEYSETMAC(ah, i, bssid); 1295 } 1296 } 1297 1298 if ((nstate == IEEE80211_S_RUN) && 1299 (ostate != IEEE80211_S_RUN)) { 1300 /* Configure the beacon and sleep timers. */ 1301 ath_beacon_config(asc); 1302 } else { 1303 asc->asc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 1304 ATH_HAL_INTRSET(ah, asc->asc_imask); 1305 } 1306 /* 1307 * Reset the rate control state. 1308 */ 1309 ath_rate_ctl_reset(asc, nstate); 1310 1311 if (nstate == IEEE80211_S_RUN && (ostate != IEEE80211_S_RUN)) { 1312 nvlist_t *attr_list = NULL; 1313 sysevent_id_t eid; 1314 int32_t err = 0; 1315 char *str_name = "ATH"; 1316 char str_value[256] = {0}; 1317 1318 ATH_DEBUG((ATH_DBG_80211, "ath: ath new state(RUN): " 1319 "ic_flags=0x%08x iv=%d" 1320 " bssid=%s capinfo=0x%04x chan=%d\n", 1321 ic->ic_flags, 1322 in->in_intval, 1323 ieee80211_macaddr_sprintf(in->in_bssid), 1324 in->in_capinfo, 1325 ieee80211_chan2ieee(ic, in->in_chan))); 1326 1327 (void) sprintf(str_value, "%s%s%d", "-i ", 1328 ddi_driver_name(asc->asc_dev), 1329 ddi_get_instance(asc->asc_dev)); 1330 if (nvlist_alloc(&attr_list, 1331 NV_UNIQUE_NAME_TYPE, KM_SLEEP) == 0) { 1332 err = nvlist_add_string(attr_list, 1333 str_name, str_value); 1334 if (err != DDI_SUCCESS) 1335 ATH_DEBUG((ATH_DBG_80211, "ath: " 1336 "ath_new_state: error log event\n")); 1337 err = ddi_log_sysevent(asc->asc_dev, 1338 DDI_VENDOR_SUNW, "class", 1339 "subclass", attr_list, 1340 &eid, DDI_NOSLEEP); 1341 if (err != DDI_SUCCESS) 1342 ATH_DEBUG((ATH_DBG_80211, "ath: " 1343 "ath_new_state(): error log event\n")); 1344 nvlist_free(attr_list); 1345 } 1346 } 1347 1348 ATH_UNLOCK(asc); 1349 done: 1350 /* 1351 * Invoke the parent method to complete the work. 1352 */ 1353 error = asc->asc_newstate(ic, nstate, arg); 1354 /* 1355 * Finally, start any timers. 1356 */ 1357 if (nstate == IEEE80211_S_RUN) { 1358 ieee80211_start_watchdog(ic, 1); 1359 } else if ((nstate == IEEE80211_S_SCAN) && (ostate != nstate)) { 1360 /* start ap/neighbor scan timer */ 1361 ASSERT(asc->asc_scan_timer == 0); 1362 asc->asc_scan_timer = timeout(ath_next_scan, (void *)asc, 1363 drv_usectohz(ath_dwelltime * 1000)); 1364 } 1365 bad: 1366 return (error); 1367 } 1368 1369 /* 1370 * Periodically recalibrate the PHY to account 1371 * for temperature/environment changes. 1372 */ 1373 static void 1374 ath_calibrate(ath_t *asc) 1375 { 1376 struct ath_hal *ah = asc->asc_ah; 1377 HAL_BOOL iqcaldone; 1378 1379 asc->asc_stats.ast_per_cal++; 1380 1381 if (ATH_HAL_GETRFGAIN(ah) == HAL_RFGAIN_NEED_CHANGE) { 1382 /* 1383 * Rfgain is out of bounds, reset the chip 1384 * to load new gain values. 1385 */ 1386 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_calibrate(): " 1387 "Need change RFgain\n")); 1388 asc->asc_stats.ast_per_rfgain++; 1389 (void) ath_reset(&asc->asc_isc); 1390 } 1391 if (!ATH_HAL_CALIBRATE(ah, &asc->asc_curchan, &iqcaldone)) { 1392 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_calibrate(): " 1393 "calibration of channel %u failed\n", 1394 asc->asc_curchan.channel)); 1395 asc->asc_stats.ast_per_calfail++; 1396 } 1397 } 1398 1399 static void 1400 ath_watchdog(void *arg) 1401 { 1402 ath_t *asc = arg; 1403 ieee80211com_t *ic = &asc->asc_isc; 1404 int ntimer = 0; 1405 1406 ATH_LOCK(asc); 1407 ic->ic_watchdog_timer = 0; 1408 if (!ATH_IS_RUNNING(asc)) { 1409 ATH_UNLOCK(asc); 1410 return; 1411 } 1412 1413 if (ic->ic_state == IEEE80211_S_RUN) { 1414 /* periodic recalibration */ 1415 ath_calibrate(asc); 1416 1417 /* 1418 * Start the background rate control thread if we 1419 * are not configured to use a fixed xmit rate. 1420 */ 1421 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1422 asc->asc_stats.ast_rate_calls ++; 1423 if (ic->ic_opmode == IEEE80211_M_STA) 1424 ath_rate_ctl(ic, ic->ic_bss); 1425 else 1426 ieee80211_iterate_nodes(&ic->ic_sta, 1427 ath_rate_cb, asc); 1428 } 1429 1430 ntimer = 1; 1431 } 1432 ATH_UNLOCK(asc); 1433 1434 ieee80211_watchdog(ic); 1435 if (ntimer != 0) 1436 ieee80211_start_watchdog(ic, ntimer); 1437 } 1438 1439 static uint_t 1440 ath_intr(caddr_t arg) 1441 { 1442 ath_t *asc = (ath_t *)arg; 1443 struct ath_hal *ah = asc->asc_ah; 1444 HAL_INT status; 1445 ieee80211com_t *ic = (ieee80211com_t *)asc; 1446 1447 ATH_LOCK(asc); 1448 1449 if (!ATH_IS_RUNNING(asc)) { 1450 /* 1451 * The hardware is not ready/present, don't touch anything. 1452 * Note this can happen early on if the IRQ is shared. 1453 */ 1454 ATH_UNLOCK(asc); 1455 return (DDI_INTR_UNCLAIMED); 1456 } 1457 1458 if (!ATH_HAL_INTRPEND(ah)) { /* shared irq, not for us */ 1459 ATH_UNLOCK(asc); 1460 return (DDI_INTR_UNCLAIMED); 1461 } 1462 1463 ATH_HAL_GETISR(ah, &status); 1464 status &= asc->asc_imask; 1465 if (status & HAL_INT_FATAL) { 1466 asc->asc_stats.ast_hardware++; 1467 goto reset; 1468 } else if (status & HAL_INT_RXORN) { 1469 asc->asc_stats.ast_rxorn++; 1470 goto reset; 1471 } else { 1472 if (status & HAL_INT_RXEOL) { 1473 asc->asc_stats.ast_rxeol++; 1474 asc->asc_rxlink = NULL; 1475 } 1476 if (status & HAL_INT_TXURN) { 1477 asc->asc_stats.ast_txurn++; 1478 ATH_HAL_UPDATETXTRIGLEVEL(ah, AH_TRUE); 1479 } 1480 1481 if (status & HAL_INT_RX) { 1482 asc->asc_rx_pend = 1; 1483 ddi_trigger_softintr(asc->asc_softint_id); 1484 } 1485 if (status & HAL_INT_TX) { 1486 ath_tx_handler(asc); 1487 } 1488 ATH_UNLOCK(asc); 1489 1490 if (status & HAL_INT_SWBA) { 1491 /* This will occur only in Host-AP or Ad-Hoc mode */ 1492 return (DDI_INTR_CLAIMED); 1493 } 1494 if (status & HAL_INT_BMISS) { 1495 if (ic->ic_state == IEEE80211_S_RUN) { 1496 (void) ieee80211_new_state(ic, 1497 IEEE80211_S_ASSOC, -1); 1498 } 1499 } 1500 } 1501 1502 return (DDI_INTR_CLAIMED); 1503 reset: 1504 (void) ath_reset(ic); 1505 ATH_UNLOCK(asc); 1506 return (DDI_INTR_CLAIMED); 1507 } 1508 1509 static uint_t 1510 ath_softint_handler(caddr_t data) 1511 { 1512 ath_t *asc = (ath_t *)data; 1513 1514 /* 1515 * Check if the soft interrupt is triggered by another 1516 * driver at the same level. 1517 */ 1518 ATH_LOCK(asc); 1519 if (asc->asc_rx_pend) { /* Soft interrupt for this driver */ 1520 asc->asc_rx_pend = 0; 1521 ATH_UNLOCK(asc); 1522 ath_rx_handler(asc); 1523 return (DDI_INTR_CLAIMED); 1524 } 1525 ATH_UNLOCK(asc); 1526 return (DDI_INTR_UNCLAIMED); 1527 } 1528 1529 /* 1530 * following are gld callback routine 1531 * ath_gld_send, ath_gld_ioctl, ath_gld_gstat 1532 * are listed in other corresponding sections. 1533 * reset the hardware w/o losing operational state. this is 1534 * basically a more efficient way of doing ath_gld_stop, ath_gld_start, 1535 * followed by state transitions to the current 802.11 1536 * operational state. used to recover from errors rx overrun 1537 * and to reset the hardware when rf gain settings must be reset. 1538 */ 1539 1540 static void 1541 ath_stop_locked(ath_t *asc) 1542 { 1543 ieee80211com_t *ic = (ieee80211com_t *)asc; 1544 struct ath_hal *ah = asc->asc_ah; 1545 1546 ATH_LOCK_ASSERT(asc); 1547 if (!asc->asc_isrunning) 1548 return; 1549 1550 /* 1551 * Shutdown the hardware and driver: 1552 * reset 802.11 state machine 1553 * turn off timers 1554 * disable interrupts 1555 * turn off the radio 1556 * clear transmit machinery 1557 * clear receive machinery 1558 * drain and release tx queues 1559 * reclaim beacon resources 1560 * power down hardware 1561 * 1562 * Note that some of this work is not possible if the 1563 * hardware is gone (invalid). 1564 */ 1565 ATH_UNLOCK(asc); 1566 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1567 ieee80211_stop_watchdog(ic); 1568 ATH_LOCK(asc); 1569 ATH_HAL_INTRSET(ah, 0); 1570 ath_draintxq(asc); 1571 if (!asc->asc_invalid) { 1572 ath_stoprecv(asc); 1573 ATH_HAL_PHYDISABLE(ah); 1574 } else { 1575 asc->asc_rxlink = NULL; 1576 } 1577 asc->asc_isrunning = 0; 1578 } 1579 1580 static void 1581 ath_m_stop(void *arg) 1582 { 1583 ath_t *asc = arg; 1584 struct ath_hal *ah = asc->asc_ah; 1585 1586 ATH_LOCK(asc); 1587 ath_stop_locked(asc); 1588 ATH_HAL_SETPOWER(ah, HAL_PM_AWAKE); 1589 asc->asc_invalid = 1; 1590 ATH_UNLOCK(asc); 1591 } 1592 1593 static int 1594 ath_start_locked(ath_t *asc) 1595 { 1596 ieee80211com_t *ic = (ieee80211com_t *)asc; 1597 struct ath_hal *ah = asc->asc_ah; 1598 HAL_STATUS status; 1599 1600 ATH_LOCK_ASSERT(asc); 1601 1602 /* 1603 * The basic interface to setting the hardware in a good 1604 * state is ``reset''. On return the hardware is known to 1605 * be powered up and with interrupts disabled. This must 1606 * be followed by initialization of the appropriate bits 1607 * and then setup of the interrupt mask. 1608 */ 1609 asc->asc_curchan.channel = ic->ic_curchan->ich_freq; 1610 asc->asc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 1611 if (!ATH_HAL_RESET(ah, (HAL_OPMODE)ic->ic_opmode, 1612 &asc->asc_curchan, AH_FALSE, &status)) { 1613 ATH_DEBUG((ATH_DBG_HAL, "ath: ath_m_start(): " 1614 "reset hardware failed: '%s' (HAL status %u)\n", 1615 ath_get_hal_status_desc(status), status)); 1616 return (ENOTACTIVE); 1617 } 1618 1619 (void) ath_startrecv(asc); 1620 1621 /* 1622 * Enable interrupts. 1623 */ 1624 asc->asc_imask = HAL_INT_RX | HAL_INT_TX 1625 | HAL_INT_RXEOL | HAL_INT_RXORN 1626 | HAL_INT_FATAL | HAL_INT_GLOBAL; 1627 ATH_HAL_INTRSET(ah, asc->asc_imask); 1628 1629 /* 1630 * The hardware should be ready to go now so it's safe 1631 * to kick the 802.11 state machine as it's likely to 1632 * immediately call back to us to send mgmt frames. 1633 */ 1634 ath_chan_change(asc, ic->ic_curchan); 1635 1636 asc->asc_isrunning = 1; 1637 1638 return (0); 1639 } 1640 1641 int 1642 ath_m_start(void *arg) 1643 { 1644 ath_t *asc = arg; 1645 int err; 1646 1647 ATH_LOCK(asc); 1648 /* 1649 * Stop anything previously setup. This is safe 1650 * whether this is the first time through or not. 1651 */ 1652 ath_stop_locked(asc); 1653 1654 if ((err = ath_start_locked(asc)) != 0) { 1655 ATH_UNLOCK(asc); 1656 return (err); 1657 } 1658 1659 asc->asc_invalid = 0; 1660 ATH_UNLOCK(asc); 1661 1662 return (0); 1663 } 1664 1665 1666 static int 1667 ath_m_unicst(void *arg, const uint8_t *macaddr) 1668 { 1669 ath_t *asc = arg; 1670 struct ath_hal *ah = asc->asc_ah; 1671 1672 ATH_DEBUG((ATH_DBG_GLD, "ath: ath_gld_saddr(): " 1673 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", 1674 macaddr[0], macaddr[1], macaddr[2], 1675 macaddr[3], macaddr[4], macaddr[5])); 1676 1677 ATH_LOCK(asc); 1678 IEEE80211_ADDR_COPY(asc->asc_isc.ic_macaddr, macaddr); 1679 ATH_HAL_SETMAC(ah, asc->asc_isc.ic_macaddr); 1680 1681 (void) ath_reset(&asc->asc_isc); 1682 ATH_UNLOCK(asc); 1683 return (0); 1684 } 1685 1686 static int 1687 ath_m_promisc(void *arg, boolean_t on) 1688 { 1689 ath_t *asc = arg; 1690 struct ath_hal *ah = asc->asc_ah; 1691 uint32_t rfilt; 1692 1693 ATH_LOCK(asc); 1694 rfilt = ATH_HAL_GETRXFILTER(ah); 1695 if (on) 1696 rfilt |= HAL_RX_FILTER_PROM; 1697 else 1698 rfilt &= ~HAL_RX_FILTER_PROM; 1699 asc->asc_promisc = on; 1700 ATH_HAL_SETRXFILTER(ah, rfilt); 1701 ATH_UNLOCK(asc); 1702 1703 return (0); 1704 } 1705 1706 static int 1707 ath_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 1708 { 1709 ath_t *asc = arg; 1710 struct ath_hal *ah = asc->asc_ah; 1711 uint32_t val, index, bit; 1712 uint8_t pos; 1713 uint32_t *mfilt = asc->asc_mcast_hash; 1714 1715 ATH_LOCK(asc); 1716 /* calculate XOR of eight 6bit values */ 1717 val = ATH_LE_READ_4(mca + 0); 1718 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1719 val = ATH_LE_READ_4(mca + 3); 1720 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1721 pos &= 0x3f; 1722 index = pos / 32; 1723 bit = 1 << (pos % 32); 1724 1725 if (add) { /* enable multicast */ 1726 asc->asc_mcast_refs[pos]++; 1727 mfilt[index] |= bit; 1728 } else { /* disable multicast */ 1729 if (--asc->asc_mcast_refs[pos] == 0) 1730 mfilt[index] &= ~bit; 1731 } 1732 ATH_HAL_SETMCASTFILTER(ah, mfilt[0], mfilt[1]); 1733 1734 ATH_UNLOCK(asc); 1735 return (0); 1736 } 1737 1738 static void 1739 ath_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1740 { 1741 ath_t *asc = arg; 1742 int32_t err; 1743 1744 err = ieee80211_ioctl(&asc->asc_isc, wq, mp); 1745 ATH_LOCK(asc); 1746 if (err == ENETRESET) { 1747 if (ATH_IS_RUNNING(asc)) { 1748 ATH_UNLOCK(asc); 1749 (void) ath_m_start(asc); 1750 (void) ieee80211_new_state(&asc->asc_isc, 1751 IEEE80211_S_SCAN, -1); 1752 ATH_LOCK(asc); 1753 } 1754 } 1755 ATH_UNLOCK(asc); 1756 } 1757 1758 static int 1759 ath_m_stat(void *arg, uint_t stat, uint64_t *val) 1760 { 1761 ath_t *asc = arg; 1762 ieee80211com_t *ic = (ieee80211com_t *)asc; 1763 struct ieee80211_node *in = ic->ic_bss; 1764 struct ieee80211_rateset *rs = &in->in_rates; 1765 1766 ATH_LOCK(asc); 1767 switch (stat) { 1768 case MAC_STAT_IFSPEED: 1769 *val = (rs->ir_rates[in->in_txrate] & IEEE80211_RATE_VAL) / 2 * 1770 1000000ull; 1771 break; 1772 case MAC_STAT_NOXMTBUF: 1773 *val = asc->asc_stats.ast_tx_nobuf + 1774 asc->asc_stats.ast_tx_nobufmgt; 1775 break; 1776 case MAC_STAT_IERRORS: 1777 *val = asc->asc_stats.ast_rx_tooshort; 1778 break; 1779 case MAC_STAT_RBYTES: 1780 *val = ic->ic_stats.is_rx_bytes; 1781 break; 1782 case MAC_STAT_IPACKETS: 1783 *val = ic->ic_stats.is_rx_frags; 1784 break; 1785 case MAC_STAT_OBYTES: 1786 *val = ic->ic_stats.is_tx_bytes; 1787 break; 1788 case MAC_STAT_OPACKETS: 1789 *val = ic->ic_stats.is_tx_frags; 1790 break; 1791 case MAC_STAT_OERRORS: 1792 case WIFI_STAT_TX_FAILED: 1793 *val = asc->asc_stats.ast_tx_fifoerr + 1794 asc->asc_stats.ast_tx_xretries + 1795 asc->asc_stats.ast_tx_discard; 1796 break; 1797 case WIFI_STAT_TX_RETRANS: 1798 *val = asc->asc_stats.ast_tx_xretries; 1799 break; 1800 case WIFI_STAT_FCS_ERRORS: 1801 *val = asc->asc_stats.ast_rx_crcerr; 1802 break; 1803 case WIFI_STAT_WEP_ERRORS: 1804 *val = asc->asc_stats.ast_rx_badcrypt; 1805 break; 1806 case WIFI_STAT_TX_FRAGS: 1807 case WIFI_STAT_MCAST_TX: 1808 case WIFI_STAT_RTS_SUCCESS: 1809 case WIFI_STAT_RTS_FAILURE: 1810 case WIFI_STAT_ACK_FAILURE: 1811 case WIFI_STAT_RX_FRAGS: 1812 case WIFI_STAT_MCAST_RX: 1813 case WIFI_STAT_RX_DUPS: 1814 ATH_UNLOCK(asc); 1815 return (ieee80211_stat(ic, stat, val)); 1816 default: 1817 ATH_UNLOCK(asc); 1818 return (ENOTSUP); 1819 } 1820 ATH_UNLOCK(asc); 1821 1822 return (0); 1823 } 1824 1825 static int 1826 ath_pci_setup(ath_t *asc) 1827 { 1828 uint16_t command; 1829 1830 /* 1831 * Enable memory mapping and bus mastering 1832 */ 1833 ASSERT(asc != NULL); 1834 command = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_COMM); 1835 command |= PCI_COMM_MAE | PCI_COMM_ME; 1836 pci_config_put16(asc->asc_cfg_handle, PCI_CONF_COMM, command); 1837 command = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_COMM); 1838 if ((command & PCI_COMM_MAE) == 0) { 1839 ath_problem("ath: ath_pci_setup(): " 1840 "failed to enable memory mapping\n"); 1841 return (EIO); 1842 } 1843 if ((command & PCI_COMM_ME) == 0) { 1844 ath_problem("ath: ath_pci_setup(): " 1845 "failed to enable bus mastering\n"); 1846 return (EIO); 1847 } 1848 ATH_DEBUG((ATH_DBG_INIT, "ath: ath_pci_setup(): " 1849 "set command reg to 0x%x \n", command)); 1850 1851 return (0); 1852 } 1853 1854 static int 1855 ath_resume(dev_info_t *devinfo) 1856 { 1857 ath_t *asc; 1858 int ret = DDI_SUCCESS; 1859 1860 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 1861 if (asc == NULL) { 1862 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: ath_resume(): " 1863 "failed to get soft state\n")); 1864 return (DDI_FAILURE); 1865 } 1866 1867 ATH_LOCK(asc); 1868 /* 1869 * Set up config space command register(s). Refuse 1870 * to resume on failure. 1871 */ 1872 if (ath_pci_setup(asc) != 0) { 1873 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: ath_resume(): " 1874 "ath_pci_setup() failed\n")); 1875 ATH_UNLOCK(asc); 1876 return (DDI_FAILURE); 1877 } 1878 1879 if (!asc->asc_invalid) 1880 ret = ath_start_locked(asc); 1881 ATH_UNLOCK(asc); 1882 1883 return (ret); 1884 } 1885 1886 static int 1887 ath_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 1888 { 1889 ath_t *asc; 1890 ieee80211com_t *ic; 1891 struct ath_hal *ah; 1892 uint8_t csz; 1893 HAL_STATUS status; 1894 caddr_t regs; 1895 uint32_t i, val; 1896 uint16_t vendor_id, device_id; 1897 const char *athname; 1898 int32_t ath_countrycode = CTRY_DEFAULT; /* country code */ 1899 int32_t err, ath_regdomain = 0; /* regulatory domain */ 1900 char strbuf[32]; 1901 int instance; 1902 wifi_data_t wd = { 0 }; 1903 mac_register_t *macp; 1904 1905 switch (cmd) { 1906 case DDI_ATTACH: 1907 break; 1908 1909 case DDI_RESUME: 1910 return (ath_resume(devinfo)); 1911 1912 default: 1913 return (DDI_FAILURE); 1914 } 1915 1916 instance = ddi_get_instance(devinfo); 1917 if (ddi_soft_state_zalloc(ath_soft_state_p, instance) != DDI_SUCCESS) { 1918 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1919 "Unable to alloc softstate\n")); 1920 return (DDI_FAILURE); 1921 } 1922 1923 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 1924 ic = (ieee80211com_t *)asc; 1925 asc->asc_dev = devinfo; 1926 1927 mutex_init(&asc->asc_genlock, NULL, MUTEX_DRIVER, NULL); 1928 mutex_init(&asc->asc_txbuflock, NULL, MUTEX_DRIVER, NULL); 1929 mutex_init(&asc->asc_rxbuflock, NULL, MUTEX_DRIVER, NULL); 1930 mutex_init(&asc->asc_resched_lock, NULL, MUTEX_DRIVER, NULL); 1931 1932 err = pci_config_setup(devinfo, &asc->asc_cfg_handle); 1933 if (err != DDI_SUCCESS) { 1934 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1935 "pci_config_setup() failed")); 1936 goto attach_fail0; 1937 } 1938 1939 if (ath_pci_setup(asc) != 0) 1940 goto attach_fail1; 1941 1942 /* 1943 * Cache line size is used to size and align various 1944 * structures used to communicate with the hardware. 1945 */ 1946 csz = pci_config_get8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ); 1947 if (csz == 0) { 1948 /* 1949 * We must have this setup properly for rx buffer 1950 * DMA to work so force a reasonable value here if it 1951 * comes up zero. 1952 */ 1953 csz = ATH_DEF_CACHE_BYTES / sizeof (uint32_t); 1954 pci_config_put8(asc->asc_cfg_handle, PCI_CONF_CACHE_LINESZ, 1955 csz); 1956 } 1957 asc->asc_cachelsz = csz << 2; 1958 vendor_id = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_VENID); 1959 device_id = pci_config_get16(asc->asc_cfg_handle, PCI_CONF_DEVID); 1960 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): vendor 0x%x, " 1961 "device id 0x%x, cache size %d\n", vendor_id, device_id, csz)); 1962 1963 athname = ath_hal_probe(vendor_id, device_id); 1964 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): athname: %s\n", 1965 athname ? athname : "Atheros ???")); 1966 1967 pci_config_put8(asc->asc_cfg_handle, PCI_CONF_LATENCY_TIMER, 0xa8); 1968 val = pci_config_get32(asc->asc_cfg_handle, 0x40); 1969 if ((val & 0x0000ff00) != 0) 1970 pci_config_put32(asc->asc_cfg_handle, 0x40, val & 0xffff00ff); 1971 1972 err = ddi_regs_map_setup(devinfo, 1, 1973 ®s, 0, 0, &ath_reg_accattr, &asc->asc_io_handle); 1974 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1975 "regs map1 = %x err=%d\n", regs, err)); 1976 if (err != DDI_SUCCESS) { 1977 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1978 "ddi_regs_map_setup() failed")); 1979 goto attach_fail1; 1980 } 1981 1982 ah = ath_hal_attach(device_id, asc, 0, regs, &status); 1983 if (ah == NULL) { 1984 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1985 "unable to attach hw: '%s' (HAL status %u)\n", 1986 ath_get_hal_status_desc(status), status)); 1987 goto attach_fail2; 1988 } 1989 ATH_HAL_INTRSET(ah, 0); 1990 asc->asc_ah = ah; 1991 1992 if (ah->ah_abi != HAL_ABI_VERSION) { 1993 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 1994 "HAL ABI mismatch detected (0x%x != 0x%x)\n", 1995 ah->ah_abi, HAL_ABI_VERSION)); 1996 goto attach_fail3; 1997 } 1998 1999 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2000 "HAL ABI version 0x%x\n", ah->ah_abi)); 2001 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2002 "HAL mac version %d.%d, phy version %d.%d\n", 2003 ah->ah_macVersion, ah->ah_macRev, 2004 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf)); 2005 if (ah->ah_analog5GhzRev) 2006 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2007 "HAL 5ghz radio version %d.%d\n", 2008 ah->ah_analog5GhzRev >> 4, 2009 ah->ah_analog5GhzRev & 0xf)); 2010 if (ah->ah_analog2GhzRev) 2011 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2012 "HAL 2ghz radio version %d.%d\n", 2013 ah->ah_analog2GhzRev >> 4, 2014 ah->ah_analog2GhzRev & 0xf)); 2015 2016 /* 2017 * Check if the MAC has multi-rate retry support. 2018 * We do this by trying to setup a fake extended 2019 * descriptor. MAC's that don't have support will 2020 * return false w/o doing anything. MAC's that do 2021 * support it will return true w/o doing anything. 2022 */ 2023 asc->asc_mrretry = ATH_HAL_SETUPXTXDESC(ah, NULL, 0, 0, 0, 0, 0, 0); 2024 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2025 "multi rate retry support=%x\n", 2026 asc->asc_mrretry)); 2027 2028 /* 2029 * Get the hardware key cache size. 2030 */ 2031 asc->asc_keymax = ATH_HAL_KEYCACHESIZE(ah); 2032 if (asc->asc_keymax > sizeof (asc->asc_keymap) * NBBY) { 2033 ATH_DEBUG((ATH_DBG_ATTACH, "ath_attach:" 2034 " Warning, using only %u entries in %u key cache\n", 2035 sizeof (asc->asc_keymap) * NBBY, asc->asc_keymax)); 2036 asc->asc_keymax = sizeof (asc->asc_keymap) * NBBY; 2037 } 2038 /* 2039 * Reset the key cache since some parts do not 2040 * reset the contents on initial power up. 2041 */ 2042 for (i = 0; i < asc->asc_keymax; i++) 2043 ATH_HAL_KEYRESET(ah, i); 2044 2045 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2046 setbit(asc->asc_keymap, i); 2047 setbit(asc->asc_keymap, i+32); 2048 setbit(asc->asc_keymap, i+64); 2049 setbit(asc->asc_keymap, i+32+64); 2050 } 2051 2052 ATH_HAL_GETREGDOMAIN(ah, (uint32_t *)&ath_regdomain); 2053 ATH_HAL_GETCOUNTRYCODE(ah, &ath_countrycode); 2054 /* 2055 * Collect the channel list using the default country 2056 * code and including outdoor channels. The 802.11 layer 2057 * is resposible for filtering this list to a set of 2058 * channels that it considers ok to use. 2059 */ 2060 asc->asc_have11g = 0; 2061 2062 /* enable outdoor use, enable extended channels */ 2063 err = ath_getchannels(asc, ath_countrycode, AH_FALSE, AH_TRUE); 2064 if (err != 0) 2065 goto attach_fail3; 2066 2067 /* 2068 * Setup rate tables for all potential media types. 2069 */ 2070 ath_rate_setup(asc, IEEE80211_MODE_11A); 2071 ath_rate_setup(asc, IEEE80211_MODE_11B); 2072 ath_rate_setup(asc, IEEE80211_MODE_11G); 2073 ath_rate_setup(asc, IEEE80211_MODE_TURBO_A); 2074 2075 /* Setup here so ath_rate_update is happy */ 2076 ath_setcurmode(asc, IEEE80211_MODE_11A); 2077 2078 err = ath_desc_alloc(devinfo, asc); 2079 if (err != DDI_SUCCESS) { 2080 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2081 "failed to allocate descriptors: %d\n", err)); 2082 goto attach_fail3; 2083 } 2084 2085 /* Setup transmit queues in the HAL */ 2086 if (ath_txq_setup(asc)) 2087 goto attach_fail4; 2088 2089 ATH_HAL_GETMAC(ah, ic->ic_macaddr); 2090 2091 /* 2092 * Initialize pointers to device specific functions which 2093 * will be used by the generic layer. 2094 */ 2095 /* 11g support is identified when we fetch the channel set */ 2096 if (asc->asc_have11g) 2097 ic->ic_caps |= IEEE80211_C_SHPREAMBLE | 2098 IEEE80211_C_SHSLOT; /* short slot time */ 2099 /* 2100 * Query the hal to figure out h/w crypto support. 2101 */ 2102 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_WEP)) 2103 ic->ic_caps |= IEEE80211_C_WEP; 2104 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_AES_OCB)) 2105 ic->ic_caps |= IEEE80211_C_AES; 2106 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_AES_CCM)) { 2107 ATH_DEBUG((ATH_DBG_ATTACH, "Atheros support H/W CCMP\n")); 2108 ic->ic_caps |= IEEE80211_C_AES_CCM; 2109 } 2110 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_CKIP)) 2111 ic->ic_caps |= IEEE80211_C_CKIP; 2112 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_TKIP)) { 2113 ATH_DEBUG((ATH_DBG_ATTACH, "Atheros support H/W TKIP\n")); 2114 ic->ic_caps |= IEEE80211_C_TKIP; 2115 /* 2116 * Check if h/w does the MIC and/or whether the 2117 * separate key cache entries are required to 2118 * handle both tx+rx MIC keys. 2119 */ 2120 if (ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_MIC)) { 2121 ATH_DEBUG((ATH_DBG_ATTACH, "Support H/W TKIP MIC\n")); 2122 ic->ic_caps |= IEEE80211_C_TKIPMIC; 2123 } 2124 if (ATH_HAL_TKIPSPLIT(ah)) 2125 asc->asc_splitmic = 1; 2126 } 2127 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */ 2128 2129 asc->asc_hasclrkey = ATH_HAL_CIPHERSUPPORTED(ah, HAL_CIPHER_CLR); 2130 ic->ic_phytype = IEEE80211_T_OFDM; 2131 ic->ic_opmode = IEEE80211_M_STA; 2132 ic->ic_state = IEEE80211_S_INIT; 2133 ic->ic_maxrssi = ATH_MAX_RSSI; 2134 ic->ic_set_shortslot = ath_set_shortslot; 2135 ic->ic_xmit = ath_xmit; 2136 ieee80211_attach(ic); 2137 2138 /* different instance has different WPA door */ 2139 (void) snprintf(ic->ic_wpadoor, MAX_IEEE80211STR, "%s_%s%d", WPA_DOOR, 2140 ddi_driver_name(devinfo), 2141 ddi_get_instance(devinfo)); 2142 2143 /* Override 80211 default routines */ 2144 ic->ic_reset = ath_reset; 2145 asc->asc_newstate = ic->ic_newstate; 2146 ic->ic_newstate = ath_newstate; 2147 ic->ic_watchdog = ath_watchdog; 2148 ic->ic_node_alloc = ath_node_alloc; 2149 ic->ic_node_free = ath_node_free; 2150 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 2151 ic->ic_crypto.cs_key_delete = ath_key_delete; 2152 ic->ic_crypto.cs_key_set = ath_key_set; 2153 ieee80211_media_init(ic); 2154 /* 2155 * initialize default tx key 2156 */ 2157 ic->ic_def_txkey = 0; 2158 2159 asc->asc_rx_pend = 0; 2160 ATH_HAL_INTRSET(ah, 0); 2161 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, 2162 &asc->asc_softint_id, NULL, 0, ath_softint_handler, (caddr_t)asc); 2163 if (err != DDI_SUCCESS) { 2164 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2165 "ddi_add_softintr() failed\n")); 2166 goto attach_fail5; 2167 } 2168 2169 if (ddi_get_iblock_cookie(devinfo, 0, &asc->asc_iblock) 2170 != DDI_SUCCESS) { 2171 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2172 "Can not get iblock cookie for INT\n")); 2173 goto attach_fail6; 2174 } 2175 2176 if (ddi_add_intr(devinfo, 0, NULL, NULL, ath_intr, 2177 (caddr_t)asc) != DDI_SUCCESS) { 2178 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2179 "Can not set intr for ATH driver\n")); 2180 goto attach_fail6; 2181 } 2182 2183 /* 2184 * Provide initial settings for the WiFi plugin; whenever this 2185 * information changes, we need to call mac_plugindata_update() 2186 */ 2187 wd.wd_opmode = ic->ic_opmode; 2188 wd.wd_secalloc = WIFI_SEC_NONE; 2189 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid); 2190 2191 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 2192 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2193 "MAC version mismatch\n")); 2194 goto attach_fail7; 2195 } 2196 2197 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 2198 macp->m_driver = asc; 2199 macp->m_dip = devinfo; 2200 macp->m_src_addr = ic->ic_macaddr; 2201 macp->m_callbacks = &ath_m_callbacks; 2202 macp->m_min_sdu = 0; 2203 macp->m_max_sdu = IEEE80211_MTU; 2204 macp->m_pdata = &wd; 2205 macp->m_pdata_size = sizeof (wd); 2206 2207 err = mac_register(macp, &ic->ic_mach); 2208 mac_free(macp); 2209 if (err != 0) { 2210 ATH_DEBUG((ATH_DBG_ATTACH, "ath: ath_attach(): " 2211 "mac_register err %x\n", err)); 2212 goto attach_fail7; 2213 } 2214 2215 /* Create minor node of type DDI_NT_NET_WIFI */ 2216 (void) snprintf(strbuf, sizeof (strbuf), "%s%d", 2217 ATH_NODENAME, instance); 2218 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR, 2219 instance + 1, DDI_NT_NET_WIFI, 0); 2220 if (err != DDI_SUCCESS) 2221 ATH_DEBUG((ATH_DBG_ATTACH, "WARN: ath: ath_attach(): " 2222 "Create minor node failed - %d\n", err)); 2223 2224 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 2225 asc->asc_invalid = 1; 2226 asc->asc_isrunning = 0; 2227 asc->asc_promisc = B_FALSE; 2228 bzero(asc->asc_mcast_refs, sizeof (asc->asc_mcast_refs)); 2229 bzero(asc->asc_mcast_hash, sizeof (asc->asc_mcast_hash)); 2230 return (DDI_SUCCESS); 2231 attach_fail7: 2232 ddi_remove_intr(devinfo, 0, asc->asc_iblock); 2233 attach_fail6: 2234 ddi_remove_softintr(asc->asc_softint_id); 2235 attach_fail5: 2236 (void) ieee80211_detach(ic); 2237 attach_fail4: 2238 ath_desc_free(asc); 2239 attach_fail3: 2240 ah->ah_detach(asc->asc_ah); 2241 attach_fail2: 2242 ddi_regs_map_free(&asc->asc_io_handle); 2243 attach_fail1: 2244 pci_config_teardown(&asc->asc_cfg_handle); 2245 attach_fail0: 2246 asc->asc_invalid = 1; 2247 mutex_destroy(&asc->asc_txbuflock); 2248 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 2249 if (ATH_TXQ_SETUP(asc, i)) { 2250 struct ath_txq *txq = &asc->asc_txq[i]; 2251 mutex_destroy(&txq->axq_lock); 2252 } 2253 } 2254 mutex_destroy(&asc->asc_rxbuflock); 2255 mutex_destroy(&asc->asc_genlock); 2256 mutex_destroy(&asc->asc_resched_lock); 2257 ddi_soft_state_free(ath_soft_state_p, instance); 2258 2259 return (DDI_FAILURE); 2260 } 2261 2262 /* 2263 * Suspend transmit/receive for powerdown 2264 */ 2265 static int 2266 ath_suspend(ath_t *asc) 2267 { 2268 ATH_LOCK(asc); 2269 ath_stop_locked(asc); 2270 ATH_UNLOCK(asc); 2271 ATH_DEBUG((ATH_DBG_SUSPEND, "ath: suspended.\n")); 2272 2273 return (DDI_SUCCESS); 2274 } 2275 2276 static int32_t 2277 ath_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2278 { 2279 ath_t *asc; 2280 2281 asc = ddi_get_soft_state(ath_soft_state_p, ddi_get_instance(devinfo)); 2282 ASSERT(asc != NULL); 2283 2284 switch (cmd) { 2285 case DDI_DETACH: 2286 break; 2287 2288 case DDI_SUSPEND: 2289 return (ath_suspend(asc)); 2290 2291 default: 2292 return (DDI_FAILURE); 2293 } 2294 2295 ath_stop_scantimer(asc); 2296 2297 /* disable interrupts */ 2298 ATH_HAL_INTRSET(asc->asc_ah, 0); 2299 2300 /* 2301 * Unregister from the MAC layer subsystem 2302 */ 2303 if (mac_unregister(asc->asc_isc.ic_mach) != 0) 2304 return (DDI_FAILURE); 2305 2306 /* free intterrupt resources */ 2307 ddi_remove_intr(devinfo, 0, asc->asc_iblock); 2308 ddi_remove_softintr(asc->asc_softint_id); 2309 2310 /* 2311 * NB: the order of these is important: 2312 * o call the 802.11 layer before detaching the hal to 2313 * insure callbacks into the driver to delete global 2314 * key cache entries can be handled 2315 * o reclaim the tx queue data structures after calling 2316 * the 802.11 layer as we'll get called back to reclaim 2317 * node state and potentially want to use them 2318 * o to cleanup the tx queues the hal is called, so detach 2319 * it last 2320 */ 2321 ieee80211_detach(&asc->asc_isc); 2322 ath_desc_free(asc); 2323 ath_txq_cleanup(asc); 2324 asc->asc_ah->ah_detach(asc->asc_ah); 2325 2326 /* free io handle */ 2327 ddi_regs_map_free(&asc->asc_io_handle); 2328 pci_config_teardown(&asc->asc_cfg_handle); 2329 2330 /* destroy locks */ 2331 mutex_destroy(&asc->asc_rxbuflock); 2332 mutex_destroy(&asc->asc_genlock); 2333 mutex_destroy(&asc->asc_resched_lock); 2334 2335 ddi_remove_minor_node(devinfo, NULL); 2336 ddi_soft_state_free(ath_soft_state_p, ddi_get_instance(devinfo)); 2337 2338 return (DDI_SUCCESS); 2339 } 2340 2341 DDI_DEFINE_STREAM_OPS(ath_dev_ops, nulldev, nulldev, ath_attach, ath_detach, 2342 nodev, NULL, D_MP, NULL); 2343 2344 static struct modldrv ath_modldrv = { 2345 &mod_driverops, /* Type of module. This one is a driver */ 2346 "ath driver 1.3.1/HAL 0.9.17.2", /* short description */ 2347 &ath_dev_ops /* driver specific ops */ 2348 }; 2349 2350 static struct modlinkage modlinkage = { 2351 MODREV_1, (void *)&ath_modldrv, NULL 2352 }; 2353 2354 2355 int 2356 _info(struct modinfo *modinfop) 2357 { 2358 return (mod_info(&modlinkage, modinfop)); 2359 } 2360 2361 int 2362 _init(void) 2363 { 2364 int status; 2365 2366 status = ddi_soft_state_init(&ath_soft_state_p, sizeof (ath_t), 1); 2367 if (status != 0) 2368 return (status); 2369 2370 mutex_init(&ath_loglock, NULL, MUTEX_DRIVER, NULL); 2371 ath_halfix_init(); 2372 mac_init_ops(&ath_dev_ops, "ath"); 2373 status = mod_install(&modlinkage); 2374 if (status != 0) { 2375 mac_fini_ops(&ath_dev_ops); 2376 ath_halfix_finit(); 2377 mutex_destroy(&ath_loglock); 2378 ddi_soft_state_fini(&ath_soft_state_p); 2379 } 2380 2381 return (status); 2382 } 2383 2384 int 2385 _fini(void) 2386 { 2387 int status; 2388 2389 status = mod_remove(&modlinkage); 2390 if (status == 0) { 2391 mac_fini_ops(&ath_dev_ops); 2392 ath_halfix_finit(); 2393 mutex_destroy(&ath_loglock); 2394 ddi_soft_state_fini(&ath_soft_state_p); 2395 } 2396 return (status); 2397 } 2398