1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2008 Atheros Communications Inc. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #ifndef _ARN_ATH9K_H 23 #define _ARN_ATH9K_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 enum ath9k_band { 30 ATH9K_BAND_2GHZ, 31 ATH9K_BAND_5GHZ, 32 ATH9K_NUM_BANDS 33 }; 34 35 #define ATHEROS_VENDOR_ID 0x168c 36 37 #define AR5416_DEVID_PCI 0x0023 38 #define AR5416_DEVID_PCIE 0x0024 39 #define AR9160_DEVID_PCI 0x0027 40 #define AR9280_DEVID_PCI 0x0029 41 #define AR9280_DEVID_PCIE 0x002a 42 #define AR9285_DEVID_PCIE 0x002b 43 44 #define AR5416_AR9100_DEVID 0x000b 45 46 #define AR_SUBVENDOR_ID_NOG 0x0e11 47 #define AR_SUBVENDOR_ID_NEW_A 0x7065 48 49 #define ATH9K_TXERR_XRETRY 0x01 50 #define ATH9K_TXERR_FILT 0x02 51 #define ATH9K_TXERR_FIFO 0x04 52 #define ATH9K_TXERR_XTXOP 0x08 53 #define ATH9K_TXERR_TIMER_EXPIRED 0x10 54 55 #define ATH9K_TX_BA 0x01 56 #define ATH9K_TX_PWRMGMT 0x02 57 #define ATH9K_TX_DESC_CFG_ERR 0x04 58 #define ATH9K_TX_DATA_UNDERRUN 0x08 59 #define ATH9K_TX_DELIM_UNDERRUN 0x10 60 #define ATH9K_TX_SW_ABORTED 0x40 61 #define ATH9K_TX_SW_FILTERED 0x80 62 63 /* should be changed later */ 64 #define BIT(n) (1UL << (n)) 65 66 struct ath_tx_status { 67 uint32_t ts_tstamp; 68 uint16_t ts_seqnum; 69 uint8_t ts_status; 70 uint8_t ts_ratecode; 71 uint8_t ts_rateindex; 72 int8_t ts_rssi; 73 uint8_t ts_shortretry; 74 uint8_t ts_longretry; 75 uint8_t ts_virtcol; 76 uint8_t ts_antenna; 77 uint8_t ts_flags; 78 int8_t ts_rssi_ctl0; 79 int8_t ts_rssi_ctl1; 80 int8_t ts_rssi_ctl2; 81 int8_t ts_rssi_ext0; 82 int8_t ts_rssi_ext1; 83 int8_t ts_rssi_ext2; 84 uint8_t pad[3]; 85 uint32_t ba_low; 86 uint32_t ba_high; 87 uint32_t evm0; 88 uint32_t evm1; 89 uint32_t evm2; 90 }; 91 92 struct ath_rx_status { 93 uint32_t rs_tstamp; 94 uint16_t rs_datalen; 95 uint8_t rs_status; 96 uint8_t rs_phyerr; 97 int8_t rs_rssi; 98 uint8_t rs_keyix; 99 uint8_t rs_rate; 100 uint8_t rs_antenna; 101 uint8_t rs_more; 102 int8_t rs_rssi_ctl0; 103 int8_t rs_rssi_ctl1; 104 int8_t rs_rssi_ctl2; 105 int8_t rs_rssi_ext0; 106 int8_t rs_rssi_ext1; 107 int8_t rs_rssi_ext2; 108 uint8_t rs_isaggr; 109 uint8_t rs_moreaggr; 110 uint8_t rs_num_delims; 111 uint8_t rs_flags; 112 uint32_t evm0; 113 uint32_t evm1; 114 uint32_t evm2; 115 }; 116 117 #define ATH9K_RXERR_CRC 0x01 118 #define ATH9K_RXERR_PHY 0x02 119 #define ATH9K_RXERR_FIFO 0x04 120 #define ATH9K_RXERR_DECRYPT 0x08 121 #define ATH9K_RXERR_MIC 0x10 122 123 #define ATH9K_RX_MORE 0x01 124 #define ATH9K_RX_MORE_AGGR 0x02 125 #define ATH9K_RX_GI 0x04 126 #define ATH9K_RX_2040 0x08 127 #define ATH9K_RX_DELIM_CRC_PRE 0x10 128 #define ATH9K_RX_DELIM_CRC_POST 0x20 129 #define ATH9K_RX_DECRYPT_BUSY 0x40 130 131 #define ATH9K_RXKEYIX_INVALID ((uint8_t)-1) 132 #define ATH9K_TXKEYIX_INVALID ((uint32_t)-1) 133 134 #pragma pack(1) 135 struct ath_desc { 136 uint32_t ds_link; 137 uint32_t ds_data; 138 uint32_t ds_ctl0; 139 uint32_t ds_ctl1; 140 uint32_t ds_hw[20]; 141 union { 142 struct ath_tx_status tx; 143 struct ath_rx_status rx; 144 void *stats; 145 } ds_us; 146 void *ds_vdata; 147 }; 148 #pragma pack() 149 150 #define ds_txstat ds_us.tx 151 #define ds_rxstat ds_us.rx 152 #define ds_stat ds_us.stats 153 154 #define ATH9K_TXDESC_CLRDMASK 0x0001 155 #define ATH9K_TXDESC_NOACK 0x0002 156 #define ATH9K_TXDESC_RTSENA 0x0004 157 #define ATH9K_TXDESC_CTSENA 0x0008 158 /* 159 * ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for 160 * the descriptor its marked on. We take a tx interrupt to reap 161 * descriptors when the h/w hits an EOL condition or 162 * when the descriptor is specifically marked to generate 163 * an interrupt with this flag. Descriptors should be 164 * marked periodically to insure timely replenishing of the 165 * supply needed for sending frames. Defering interrupts 166 * reduces system load and potentially allows more concurrent 167 * work to be done but if done to aggressively can cause 168 * senders to backup. When the hardware queue is left too 169 * large rate control information may also be too out of 170 * date. An Alternative for this is TX interrupt mitigation 171 * but this needs more testing. 172 */ 173 #define ATH9K_TXDESC_INTREQ 0x0010 174 #define ATH9K_TXDESC_VEOL 0x0020 175 #define ATH9K_TXDESC_EXT_ONLY 0x0040 176 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 177 #define ATH9K_TXDESC_VMF 0x0100 178 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 179 #define ATH9K_TXDESC_CAB 0x0400 180 181 #define ATH9K_RXDESC_INTREQ 0x0020 182 183 enum wireless_mode { 184 ATH9K_MODE_11A = 0, 185 ATH9K_MODE_11B = 2, 186 ATH9K_MODE_11G = 3, 187 ATH9K_MODE_11NA_HT20 = 6, 188 ATH9K_MODE_11NG_HT20 = 7, 189 ATH9K_MODE_11NA_HT40PLUS = 8, 190 ATH9K_MODE_11NA_HT40MINUS = 9, 191 ATH9K_MODE_11NG_HT40PLUS = 10, 192 ATH9K_MODE_11NG_HT40MINUS = 11, 193 ATH9K_MODE_MAX 194 }; 195 196 enum ath9k_hw_caps { 197 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), 198 ATH9K_HW_CAP_MIC_AESCCM = BIT(1), 199 ATH9K_HW_CAP_MIC_CKIP = BIT(2), 200 ATH9K_HW_CAP_MIC_TKIP = BIT(3), 201 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), 202 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), 203 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), 204 ATH9K_HW_CAP_VEOL = BIT(7), 205 ATH9K_HW_CAP_BSSIDMASK = BIT(8), 206 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), 207 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), 208 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), 209 ATH9K_HW_CAP_HT = BIT(12), 210 ATH9K_HW_CAP_GTT = BIT(13), 211 ATH9K_HW_CAP_FASTCC = BIT(14), 212 ATH9K_HW_CAP_RFSILENT = BIT(15), 213 ATH9K_HW_CAP_WOW = BIT(16), 214 ATH9K_HW_CAP_CST = BIT(17), 215 ATH9K_HW_CAP_ENHANCEDPM = BIT(18), 216 ATH9K_HW_CAP_AUTOSLEEP = BIT(19), 217 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), 218 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), 219 }; 220 221 enum ath9k_capability_type { 222 ATH9K_CAP_CIPHER = 0, 223 ATH9K_CAP_TKIP_MIC, 224 ATH9K_CAP_TKIP_SPLIT, 225 ATH9K_CAP_PHYCOUNTERS, 226 ATH9K_CAP_DIVERSITY, 227 ATH9K_CAP_TXPOW, 228 ATH9K_CAP_PHYDIAG, 229 ATH9K_CAP_MCAST_KEYSRCH, 230 ATH9K_CAP_TSF_ADJUST, 231 ATH9K_CAP_WME_TKIPMIC, 232 ATH9K_CAP_RFSILENT, 233 ATH9K_CAP_ANT_CFG_2GHZ, 234 ATH9K_CAP_ANT_CFG_5GHZ 235 }; 236 237 struct ath9k_hw_capabilities { 238 uint32_t hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ 239 uint8_t wireless_modes[4]; /* ATH9K_MODE_* */ 240 uint16_t total_queues; 241 uint16_t keycache_size; 242 uint16_t low_5ghz_chan, high_5ghz_chan; 243 uint16_t low_2ghz_chan, high_2ghz_chan; 244 uint16_t num_mr_retries; 245 uint16_t rts_aggr_limit; 246 uint8_t tx_chainmask; 247 uint8_t rx_chainmask; 248 uint16_t tx_triglevel_max; 249 uint16_t reg_cap; 250 uint8_t num_gpio_pins; 251 uint8_t num_antcfg_2ghz; 252 uint8_t num_antcfg_5ghz; 253 }; 254 255 struct ath9k_ops_config { 256 int dma_beacon_response_time; 257 int sw_beacon_response_time; 258 int additional_swba_backoff; 259 int ack_6mb; 260 int cwm_ignore_extcca; 261 uint8_t pcie_powersave_enable; 262 uint8_t pcie_l1skp_enable; 263 uint8_t pcie_clock_req; 264 uint32_t pcie_waen; 265 int pcie_power_reset; 266 uint8_t pcie_restore; 267 uint8_t analog_shiftreg; 268 uint8_t ht_enable; 269 uint32_t ofdm_trig_low; 270 uint32_t ofdm_trig_high; 271 uint32_t cck_trig_high; 272 uint32_t cck_trig_low; 273 uint32_t enable_ani; 274 uint8_t noise_immunity_level; 275 uint32_t ofdm_weaksignal_det; 276 uint32_t cck_weaksignal_thr; 277 uint8_t spur_immunity_level; 278 uint8_t firstep_level; 279 int8_t rssi_thr_high; 280 int8_t rssi_thr_low; 281 uint16_t diversity_control; 282 uint16_t antenna_switch_swap; 283 int serialize_regmode; 284 int intr_mitigation; 285 #define SPUR_DISABLE 0 286 #define SPUR_ENABLE_IOCTL 1 287 #define SPUR_ENABLE_EEPROM 2 288 #define AR_EEPROM_MODAL_SPURS 5 289 #define AR_SPUR_5413_1 1640 290 #define AR_SPUR_5413_2 1200 291 #define AR_NO_SPUR 0x8000 292 #define AR_BASE_FREQ_2GHZ 2300 293 #define AR_BASE_FREQ_5GHZ 4900 294 #define AR_SPUR_FEEQ_BOUND_HT40 19 295 #define AR_SPUR_FEEQ_BOUND_HT20 10 296 int spurmode; 297 uint16_t spurchans[AR_EEPROM_MODAL_SPURS][2]; 298 }; 299 300 enum ath9k_tx_queue { 301 ATH9K_TX_QUEUE_INACTIVE = 0, 302 ATH9K_TX_QUEUE_DATA, 303 ATH9K_TX_QUEUE_BEACON, 304 ATH9K_TX_QUEUE_CAB, 305 ATH9K_TX_QUEUE_UAPSD, 306 ATH9K_TX_QUEUE_PSPOLL 307 }; 308 309 #define ATH9K_NUM_TX_QUEUES 10 310 311 enum ath9k_tx_queue_subtype { 312 ATH9K_WME_AC_BK = 0, 313 ATH9K_WME_AC_BE, 314 ATH9K_WME_AC_VI, 315 ATH9K_WME_AC_VO, 316 ATH9K_WME_UPSD 317 }; 318 319 enum ath9k_tx_queue_flags { 320 TXQ_FLAG_TXOKINT_ENABLE = 0x0001, 321 TXQ_FLAG_TXERRINT_ENABLE = 0x0001, 322 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, 323 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, 324 TXQ_FLAG_TXURNINT_ENABLE = 0x0008, 325 TXQ_FLAG_BACKOFF_DISABLE = 0x0010, 326 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, 327 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, 328 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, 329 }; 330 331 #define ATH9K_TXQ_USEDEFAULT ((uint32_t)(-1)) 332 333 #define ATH9K_DECOMP_MASK_SIZE 128 334 #define ATH9K_READY_TIME_LO_BOUND 50 335 #define ATH9K_READY_TIME_HI_BOUND 96 336 337 enum ath9k_pkt_type { 338 ATH9K_PKT_TYPE_NORMAL = 0, 339 ATH9K_PKT_TYPE_ATIM, 340 ATH9K_PKT_TYPE_PSPOLL, 341 ATH9K_PKT_TYPE_BEACON, 342 ATH9K_PKT_TYPE_PROBE_RESP, 343 ATH9K_PKT_TYPE_CHIRP, 344 ATH9K_PKT_TYPE_GRP_POLL, 345 }; 346 347 struct ath9k_tx_queue_info { 348 uint32_t tqi_ver; 349 enum ath9k_tx_queue tqi_type; 350 enum ath9k_tx_queue_subtype tqi_subtype; 351 enum ath9k_tx_queue_flags tqi_qflags; 352 uint32_t tqi_priority; 353 uint32_t tqi_aifs; 354 uint32_t tqi_cwmin; 355 uint32_t tqi_cwmax; 356 uint16_t tqi_shretry; 357 uint16_t tqi_lgretry; 358 uint32_t tqi_cbrPeriod; 359 uint32_t tqi_cbrOverflowLimit; 360 uint32_t tqi_burstTime; 361 uint32_t tqi_readyTime; 362 uint32_t tqi_physCompBuf; 363 uint32_t tqi_intFlags; 364 }; 365 366 enum ath9k_rx_filter { 367 ATH9K_RX_FILTER_UCAST = 0x00000001, 368 ATH9K_RX_FILTER_MCAST = 0x00000002, 369 ATH9K_RX_FILTER_BCAST = 0x00000004, 370 ATH9K_RX_FILTER_CONTROL = 0x00000008, 371 ATH9K_RX_FILTER_BEACON = 0x00000010, 372 ATH9K_RX_FILTER_PROM = 0x00000020, 373 ATH9K_RX_FILTER_PROBEREQ = 0x00000080, 374 ATH9K_RX_FILTER_PSPOLL = 0x00004000, 375 ATH9K_RX_FILTER_PHYERR = 0x00000100, 376 ATH9K_RX_FILTER_PHYRADAR = 0x00002000, 377 }; 378 379 enum ath9k_int { 380 ATH9K_INT_RX = 0x00000001, 381 ATH9K_INT_RXDESC = 0x00000002, 382 ATH9K_INT_RXNOFRM = 0x00000008, 383 ATH9K_INT_RXEOL = 0x00000010, 384 ATH9K_INT_RXORN = 0x00000020, 385 ATH9K_INT_TX = 0x00000040, 386 ATH9K_INT_TXDESC = 0x00000080, 387 ATH9K_INT_TIM_TIMER = 0x00000100, 388 ATH9K_INT_TXURN = 0x00000800, 389 ATH9K_INT_MIB = 0x00001000, 390 ATH9K_INT_RXPHY = 0x00004000, 391 ATH9K_INT_RXKCM = 0x00008000, 392 ATH9K_INT_SWBA = 0x00010000, 393 ATH9K_INT_BMISS = 0x00040000, 394 ATH9K_INT_BNR = 0x00100000, 395 ATH9K_INT_TIM = 0x00200000, 396 ATH9K_INT_DTIM = 0x00400000, 397 ATH9K_INT_DTIMSYNC = 0x00800000, 398 ATH9K_INT_GPIO = 0x01000000, 399 ATH9K_INT_CABEND = 0x02000000, 400 ATH9K_INT_CST = 0x10000000, 401 ATH9K_INT_GTT = 0x20000000, 402 ATH9K_INT_FATAL = 0x40000000, 403 ATH9K_INT_GLOBAL = INT_MIN, 404 ATH9K_INT_BMISC = ATH9K_INT_TIM | 405 ATH9K_INT_DTIM | 406 ATH9K_INT_DTIMSYNC | 407 ATH9K_INT_CABEND, 408 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | 409 ATH9K_INT_RXDESC | 410 ATH9K_INT_RXEOL | 411 ATH9K_INT_RXORN | 412 ATH9K_INT_TXURN | 413 ATH9K_INT_TXDESC | 414 ATH9K_INT_MIB | 415 ATH9K_INT_RXPHY | 416 ATH9K_INT_RXKCM | 417 ATH9K_INT_SWBA | 418 ATH9K_INT_BMISS | 419 ATH9K_INT_GPIO, 420 ATH9K_INT_NOCARD = -1 421 }; 422 423 #define ATH9K_RATESERIES_RTS_CTS 0x0001 424 #define ATH9K_RATESERIES_2040 0x0002 425 #define ATH9K_RATESERIES_HALFGI 0x0004 426 427 struct ath9k_11n_rate_series { 428 uint32_t Tries; 429 uint32_t Rate; 430 uint32_t PktDuration; 431 uint32_t ChSel; 432 uint32_t RateFlags; 433 }; 434 435 #define CHANNEL_CW_INT 0x00002 436 #define CHANNEL_CCK 0x00020 437 #define CHANNEL_OFDM 0x00040 438 #define CHANNEL_2GHZ 0x00080 439 #define CHANNEL_5GHZ 0x00100 440 #define CHANNEL_PASSIVE 0x00200 441 #define CHANNEL_DYN 0x00400 442 #define CHANNEL_HALF 0x04000 443 #define CHANNEL_QUARTER 0x08000 444 #define CHANNEL_HT20 0x10000 445 #define CHANNEL_HT40PLUS 0x20000 446 #define CHANNEL_HT40MINUS 0x40000 447 448 #define CHANNEL_INTERFERENCE 0x01 449 #define CHANNEL_DFS 0x02 450 #define CHANNEL_4MS_LIMIT 0x04 451 #define CHANNEL_DFS_CLEAR 0x08 452 #define CHANNEL_DISALLOW_ADHOC 0x10 453 #define CHANNEL_PER_11D_ADHOC 0x20 454 455 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 456 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 457 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 458 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) 459 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) 460 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) 461 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) 462 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) 463 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) 464 #define CHANNEL_ALL \ 465 (CHANNEL_OFDM| \ 466 CHANNEL_CCK| \ 467 CHANNEL_2GHZ | \ 468 CHANNEL_5GHZ | \ 469 CHANNEL_HT20 | \ 470 CHANNEL_HT40PLUS | \ 471 CHANNEL_HT40MINUS) 472 473 struct ath9k_channel { 474 uint16_t channel; 475 uint32_t channelFlags; 476 uint8_t privFlags; 477 int8_t maxRegTxPower; 478 int8_t maxTxPower; 479 int8_t minTxPower; 480 uint32_t chanmode; 481 int32_t CalValid; 482 boolean_t oneTimeCalsDone; 483 int8_t iCoff; 484 int8_t qCoff; 485 int16_t rawNoiseFloor; 486 int8_t antennaMax; 487 uint32_t regDmnFlags; 488 uint32_t conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */ 489 #ifdef ARN_NF_PER_CHAN 490 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 491 #endif 492 }; 493 494 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ 495 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \ 496 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \ 497 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) 498 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ 499 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ 500 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ 501 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) 502 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) 503 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) 504 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) 505 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) 506 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) 507 #define IS_CHAN_QUARTER_RATE(_c) \ 508 (((_c)->channelFlags & CHANNEL_QUARTER) != 0) 509 510 /* These macros check chanmode and not channelFlags */ 511 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) 512 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ 513 ((_c)->chanmode == CHANNEL_G_HT20)) 514 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ 515 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ 516 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ 517 ((_c)->chanmode == CHANNEL_G_HT40MINUS)) 518 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) 519 520 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) 521 #define IS_CHAN_A_5MHZ_SPACED(_c) \ 522 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ 523 (((_c)->channel % 20) != 0) && \ 524 (((_c)->channel % 10) != 0)) 525 526 struct ath9k_keyval { 527 uint8_t kv_type; 528 uint8_t kv_pad; 529 uint16_t kv_len; 530 uint8_t kv_val[16]; 531 uint8_t kv_mic[8]; 532 uint8_t kv_txmic[8]; 533 }; 534 535 enum ath9k_key_type { 536 ATH9K_KEY_TYPE_CLEAR, 537 ATH9K_KEY_TYPE_WEP, 538 ATH9K_KEY_TYPE_AES, 539 ATH9K_KEY_TYPE_TKIP, 540 }; 541 542 enum ath9k_cipher { 543 ATH9K_CIPHER_WEP = 0, 544 ATH9K_CIPHER_AES_OCB = 1, 545 ATH9K_CIPHER_AES_CCM = 2, 546 ATH9K_CIPHER_CKIP = 3, 547 ATH9K_CIPHER_TKIP = 4, 548 ATH9K_CIPHER_CLR = 5, 549 ATH9K_CIPHER_MIC = 127 550 }; 551 552 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 553 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 554 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 555 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 556 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 557 #define AR_EEPROM_EEPCAP_MAXQCU_S 4 558 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 559 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 560 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 561 562 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 563 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 564 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 565 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 566 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 567 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 568 569 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 570 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 571 572 #define SD_NO_CTL 0xE0 573 #define NO_CTL 0xff 574 #define CTL_MODE_M 7 575 #define CTL_11A 0 576 #define CTL_11B 1 577 #define CTL_11G 2 578 #define CTL_2GHT20 5 579 #define CTL_5GHT20 6 580 #define CTL_2GHT40 7 581 #define CTL_5GHT40 8 582 583 #define AR_EEPROM_MAC(i) (0x1d+(i)) 584 585 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c 586 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 587 #define AR_EEPROM_RFSILENT_POLARITY 0x0002 588 #define AR_EEPROM_RFSILENT_POLARITY_S 1 589 590 #define CTRY_DEBUG 0x1ff 591 #define CTRY_DEFAULT 0 592 593 enum reg_ext_bitmap { 594 REG_EXT_JAPAN_MIDBAND = 1, 595 REG_EXT_FCC_DFS_HT40 = 2, 596 REG_EXT_JAPAN_NONDFS_HT40 = 3, 597 REG_EXT_JAPAN_DFS_HT40 = 4 598 }; 599 600 struct ath9k_country_entry { 601 uint16_t countryCode; 602 uint16_t regDmnEnum; 603 uint16_t regDmn5G; 604 uint16_t regDmn2G; 605 uint8_t isMultidomain; 606 uint8_t iso[3]; 607 }; 608 609 /* Register read/write primitives */ 610 #define REG_WRITE(_ah, _reg, _val) arn_iowrite32((_ah), (_reg), (_val)) 611 #define REG_READ(_ah, _reg) arn_ioread32((_ah), (_reg)) 612 #define FLASH_READ(_ah, _reg) \ 613 ddi_get16((_ah->ah_sc)->sc_io_handle, \ 614 (uint16_t *)((uintptr_t)(_ah)->ah_sh + (_reg))) 615 616 #define SM(_v, _f) (((_v) << _f##_S) & _f) 617 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 618 #define REG_RMW(_a, _r, _set, _clr) \ 619 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) 620 #define REG_RMW_FIELD(_a, _r, _f, _v) \ 621 REG_WRITE(_a, _r, \ 622 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) 623 #define REG_SET_BIT(_a, _r, _f) \ 624 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) 625 #define REG_CLR_BIT(_a, _r, _f) \ 626 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) 627 628 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 629 630 #define INIT_AIFS 2 631 #define INIT_CWMIN 15 632 #define INIT_CWMIN_11B 31 633 #define INIT_CWMAX 1023 634 #define INIT_SH_RETRY 10 635 #define INIT_LG_RETRY 10 636 #define INIT_SSH_RETRY 32 637 #define INIT_SLG_RETRY 32 638 639 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) 640 641 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) 642 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX 643 644 #define IEEE80211_WEP_IVLEN 3 645 #define IEEE80211_WEP_KIDLEN 1 646 #define IEEE80211_WEP_CRCLEN 4 647 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ 648 (IEEE80211_WEP_IVLEN + \ 649 IEEE80211_WEP_KIDLEN + \ 650 IEEE80211_WEP_CRCLEN)) 651 #define MAX_RATE_POWER 63 652 653 enum ath9k_power_mode { 654 ATH9K_PM_AWAKE = 0, 655 ATH9K_PM_FULL_SLEEP, 656 ATH9K_PM_NETWORK_SLEEP, 657 ATH9K_PM_UNDEFINED 658 }; 659 660 struct ath9k_mib_stats { 661 uint32_t ackrcv_bad; 662 uint32_t rts_bad; 663 uint32_t rts_good; 664 uint32_t fcs_bad; 665 uint32_t beacons; 666 }; 667 668 enum ath9k_ant_setting { 669 ATH9K_ANT_VARIABLE = 0, 670 ATH9K_ANT_FIXED_A, 671 ATH9K_ANT_FIXED_B 672 }; 673 674 675 enum ath9k_opmode { 676 ATH9K_M_STA = 1, 677 ATH9K_M_IBSS = 0, 678 ATH9K_M_HOSTAP = 6, 679 ATH9K_M_MONITOR = 8 680 }; 681 682 683 #define ATH9K_SLOT_TIME_6 6 684 #define ATH9K_SLOT_TIME_9 9 685 #define ATH9K_SLOT_TIME_20 20 686 687 enum ath9k_ht_macmode { 688 ATH9K_HT_MACMODE_20 = 0, 689 ATH9K_HT_MACMODE_2040 = 1, 690 }; 691 692 enum ath9k_ht_extprotspacing { 693 ATH9K_HT_EXTPROTSPACING_20 = 0, 694 ATH9K_HT_EXTPROTSPACING_25 = 1, 695 }; 696 697 struct ath9k_ht_cwm { 698 enum ath9k_ht_macmode ht_macmode; 699 enum ath9k_ht_extprotspacing ht_extprotspacing; 700 }; 701 702 enum ath9k_ani_cmd { 703 ATH9K_ANI_PRESENT = 0x1, 704 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, 705 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, 706 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, 707 ATH9K_ANI_FIRSTEP_LEVEL = 0x10, 708 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, 709 ATH9K_ANI_MODE = 0x40, 710 ATH9K_ANI_PHYERR_RESET = 0x80, 711 ATH9K_ANI_ALL = 0xff 712 }; 713 714 enum { 715 WLAN_RC_PHY_OFDM, 716 WLAN_RC_PHY_CCK, 717 WLAN_RC_PHY_HT_20_SS, 718 WLAN_RC_PHY_HT_20_DS, 719 WLAN_RC_PHY_HT_40_SS, 720 WLAN_RC_PHY_HT_40_DS, 721 WLAN_RC_PHY_HT_20_SS_HGI, 722 WLAN_RC_PHY_HT_20_DS_HGI, 723 WLAN_RC_PHY_HT_40_SS_HGI, 724 WLAN_RC_PHY_HT_40_DS_HGI, 725 WLAN_RC_PHY_MAX 726 }; 727 728 enum ath9k_tp_scale { 729 ATH9K_TP_SCALE_MAX = 0, 730 ATH9K_TP_SCALE_50, 731 ATH9K_TP_SCALE_25, 732 ATH9K_TP_SCALE_12, 733 ATH9K_TP_SCALE_MIN 734 }; 735 736 enum ser_reg_mode { 737 SER_REG_MODE_OFF = 0, 738 SER_REG_MODE_ON = 1, 739 SER_REG_MODE_AUTO = 2, 740 }; 741 742 #define AR_PHY_CCA_MAX_GOOD_VALUE -85 743 #define AR_PHY_CCA_MAX_HIGH_VALUE -62 744 #define AR_PHY_CCA_MIN_BAD_VALUE -121 745 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3 746 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5 747 748 #define ATH9K_NF_CAL_HIST_MAX 5 749 #define NUM_NF_READINGS 6 750 751 struct ath9k_nfcal_hist { 752 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX]; 753 uint8_t currIndex; 754 int16_t privNF; 755 uint8_t invalidNFcount; 756 }; 757 758 struct ath9k_beacon_state { 759 uint32_t bs_nexttbtt; 760 uint32_t bs_nextdtim; 761 uint32_t bs_intval; 762 #define ATH9K_BEACON_PERIOD 0x0000ffff 763 #define ATH9K_BEACON_ENA 0x00800000 764 #define ATH9K_BEACON_RESET_TSF 0x01000000 765 uint32_t bs_dtimperiod; 766 uint16_t bs_cfpperiod; 767 uint16_t bs_cfpmaxduration; 768 uint32_t bs_cfpnext; 769 uint16_t bs_timoffset; 770 uint16_t bs_bmissthreshold; 771 uint32_t bs_sleepduration; 772 }; 773 774 struct ath9k_node_stats { 775 uint32_t ns_avgbrssi; 776 uint32_t ns_avgrssi; 777 uint32_t ns_avgtxrssi; 778 uint32_t ns_avgtxrate; 779 }; 780 781 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) 782 783 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 784 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 785 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 786 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 787 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 788 789 enum { 790 ATH9K_RESET_POWER_ON, 791 ATH9K_RESET_WARM, 792 ATH9K_RESET_COLD, 793 }; 794 795 #define AH_USE_EEPROM 0x1 796 797 struct ath_hal { 798 uint32_t ah_magic; 799 uint16_t ah_devid; 800 uint16_t ah_subvendorid; 801 uint32_t ah_macVersion; 802 uint16_t ah_macRev; 803 uint16_t ah_phyRev; 804 uint16_t ah_analog5GhzRev; 805 uint16_t ah_analog2GhzRev; 806 807 caddr_t ah_sh; 808 struct arn_softc *ah_sc; 809 enum ath9k_opmode ah_opmode; 810 struct ath9k_ops_config ah_config; 811 struct ath9k_hw_capabilities ah_caps; 812 813 uint16_t ah_countryCode; 814 uint32_t ah_flags; 815 int16_t ah_powerLimit; 816 uint16_t ah_maxPowerLevel; 817 uint32_t ah_tpScale; 818 uint16_t ah_currentRD; 819 uint16_t ah_currentRDExt; 820 uint16_t ah_currentRDInUse; 821 uint16_t ah_currentRD5G; 822 uint16_t ah_currentRD2G; 823 char ah_iso[4]; 824 825 struct ath9k_channel ah_channels[150]; 826 struct ath9k_channel *ah_curchan; 827 uint32_t ah_nchan; 828 829 boolean_t ah_isPciExpress; 830 uint16_t ah_txTrigLevel; 831 uint16_t ah_rfsilent; 832 uint32_t ah_rfkill_gpio; 833 uint32_t ah_rfkill_polarity; 834 835 #ifndef ARN_NF_PER_CHAN 836 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 837 #endif 838 }; 839 840 struct chan_centers { 841 uint16_t synth_center; 842 uint16_t ctl_center; 843 uint16_t ext_center; 844 }; 845 846 struct ath_rate_table; 847 848 /* Helpers */ 849 850 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah, 851 const struct ath9k_channel *chan); 852 boolean_t ath9k_hw_wait(struct ath_hal *ah, uint32_t reg, uint32_t mask, 853 uint32_t val); 854 uint32_t ath9k_hw_reverse_bits(uint32_t val, uint32_t n); 855 boolean_t ath9k_get_channel_edges(struct ath_hal *ah, 856 uint16_t flags, uint16_t *low, uint16_t *high); 857 uint16_t ath9k_hw_computetxtime(struct ath_hal *ah, 858 struct ath_rate_table *rates, 859 uint32_t frameLen, uint16_t rateix, 860 boolean_t shortPreamble); 861 uint32_t ath9k_hw_mhz2ieee(struct ath_hal *ah, uint32_t freq, uint32_t flags); 862 void ath9k_hw_get_channel_centers(struct ath_hal *ah, 863 struct ath9k_channel *chan, 864 struct chan_centers *centers); 865 866 /* Attach, Detach */ 867 868 const char *ath9k_hw_probe(uint16_t vendorid, uint16_t devid); 869 void ath9k_hw_detach(struct ath_hal *ah); 870 struct ath_hal *ath9k_hw_attach(uint16_t devid, struct arn_softc *sc, 871 caddr_t mem, int *error); 872 void ath9k_hw_rfdetach(struct ath_hal *ah); 873 874 875 /* HW Reset */ 876 877 boolean_t ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, 878 enum ath9k_ht_macmode macmode, 879 uint8_t txchainmask, uint8_t rxchainmask, 880 enum ath9k_ht_extprotspacing extprotspacing, 881 boolean_t bChannelChange, int *status); 882 883 /* Key Cache Management */ 884 885 boolean_t ath9k_hw_keyreset(struct ath_hal *ah, uint16_t entry); 886 boolean_t ath9k_hw_keysetmac(struct ath_hal *ah, uint16_t entry, 887 const uint8_t *mac); 888 boolean_t ath9k_hw_set_keycache_entry(struct ath_hal *ah, uint16_t entry, 889 const struct ath9k_keyval *k, const uint8_t *mac, int xorKey); 890 boolean_t ath9k_hw_keyisvalid(struct ath_hal *ah, uint16_t entry); 891 892 /* Power Management */ 893 894 boolean_t ath9k_hw_setpower(struct ath_hal *ah, 895 enum ath9k_power_mode mode); 896 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); 897 898 /* Beacon timers */ 899 900 void ath9k_hw_beaconinit(struct ath_hal *ah, uint32_t next_beacon, 901 uint32_t beacon_period); 902 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, 903 const struct ath9k_beacon_state *bs); 904 /* HW Capabilities */ 905 906 boolean_t ath9k_hw_fill_cap_info(struct ath_hal *ah); 907 boolean_t ath9k_hw_getcapability(struct ath_hal *ah, 908 enum ath9k_capability_type type, 909 uint32_t capability, uint32_t *result); 910 boolean_t ath9k_hw_setcapability(struct ath_hal *ah, 911 enum ath9k_capability_type type, 912 uint32_t capability, uint32_t setting, 913 int *status); 914 915 /* GPIO / RFKILL / Antennae */ 916 917 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, uint32_t gpio); 918 uint32_t ath9k_hw_gpio_get(struct ath_hal *ah, uint32_t gpio); 919 void ath9k_hw_cfg_output(struct ath_hal *ah, uint32_t gpio, 920 uint32_t ah_signal_type); 921 void ath9k_hw_set_gpio(struct ath_hal *ah, uint32_t gpio, uint32_t val); 922 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 923 void ath9k_enable_rfkill(struct ath_hal *ah); 924 #endif 925 int ath9k_hw_select_antconfig(struct ath_hal *ah, uint32_t cfg); 926 uint32_t ath9k_hw_getdefantenna(struct ath_hal *ah); 927 void ath9k_hw_setantenna(struct ath_hal *ah, uint32_t antenna); 928 boolean_t ath9k_hw_setantennaswitch(struct ath_hal *ah, 929 enum ath9k_ant_setting settings, 930 struct ath9k_channel *chan, 931 uint8_t *tx_chainmask, 932 uint8_t *rx_chainmask, 933 uint8_t *antenna_cfgd); 934 935 /* General Operation */ 936 937 uint32_t ath9k_hw_getrxfilter(struct ath_hal *ah); 938 void ath9k_hw_setrxfilter(struct ath_hal *ah, uint32_t bits); 939 boolean_t ath9k_hw_phy_disable(struct ath_hal *ah); 940 boolean_t ath9k_hw_disable(struct ath_hal *ah); 941 boolean_t ath9k_hw_set_txpowerlimit(struct ath_hal *ah, uint32_t limit); 942 void ath9k_hw_getmac(struct ath_hal *ah, uint8_t *mac); 943 boolean_t ath9k_hw_setmac(struct ath_hal *ah, const uint8_t *mac); 944 void ath9k_hw_setopmode(struct ath_hal *ah); 945 void ath9k_hw_setmcastfilter(struct ath_hal *ah, uint32_t filter0, 946 uint32_t filter1); 947 void ath9k_hw_getbssidmask(struct ath_hal *ah, uint8_t *mask); 948 boolean_t ath9k_hw_setbssidmask(struct ath_hal *ah, const uint8_t *mask); 949 void ath9k_hw_write_associd(struct ath_hal *ah, const uint8_t *bssid, 950 uint16_t assocId); 951 uint64_t ath9k_hw_gettsf64(struct ath_hal *ah); 952 void ath9k_hw_reset_tsf(struct ath_hal *ah); 953 boolean_t ath9k_hw_set_tsfadjust(struct ath_hal *ah, uint32_t setting); 954 boolean_t ath9k_hw_setslottime(struct ath_hal *ah, uint32_t us); 955 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); 956 957 /* Regulatory */ 958 959 boolean_t ath9k_regd_is_public_safety_sku(struct ath_hal *ah); 960 struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah, 961 const struct ath9k_channel *c); 962 uint32_t ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); 963 uint32_t ath9k_regd_get_antenna_allowed(struct ath_hal *ah, 964 struct ath9k_channel *chan); 965 boolean_t ath9k_regd_init_channels(struct ath_hal *ah, 966 uint32_t maxchans, uint32_t *nchans, uint8_t *regclassids, 967 uint32_t maxregids, uint32_t *nregids, uint16_t cc, 968 boolean_t enableOutdoor, boolean_t enableExtendedChannels); 969 970 /* ANI */ 971 972 void ath9k_ani_reset(struct ath_hal *ah); 973 void ath9k_hw_ani_monitor(struct ath_hal *ah, 974 const struct ath9k_node_stats *stats, 975 struct ath9k_channel *chan); 976 boolean_t ath9k_hw_phycounters(struct ath_hal *ah); 977 void ath9k_enable_mib_counters(struct ath_hal *ah); 978 void ath9k_hw_disable_mib_counters(struct ath_hal *ah); 979 uint32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, 980 uint32_t *rxc_pcnt, 981 uint32_t *rxf_pcnt, 982 uint32_t *txf_pcnt); 983 void ath9k_hw_procmibevent(struct ath_hal *ah, 984 const struct ath9k_node_stats *stats); 985 void ath9k_hw_ani_setup(struct ath_hal *ah); 986 void ath9k_hw_ani_attach(struct ath_hal *ah); 987 void ath9k_hw_ani_detach(struct ath_hal *ah); 988 989 /* Calibration */ 990 991 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan, 992 boolean_t *isCalDone); 993 void ath9k_hw_start_nfcal(struct ath_hal *ah); 994 void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan); 995 int16_t ath9k_hw_getnf(struct ath_hal *ah, struct ath9k_channel *chan); 996 void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); 997 signed short ath9k_hw_getchan_noise(struct ath_hal *ah, 998 struct ath9k_channel *chan); 999 boolean_t ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, 1000 uint8_t rxchainmask, boolean_t longcal, boolean_t *isCalDone); 1001 boolean_t ath9k_hw_init_cal(struct ath_hal *ah, 1002 struct ath9k_channel *chan); 1003 1004 1005 /* EEPROM */ 1006 1007 int ath9k_hw_set_txpower(struct ath_hal *ah, 1008 struct ath9k_channel *chan, 1009 uint16_t cfgCtl, 1010 uint8_t twiceAntennaReduction, 1011 uint8_t twiceMaxRegulatoryPower, 1012 uint8_t powerLimit); 1013 void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); 1014 boolean_t ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, 1015 struct ath9k_channel *chan, 1016 int16_t *ratesArray, 1017 uint16_t cfgCtl, 1018 uint8_t AntennaReduction, 1019 uint8_t twiceMaxRegulatoryPower, 1020 uint8_t powerLimit); 1021 boolean_t ath9k_hw_set_power_cal_table(struct ath_hal *ah, 1022 struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset); 1023 boolean_t ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, 1024 struct ath9k_channel *chan); 1025 int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, 1026 struct ath9k_channel *chan, uint8_t index, uint16_t *config); 1027 1028 uint8_t ath9k_hw_get_num_ant_config(struct ath_hal *ah, 1029 enum ath9k_band freq_band); 1030 1031 uint16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, uint16_t i, 1032 boolean_t is2GHz); 1033 int ath9k_hw_eeprom_attach(struct ath_hal *ah); 1034 1035 /* Interrupt Handling */ 1036 1037 boolean_t ath9k_hw_intrpend(struct ath_hal *ah); 1038 boolean_t ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); 1039 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); 1040 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints); 1041 1042 /* MAC (PCU/QCU) */ 1043 1044 void ath9k_hw_dmaRegDump(struct ath_hal *ah); 1045 uint32_t ath9k_hw_gettxbuf(struct ath_hal *ah, uint32_t q); 1046 boolean_t ath9k_hw_puttxbuf(struct ath_hal *ah, uint32_t q, uint32_t txdp); 1047 boolean_t ath9k_hw_txstart(struct ath_hal *ah, uint32_t q); 1048 uint32_t ath9k_hw_numtxpending(struct ath_hal *ah, uint32_t q); 1049 boolean_t ath9k_hw_updatetxtriglevel(struct ath_hal *ah, 1050 boolean_t bIncTrigLevel); 1051 boolean_t ath9k_hw_stoptxdma(struct ath_hal *ah, uint32_t q); 1052 boolean_t ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, 1053 uint32_t segLen, boolean_t firstSeg, 1054 boolean_t lastSeg, const struct ath_desc *ds0); 1055 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); 1056 int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds); 1057 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, 1058 uint32_t pktLen, enum ath9k_pkt_type type, uint32_t txPower, 1059 uint32_t keyIx, enum ath9k_key_type keyType, uint32_t flags); 1060 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, 1061 struct ath_desc *lastds, 1062 uint32_t durUpdateEn, uint32_t rtsctsRate, 1063 uint32_t rtsctsDuration, 1064 struct ath9k_11n_rate_series series[], 1065 uint32_t nseries, uint32_t flags); 1066 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 1067 uint32_t aggrLen); 1068 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 1069 uint32_t numDelims); 1070 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); 1071 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); 1072 void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, 1073 uint32_t burstDuration); 1074 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, 1075 uint32_t vmf); 1076 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, uint32_t *txqs); 1077 boolean_t ath9k_hw_set_txq_props(struct ath_hal *ah, int q, 1078 const struct ath9k_tx_queue_info *qinfo); 1079 boolean_t ath9k_hw_get_txq_props(struct ath_hal *ah, int q, 1080 struct ath9k_tx_queue_info *qinfo); 1081 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, 1082 const struct ath9k_tx_queue_info *qinfo); 1083 boolean_t ath9k_hw_releasetxqueue(struct ath_hal *ah, uint32_t q); 1084 boolean_t ath9k_hw_resettxqueue(struct ath_hal *ah, uint32_t q); 1085 int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, 1086 uint32_t pa, struct ath_desc *nds, uint64_t tsf); 1087 boolean_t ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, 1088 uint32_t size, uint32_t flags); 1089 boolean_t ath9k_hw_setrxabort(struct ath_hal *ah, boolean_t set); 1090 void ath9k_hw_putrxbuf(struct ath_hal *ah, uint32_t rxdp); 1091 void ath9k_hw_rxena(struct ath_hal *ah); 1092 void ath9k_hw_startpcureceive(struct ath_hal *ah); 1093 void ath9k_hw_stoppcurecv(struct ath_hal *ah); 1094 boolean_t ath9k_hw_stopdmarecv(struct ath_hal *ah); 1095 1096 #ifdef __cplusplus 1097 } 1098 #endif 1099 1100 #endif /* _ARN_ATH9K_H */ 1101