xref: /titanic_52/usr/src/lib/libdtrace/common/sched.d (revision 49d3bc91e27cd871b950d56c01398fa2f2e12ab4)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #pragma D depends_on module unix
29 #pragma D depends_on provider sched
30 
31 struct cpuinfo {
32 	processorid_t cpu_id;		/* CPU identifier */
33 	psetid_t cpu_pset;		/* processor set identifier */
34 	chipid_t cpu_chip;		/* chip identifier */
35 	lgrp_id_t cpu_lgrp;		/* locality group identifer */
36 	processor_info_t cpu_info;	/* CPU information */
37 };
38 
39 typedef struct cpuinfo cpuinfo_t;
40 
41 translator cpuinfo_t < cpu_t *C > {
42 	cpu_id = C->cpu_id;
43 	cpu_pset = C->cpu_part->cp_id;
44 	cpu_chip = C->cpu_physid->cpu_chipid;
45 	cpu_lgrp = C->cpu_lpl->lpl_lgrpid;
46 	cpu_info = (processor_info_t)C->cpu_type_info;
47 };
48 
49 translator cpuinfo_t < disp_t *D > {
50 	cpu_id = D->disp_cpu == NULL ? -1 :
51 	    xlate <cpuinfo_t> (D->disp_cpu).cpu_id;
52 	cpu_pset = D->disp_cpu == NULL ? -1 :
53 	    xlate <cpuinfo_t> (D->disp_cpu).cpu_pset;
54 	cpu_chip = D->disp_cpu == NULL ? -1 :
55 	    xlate <cpuinfo_t> (D->disp_cpu).cpu_chip;
56 	cpu_lgrp = D->disp_cpu == NULL ? -1 :
57 	    xlate <cpuinfo_t> (D->disp_cpu).cpu_lgrp;
58 	cpu_info = D->disp_cpu == NULL ?
59 	    *((processor_info_t *)dtrace`dtrace_zero) :
60 	    (processor_info_t)xlate <cpuinfo_t> (D->disp_cpu).cpu_info;
61 };
62 
63 inline cpuinfo_t *curcpu = xlate <cpuinfo_t *> (curthread->t_cpu);
64 #pragma D attributes Stable/Stable/Common curcpu
65 #pragma D binding "1.0" curcpu
66 
67 inline processorid_t cpu = curcpu->cpu_id;
68 #pragma D attributes Stable/Stable/Common cpu
69 #pragma D binding "1.0" cpu
70 
71 inline psetid_t pset = curcpu->cpu_pset;
72 #pragma D attributes Stable/Stable/Common pset
73 #pragma D binding "1.0" pset
74 
75 inline chipid_t chip = curcpu->cpu_chip;
76 #pragma D attributes Stable/Stable/Common chip
77 #pragma D binding "1.0" chip
78 
79 inline lgrp_id_t lgrp = curcpu->cpu_lgrp;
80 #pragma D attributes Stable/Stable/Common lgrp
81 #pragma D binding "1.0" lgrp
82 
83