1--------------------- 2This package contains performance monitoring event lists for Intel processors, as well as a mapping file 3to help match event lists to processor Family/Model/Stepping codes. 4--------------------- 5 6The event lists are available in 2 formats: 7 Tab delimited (.tsv) 8 Json (.json) 9 10Event lists are created per microarchitecture, and each has a version. Versions are listed in the event list 11name as well as the header for each file. For some microarchitectures, up to three different event lists will 12be available. These event lists correspond to the types of events that can be collected: 13 14core - Contains events counted from within a logical processor core. 15offcore - Contains matrix events counted from the core, but measuring responses that come from offcore. 16 17The event list filename indicates which type of list it contains, and follows this format: 18<microarchitecture-codename>_<core/offcore>_<version> 19 20New version releases will be announced in the mail list perfmon-announce@lists.01.org 21 22Different microarchitectures provide different performance monitoring capabilities, so field names and categories 23of events may vary. 24 25--------------------- 26Event List Field Defitions: 27--------------------- 28Below is a list of the fields/headers in the event files and a description of how SW tools should 29interpret these values. A particular event list from this package may not contain all the fields described 30below. For more detailed information of the Performance monitoring unit please refer to chapters 18 and 19 31of Intel� 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. 32 33http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html 34 35 36----EventCode---- 37This field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs. The set of values for this field 38is defined architecturally. Each value corresponds to an event logic unit and should be used with a unit 39mask value to obtain an architectural performance event. 40 41----UMask---- 42This field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs. It further qualifies the event logic 43unit selected in the event select field to detect a specific micro-architectural condition. 44 45----EventName---- 46It is a string of characters to identify the programming of an event. 47 48----BriefDescription---- 49This field contains a description of what is being counted by a particular event. 50 51----PublicDescription---- 52In some cases, this field will contain a more detailed description of what is counted by an event. 53 54----Counter---- 55This field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX) counters that can be used to count the event. 56 57----CounterHTOff---- 58This field lists the counters where this event can be sampled when Intel� Hyper-Threading Technology (Intel� HT Technology) is 59disabled. When Intel� HT Technology is disabled, some processor cores gain access to the programmable counters of the second 60thread, making a total of eight programmable counters available. The additional counters will be numbered 4,5,6,7. Fixed counter 61behavior remains unaffected. 62 63----PEBScounters---- 64This field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event. 65 66----SampleAfterValue---- 67Sample After Value (SAV) is the value that can be pre-loaded into the counter registers to set the point at which they will overflow. 68To make the counter overflow after N occurrences of the event, it should be loaded with (0xFF..FF � N) or �(N-1). On overflow a 69hardware interrupt is generated through the Local APIC and additional architectural state can be collected in the interrupt handler. 70This is useful in event-based sampling. This field gives a recommended default overflow value, which may be adjusted based on 71workload or tool preference. 72 73----MSRIndex---- 74Additional MSRs may be required for programming certain events. This field gives the address of such MSRS. 75Potential values are: 760x3F6: MSR_PEBS_LD_LAT - used to configure the Load Latency Perforamnce Monitoring Facility 770x1A6/0x1A7: MSR_OFFCORE_RSP_X - used to configure the offcore response events 78 79----MSRValue---- 80When an MSRIndex is used (indicated by the MSRIndex column), this field will contain the value that needs to be loaded into the 81register whose address is given in MSRIndex column. For example, in the case of the load latency events, MSRValue defines the 82latency threshold value to write into the MSR defined in MSRIndex (0x3F6). 83 84----CollectPEBSRecord---- 85Applies to processors that support both precise and non-precise events in Processor Event Based Sampling, such as Goldmont. 860: The event cannot be programmed to collect a PEBS record. 871: The event may be programmed to collect a PEBS record, but caution is advised. 88For instance, PEBS collection of this event may consume limited PEBS resources whereas interrupt-based sampling may be sufficient for the usage model. 892: The event may programmed to collect a PEBS record, and due to the nature of the event, PEBS collection may be preferred. For instance, 90PEBS collection of Goldmont�s HW_INTERUPTS.RECIEVED event is recommended because the hardware interrupt being counted may lead to the masking of 91interrupts which would interfere with interrupt-based sampling. 92 93 94 ----TakenAlone---- 95This field is set for an event which can only be sampled or counted by itself, meaning that when this event is being collected, 96the remaining programmable counters are not available to count any other events. 97 98----CounterMask---- 99This field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR. 100 101----Invert---- 102This field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR. 103 104----AnyThread---- 105This field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR. 106 107----EdgeDetect---- 108This field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR. 109 110----PEBS---- 111A '0' in this field means that the event cannot collect a PEBS record with a Precise IP. A '1' in this field means that the event is a 112precise event and can be programmed in one of two ways � as a regular event or as a PEBS event. And a '2' in this field means 113that the event can only be programmed as a PEBS event. 114 115----PRECISE_STORE---- 116A '1' in this field means the event uses the Precise Store feature and Bit 3 and bit 63 in IA32_PEBS_ENABLE MSR must be set 117to enable IA32_PMC3 as a PEBS counter and enable the precise store facility respectively. Processors based on SandyBridge and 118IvyBridge micro-architecture offer a precise store capability that provides a means to profile store memory references in 119the system. 120 121----DATA_LA---- 122A '1' in this field means that when the event is configured as a PEBS event, the Data Linear Address facility is supported. 123The Data Linear Address facility is a new feature added to Haswell as a replacement or extension of the precise store facility 124in SNB. 125 126----L1_HIT_INDICATION---- 127A '1' in this field means that when the event is configured as a PEBS event, the DCU hit field of the PEBS record is set to 1 128when the store hits in the L1 cache and 0 when it misses. 129 130----Errata---- 131This field lists the known bugs that apply to the events. For the latest, up to date errata refer to 132 133Haswell: 134http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-mobile-specification-update.pdf 135 136IvyBridge: 137https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdf 138 139SandyBridge: 140https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-family-mobile-specification-update.pdf 141 142----offcore---- 143This field is specific to the json format. There is only 1 file for core and offcore events in this format. This field is set to 1 for offcore events 144and 0 for core events. 145 146--------------------- 147For additional information: 148--------------------- 149Intel Platform Monitoring Homepage 150http://software.intel.com/en-us/platform-monitoring/ 151 152http://software.intel.com/en-us/articles/performance-monitoring-on-intel-xeon-processor-e5-family 153 154http://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel 155 156http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/4th-gen-core-family-desktop-specification-update.pdf 157 158--------------------- 159For questions: 160--------------------- 161email perfmon-discuss@lists.01.org 162 163--------------------- 164Notices: 165--------------------- 166INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. 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