xref: /titanic_52/usr/src/data/perfmon/SLM/Silvermont_matrix_V14.json (revision 53548f91e84cd97a638c23b5b295cc69089a5030)

[
  {
    "MATRIX_REQUEST": "DEMAND_DATA_RD",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000001",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts demand and DCU prefetch data read"
  },
  {
    "MATRIX_REQUEST": "DEMAND_RFO",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000002",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts demand and DCU prefetch RFOs"
  },
  {
    "MATRIX_REQUEST": "DEMAND_CODE_RD",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000004",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts demand and DCU prefetch instruction cacheline"
  },
  {
    "MATRIX_REQUEST": "COREWB",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000008",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts writeback (modified to exclusive)"
  },
  {
    "MATRIX_REQUEST": "PF_L2_DATA_RD",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000010",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts data cacheline reads generated by L2 prefetchers"
  },
  {
    "MATRIX_REQUEST": "PF_L2_RFO",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000020",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts RFO requests generated by L2 prefetchers"
  },
  {
    "MATRIX_REQUEST": "PF_L2_CODE_RD",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000040",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts code reads generated by L2 prefetchers"
  },
  {
    "MATRIX_REQUEST": "PARTIAL_READS",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000080",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts demand reads of partial cache lines (including UC and WC)"
  },
  {
    "MATRIX_REQUEST": "PARTIAL_WRITES",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000100",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Countsof demand RFO requests to write to partial cache lines"
  },
  {
    "MATRIX_REQUEST": "UC_CODE_READS",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000200",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts UC instruction fetch"
  },
  {
    "MATRIX_REQUEST": "BUS_LOCKS",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000400",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Bus lock and split lock"
  },
  {
    "MATRIX_REQUEST": "PF_L1_DATA_RD",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000002000",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts DCU hardware prefetcher data read"
  },
  {
    "MATRIX_REQUEST": "ANY_REQUEST",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000008008",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts any request"
  },
  {
    "MATRIX_REQUEST": "STREAMING_STORES",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000004800",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts streaming store"
  },
  {
    "MATRIX_REQUEST": "ANY_DATA_RD",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000003091",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts any data read (demand & prefetch)"
  },
  {
    "MATRIX_REQUEST": "ANY_RFO",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000022",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts any rfo reads (demand & prefetch)"
  },
  {
    "MATRIX_REQUEST": "ANY_CODE_RD",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000044",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts any code reads (demand & prefetch)"
  },
  {
    "MATRIX_REQUEST": "ANY_READS",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x00000032f7",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts any data/code/rfo reads (demand & prefetch)"
  },
  {
    "MATRIX_REQUEST": "ANY_PF_L2",
    "MATRIX_RESPONSE": "Null",
    "MATRIX_VALUE": "0x0000000070",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "Counts any prefetch read"
  },
  {
    "MATRIX_REQUEST": "Null",
    "MATRIX_RESPONSE": "ANY_RESPONSE",
    "MATRIX_VALUE": "0x0000010000",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "have any response type."
  },
  {
    "MATRIX_REQUEST": "Null",
    "MATRIX_RESPONSE": "L2_MISS.NO_SNOOP_NEEDED",
    "MATRIX_VALUE": "0x0080000000",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "miss L2 with no details on snoop-related information."
  },
  {
    "MATRIX_REQUEST": "Null",
    "MATRIX_RESPONSE": "L2_MISS.SNOOP_MISS",
    "MATRIX_VALUE": "0x0200000000",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "miss L2 with a snoop miss response."
  },
  {
    "MATRIX_REQUEST": "Null",
    "MATRIX_RESPONSE": "L2_MISS.HIT_OTHER_CORE_NO_FWD",
    "MATRIX_VALUE": "0x0400000000",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded."
  },
  {
    "MATRIX_REQUEST": "Null",
    "MATRIX_RESPONSE": "L2_MISS.HITM_OTHER_CORE",
    "MATRIX_VALUE": "0x1000000000",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "hit in the other module where modified copies were found in other core's L1 cache."
  },
  {
    "MATRIX_REQUEST": "Null",
    "MATRIX_RESPONSE": "L2_MISS.NON_DRAM",
    "MATRIX_VALUE": "0x2000000000",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "miss L2 and the target was non-DRAM system address."
  },
  {
    "MATRIX_REQUEST": "Null",
    "MATRIX_RESPONSE": "L2_MISS.ANY",
    "MATRIX_VALUE": "0x1680000000",
    "MATRIX_REGISTER": "0,1",
    "DESCRIPTION": "miss L2."
  },
  {
    "MATRIX_REQUEST": "Null",
    "MATRIX_RESPONSE": "OUTSTANDING",
    "MATRIX_VALUE": "0x4000000000",
    "MATRIX_REGISTER": "0",
    "DESCRIPTION": "are outstanding, per cycle, from the time of the L2 miss to when any response is received."
  }
]