xref: /titanic_52/usr/src/cmd/fm/dicts/SUN4V.dict (revision 4df55fde49134f9735f84011f23a767c75e393c7)

#
# Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
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# When distributing Covered Code, include this CDDL HEADER in each
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# DO NOT EDIT -- this file is generated by the Event Registry.
#

FMDICT: name=SUN4V version=1 maxkey=3 dictid=0x3456

fault.cpu.ultraSPARC-T1.ireg=1
fault.cpu.ultraSPARC-T1.freg=2
fault.cpu.ultraSPARC-T1.itlb=3
fault.cpu.ultraSPARC-T1.dtlb=4
fault.cpu.ultraSPARC-T1.icache=5
fault.cpu.ultraSPARC-T1.dcache=6
fault.cpu.ultraSPARC-T1.mau=7
fault.cpu.ultraSPARC-T1.l2cachedata=8
fault.cpu.ultraSPARC-T1.l2cachetag=9
fault.cpu.ultraSPARC-T1.l2cachectl=10
fault.memory.page=11
fault.memory.dimm=12
fault.memory.bank=13
fault.memory.link-c=14
fault.cpu.ultraSPARC-T2.ireg=15
fault.cpu.ultraSPARC-T2.freg=16
fault.cpu.ultraSPARC-T2.misc_reg=17
fault.cpu.ultraSPARC-T2.itlb=18
fault.cpu.ultraSPARC-T2.dtlb=19
fault.cpu.ultraSPARC-T2.icache=20
fault.cpu.ultraSPARC-T2.dcache=21
fault.cpu.ultraSPARC-T2.mau=22
fault.cpu.ultraSPARC-T2.l2data-c=23
fault.cpu.ultraSPARC-T2.l2cachetag=24
fault.cpu.ultraSPARC-T2.l2cachectl=25
fault.memory.link-u=26
fault.cpu.ultraSPARC-T2.l2data-u=27
fault.cpu.ultraSPARC-T1.l2data-c=28
fault.cpu.ultraSPARC-T1.l2data-u=29
fault.memory.datapath=30
fault.io.n2.ncu=31
fault.io.n2.dmu=32
fault.io.n2.niu=33
fault.io.n2.siu=34
fault.io.n2.soc=35
fault.io.n2.crossbar=36
fault.io.fire.fw-epkt fault.io.fire.sw-epkt fault.io.fire.sw-fw-mismatch=37
fault.io.vf.ncx=38
fault.memory.link-f=39
fault.cpu.ultraSPARC-T2plus.ireg=40
fault.cpu.ultraSPARC-T2plus.freg=41
fault.cpu.ultraSPARC-T2plus.misc_reg=42
fault.cpu.ultraSPARC-T2plus.itlb=43
fault.cpu.ultraSPARC-T2plus.dtlb=44
fault.cpu.ultraSPARC-T2plus.icache=45
fault.cpu.ultraSPARC-T2plus.dcache=46
fault.cpu.ultraSPARC-T2plus.mau=47
fault.cpu.ultraSPARC-T2plus.l2data-c=48
fault.cpu.ultraSPARC-T2plus.l2cachetag=49
fault.cpu.ultraSPARC-T2plus.l2cachectl=50
fault.cpu.ultraSPARC-T2plus.l2data-u=51
fault.cpu.ultraSPARC-T2plus.lfu-f=52
fault.cpu.ultraSPARC-T2plus.lfu-p=53
fault.cpu.ultraSPARC-T2plus.lfu-u=54
fault.asic.ultraSPARC-T2plus.interconnect.opu-u=55
fault.asic.ultraSPARC-T2plus.interconnect.opu-c=56
fault.cpu.ultraSPARC-T2plus.chip=57
fault.asic.ultraSPARC-T2plus.interconnect.lfu-c fault.cpu.ultraSPARC-T2plus.chip=58
fault.asic.ultraSPARC-T2plus.interconnect.lfu-f fault.cpu.ultraSPARC-T2plus.chip=59
fault.asic.ultraSPARC-T2plus.interconnect.lfu-u fault.cpu.ultraSPARC-T2plus.chip=60
fault.asic.ultraSPARC-T2plus.interconnect.lfu-u=61
fault.asic.ultraSPARC-T2plus.interconnect.gpd-u fault.cpu.ultraSPARC-T2plus.chip=62
fault.asic.ultraSPARC-T2plus.interconnect.gpd-c fault.cpu.ultraSPARC-T2plus.chip=63
fault.asic.ultraSPARC-T2plus.interconnect.gpd-c=64
fault.asic.fpga fault.asic.ultraSPARC-T2plus.interconnect.gpd-c=65
fault.asic.ultraSPARC-T2plus.interconnect.asu=66
fault.memory.dimm-page-retires-excessive=67
fault.memory.dimm-ue-imminent=68
fault.memory.dram-ue-imminent=69
fault.cpu.generic-sparc.strand=70
fault.cpu.generic-sparc.strand-nr=71
fault.cpu.generic-sparc.strand-uc=72
fault.cpu.generic-sparc.strand-uc-nr=73
fault.cpu.generic-sparc.core=74
fault.cpu.generic-sparc.core-nr=75
fault.cpu.generic-sparc.core-uc=76
fault.cpu.generic-sparc.core-uc-nr=77
fault.cpu.generic-sparc.chip=78
fault.cpu.generic-sparc.chip-nr=79
fault.cpu.generic-sparc.chip-uc=80
fault.cpu.generic-sparc.chip-uc-nr=81
fault.cpu.generic-sparc.c2c=82
fault.cpu.generic-sparc.c2c-failover=83
fault.cpu.generic-sparc.c2c-uc=84
fault.memory.memlink=85
fault.memory.memlink-failover=86
fault.memory.memlink-uc=87
defect.fw.generic-sparc.addr-oob=88
defect.fw.generic-sparc.erpt-gen=89
fault.cpu.generic-sparc.bootbus=90
fault.sp.failed=91