1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NIAGARAREGS_H 28 #define _SYS_NIAGARAREGS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Niagara SPARC Performance Instrumentation Counter 38 */ 39 #define PIC0_MASK (((uint64_t)1 << 32) - 1) /* pic0 in bits 31:0 */ 40 #define PIC1_SHIFT 32 /* pic1 in bits 64:32 */ 41 42 /* 43 * Niagara SPARC Performance Control Register 44 */ 45 46 #define CPC_NIAGARA_PCR_PRIVPIC 0 47 #define CPC_NIAGARA_PCR_SYS 1 48 #define CPC_NIAGARA_PCR_USR 2 49 50 #define CPC_NIAGARA_PCR_PIC0_SHIFT 4 51 #define CPC_NIAGARA_PCR_PIC1_SHIFT 0 52 #define CPC_NIAGARA_PCR_PIC0_MASK UINT64_C(0x7) 53 #define CPC_NIAGARA_PCR_PIC1_MASK UINT64_C(0) 54 55 #define CPC_NIAGARA_PCR_OVF_MASK UINT64_C(0x300) 56 #define CPC_NIAGARA_PCR_OVF_SHIFT 8 57 58 /* 59 * Niagara DRAM performance counters 60 */ 61 #define NIAGARA_DRAM_BANKS 0x4 62 63 #define NIAGARA_DRAM_PIC0_SEL_SHIFT 0x4 64 #define NIAGARA_DRAM_PIC1_SEL_SHIFT 0x0 65 66 #define NIAGARA_DRAM_PIC0_SHIFT 0x20 67 #define NIAGARA_DRAM_PIC0_MASK 0x7fffffff 68 #define NIAGARA_DRAM_PIC1_SHIFT 0x0 69 #define NIAGARA_DRAM_PIC1_MASK 0x7fffffff 70 71 /* 72 * Niagara JBUS performance counters 73 */ 74 #define NIAGARA_JBUS_PIC0_SEL_SHIFT 0x4 75 #define NIAGARA_JBUS_PIC1_SEL_SHIFT 0x0 76 77 #define NIAGARA_JBUS_PIC0_SHIFT 0x20 78 #define NIAGARA_JBUS_PIC0_MASK 0x7fffffff 79 #define NIAGARA_JBUS_PIC1_SHIFT 0x0 80 #define NIAGARA_JBUS_PIC1_MASK 0x7fffffff 81 82 83 /* 84 * Hypervisor FAST_TRAP API function numbers to get/set DRAM and 85 * JBUS performance counters 86 */ 87 #define HV_NIAGARA_GETPERF 0x100 88 #define HV_NIAGARA_SETPERF 0x101 89 90 91 /* 92 * DRAM/JBUS performance counter register numbers for HV_NIAGARA_GETPERF 93 * and HV_NIAGARA_SETPERF 94 */ 95 #define HV_NIAGARA_JBUS_CTL 0x0 96 #define HV_NIAGARA_JBUS_COUNT 0x1 97 #define HV_NIAGARA_DRAM_CTL0 0x2 98 #define HV_NIAGARA_DRAM_COUNT0 0x3 99 #define HV_NIAGARA_DRAM_CTL1 0x4 100 #define HV_NIAGARA_DRAM_COUNT1 0x5 101 #define HV_NIAGARA_DRAM_CTL2 0x6 102 #define HV_NIAGARA_DRAM_COUNT2 0x7 103 #define HV_NIAGARA_DRAM_CTL3 0x8 104 #define HV_NIAGARA_DRAM_COUNT3 0x9 105 106 /* 107 * prototypes for hypervisor interface to get/set DRAM and JBUS 108 * performance counters 109 */ 110 #ifndef _ASM 111 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val); 112 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val); 113 #endif 114 115 /* 116 * Bits defined in L2 Error Status Register 117 * 118 * +---+---+---+---+----+----+----+----+----+----+----+----+----+----+ 119 * |MEU|MEC|RW |RSV|MODA|VCID|LDAC|LDAU|LDWC|LDWU|LDRC|LDRU|LDSC|LDSU| 120 * +---+---+---+---+----+----+----+----+----+----+----+----+----+----+ 121 * 63 62 61 60 59 58-54 53 52 51 50 49 48 47 46 122 * 123 * +---+---+---+---+---+---+---+---+---+---+---+-------+------+ 124 * |LTC|LRU|LVU|DAC|DAU|DRC|DRU|DSC|DSU|VEC|VEU| RSVD1 | SYND | 125 * +---+---+---+---+---+---+---+---+---+---+---+-------+------+ 126 * 45 44 43 42 41 40 39 38 37 36 35 34-32 31-0 127 */ 128 #define NI_L2AFSR_MEU 0x8000000000000000 129 #define NI_L2AFSR_MEC 0x4000000000000000 130 #define NI_L2AFSR_RW 0x2000000000000000 131 #define NI_L2AFSR_RSVD0 0x1000000000000000 132 #define NI_L2AFSR_MODA 0x0800000000000000 133 #define NI_L2AFSR_VCID 0x07C0000000000000 134 #define NI_L2AFSR_LDAC 0x0020000000000000 135 #define NI_L2AFSR_LDAU 0x0010000000000000 136 #define NI_L2AFSR_LDWC 0x0008000000000000 137 #define NI_L2AFSR_LDWU 0x0004000000000000 138 #define NI_L2AFSR_LDRC 0x0002000000000000 139 #define NI_L2AFSR_LDRU 0x0001000000000000 140 #define NI_L2AFSR_LDSC 0x0000800000000000 141 #define NI_L2AFSR_LDSU 0x0000400000000000 142 #define NI_L2AFSR_LTC 0x0000200000000000 143 #define NI_L2AFSR_LRU 0x0000100000000000 144 #define NI_L2AFSR_LVU 0x0000080000000000 145 #define NI_L2AFSR_DAC 0x0000040000000000 146 #define NI_L2AFSR_DAU 0x0000020000000000 147 #define NI_L2AFSR_DRC 0x0000010000000000 148 #define NI_L2AFSR_DRU 0x0000008000000000 149 #define NI_L2AFSR_DSC 0x0000004000000000 150 #define NI_L2AFSR_DSU 0x0000002000000000 151 #define NI_L2AFSR_VEC 0x0000001000000000 152 #define NI_L2AFSR_VEU 0x0000000800000000 153 #define NI_L2AFSR_RSVD1 0x0000000700000000 154 #define NI_L2AFSR_SYND 0x00000000FFFFFFFF 155 156 /* 157 * These L2 bit masks are used to determine if another bit of higher priority 158 * is set. This tells us whether the reported syndrome and address are valid 159 * for this ereport. If the error in hand is Pn, use Pn-1 to bitwise & with 160 * the l2-afsr value. If result is 0, then this ereport's afsr is valid. 161 */ 162 #define NI_L2AFSR_P01 (NI_L2AFSR_LVU) 163 #define NI_L2AFSR_P02 (NI_L2AFSR_P01 | NI_L2AFSR_LRU) 164 #define NI_L2AFSR_P03 (NI_L2AFSR_P02 | NI_L2AFSR_LDAU | NI_L2AFSR_LDSU) 165 #define NI_L2AFSR_P04 (NI_L2AFSR_P03 | NI_L2AFSR_LDWU) 166 #define NI_L2AFSR_P05 (NI_L2AFSR_P04 | NI_L2AFSR_LDRU) 167 #define NI_L2AFSR_P06 (NI_L2AFSR_P05 | NI_L2AFSR_DAU | NI_L2AFSR_DRU) 168 #define NI_L2AFSR_P07 (NI_L2AFSR_P06 | NI_L2AFSR_LTC) 169 #define NI_L2AFSR_P08 (NI_L2AFSR_P07 | NI_L2AFSR_LDAC | NI_L2AFSR_LDSC) 170 #define NI_L2AFSR_P09 (NI_L2AFSR_P08 | NI_L2AFSR_LDWC) 171 #define NI_L2AFSR_P10 (NI_L2AFSR_P09 | NI_L2AFSR_LDRC) 172 #define NI_L2AFSR_P11 (NI_L2AFSR_P10 | NI_L2AFSR_DAC | NI_L2AFSR_DRC) 173 174 /* 175 * Bits defined in DRAM Error Status Register 176 * 177 * +---+---+---+---+---+---+---+----------+------+ 178 * |MEU|MEC|DAC|DAU|DSC|DSU|DBU| RESERVED | SYND | 179 * +---+---+---+---+---+---+---+----------+------+ 180 * 63 62 61 60 59 58 57 56-16 15-0 181 * 182 */ 183 #define NI_DMAFSR_MEU 0x8000000000000000 184 #define NI_DMAFSR_MEC 0x4000000000000000 185 #define NI_DMAFSR_DAC 0x2000000000000000 186 #define NI_DMAFSR_DAU 0x1000000000000000 187 #define NI_DMAFSR_DSC 0x0800000000000000 188 #define NI_DMAFSR_DSU 0x0400000000000000 189 #define NI_DMAFSR_DBU 0x0200000000000000 190 #define NI_DMAFSR_RSVD 0x01FFFFFFFFFF0000 191 #define NI_DMAFSR_SYND 0x000000000000FFFF 192 193 /* Bit mask for DRAM priority determination */ 194 #define NI_DMAFSR_P01 (NI_DMAFSR_DSU | NI_DMAFSR_DAU) 195 196 /* 197 * The following is the syndrome value placed in memory 198 * when an uncorrectable error is written back from L2 cache. 199 */ 200 #define NI_DRAM_POISON_SYND_FROM_LDWU 0x1118 201 202 /* 203 * This L2 poison syndrome is placed on 4 byte checkwords of L2 204 * when a UE is loaded or DMA'ed into L2 205 */ 206 #define NI_L2_POISON_SYND_FROM_DAU 0x3 207 #define NI_L2_POISON_SYND_MASK 0x7F 208 #define NI_L2_POISON_SYND_SIZE 7 209 210 #ifdef __cplusplus 211 } 212 #endif 213 214 #endif /* _SYS_NIAGARAREGS_H */ 215