1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NIAGARA2REGS_H 27 #define _SYS_NIAGARA2REGS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define MB(n) ((n) * 1024 * 1024) 36 37 #define L2CACHE_SIZE MB(4) 38 #define L2CACHE_LINESIZE 64 39 #define L2CACHE_ASSOCIATIVITY 16 40 41 #define NIAGARA2_HSVC_MAJOR 1 42 #define NIAGARA2_HSVC_MINOR 0 43 44 #define VFALLS_HSVC_MAJOR 1 45 #define VFALLS_HSVC_MINOR 0 46 47 #define NIAGARA2_PREALLOC_BASE MB(196) 48 49 /* PIC overflow range is -16 to -1 */ 50 #define PIC_IN_OV_RANGE(x) (((uint32_t)x >= 0xfffffff0) ? 1 : 0) 51 52 /* 53 * Niagara2 SPARC Performance Instrumentation Counter 54 */ 55 #define PIC0_MASK (((uint64_t)1 << 32) - 1) /* pic0 in bits 31:0 */ 56 #define PIC1_SHIFT 32 /* pic1 in bits 64:32 */ 57 58 /* 59 * Niagara2 SPARC Performance Control Register 60 */ 61 #define CPC_NIAGARA2_PCR_PRIV_SHIFT 0 62 #define CPC_NIAGARA2_PCR_ST_SHIFT 1 63 #define CPC_NIAGARA2_PCR_UT_SHIFT 2 64 65 #define CPC_NIAGARA2_PCR_HT_SHIFT 3 66 #define CPC_NIAGARA2_PCR_HT (1ull << CPC_NIAGARA2_PCR_HT_SHIFT) 67 68 #define CPC_NIAGARA2_PCR_TOE0_SHIFT 4 69 #define CPC_NIAGARA2_PCR_TOE1_SHIFT 5 70 #define CPC_NIAGARA2_PCR_TOE0 (1ull << CPC_NIAGARA2_PCR_TOE0_SHIFT) 71 #define CPC_NIAGARA2_PCR_TOE1 (1ull << CPC_NIAGARA2_PCR_TOE1_SHIFT) 72 73 #define CPC_NIAGARA2_PCR_PIC0_SHIFT 6 74 #define CPC_NIAGARA2_PCR_PIC1_SHIFT 19 75 #define CPC_NIAGARA2_PCR_PIC0_MASK UINT64_C(0xfff) 76 #define CPC_NIAGARA2_PCR_PIC1_MASK UINT64_C(0xfff) 77 78 #define CPC_NIAGARA2_PCR_OV0_SHIFT 18 79 #define CPC_NIAGARA2_PCR_OV1_SHIFT 30 80 #define CPC_NIAGARA2_PCR_OV0_MASK UINT64_C(0x40000) 81 #define CPC_NIAGARA2_PCR_OV1_MASK UINT64_C(0x80000000) 82 83 #define CPC_NIAGARA2_PCR_HOLDOV0_SHIFT 62 84 #define CPC_NIAGARA2_PCR_HOLDOV1_SHIFT 63 85 #define CPC_NIAGARA2_PCR_HOLDOV0 (1ull << CPC_NIAGARA2_PCR_HOLDOV0_SHIFT) 86 #define CPC_NIAGARA2_PCR_HOLDOV1 (1ull << CPC_NIAGARA2_PCR_HOLDOV1_SHIFT) 87 88 /* 89 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 90 * performance counters for Niagara2 91 */ 92 #define HV_NIAGARA2_GETPERF 0x104 93 #define HV_NIAGARA2_SETPERF 0x105 94 95 /* 96 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 97 * performance counters for Victoria Falls 98 */ 99 #define HV_VFALLS_GETPERF 0x106 100 #define HV_VFALLS_SETPERF 0x107 101 102 /* 103 * Niagara2 DRAM performance counters 104 */ 105 #define NIAGARA_DRAM_BANKS 0x4 106 107 #define NIAGARA_DRAM_PIC0_SEL_SHIFT 0x4 108 #define NIAGARA_DRAM_PIC1_SEL_SHIFT 0x0 109 110 #define NIAGARA_DRAM_PIC0_SHIFT 0x20 111 #define NIAGARA_DRAM_PIC0_MASK 0x7fffffff 112 #define NIAGARA_DRAM_PIC1_SHIFT 0x0 113 #define NIAGARA_DRAM_PIC1_MASK 0x7fffffff 114 115 #if defined(NIAGARA2_IMPL) 116 /* 117 * SPARC/DRAM performance counter register numbers for HV_NIAGARA2_GETPERF 118 * and HV_NIAGARA2_SETPERF for Niagara2 119 */ 120 #define HV_NIAGARA_SPARC_CTL 0x0 121 #define HV_NIAGARA_DRAM_CTL0 0x1 122 #define HV_NIAGARA_DRAM_COUNT0 0x2 123 #define HV_NIAGARA_DRAM_CTL1 0x3 124 #define HV_NIAGARA_DRAM_COUNT1 0x4 125 #define HV_NIAGARA_DRAM_CTL2 0x5 126 #define HV_NIAGARA_DRAM_COUNT2 0x6 127 #define HV_NIAGARA_DRAM_CTL3 0x7 128 #define HV_NIAGARA_DRAM_COUNT3 0x8 129 130 #elif defined(VFALLS_IMPL) 131 /* 132 * SPARC/DRAM performance counter register numbers for HV_VFALLS_GETPERF 133 * and HV_VFALLS_SETPERF for Victoria Falls 134 * Support for 2-node configuration 135 */ 136 #define HV_NIAGARA_SPARC_CTL 0x0 137 #define HV_NIAGARA_L2_CTL 0x1 138 #define HV_NIAGARA_DRAM_CTL0 0x2 139 #define HV_NIAGARA_DRAM_COUNT0 0x3 140 #define HV_NIAGARA_DRAM_CTL1 0x4 141 #define HV_NIAGARA_DRAM_COUNT1 0x5 142 #define HV_NIAGARA_DRAM_CTL2 0x6 143 #define HV_NIAGARA_DRAM_COUNT2 0x7 144 #define HV_NIAGARA_DRAM_CTL3 0x8 145 #define HV_NIAGARA_DRAM_COUNT3 0x9 146 147 #define VFALLS_L2_CTL_MASK 0x3 148 #define VFALLS_SL3_MASK 0x300 149 150 #endif 151 152 #ifndef _ASM 153 /* 154 * prototypes for hypervisor interface to get/set SPARC and DRAM 155 * performance counters 156 */ 157 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val); 158 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val); 159 #endif 160 161 #ifdef __cplusplus 162 } 163 #endif 164 165 #endif /* _SYS_NIAGARA2REGS_H */ 166