xref: /titanic_51/usr/src/uts/sun4v/sys/niagara2regs.h (revision 14ea4bb737263733ad80a36b4f73f681c30a6b45)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_NIAGARA2REGS_H
27 #define	_SYS_NIAGARA2REGS_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 #define	MB(n)	((n) * 1024 * 1024)
36 
37 #define	L2CACHE_SIZE		MB(4)
38 #define	L2CACHE_LINESIZE	64
39 #define	L2CACHE_ASSOCIATIVITY	16
40 
41 #define	NIAGARA2_HSVC_MAJOR	1
42 #define	NIAGARA2_HSVC_MINOR	0
43 
44 /* PIC overflow range is -16 to -1 */
45 #define	PIC_IN_OV_RANGE(x)	(((uint32_t)x >= 0xfffffff0) ? 1 : 0)
46 
47 /*
48  * Niagara2 SPARC Performance Instrumentation Counter
49  */
50 #define	PIC0_MASK	(((uint64_t)1 << 32) - 1)	/* pic0 in bits 31:0 */
51 #define	PIC1_SHIFT	32				/* pic1 in bits 64:32 */
52 
53 /*
54  * Niagara2 SPARC Performance Control Register
55  */
56 #define	CPC_NIAGARA2_PCR_PRIVPIC_SHIFT	0
57 #define	CPC_NIAGARA2_PCR_SYS_SHIFT	1
58 #define	CPC_NIAGARA2_PCR_USR_SHIFT	2
59 #define	CPC_NIAGARA2_PCR_HPRIV_SHIFT	3
60 #define	CPC_NIAGARA2_PCR_TOE0_SHIFT	4
61 #define	CPC_NIAGARA2_PCR_TOE1_SHIFT	5
62 
63 #define	CPC_COUNT_HPRIV			(1ull << CPC_NIAGARA2_PCR_HPRIV_SHIFT)
64 #define	CPC_COUNT_TOE0			(1ull << CPC_NIAGARA2_PCR_TOE0_SHIFT)
65 #define	CPC_COUNT_TOE1			(1ull << CPC_NIAGARA2_PCR_TOE1_SHIFT)
66 
67 #define	CPC_NIAGARA2_PCR_PIC0_SHIFT	6
68 #define	CPC_NIAGARA2_PCR_PIC1_SHIFT	19
69 #define	CPC_NIAGARA2_PCR_PIC0_MASK	UINT64_C(0xfff)
70 #define	CPC_NIAGARA2_PCR_PIC1_MASK	UINT64_C(0xfff)
71 
72 #define	CPC_NIAGARA2_PCR_OV0_MASK	UINT64_C(0x40000)
73 #define	CPC_NIAGARA2_PCR_OV1_MASK	UINT64_C(0x80000000)
74 #define	CPC_NIAGARA2_PCR_OV0_SHIFT	18
75 #define	CPC_NIAGARA2_PCR_OV1_SHIFT	30
76 
77 /*
78  * Hypervisor FAST_TRAP API function numbers to get/set DRAM
79  * performance counters
80  */
81 #define	HV_NIAGARA2_GETPERF		0x104
82 #define	HV_NIAGARA2_SETPERF		0x105
83 
84 /*
85  * Niagara2 DRAM performance counters
86  */
87 #define	NIAGARA_DRAM_BANKS		0x4
88 
89 #define	NIAGARA_DRAM_PIC0_SEL_SHIFT	0x4
90 #define	NIAGARA_DRAM_PIC1_SEL_SHIFT	0x0
91 
92 #define	NIAGARA_DRAM_PIC0_SHIFT		0x20
93 #define	NIAGARA_DRAM_PIC0_MASK		0x7fffffff
94 #define	NIAGARA_DRAM_PIC1_SHIFT		0x0
95 #define	NIAGARA_DRAM_PIC1_MASK		0x7fffffff
96 
97 /*
98  * SPARC/DRAM performance counter register numbers for HV_NIAGARA2_GETPERF
99  * and HV_NIAGARA2_SETPERF
100  */
101 #define	HV_NIAGARA_SPARC_CTL		0x0
102 #define	HV_NIAGARA_DRAM_CTL0		0x1
103 #define	HV_NIAGARA_DRAM_COUNT0		0x2
104 #define	HV_NIAGARA_DRAM_CTL1		0x3
105 #define	HV_NIAGARA_DRAM_COUNT1		0x4
106 #define	HV_NIAGARA_DRAM_CTL2		0x5
107 #define	HV_NIAGARA_DRAM_COUNT2		0x6
108 #define	HV_NIAGARA_DRAM_CTL3		0x7
109 #define	HV_NIAGARA_DRAM_COUNT3		0x8
110 
111 #ifndef _ASM
112 /*
113  * prototypes for hypervisor interface to get/set SPARC and DRAM
114  * performance counters
115  */
116 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val);
117 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val);
118 #endif
119 
120 #ifdef __cplusplus
121 }
122 #endif
123 
124 #endif /* _SYS_NIAGARA2REGS_H */
125