1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_HYPERVISOR_API_H 28 #define _SYS_HYPERVISOR_API_H 29 30 /* 31 * sun4v Hypervisor API 32 * 33 * Reference: api.pdf Revision 0.12 dated May 12, 2004. 34 * io-api.txt version 1.11 dated 10/19/2004 35 */ 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /* 42 * Trap types 43 */ 44 #define FAST_TRAP 0x80 /* Function # in %o5 */ 45 #define CPU_TICK_NPT 0x81 46 #define CPU_STICK_NPT 0x82 47 #define MMU_MAP_ADDR 0x83 48 #define MMU_UNMAP_ADDR 0x84 49 #define MMU_MAP_TTE 0x86 50 51 #define CORE_TRAP 0xff 52 53 /* 54 * Error returns in %o0. 55 * (Additional result is returned in %o1.) 56 */ 57 #define H_EOK 0 /* Successful return */ 58 #define H_ENOCPU 1 /* Invalid CPU id */ 59 #define H_ENORADDR 2 /* Invalid real address */ 60 #define H_ENOINTR 3 /* Invalid interrupt id */ 61 #define H_EBADPGSZ 4 /* Invalid pagesize encoding */ 62 #define H_EBADTSB 5 /* Invalid TSB description */ 63 #define H_EINVAL 6 /* Invalid argument */ 64 #define H_EBADTRAP 7 /* Invalid function number */ 65 #define H_EBADALIGN 8 /* Invalid address alignment */ 66 #define H_EWOULDBLOCK 9 /* Cannot complete operation */ 67 /* without blocking */ 68 #define H_ENOACCESS 10 /* No access to resource */ 69 #define H_EIO 11 /* I/O error */ 70 #define H_ECPUERROR 12 /* CPU is in error state */ 71 #define H_ENOTSUPPORTED 13 /* Function not supported */ 72 #define H_ENOMAP 14 /* Mapping is not valid, */ 73 /* no translation exists */ 74 #define H_EBUSY 17 /* Resource busy */ 75 #define H_ETOOMANY 15 /* Hard resource limit exceeded */ 76 #define H_ECHANNEL 16 /* Illegal LDC channel */ 77 78 #define H_BREAK -1 /* Console Break */ 79 #define H_HUP -2 /* Console Break */ 80 81 /* 82 * Mondo CPU ID argument processing. 83 */ 84 #define HV_SEND_MONDO_ENTRYDONE 0xffff 85 86 /* 87 * Function numbers for FAST_TRAP. 88 */ 89 #define HV_MACH_EXIT 0x00 90 #define HV_MACH_DESC 0x01 91 #define HV_MACH_SIR 0x02 92 #define MACH_SET_WATCHDOG 0x05 93 94 #define HV_CPU_START 0x10 95 #define HV_CPU_STOP 0x11 96 #define HV_CPU_YIELD 0x12 97 #define HV_CPU_QCONF 0x14 98 #define HV_CPU_STATE 0x17 99 #define HV_CPU_SET_RTBA 0x18 100 101 #define MMU_TSB_CTX0 0x20 102 #define MMU_TSB_CTXNON0 0x21 103 #define MMU_DEMAP_PAGE 0x22 104 #define MMU_DEMAP_CTX 0x23 105 #define MMU_DEMAP_ALL 0x24 106 #define MAP_PERM_ADDR 0x25 107 #define MMU_SET_INFOPTR 0x26 108 #define MMU_ENABLE 0x27 109 #define UNMAP_PERM_ADDR 0x28 110 111 #define HV_MEM_SCRUB 0x31 112 #define HV_MEM_SYNC 0x32 113 #define HV_MEM_IFLUSH 0x33 114 #define HV_MEM_IFLUSH_ALL 0x34 115 116 #define HV_INTR_SEND 0x42 117 118 #define TOD_GET 0x50 119 #define TOD_SET 0x51 120 121 #define CONS_GETCHAR 0x60 122 #define CONS_PUTCHAR 0x61 123 #define CONS_READ 0x62 124 #define CONS_WRITE 0x63 125 126 #define SOFT_STATE_SET 0x70 127 #define SOFT_STATE_GET 0x71 128 129 #define TTRACE_BUF_CONF 0x90 130 #define TTRACE_BUF_INFO 0x91 131 #define TTRACE_ENABLE 0x92 132 #define TTRACE_FREEZE 0x93 133 #define DUMP_BUF_UPDATE 0x94 134 135 #define HVIO_INTR_DEVINO2SYSINO 0xa0 136 #define HVIO_INTR_GETVALID 0xa1 137 #define HVIO_INTR_SETVALID 0xa2 138 #define HVIO_INTR_GETSTATE 0xa3 139 #define HVIO_INTR_SETSTATE 0xa4 140 #define HVIO_INTR_GETTARGET 0xa5 141 #define HVIO_INTR_SETTARGET 0xa6 142 143 #define VINTR_GET_COOKIE 0xa7 144 #define VINTR_SET_COOKIE 0xa8 145 #define VINTR_GET_VALID 0xa9 146 #define VINTR_SET_VALID 0xaa 147 #define VINTR_GET_STATE 0xab 148 #define VINTR_SET_STATE 0xac 149 #define VINTR_GET_TARGET 0xad 150 #define VINTR_SET_TARGET 0xae 151 152 #define LDC_TX_QCONF 0xe0 153 #define LDC_TX_QINFO 0xe1 154 #define LDC_TX_GET_STATE 0xe2 155 #define LDC_TX_SET_QTAIL 0xe3 156 #define LDC_RX_QCONF 0xe4 157 #define LDC_RX_QINFO 0xe5 158 #define LDC_RX_GET_STATE 0xe6 159 #define LDC_RX_SET_QHEAD 0xe7 160 161 #define LDC_SET_MAP_TABLE 0xea 162 #define LDC_GET_MAP_TABLE 0xeb 163 #define LDC_COPY 0xec 164 #define LDC_MAPIN 0xed 165 #define LDC_UNMAP 0xee 166 #define LDC_REVOKE 0xef 167 168 #ifdef SET_MMU_STATS 169 #define MMU_STAT_AREA 0xfc 170 #endif /* SET_MMU_STATS */ 171 172 #define HV_TM_ENABLE 0x180 173 174 #define HV_RA2PA 0x200 175 #define HV_HPRIV 0x201 176 177 /* 178 * Function numbers for CORE_TRAP. 179 */ 180 #define API_SET_VERSION 0x00 181 #define API_PUT_CHAR 0x01 182 #define API_EXIT 0x02 183 #define API_GET_VERSION 0x03 184 185 186 /* 187 * Definitions for MACH_SOFT_STATE routines 188 */ 189 190 #define SIS_NORMAL 0x01 191 #define SIS_TRANSITION 0x02 192 193 /* 194 * Bits for MMU functions flags argument: 195 * arg3 of MMU_MAP_ADDR 196 * arg3 of MMU_DEMAP_CTX 197 * arg2 of MMU_DEMAP_ALL 198 */ 199 #define MAP_DTLB 0x1 200 #define MAP_ITLB 0x2 201 202 /* 203 * Definitions for TLB Search Order functions 204 */ 205 #define TLB_SO_DATA 0x1 206 #define TLB_SO_INS 0x2 207 #define TLB_SO_ID TLB_SO_DATA | TLB_SO_INS 208 209 /* 210 * Interrupt state manipulation definitions. 211 */ 212 213 #define HV_INTR_IDLE_STATE 0 214 #define HV_INTR_RECEIVED_STATE 1 215 #define HV_INTR_DELIVERED_STATE 2 216 217 #define HV_INTR_NOTVALID 0 218 #define HV_INTR_VALID 1 219 220 #ifndef _ASM 221 222 /* 223 * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0. 224 */ 225 typedef struct hv_tsb_info { 226 uint16_t hvtsb_idxpgsz; /* page size used to index TSB */ 227 uint16_t hvtsb_assoc; /* TSB associativity */ 228 uint32_t hvtsb_ntte; /* TSB size (#TTE entries) */ 229 uint32_t hvtsb_ctx_index; /* context reg index */ 230 uint32_t hvtsb_pgszs; /* sizes in use */ 231 uint64_t hvtsb_pa; /* real address of TSB base */ 232 uint64_t hvtsb_rsvd; /* reserved */ 233 } hv_tsb_info_t; 234 235 #define HVTSB_SHARE_INDEX ((uint32_t)-1) 236 237 #ifdef SET_MMU_STATS 238 #ifndef TTE4V_NPGSZ 239 #define TTE4V_NPGSZ 8 240 #endif /* TTE4V_NPGSZ */ 241 /* 242 * MMU statistics structure for MMU_STAT_AREA 243 */ 244 struct mmu_stat_one { 245 uint64_t hit_ctx0[TTE4V_NPGSZ]; 246 uint64_t hit_ctxn0[TTE4V_NPGSZ]; 247 uint64_t tsb_miss; 248 uint64_t tlb_miss; /* miss, no TSB set */ 249 uint64_t map_ctx0[TTE4V_NPGSZ]; 250 uint64_t map_ctxn0[TTE4V_NPGSZ]; 251 }; 252 253 struct mmu_stat { 254 struct mmu_stat_one immu_stat; 255 struct mmu_stat_one dmmu_stat; 256 uint64_t set_ctx0; 257 uint64_t set_ctxn0; 258 }; 259 #endif /* SET_MMU_STATS */ 260 261 #endif /* ! _ASM */ 262 263 /* 264 * CPU States 265 */ 266 #define CPU_STATE_INVALID 0x0 267 #define CPU_STATE_STOPPED 0x1 /* cpu not started */ 268 #define CPU_STATE_RUNNING 0x2 /* cpu running guest code */ 269 #define CPU_STATE_ERROR 0x3 /* cpu is in the error state */ 270 #define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */ 271 272 /* 273 * MMU fault status area 274 */ 275 276 #define MMFSA_TYPE_ 0x00 /* fault type */ 277 #define MMFSA_ADDR_ 0x08 /* fault address */ 278 #define MMFSA_CTX_ 0x10 /* fault context */ 279 280 #define MMFSA_I_ 0x00 /* start of fields for I */ 281 #define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */ 282 #define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */ 283 #define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */ 284 285 #define MMFSA_D_ 0x40 /* start of fields for D */ 286 #define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */ 287 #define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */ 288 #define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */ 289 290 #define MMFSA_F_FMISS 1 /* fast miss */ 291 #define MMFSA_F_FPROT 2 /* fast protection */ 292 #define MMFSA_F_MISS 3 /* mmu miss */ 293 #define MMFSA_F_INVRA 4 /* invalid RA */ 294 #define MMFSA_F_PRIV 5 /* privilege violation */ 295 #define MMFSA_F_PROT 6 /* protection violation */ 296 #define MMFSA_F_NFO 7 /* NFO access */ 297 #define MMFSA_F_SOPG 8 /* so page */ 298 #define MMFSA_F_INVVA 9 /* invalid VA */ 299 #define MMFSA_F_INVASI 10 /* invalid ASI */ 300 #define MMFSA_F_NCATM 11 /* non-cacheable atomic */ 301 #define MMFSA_F_PRVACT 12 /* privileged action */ 302 #define MMFSA_F_WPT 13 /* watchpoint hit */ 303 #define MMFSA_F_UNALIGN 14 /* unaligned access */ 304 #define MMFSA_F_INVPGSZ 15 /* invalid page size */ 305 306 #define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */ 307 308 /* 309 * MMU fault status - MMFSA_IFS and MMFSA_DFS 310 */ 311 #define MMFS_FV 0x00000001 312 #define MMFS_OW 0x00000002 313 #define MMFS_W 0x00000004 314 #define MMFS_PR 0x00000008 315 #define MMFS_CT 0x00000030 316 #define MMFS_E 0x00000040 317 #define MMFS_FT 0x00003f80 318 #define MMFS_ME 0x00004000 319 #define MMFS_TM 0x00008000 320 #define MMFS_ASI 0x00ff0000 321 #define MMFS_NF 0x01000000 322 323 /* 324 * DMA sync parameter definitions 325 */ 326 #define HVIO_DMA_SYNC_DIR_TO_DEV 0x01 327 #define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02 328 #define HVIO_DMA_SYNC_DIR_NO_ICACHE_FLUSH 0x04 329 330 /* 331 * LDC Channel States 332 */ 333 #define LDC_CHANNEL_DOWN 0x0 334 #define LDC_CHANNEL_UP 0x1 335 #define LDC_CHANNEL_RESET 0x2 336 337 #ifndef _ASM 338 339 extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int); 340 extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int); 341 extern uint64_t hv_mach_exit(uint64_t exit_code); 342 extern uint64_t hv_mach_sir(void); 343 344 extern uint64_t hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, 345 uint64_t arg); 346 extern uint64_t hv_cpu_stop(uint64_t cpuid); 347 extern uint64_t hv_cpu_set_rtba(uint64_t *rtba); 348 349 extern uint64_t hv_set_ctx0(uint64_t, uint64_t); 350 extern uint64_t hv_set_ctxnon0(uint64_t, uint64_t); 351 extern uint64_t hv_mmu_fault_area_conf(void *raddr); 352 #ifdef SET_MMU_STATS 353 extern uint64_t hv_mmu_set_stat_area(uint64_t, uint64_t); 354 #endif /* SET_MMU_STATS */ 355 356 extern uint64_t hv_cpu_qconf(int queue, uint64_t paddr, int size); 357 extern uint64_t hv_cpu_yield(void); 358 extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 359 extern uint64_t hv_mem_scrub(uint64_t real_addr, uint64_t length, 360 uint64_t *scrubbed_len); 361 extern uint64_t hv_mem_sync(uint64_t real_addr, uint64_t length, 362 uint64_t *flushed_len); 363 extern uint64_t hv_mem_iflush(uint64_t real_addr, uint64_t length, 364 uint64_t *flushed_len); 365 extern uint64_t hv_mem_iflush_all(void); 366 extern uint64_t hv_tm_enable(uint64_t enable); 367 368 extern uint64_t hv_service_recv(uint64_t s_id, uint64_t buf_pa, 369 uint64_t size, uint64_t *recv_bytes); 370 extern uint64_t hv_service_send(uint64_t s_id, uint64_t buf_pa, 371 uint64_t size, uint64_t *send_bytes); 372 extern uint64_t hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 373 extern uint64_t hv_service_setstatus(uint64_t s_id, uint64_t bits); 374 extern uint64_t hv_service_clrstatus(uint64_t s_id, uint64_t bits); 375 extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep); 376 377 extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *); 378 extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *); 379 extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *); 380 extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *); 381 extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *); 382 extern uint64_t hv_mach_set_watchdog(uint64_t, uint64_t *); 383 384 extern int64_t hv_cnputchar(uint8_t); 385 extern int64_t hv_cngetchar(uint8_t *); 386 extern int64_t hv_cnwrite(uint64_t, uint64_t, uint64_t *); 387 extern int64_t hv_cnread(uint64_t, uint64_t, int64_t *); 388 389 extern uint64_t hv_tod_get(uint64_t *seconds); 390 extern uint64_t hv_tod_set(uint64_t); 391 392 extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, 393 uint64_t *sysino); 394 extern uint64_t hvio_intr_getvalid(uint64_t sysino, 395 int *intr_valid_state); 396 extern uint64_t hvio_intr_setvalid(uint64_t sysino, 397 int intr_valid_state); 398 extern uint64_t hvio_intr_getstate(uint64_t sysino, 399 int *intr_state); 400 extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state); 401 extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid); 402 extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid); 403 extern uint64_t hv_soft_state_set(uint64_t state, uint64_t string_ra); 404 extern uint64_t hv_soft_state_get(uint64_t string_ra, uint64_t *state); 405 406 extern uint64_t hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 407 uint64_t nentries); 408 extern uint64_t hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 409 uint64_t *nentries); 410 extern uint64_t hv_ldc_tx_get_state(uint64_t channel, uint64_t *headp, 411 uint64_t *tailp, uint64_t *state); 412 extern uint64_t hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail); 413 extern uint64_t hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 414 uint64_t nentries); 415 extern uint64_t hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 416 uint64_t *nentries); 417 extern uint64_t hv_ldc_rx_get_state(uint64_t channel, uint64_t *headp, 418 uint64_t *tailp, uint64_t *state); 419 extern uint64_t hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head); 420 421 extern uint64_t hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 422 uint64_t tbl_entries); 423 extern uint64_t hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 424 uint64_t *tbl_entries); 425 extern uint64_t hv_ldc_copy(uint64_t channel, uint64_t request, 426 uint64_t cookie, uint64_t raddr, uint64_t length, uint64_t *lengthp); 427 extern uint64_t hv_ldc_mapin(uint64_t channel, uint64_t cookie, 428 uint64_t *raddr, uint64_t *perm); 429 extern uint64_t hv_ldc_unmap(uint64_t raddr); 430 extern uint64_t hv_ldc_revoke(uint64_t channel, uint64_t cookie, 431 uint64_t revoke_cookie); 432 extern uint64_t hv_api_get_version(uint64_t api_group, uint64_t *majorp, 433 uint64_t *minorp); 434 extern uint64_t hv_api_set_version(uint64_t api_group, uint64_t major, 435 uint64_t minor, uint64_t *supported_minor); 436 437 extern uint64_t hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 438 uint64_t *cookie); 439 extern uint64_t hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 440 uint64_t cookie); 441 extern uint64_t hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 442 int *intr_valid_state); 443 extern uint64_t hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 444 int intr_valid_state); 445 extern uint64_t hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 446 int *intr_state); 447 extern uint64_t hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 448 int intr_state); 449 extern uint64_t hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 450 uint32_t *cpuid); 451 extern uint64_t hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 452 uint32_t cpuid); 453 454 #endif /* ! _ASM */ 455 456 457 #ifdef __cplusplus 458 } 459 #endif 460 461 #endif /* _SYS_HYPERVISOR_API_H */ 462