xref: /titanic_51/usr/src/uts/sun4v/promif/promif_cpu.c (revision 4a6ec905b96eb96a398c346f59e034a90ce8ad37)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 #include <sys/promif_impl.h>
30 #include <sys/machsystm.h>
31 #include <sys/hypervisor_api.h>
32 #include <sys/lpad.h>
33 
34 extern int (*prom_cif_handler)(void *);
35 extern int cif_cpu_mp_ready;
36 
37 int
38 promif_set_mmfsa_traptable(void *p)
39 {
40 	cell_t		*ci = (cell_t *)p;
41 	uint64_t	rtba;
42 	caddr_t		tba;
43 	uint64_t	mmfsa_ra;
44 	int		rv, ret;
45 
46 	ASSERT(ci[1] == 2);
47 
48 	/*
49 	 * We use the same trap table for the rtba as well.
50 	 */
51 	rtba = va_to_pa(p1275_cell2ptr(ci[3]));
52 
53 	/*
54 	 * if cif_cpu_mp_ready is not set the prom is still
55 	 * setting the mmfsa and trap table. Set the rtba
56 	 * after the prom cif call.
57 	 */
58 	if (!cif_cpu_mp_ready) {
59 		ret = (*prom_cif_handler)(p);
60 		if ((rv = hv_cpu_set_rtba(&rtba)) != H_EOK)
61 			panic("hv_cpu_set_rtba failed: %d\n", rv);
62 		return (ret);
63 	}
64 
65 	tba = p1275_cell2ptr(ci[3]);
66 	mmfsa_ra = (uint64_t)p1275_cell2ptr(ci[4]);
67 
68 	if (tba != (caddr_t)KERNELBASE)
69 		return (-1);
70 
71 	(void) set_tba(tba);
72 
73 	if ((rv = hv_mmu_fault_area_conf(&mmfsa_ra)) != H_EOK) {
74 		panic("hv_mmu_fault_area_conf failed: %d\n", rv);
75 	}
76 
77 	if ((rv = hv_cpu_set_rtba(&rtba)) != H_EOK) {
78 		panic("hv_cpu_set_rtba failed: %d\n", rv);
79 	}
80 
81 	return (0);
82 }
83 
84 int
85 promif_start_cpu(void *p)
86 {
87 	cell_t		*ci = (cell_t *)p;
88 	int		cpuid;
89 	caddr_t		pc;
90 	int		arg;
91 	uint64_t	rtba = 0;
92 	int		rv;
93 	uint64_t	*lpp;
94 
95 	ASSERT(ci[1] == 3);
96 
97 	cpuid = p1275_cell2int(ci[3]);
98 	pc = p1275_cell2ptr(ci[4]);
99 	arg = p1275_cell2int(ci[5]);
100 
101 	if (!cif_cpu_mp_ready)
102 		return ((*prom_cif_handler)(p));
103 
104 	rtba = va_to_pa(&trap_table);
105 
106 	lpp = lpad_setup(cpuid, (uint64_t)pc, (uint64_t)arg);
107 
108 	ASSERT(lpp);
109 
110 	pc = (caddr_t)lpp;
111 
112 	rv = hv_cpu_start(cpuid, va_to_pa(pc), rtba, cpuid);
113 
114 	if (rv != H_EOK) {
115 		panic("promif_start_cpu: failed to start cpu %d (%d)\n",
116 		    cpuid, rv);
117 	}
118 
119 	ci[6] = p1275_int2cell(rv);
120 
121 	return (0);
122 }
123