xref: /titanic_51/usr/src/uts/sun4v/os/mach_startup.c (revision 5e45752a44935a6b2445ae1c763867d868fa3fbb)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 #include <sys/machsystm.h>
30 #include <sys/archsystm.h>
31 #include <sys/prom_plat.h>
32 #include <sys/promif.h>
33 #include <sys/vm.h>
34 #include <sys/cpu.h>
35 #include <sys/atomic.h>
36 #include <sys/cpupart.h>
37 #include <sys/disp.h>
38 #include <sys/hypervisor_api.h>
39 #include <sys/traptrace.h>
40 #include <sys/modctl.h>
41 #include <sys/ldoms.h>
42 
43 #ifdef TRAPTRACE
44 int mach_htraptrace_enable = 1;
45 #else
46 int mach_htraptrace_enable = 0;
47 #endif
48 int htrap_tr0_inuse = 0;
49 extern char htrap_tr0[];	/* prealloc buf for boot cpu */
50 
51 caddr_t	mmu_fault_status_area;
52 
53 extern void sfmmu_set_tsbs(void);
54 /*
55  * CPU IDLE optimization variables/routines
56  */
57 static int enable_halt_idle_cpus = 1;
58 
59 void
60 setup_trap_table(void)
61 {
62 	caddr_t mmfsa_va;
63 	extern	 caddr_t mmu_fault_status_area;
64 	mmfsa_va =
65 	    mmu_fault_status_area + (MMFSA_SIZE * CPU->cpu_id);
66 
67 	intr_init(CPU);		/* init interrupt request free list */
68 	setwstate(WSTATE_KERN);
69 	set_mmfsa_scratchpad(mmfsa_va);
70 	prom_set_mmfsa_traptable(&trap_table, va_to_pa(mmfsa_va));
71 	sfmmu_set_tsbs();
72 }
73 
74 void
75 phys_install_has_changed(void)
76 {
77 
78 }
79 
80 /*
81  * Halt the present CPU until awoken via an interrupt
82  */
83 static void
84 cpu_halt(void)
85 {
86 	cpu_t *cpup = CPU;
87 	processorid_t cpun = cpup->cpu_id;
88 	cpupart_t *cp = cpup->cpu_part;
89 	int hset_update = 1;
90 	volatile int *p = &cpup->cpu_disp->disp_nrunnable;
91 	uint_t s;
92 
93 	/*
94 	 * If this CPU is online, and there's multiple CPUs
95 	 * in the system, then we should notate our halting
96 	 * by adding ourselves to the partition's halted CPU
97 	 * bitmap. This allows other CPUs to find/awaken us when
98 	 * work becomes available.
99 	 */
100 	if (CPU->cpu_flags & CPU_OFFLINE || ncpus == 1)
101 		hset_update = 0;
102 
103 	/*
104 	 * Add ourselves to the partition's halted CPUs bitmask
105 	 * and set our HALTED flag, if necessary.
106 	 *
107 	 * When a thread becomes runnable, it is placed on the queue
108 	 * and then the halted cpuset is checked to determine who
109 	 * (if anyone) should be awoken. We therefore need to first
110 	 * add ourselves to the halted cpuset, and then check if there
111 	 * is any work available.
112 	 */
113 	if (hset_update) {
114 		cpup->cpu_disp_flags |= CPU_DISP_HALTED;
115 		membar_producer();
116 		CPUSET_ATOMIC_ADD(cp->cp_mach->mc_haltset, cpun);
117 	}
118 
119 	/*
120 	 * Check to make sure there's really nothing to do.
121 	 * Work destined for this CPU may become available after
122 	 * this check. We'll be notified through the clearing of our
123 	 * bit in the halted CPU bitmask, and a poke.
124 	 */
125 	if (disp_anywork()) {
126 		if (hset_update) {
127 			cpup->cpu_disp_flags &= ~CPU_DISP_HALTED;
128 			CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpun);
129 		}
130 		return;
131 	}
132 
133 	/*
134 	 * We're on our way to being halted.  Wait until something becomes
135 	 * runnable locally or we are awaken (i.e. removed from the halt set).
136 	 * Note that the call to hv_cpu_yield() can return even if we have
137 	 * nothing to do.
138 	 *
139 	 * Disable interrupts now, so that we'll awaken immediately
140 	 * after halting if someone tries to poke us between now and
141 	 * the time we actually halt.
142 	 *
143 	 * We check for the presence of our bit after disabling interrupts.
144 	 * If it's cleared, we'll return. If the bit is cleared after
145 	 * we check then the poke will pop us out of the halted state.
146 	 * Also, if the offlined CPU has been brought back on-line, then
147 	 * we return as well.
148 	 *
149 	 * The ordering of the poke and the clearing of the bit by cpu_wakeup
150 	 * is important.
151 	 * cpu_wakeup() must clear, then poke.
152 	 * cpu_halt() must disable interrupts, then check for the bit.
153 	 *
154 	 * The check for anything locally runnable is here for performance
155 	 * and isn't needed for correctness. disp_nrunnable ought to be
156 	 * in our cache still, so it's inexpensive to check, and if there
157 	 * is anything runnable we won't have to wait for the poke.
158 	 *
159 	 */
160 	s = disable_vec_intr();
161 	while (*p == 0 &&
162 	    ((hset_update && CPU_IN_SET(cp->cp_mach->mc_haltset, cpun)) ||
163 	    (!hset_update && (CPU->cpu_flags & CPU_OFFLINE)))) {
164 		(void) hv_cpu_yield();
165 		enable_vec_intr(s);
166 		s = disable_vec_intr();
167 	}
168 
169 	/*
170 	 * We're no longer halted
171 	 */
172 	enable_vec_intr(s);
173 	if (hset_update) {
174 		cpup->cpu_disp_flags &= ~CPU_DISP_HALTED;
175 		CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpun);
176 	}
177 }
178 
179 /*
180  * If "cpu" is halted, then wake it up clearing its halted bit in advance.
181  * Otherwise, see if other CPUs in the cpu partition are halted and need to
182  * be woken up so that they can steal the thread we placed on this CPU.
183  * This function is only used on MP systems.
184  */
185 static void
186 cpu_wakeup(cpu_t *cpu, int bound)
187 {
188 	uint_t		cpu_found;
189 	int		result;
190 	cpupart_t	*cp;
191 
192 	cp = cpu->cpu_part;
193 	if (CPU_IN_SET(cp->cp_mach->mc_haltset, cpu->cpu_id)) {
194 		/*
195 		 * Clear the halted bit for that CPU since it will be
196 		 * poked in a moment.
197 		 */
198 		CPUSET_ATOMIC_DEL(cp->cp_mach->mc_haltset, cpu->cpu_id);
199 		/*
200 		 * We may find the current CPU present in the halted cpuset
201 		 * if we're in the context of an interrupt that occurred
202 		 * before we had a chance to clear our bit in cpu_halt().
203 		 * Poking ourself is obviously unnecessary, since if
204 		 * we're here, we're not halted.
205 		 */
206 		if (cpu != CPU)
207 			poke_cpu(cpu->cpu_id);
208 		return;
209 	} else {
210 		/*
211 		 * This cpu isn't halted, but it's idle or undergoing a
212 		 * context switch. No need to awaken anyone else.
213 		 */
214 		if (cpu->cpu_thread == cpu->cpu_idle_thread ||
215 		    cpu->cpu_disp_flags & CPU_DISP_DONTSTEAL)
216 			return;
217 	}
218 
219 	/*
220 	 * No need to wake up other CPUs if the thread we just enqueued
221 	 * is bound.
222 	 */
223 	if (bound)
224 		return;
225 
226 	/*
227 	 * See if there's any other halted CPUs. If there are, then
228 	 * select one, and awaken it.
229 	 * It's possible that after we find a CPU, somebody else
230 	 * will awaken it before we get the chance.
231 	 * In that case, look again.
232 	 */
233 	do {
234 		CPUSET_FIND(cp->cp_mach->mc_haltset, cpu_found);
235 		if (cpu_found == CPUSET_NOTINSET)
236 			return;
237 
238 		ASSERT(cpu_found >= 0 && cpu_found < NCPU);
239 		CPUSET_ATOMIC_XDEL(cp->cp_mach->mc_haltset, cpu_found, result);
240 	} while (result < 0);
241 
242 	if (cpu_found != CPU->cpu_id)
243 		poke_cpu(cpu_found);
244 }
245 
246 void
247 mach_cpu_halt_idle()
248 {
249 	if (enable_halt_idle_cpus) {
250 		idle_cpu = cpu_halt;
251 		disp_enq_thread = cpu_wakeup;
252 	}
253 }
254 
255 int
256 ndata_alloc_mmfsa(struct memlist *ndata)
257 {
258 	size_t	size;
259 
260 	size = MMFSA_SIZE * max_ncpus;
261 	mmu_fault_status_area = ndata_alloc(ndata, size, ecache_alignsize);
262 	if (mmu_fault_status_area == NULL)
263 		return (-1);
264 	return (0);
265 }
266 
267 void
268 mach_memscrub(void)
269 {
270 	/* no memscrub support for sun4v for now */
271 }
272 
273 void
274 mach_fpras()
275 {
276 	/* no fpras support for sun4v for now */
277 }
278 
279 void
280 mach_hw_copy_limit(void)
281 {
282 	/* HW copy limits set by individual CPU module */
283 }
284 
285 /*
286  * We need to enable soft ring functionality on Niagara platform since
287  * one strand can't handle interrupts for a 1Gb NIC. Set the tunable
288  * ip_squeue_soft_ring by default on this platform. We can also set
289  * ip_threads_per_cpu to track number of threads per core. The variables
290  * themselves are defined in space.c and used by IP module
291  */
292 extern uint_t ip_threads_per_cpu;
293 extern boolean_t ip_squeue_soft_ring;
294 void
295 startup_platform(void)
296 {
297 	ip_squeue_soft_ring = B_TRUE;
298 }
299 
300 /*
301  * This function sets up hypervisor traptrace buffer
302  * This routine is called by the boot cpu only
303  */
304 void
305 mach_htraptrace_setup(int cpuid)
306 {
307 	TRAP_TRACE_CTL	*ctlp;
308 	int bootcpuid = getprocessorid(); /* invoked on boot cpu only */
309 
310 	if (mach_htraptrace_enable && ((cpuid != bootcpuid) ||
311 	    !htrap_tr0_inuse)) {
312 		ctlp = &trap_trace_ctl[cpuid];
313 		ctlp->d.hvaddr_base = (cpuid == bootcpuid) ? htrap_tr0 :
314 		    contig_mem_alloc_align(HTRAP_TSIZE, HTRAP_TSIZE);
315 		if (ctlp->d.hvaddr_base == NULL) {
316 			ctlp->d.hlimit = 0;
317 			ctlp->d.hpaddr_base = NULL;
318 			cmn_err(CE_WARN, "!cpu%d: failed to allocate HV "
319 			    "traptrace buffer", cpuid);
320 		} else {
321 			ctlp->d.hlimit = HTRAP_TSIZE;
322 			ctlp->d.hpaddr_base = va_to_pa(ctlp->d.hvaddr_base);
323 		}
324 	}
325 }
326 
327 /*
328  * This function enables or disables the hypervisor traptracing
329  */
330 void
331 mach_htraptrace_configure(int cpuid)
332 {
333 	uint64_t ret;
334 	uint64_t prev_buf, prev_bufsize;
335 	uint64_t prev_enable;
336 	uint64_t size;
337 	TRAP_TRACE_CTL	*ctlp;
338 
339 	ctlp = &trap_trace_ctl[cpuid];
340 	if (mach_htraptrace_enable) {
341 		if ((ctlp->d.hvaddr_base != NULL) &&
342 		    ((ctlp->d.hvaddr_base != htrap_tr0) ||
343 		    (!htrap_tr0_inuse))) {
344 			ret = hv_ttrace_buf_info(&prev_buf, &prev_bufsize);
345 			if ((ret == H_EOK) && (prev_bufsize != 0)) {
346 				cmn_err(CE_CONT,
347 				    "!cpu%d: previous HV traptrace buffer of "
348 				    "size 0x%lx at address 0x%lx", cpuid,
349 				    prev_bufsize, prev_buf);
350 			}
351 
352 			ret = hv_ttrace_buf_conf(ctlp->d.hpaddr_base,
353 			    ctlp->d.hlimit /
354 			    (sizeof (struct htrap_trace_record)), &size);
355 			if (ret == H_EOK) {
356 				ret = hv_ttrace_enable(\
357 				    (uint64_t)TRAP_TENABLE_ALL, &prev_enable);
358 				if (ret != H_EOK) {
359 					cmn_err(CE_WARN,
360 					    "!cpu%d: HV traptracing not "
361 					    "enabled, ta: 0x%x returned error: "
362 					    "%ld", cpuid, TTRACE_ENABLE, ret);
363 				} else {
364 					if (ctlp->d.hvaddr_base == htrap_tr0)
365 						htrap_tr0_inuse = 1;
366 				}
367 			} else {
368 				cmn_err(CE_WARN,
369 				    "!cpu%d: HV traptrace buffer not "
370 				    "configured, ta: 0x%x returned error: %ld",
371 				    cpuid, TTRACE_BUF_CONF, ret);
372 			}
373 			/*
374 			 * set hvaddr_base to NULL when traptrace buffer
375 			 * registration fails
376 			 */
377 			if (ret != H_EOK) {
378 				ctlp->d.hvaddr_base = NULL;
379 				ctlp->d.hlimit = 0;
380 				ctlp->d.hpaddr_base = NULL;
381 			}
382 		}
383 	} else {
384 		ret = hv_ttrace_buf_info(&prev_buf, &prev_bufsize);
385 		if ((ret == H_EOK) && (prev_bufsize != 0)) {
386 			ret = hv_ttrace_enable((uint64_t)TRAP_TDISABLE_ALL,
387 			    &prev_enable);
388 			if (ret == H_EOK) {
389 				if (ctlp->d.hvaddr_base == htrap_tr0)
390 					htrap_tr0_inuse = 0;
391 				ctlp->d.hvaddr_base = NULL;
392 				ctlp->d.hlimit = 0;
393 				ctlp->d.hpaddr_base = NULL;
394 			} else
395 				cmn_err(CE_WARN,
396 				    "!cpu%d: HV traptracing is not disabled, "
397 				    "ta: 0x%x returned error: %ld",
398 				    cpuid, TTRACE_ENABLE, ret);
399 		}
400 	}
401 }
402 
403 /*
404  * This function cleans up the hypervisor traptrace buffer
405  */
406 void
407 mach_htraptrace_cleanup(int cpuid)
408 {
409 	if (mach_htraptrace_enable) {
410 		TRAP_TRACE_CTL *ctlp;
411 		caddr_t httrace_buf_va;
412 
413 		ASSERT(cpuid < max_ncpus);
414 		ctlp = &trap_trace_ctl[cpuid];
415 		httrace_buf_va = ctlp->d.hvaddr_base;
416 		if (httrace_buf_va == htrap_tr0) {
417 			bzero(httrace_buf_va, HTRAP_TSIZE);
418 		} else if (httrace_buf_va != NULL) {
419 			contig_mem_free(httrace_buf_va, HTRAP_TSIZE);
420 		}
421 		ctlp->d.hvaddr_base = NULL;
422 		ctlp->d.hlimit = 0;
423 		ctlp->d.hpaddr_base = NULL;
424 	}
425 }
426 
427 /*
428  * Load any required machine class (sun4v) specific drivers.
429  */
430 void
431 load_mach_drivers(void)
432 {
433 	/*
434 	 * We don't want to load these LDOMs-specific
435 	 * modules if domaining is not supported.  Also,
436 	 * we must be able to run on non-LDOMs firmware.
437 	 */
438 	if (!(domaining_capabilities & DOMAINING_SUPPORTED))
439 		return;
440 
441 	/*
442 	 * Load the core domain services module
443 	 */
444 	if (modload("misc", "ds") == -1)
445 		cmn_err(CE_NOTE, "!'ds' module failed to load");
446 
447 	/*
448 	 * Load the rest of the domain services
449 	 */
450 	if (modload("misc", "fault_iso") == -1)
451 		cmn_err(CE_NOTE, "!'fault_iso' module failed to load");
452 
453 	if (modload("misc", "platsvc") == -1)
454 		cmn_err(CE_NOTE, "!'platsvc' module failed to load");
455 
456 	if ((domaining_capabilities & DOMAINING_ENABLED) &&
457 	    modload("misc", "dr_cpu") == -1)
458 		cmn_err(CE_NOTE, "!'dr_cpu' module failed to load");
459 
460 	/*
461 	 * Attempt to attach any virtual device servers. These
462 	 * drivers must be loaded at start of day so that they
463 	 * can respond to any updates to the machine description.
464 	 *
465 	 * Since it is quite likely that a domain will not support
466 	 * one or more of these servers, failures are ignored.
467 	 */
468 
469 	/* virtual disk server */
470 	(void) i_ddi_attach_hw_nodes("vds");
471 
472 	/* virtual network switch */
473 	(void) i_ddi_attach_hw_nodes("vsw");
474 
475 	/* virtual console concentrator */
476 	(void) i_ddi_attach_hw_nodes("vcc");
477 }
478