1b7f45089Sdf157793 /* 2b7f45089Sdf157793 * CDDL HEADER START 3b7f45089Sdf157793 * 4b7f45089Sdf157793 * The contents of this file are subject to the terms of the 5b7f45089Sdf157793 * Common Development and Distribution License, Version 1.0 only 6b7f45089Sdf157793 * (the "License"). You may not use this file except in compliance 7b7f45089Sdf157793 * with the License. 8b7f45089Sdf157793 * 9b7f45089Sdf157793 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10b7f45089Sdf157793 * or http://www.opensolaris.org/os/licensing. 11b7f45089Sdf157793 * See the License for the specific language governing permissions 12b7f45089Sdf157793 * and limitations under the License. 13b7f45089Sdf157793 * 14b7f45089Sdf157793 * When distributing Covered Code, include this CDDL HEADER in each 15b7f45089Sdf157793 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16b7f45089Sdf157793 * If applicable, add the following below this CDDL HEADER, with the 17b7f45089Sdf157793 * fields enclosed by brackets "[]" replaced with your own identifying 18b7f45089Sdf157793 * information: Portions Copyright [yyyy] [name of copyright owner] 19b7f45089Sdf157793 * 20b7f45089Sdf157793 * CDDL HEADER END 21b7f45089Sdf157793 */ 22b7f45089Sdf157793 23b7f45089Sdf157793 /* 24b7f45089Sdf157793 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 25b7f45089Sdf157793 * Use is subject to license terms. 26b7f45089Sdf157793 */ 27b7f45089Sdf157793 28b7f45089Sdf157793 #pragma ident "%Z%%M% %I% %E% SMI" 29b7f45089Sdf157793 30b7f45089Sdf157793 #include <sys/param.h> 31b7f45089Sdf157793 #include <sys/systm.h> 32b7f45089Sdf157793 #include <sys/sysmacros.h> 33b7f45089Sdf157793 #include <sys/sunddi.h> 34b7f45089Sdf157793 #include <sys/esunddi.h> 35b7f45089Sdf157793 #include <sys/sunndi.h> 36b7f45089Sdf157793 37b7f45089Sdf157793 #include <sys/platform_module.h> 38b7f45089Sdf157793 #include <sys/errno.h> 39b7f45089Sdf157793 #include <sys/utsname.h> 40b7f45089Sdf157793 #include <sys/modctl.h> 41b7f45089Sdf157793 #include <sys/systeminfo.h> 42b7f45089Sdf157793 #include <sys/promif.h> 43b7f45089Sdf157793 #include <sys/bootconf.h> 44b7f45089Sdf157793 45b7f45089Sdf157793 /* 46b7f45089Sdf157793 * Definitions for accessing the pci config space of the isa node 47b7f45089Sdf157793 * of Southbridge. 48b7f45089Sdf157793 */ 496acc6190Sdf157793 #define ONTARIO_ISA_PATHNAME "/pci@7c0/pci@0/pci@1/pci@0/isa@2" 506acc6190Sdf157793 #define ONTARIO_IDE_PATHNAME "/pci@7c0/pci@0/pci@1/pci@0/ide@8" 51b7f45089Sdf157793 52b7f45089Sdf157793 /* 53b7f45089Sdf157793 * Handle for isa pci space 54b7f45089Sdf157793 */ 55b7f45089Sdf157793 static ddi_acc_handle_t isa_handle; 56b7f45089Sdf157793 57b7f45089Sdf157793 /* 58b7f45089Sdf157793 * Platform power management drivers list - empty by default 59b7f45089Sdf157793 */ 60b7f45089Sdf157793 char *platform_module_list[] = { 61b7f45089Sdf157793 (char *)0 62b7f45089Sdf157793 }; 63b7f45089Sdf157793 64b7f45089Sdf157793 65b7f45089Sdf157793 /*ARGSUSED*/ 66b7f45089Sdf157793 void 67b7f45089Sdf157793 plat_tod_fault(enum tod_fault_type tod_bad) 68b7f45089Sdf157793 { 69b7f45089Sdf157793 } 70b7f45089Sdf157793 71b7f45089Sdf157793 void 72b7f45089Sdf157793 load_platform_drivers(void) 73b7f45089Sdf157793 { 74b7f45089Sdf157793 dev_info_t *dip; /* dip of the isa driver */ 75*fa9e4066Sahrens pnode_t nodeid; 76b7f45089Sdf157793 77b7f45089Sdf157793 /* 78b7f45089Sdf157793 * Install ISA driver. This is required for the southbridge IDE 79b7f45089Sdf157793 * workaround - to reset the IDE channel during IDE bus reset. 80b7f45089Sdf157793 * Panic the system in case ISA driver could not be loaded or 81b7f45089Sdf157793 * any problem in accessing its pci config space. Since the register 82b7f45089Sdf157793 * to reset the channel for IDE is in ISA config space!. 83b7f45089Sdf157793 */ 84b7f45089Sdf157793 85b7f45089Sdf157793 nodeid = prom_finddevice(ONTARIO_IDE_PATHNAME); 86b7f45089Sdf157793 if (nodeid == OBP_BADNODE) { 87b7f45089Sdf157793 return; 88b7f45089Sdf157793 } 89b7f45089Sdf157793 dip = e_ddi_hold_devi_by_path(ONTARIO_ISA_PATHNAME, 0); 90b7f45089Sdf157793 if (dip == NULL) { 91b7f45089Sdf157793 cmn_err(CE_PANIC, "Could not install the isa driver\n"); 92b7f45089Sdf157793 return; 93b7f45089Sdf157793 } 94b7f45089Sdf157793 95b7f45089Sdf157793 if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) { 96b7f45089Sdf157793 cmn_err(CE_PANIC, "Could not get the config space of isa\n"); 97b7f45089Sdf157793 return; 98b7f45089Sdf157793 } 99b7f45089Sdf157793 } 100b7f45089Sdf157793 101b7f45089Sdf157793 /* 102b7f45089Sdf157793 * This routine provides a workaround for a bug in the SB chip which 103b7f45089Sdf157793 * can cause data corruption. Will be invoked from the IDE HBA driver for 104b7f45089Sdf157793 * Acer SouthBridge at the time of IDE bus reset. 105b7f45089Sdf157793 */ 106b7f45089Sdf157793 /*ARGSUSED*/ 107b7f45089Sdf157793 int 108b7f45089Sdf157793 plat_ide_chipreset(dev_info_t *dip, int chno) 109b7f45089Sdf157793 { 110b7f45089Sdf157793 uint8_t val; 111b7f45089Sdf157793 int ret = DDI_SUCCESS; 112b7f45089Sdf157793 113b7f45089Sdf157793 if (isa_handle == NULL) { 114b7f45089Sdf157793 return (DDI_FAILURE); 115b7f45089Sdf157793 } 116b7f45089Sdf157793 117b7f45089Sdf157793 val = pci_config_get8(isa_handle, 0x58); 118b7f45089Sdf157793 /* 119b7f45089Sdf157793 * The dip passed as the argument is not used here. 120b7f45089Sdf157793 * This will be needed for platforms which have multiple on-board SB, 121b7f45089Sdf157793 * The dip passed will be used to match the corresponding ISA node. 122b7f45089Sdf157793 */ 123b7f45089Sdf157793 switch (chno) { 124b7f45089Sdf157793 case 0: 125b7f45089Sdf157793 /* 126b7f45089Sdf157793 * First disable the primary channel then re-enable it. 127b7f45089Sdf157793 * As per ALI no wait should be required in between have 128b7f45089Sdf157793 * given 1ms delay in between to be on safer side. 129b7f45089Sdf157793 * bit 2 of register 0x58 when 0 disable the channel 0. 130b7f45089Sdf157793 * bit 2 of register 0x58 when 1 enables the channel 0. 131b7f45089Sdf157793 */ 132b7f45089Sdf157793 pci_config_put8(isa_handle, 0x58, val & 0xFB); 133b7f45089Sdf157793 drv_usecwait(1000); 134b7f45089Sdf157793 pci_config_put8(isa_handle, 0x58, val); 135b7f45089Sdf157793 break; 136b7f45089Sdf157793 case 1: 137b7f45089Sdf157793 /* 138b7f45089Sdf157793 * bit 3 of register 0x58 when 0 disable the channel 1. 139b7f45089Sdf157793 * bit 3 of register 0x58 when 1 enables the channel 1. 140b7f45089Sdf157793 */ 141b7f45089Sdf157793 pci_config_put8(isa_handle, 0x58, val & 0xF7); 142b7f45089Sdf157793 drv_usecwait(1000); 143b7f45089Sdf157793 pci_config_put8(isa_handle, 0x58, val); 144b7f45089Sdf157793 break; 145b7f45089Sdf157793 default: 146b7f45089Sdf157793 /* 147b7f45089Sdf157793 * Unknown channel number passed. Return failure. 148b7f45089Sdf157793 */ 149b7f45089Sdf157793 ret = DDI_FAILURE; 150b7f45089Sdf157793 } 151b7f45089Sdf157793 152b7f45089Sdf157793 return (ret); 153b7f45089Sdf157793 } 154