1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#if !defined(lint) 28#include "assym.h" 29#endif /* !lint */ 30#include <sys/asm_linkage.h> 31#include <sys/privregs.h> 32#include <sys/sun4asi.h> 33#include <sys/machasi.h> 34#include <sys/hypervisor_api.h> 35#include <sys/machtrap.h> 36#include <sys/machthread.h> 37#include <sys/machbrand.h> 38#include <sys/pcb.h> 39#include <sys/pte.h> 40#include <sys/mmu.h> 41#include <sys/machpcb.h> 42#include <sys/async.h> 43#include <sys/intreg.h> 44#include <sys/scb.h> 45#include <sys/psr_compat.h> 46#include <sys/syscall.h> 47#include <sys/machparam.h> 48#include <sys/traptrace.h> 49#include <vm/hat_sfmmu.h> 50#include <sys/archsystm.h> 51#include <sys/utrap.h> 52#include <sys/clock.h> 53#include <sys/intr.h> 54#include <sys/fpu/fpu_simulator.h> 55#include <vm/seg_spt.h> 56 57/* 58 * WARNING: If you add a fast trap handler which can be invoked by a 59 * non-privileged user, you may have to use the FAST_TRAP_DONE macro 60 * instead of "done" instruction to return back to the user mode. See 61 * comments for the "fast_trap_done" entry point for more information. 62 * 63 * An alternate FAST_TRAP_DONE_CHK_INTR macro should be used for the 64 * cases where you always want to process any pending interrupts before 65 * returning back to the user mode. 66 */ 67#define FAST_TRAP_DONE \ 68 ba,a fast_trap_done 69 70#define FAST_TRAP_DONE_CHK_INTR \ 71 ba,a fast_trap_done_chk_intr 72 73/* 74 * SPARC V9 Trap Table 75 * 76 * Most of the trap handlers are made from common building 77 * blocks, and some are instantiated multiple times within 78 * the trap table. So, I build a bunch of macros, then 79 * populate the table using only the macros. 80 * 81 * Many macros branch to sys_trap. Its calling convention is: 82 * %g1 kernel trap handler 83 * %g2, %g3 args for above 84 * %g4 desire %pil 85 */ 86 87#ifdef TRAPTRACE 88 89/* 90 * Tracing macro. Adds two instructions if TRAPTRACE is defined. 91 */ 92#define TT_TRACE(label) \ 93 ba label ;\ 94 rd %pc, %g7 95#define TT_TRACE_INS 2 96 97#define TT_TRACE_L(label) \ 98 ba label ;\ 99 rd %pc, %l4 ;\ 100 clr %l4 101#define TT_TRACE_L_INS 3 102 103#else 104 105#define TT_TRACE(label) 106#define TT_TRACE_INS 0 107 108#define TT_TRACE_L(label) 109#define TT_TRACE_L_INS 0 110 111#endif 112 113/* 114 * This first set are funneled to trap() with %tt as the type. 115 * Trap will then either panic or send the user a signal. 116 */ 117/* 118 * NOT is used for traps that just shouldn't happen. 119 * It comes in both single and quadruple flavors. 120 */ 121#if !defined(lint) 122 .global trap 123#endif /* !lint */ 124#define NOT \ 125 TT_TRACE(trace_gen) ;\ 126 set trap, %g1 ;\ 127 rdpr %tt, %g3 ;\ 128 ba,pt %xcc, sys_trap ;\ 129 sub %g0, 1, %g4 ;\ 130 .align 32 131#define NOT4 NOT; NOT; NOT; NOT 132 133#define NOTP \ 134 TT_TRACE(trace_gen) ;\ 135 ba,pt %xcc, ptl1_panic ;\ 136 mov PTL1_BAD_TRAP, %g1 ;\ 137 .align 32 138#define NOTP4 NOTP; NOTP; NOTP; NOTP 139 140 141/* 142 * BAD is used for trap vectors we don't have a kernel 143 * handler for. 144 * It also comes in single and quadruple versions. 145 */ 146#define BAD NOT 147#define BAD4 NOT4 148 149#define DONE \ 150 done; \ 151 .align 32 152 153/* 154 * TRAP vectors to the trap() function. 155 * It's main use is for user errors. 156 */ 157#if !defined(lint) 158 .global trap 159#endif /* !lint */ 160#define TRAP(arg) \ 161 TT_TRACE(trace_gen) ;\ 162 set trap, %g1 ;\ 163 mov arg, %g3 ;\ 164 ba,pt %xcc, sys_trap ;\ 165 sub %g0, 1, %g4 ;\ 166 .align 32 167 168/* 169 * SYSCALL is used for unsupported syscall interfaces (with 'which' 170 * set to 'nosys') and legacy support of old SunOS 4.x syscalls (with 171 * 'which' set to 'syscall_trap32'). 172 * 173 * The SYSCALL_TRAP* macros are used for syscall entry points. 174 * SYSCALL_TRAP is used to support LP64 syscalls and SYSCALL_TRAP32 175 * is used to support ILP32. Each macro can only be used once 176 * since they each define a symbol. The symbols are used as hot patch 177 * points by the brand infrastructure to dynamically enable and disable 178 * brand syscall interposition. See the comments around BRAND_CALLBACK 179 * and brand_plat_interposition_enable() for more information. 180 */ 181#define SYSCALL_NOTT(which) \ 182 set (which), %g1 ;\ 183 ba,pt %xcc, user_trap ;\ 184 sub %g0, 1, %g4 ;\ 185 .align 32 186 187#define SYSCALL(which) \ 188 TT_TRACE(trace_gen) ;\ 189 SYSCALL_NOTT(which) 190 191#define SYSCALL_TRAP32 \ 192 TT_TRACE(trace_gen) ;\ 193 ALTENTRY(syscall_trap32_patch_point) \ 194 SYSCALL_NOTT(syscall_trap32) 195 196#define SYSCALL_TRAP \ 197 TT_TRACE(trace_gen) ;\ 198 ALTENTRY(syscall_trap_patch_point) \ 199 SYSCALL_NOTT(syscall_trap) 200 201/* 202 * GOTO just jumps to a label. 203 * It's used for things that can be fixed without going thru sys_trap. 204 */ 205#define GOTO(label) \ 206 .global label ;\ 207 ba,a label ;\ 208 .empty ;\ 209 .align 32 210 211/* 212 * GOTO_TT just jumps to a label. 213 * correctable ECC error traps at level 0 and 1 will use this macro. 214 * It's used for things that can be fixed without going thru sys_trap. 215 */ 216#define GOTO_TT(label, ttlabel) \ 217 .global label ;\ 218 TT_TRACE(ttlabel) ;\ 219 ba,a label ;\ 220 .empty ;\ 221 .align 32 222 223/* 224 * Privileged traps 225 * Takes breakpoint if privileged, calls trap() if not. 226 */ 227#define PRIV(label) \ 228 rdpr %tstate, %g1 ;\ 229 btst TSTATE_PRIV, %g1 ;\ 230 bnz label ;\ 231 rdpr %tt, %g3 ;\ 232 set trap, %g1 ;\ 233 ba,pt %xcc, sys_trap ;\ 234 sub %g0, 1, %g4 ;\ 235 .align 32 236 237 238/* 239 * DTrace traps. 240 */ 241#define DTRACE_PID \ 242 .global dtrace_pid_probe ;\ 243 set dtrace_pid_probe, %g1 ;\ 244 ba,pt %xcc, user_trap ;\ 245 sub %g0, 1, %g4 ;\ 246 .align 32 247 248#define DTRACE_RETURN \ 249 .global dtrace_return_probe ;\ 250 set dtrace_return_probe, %g1 ;\ 251 ba,pt %xcc, user_trap ;\ 252 sub %g0, 1, %g4 ;\ 253 .align 32 254 255/* 256 * REGISTER WINDOW MANAGEMENT MACROS 257 */ 258 259/* 260 * various convenient units of padding 261 */ 262#define SKIP(n) .skip 4*(n) 263 264/* 265 * CLEAN_WINDOW is the simple handler for cleaning a register window. 266 */ 267#define CLEAN_WINDOW \ 268 TT_TRACE_L(trace_win) ;\ 269 rdpr %cleanwin, %l0; inc %l0; wrpr %l0, %cleanwin ;\ 270 clr %l0; clr %l1; clr %l2; clr %l3 ;\ 271 clr %l4; clr %l5; clr %l6; clr %l7 ;\ 272 clr %o0; clr %o1; clr %o2; clr %o3 ;\ 273 clr %o4; clr %o5; clr %o6; clr %o7 ;\ 274 retry; .align 128 275 276#if !defined(lint) 277 278/* 279 * If we get an unresolved tlb miss while in a window handler, the fault 280 * handler will resume execution at the last instruction of the window 281 * hander, instead of delivering the fault to the kernel. Spill handlers 282 * use this to spill windows into the wbuf. 283 * 284 * The mixed handler works by checking %sp, and branching to the correct 285 * handler. This is done by branching back to label 1: for 32b frames, 286 * or label 2: for 64b frames; which implies the handler order is: 32b, 287 * 64b, mixed. The 1: and 2: labels are offset into the routines to 288 * allow the branchs' delay slots to contain useful instructions. 289 */ 290 291/* 292 * SPILL_32bit spills a 32-bit-wide kernel register window. It 293 * assumes that the kernel context and the nucleus context are the 294 * same. The stack pointer is required to be eight-byte aligned even 295 * though this code only needs it to be four-byte aligned. 296 */ 297#define SPILL_32bit(tail) \ 298 srl %sp, 0, %sp ;\ 2991: st %l0, [%sp + 0] ;\ 300 st %l1, [%sp + 4] ;\ 301 st %l2, [%sp + 8] ;\ 302 st %l3, [%sp + 12] ;\ 303 st %l4, [%sp + 16] ;\ 304 st %l5, [%sp + 20] ;\ 305 st %l6, [%sp + 24] ;\ 306 st %l7, [%sp + 28] ;\ 307 st %i0, [%sp + 32] ;\ 308 st %i1, [%sp + 36] ;\ 309 st %i2, [%sp + 40] ;\ 310 st %i3, [%sp + 44] ;\ 311 st %i4, [%sp + 48] ;\ 312 st %i5, [%sp + 52] ;\ 313 st %i6, [%sp + 56] ;\ 314 st %i7, [%sp + 60] ;\ 315 TT_TRACE_L(trace_win) ;\ 316 saved ;\ 317 retry ;\ 318 SKIP(31-19-TT_TRACE_L_INS) ;\ 319 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 320 .empty 321 322/* 323 * SPILL_32bit_asi spills a 32-bit-wide register window into a 32-bit 324 * wide address space via the designated asi. It is used to spill 325 * non-kernel windows. The stack pointer is required to be eight-byte 326 * aligned even though this code only needs it to be four-byte 327 * aligned. 328 */ 329#define SPILL_32bit_asi(asi_num, tail) \ 330 srl %sp, 0, %sp ;\ 3311: sta %l0, [%sp + %g0]asi_num ;\ 332 mov 4, %g1 ;\ 333 sta %l1, [%sp + %g1]asi_num ;\ 334 mov 8, %g2 ;\ 335 sta %l2, [%sp + %g2]asi_num ;\ 336 mov 12, %g3 ;\ 337 sta %l3, [%sp + %g3]asi_num ;\ 338 add %sp, 16, %g4 ;\ 339 sta %l4, [%g4 + %g0]asi_num ;\ 340 sta %l5, [%g4 + %g1]asi_num ;\ 341 sta %l6, [%g4 + %g2]asi_num ;\ 342 sta %l7, [%g4 + %g3]asi_num ;\ 343 add %g4, 16, %g4 ;\ 344 sta %i0, [%g4 + %g0]asi_num ;\ 345 sta %i1, [%g4 + %g1]asi_num ;\ 346 sta %i2, [%g4 + %g2]asi_num ;\ 347 sta %i3, [%g4 + %g3]asi_num ;\ 348 add %g4, 16, %g4 ;\ 349 sta %i4, [%g4 + %g0]asi_num ;\ 350 sta %i5, [%g4 + %g1]asi_num ;\ 351 sta %i6, [%g4 + %g2]asi_num ;\ 352 sta %i7, [%g4 + %g3]asi_num ;\ 353 TT_TRACE_L(trace_win) ;\ 354 saved ;\ 355 retry ;\ 356 SKIP(31-25-TT_TRACE_L_INS) ;\ 357 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 358 .empty 359 360#define SPILL_32bit_tt1(asi_num, tail) \ 361 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 362 .empty ;\ 363 .align 128 364 365 366/* 367 * FILL_32bit fills a 32-bit-wide kernel register window. It assumes 368 * that the kernel context and the nucleus context are the same. The 369 * stack pointer is required to be eight-byte aligned even though this 370 * code only needs it to be four-byte aligned. 371 */ 372#define FILL_32bit(tail) \ 373 srl %sp, 0, %sp ;\ 3741: TT_TRACE_L(trace_win) ;\ 375 ld [%sp + 0], %l0 ;\ 376 ld [%sp + 4], %l1 ;\ 377 ld [%sp + 8], %l2 ;\ 378 ld [%sp + 12], %l3 ;\ 379 ld [%sp + 16], %l4 ;\ 380 ld [%sp + 20], %l5 ;\ 381 ld [%sp + 24], %l6 ;\ 382 ld [%sp + 28], %l7 ;\ 383 ld [%sp + 32], %i0 ;\ 384 ld [%sp + 36], %i1 ;\ 385 ld [%sp + 40], %i2 ;\ 386 ld [%sp + 44], %i3 ;\ 387 ld [%sp + 48], %i4 ;\ 388 ld [%sp + 52], %i5 ;\ 389 ld [%sp + 56], %i6 ;\ 390 ld [%sp + 60], %i7 ;\ 391 restored ;\ 392 retry ;\ 393 SKIP(31-19-TT_TRACE_L_INS) ;\ 394 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 395 .empty 396 397/* 398 * FILL_32bit_asi fills a 32-bit-wide register window from a 32-bit 399 * wide address space via the designated asi. It is used to fill 400 * non-kernel windows. The stack pointer is required to be eight-byte 401 * aligned even though this code only needs it to be four-byte 402 * aligned. 403 */ 404#define FILL_32bit_asi(asi_num, tail) \ 405 srl %sp, 0, %sp ;\ 4061: TT_TRACE_L(trace_win) ;\ 407 mov 4, %g1 ;\ 408 lda [%sp + %g0]asi_num, %l0 ;\ 409 mov 8, %g2 ;\ 410 lda [%sp + %g1]asi_num, %l1 ;\ 411 mov 12, %g3 ;\ 412 lda [%sp + %g2]asi_num, %l2 ;\ 413 lda [%sp + %g3]asi_num, %l3 ;\ 414 add %sp, 16, %g4 ;\ 415 lda [%g4 + %g0]asi_num, %l4 ;\ 416 lda [%g4 + %g1]asi_num, %l5 ;\ 417 lda [%g4 + %g2]asi_num, %l6 ;\ 418 lda [%g4 + %g3]asi_num, %l7 ;\ 419 add %g4, 16, %g4 ;\ 420 lda [%g4 + %g0]asi_num, %i0 ;\ 421 lda [%g4 + %g1]asi_num, %i1 ;\ 422 lda [%g4 + %g2]asi_num, %i2 ;\ 423 lda [%g4 + %g3]asi_num, %i3 ;\ 424 add %g4, 16, %g4 ;\ 425 lda [%g4 + %g0]asi_num, %i4 ;\ 426 lda [%g4 + %g1]asi_num, %i5 ;\ 427 lda [%g4 + %g2]asi_num, %i6 ;\ 428 lda [%g4 + %g3]asi_num, %i7 ;\ 429 restored ;\ 430 retry ;\ 431 SKIP(31-25-TT_TRACE_L_INS) ;\ 432 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 433 .empty 434 435 436/* 437 * SPILL_64bit spills a 64-bit-wide kernel register window. It 438 * assumes that the kernel context and the nucleus context are the 439 * same. The stack pointer is required to be eight-byte aligned. 440 */ 441#define SPILL_64bit(tail) \ 4422: stx %l0, [%sp + V9BIAS64 + 0] ;\ 443 stx %l1, [%sp + V9BIAS64 + 8] ;\ 444 stx %l2, [%sp + V9BIAS64 + 16] ;\ 445 stx %l3, [%sp + V9BIAS64 + 24] ;\ 446 stx %l4, [%sp + V9BIAS64 + 32] ;\ 447 stx %l5, [%sp + V9BIAS64 + 40] ;\ 448 stx %l6, [%sp + V9BIAS64 + 48] ;\ 449 stx %l7, [%sp + V9BIAS64 + 56] ;\ 450 stx %i0, [%sp + V9BIAS64 + 64] ;\ 451 stx %i1, [%sp + V9BIAS64 + 72] ;\ 452 stx %i2, [%sp + V9BIAS64 + 80] ;\ 453 stx %i3, [%sp + V9BIAS64 + 88] ;\ 454 stx %i4, [%sp + V9BIAS64 + 96] ;\ 455 stx %i5, [%sp + V9BIAS64 + 104] ;\ 456 stx %i6, [%sp + V9BIAS64 + 112] ;\ 457 stx %i7, [%sp + V9BIAS64 + 120] ;\ 458 TT_TRACE_L(trace_win) ;\ 459 saved ;\ 460 retry ;\ 461 SKIP(31-18-TT_TRACE_L_INS) ;\ 462 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 463 .empty 464 465#define SPILL_64bit_ktt1(tail) \ 466 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 467 .empty ;\ 468 .align 128 469 470#define SPILL_mixed_ktt1(tail) \ 471 btst 1, %sp ;\ 472 bz,a,pt %xcc, fault_32bit_/**/tail ;\ 473 srl %sp, 0, %sp ;\ 474 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 475 .empty ;\ 476 .align 128 477 478/* 479 * SPILL_64bit_asi spills a 64-bit-wide register window into a 64-bit 480 * wide address space via the designated asi. It is used to spill 481 * non-kernel windows. The stack pointer is required to be eight-byte 482 * aligned. 483 */ 484#define SPILL_64bit_asi(asi_num, tail) \ 485 mov 0 + V9BIAS64, %g1 ;\ 4862: stxa %l0, [%sp + %g1]asi_num ;\ 487 mov 8 + V9BIAS64, %g2 ;\ 488 stxa %l1, [%sp + %g2]asi_num ;\ 489 mov 16 + V9BIAS64, %g3 ;\ 490 stxa %l2, [%sp + %g3]asi_num ;\ 491 mov 24 + V9BIAS64, %g4 ;\ 492 stxa %l3, [%sp + %g4]asi_num ;\ 493 add %sp, 32, %g5 ;\ 494 stxa %l4, [%g5 + %g1]asi_num ;\ 495 stxa %l5, [%g5 + %g2]asi_num ;\ 496 stxa %l6, [%g5 + %g3]asi_num ;\ 497 stxa %l7, [%g5 + %g4]asi_num ;\ 498 add %g5, 32, %g5 ;\ 499 stxa %i0, [%g5 + %g1]asi_num ;\ 500 stxa %i1, [%g5 + %g2]asi_num ;\ 501 stxa %i2, [%g5 + %g3]asi_num ;\ 502 stxa %i3, [%g5 + %g4]asi_num ;\ 503 add %g5, 32, %g5 ;\ 504 stxa %i4, [%g5 + %g1]asi_num ;\ 505 stxa %i5, [%g5 + %g2]asi_num ;\ 506 stxa %i6, [%g5 + %g3]asi_num ;\ 507 stxa %i7, [%g5 + %g4]asi_num ;\ 508 TT_TRACE_L(trace_win) ;\ 509 saved ;\ 510 retry ;\ 511 SKIP(31-25-TT_TRACE_L_INS) ;\ 512 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 513 .empty 514 515#define SPILL_64bit_tt1(asi_num, tail) \ 516 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 517 .empty ;\ 518 .align 128 519 520/* 521 * FILL_64bit fills a 64-bit-wide kernel register window. It assumes 522 * that the kernel context and the nucleus context are the same. The 523 * stack pointer is required to be eight-byte aligned. 524 */ 525#define FILL_64bit(tail) \ 5262: TT_TRACE_L(trace_win) ;\ 527 ldx [%sp + V9BIAS64 + 0], %l0 ;\ 528 ldx [%sp + V9BIAS64 + 8], %l1 ;\ 529 ldx [%sp + V9BIAS64 + 16], %l2 ;\ 530 ldx [%sp + V9BIAS64 + 24], %l3 ;\ 531 ldx [%sp + V9BIAS64 + 32], %l4 ;\ 532 ldx [%sp + V9BIAS64 + 40], %l5 ;\ 533 ldx [%sp + V9BIAS64 + 48], %l6 ;\ 534 ldx [%sp + V9BIAS64 + 56], %l7 ;\ 535 ldx [%sp + V9BIAS64 + 64], %i0 ;\ 536 ldx [%sp + V9BIAS64 + 72], %i1 ;\ 537 ldx [%sp + V9BIAS64 + 80], %i2 ;\ 538 ldx [%sp + V9BIAS64 + 88], %i3 ;\ 539 ldx [%sp + V9BIAS64 + 96], %i4 ;\ 540 ldx [%sp + V9BIAS64 + 104], %i5 ;\ 541 ldx [%sp + V9BIAS64 + 112], %i6 ;\ 542 ldx [%sp + V9BIAS64 + 120], %i7 ;\ 543 restored ;\ 544 retry ;\ 545 SKIP(31-18-TT_TRACE_L_INS) ;\ 546 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 547 .empty 548 549/* 550 * FILL_64bit_asi fills a 64-bit-wide register window from a 64-bit 551 * wide address space via the designated asi. It is used to fill 552 * non-kernel windows. The stack pointer is required to be eight-byte 553 * aligned. 554 */ 555#define FILL_64bit_asi(asi_num, tail) \ 556 mov V9BIAS64 + 0, %g1 ;\ 5572: TT_TRACE_L(trace_win) ;\ 558 ldxa [%sp + %g1]asi_num, %l0 ;\ 559 mov V9BIAS64 + 8, %g2 ;\ 560 ldxa [%sp + %g2]asi_num, %l1 ;\ 561 mov V9BIAS64 + 16, %g3 ;\ 562 ldxa [%sp + %g3]asi_num, %l2 ;\ 563 mov V9BIAS64 + 24, %g4 ;\ 564 ldxa [%sp + %g4]asi_num, %l3 ;\ 565 add %sp, 32, %g5 ;\ 566 ldxa [%g5 + %g1]asi_num, %l4 ;\ 567 ldxa [%g5 + %g2]asi_num, %l5 ;\ 568 ldxa [%g5 + %g3]asi_num, %l6 ;\ 569 ldxa [%g5 + %g4]asi_num, %l7 ;\ 570 add %g5, 32, %g5 ;\ 571 ldxa [%g5 + %g1]asi_num, %i0 ;\ 572 ldxa [%g5 + %g2]asi_num, %i1 ;\ 573 ldxa [%g5 + %g3]asi_num, %i2 ;\ 574 ldxa [%g5 + %g4]asi_num, %i3 ;\ 575 add %g5, 32, %g5 ;\ 576 ldxa [%g5 + %g1]asi_num, %i4 ;\ 577 ldxa [%g5 + %g2]asi_num, %i5 ;\ 578 ldxa [%g5 + %g3]asi_num, %i6 ;\ 579 ldxa [%g5 + %g4]asi_num, %i7 ;\ 580 restored ;\ 581 retry ;\ 582 SKIP(31-25-TT_TRACE_L_INS) ;\ 583 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 584 .empty 585 586 587#endif /* !lint */ 588 589/* 590 * SPILL_mixed spills either size window, depending on 591 * whether %sp is even or odd, to a 32-bit address space. 592 * This may only be used in conjunction with SPILL_32bit/ 593 * FILL_64bit. 594 * Clear upper 32 bits of %sp if it is odd. 595 * We won't need to clear them in 64 bit kernel. 596 */ 597#define SPILL_mixed \ 598 btst 1, %sp ;\ 599 bz,a,pt %xcc, 1b ;\ 600 srl %sp, 0, %sp ;\ 601 ba,pt %xcc, 2b ;\ 602 nop ;\ 603 .align 128 604 605/* 606 * FILL_mixed(ASI) fills either size window, depending on 607 * whether %sp is even or odd, from a 32-bit address space. 608 * This may only be used in conjunction with FILL_32bit/ 609 * FILL_64bit. New versions of FILL_mixed_{tt1,asi} would be 610 * needed for use with FILL_{32,64}bit_{tt1,asi}. Particular 611 * attention should be paid to the instructions that belong 612 * in the delay slots of the branches depending on the type 613 * of fill handler being branched to. 614 * Clear upper 32 bits of %sp if it is odd. 615 * We won't need to clear them in 64 bit kernel. 616 */ 617#define FILL_mixed \ 618 btst 1, %sp ;\ 619 bz,a,pt %xcc, 1b ;\ 620 srl %sp, 0, %sp ;\ 621 ba,pt %xcc, 2b ;\ 622 nop ;\ 623 .align 128 624 625 626/* 627 * SPILL_32clean/SPILL_64clean spill 32-bit and 64-bit register windows, 628 * respectively, into the address space via the designated asi. The 629 * unbiased stack pointer is required to be eight-byte aligned (even for 630 * the 32-bit case even though this code does not require such strict 631 * alignment). 632 * 633 * With SPARC v9 the spill trap takes precedence over the cleanwin trap 634 * so when cansave == 0, canrestore == 6, and cleanwin == 6 the next save 635 * will cause cwp + 2 to be spilled but will not clean cwp + 1. That 636 * window may contain kernel data so in user_rtt we set wstate to call 637 * these spill handlers on the first user spill trap. These handler then 638 * spill the appropriate window but also back up a window and clean the 639 * window that didn't get a cleanwin trap. 640 */ 641#define SPILL_32clean(asi_num, tail) \ 642 srl %sp, 0, %sp ;\ 643 sta %l0, [%sp + %g0]asi_num ;\ 644 mov 4, %g1 ;\ 645 sta %l1, [%sp + %g1]asi_num ;\ 646 mov 8, %g2 ;\ 647 sta %l2, [%sp + %g2]asi_num ;\ 648 mov 12, %g3 ;\ 649 sta %l3, [%sp + %g3]asi_num ;\ 650 add %sp, 16, %g4 ;\ 651 sta %l4, [%g4 + %g0]asi_num ;\ 652 sta %l5, [%g4 + %g1]asi_num ;\ 653 sta %l6, [%g4 + %g2]asi_num ;\ 654 sta %l7, [%g4 + %g3]asi_num ;\ 655 add %g4, 16, %g4 ;\ 656 sta %i0, [%g4 + %g0]asi_num ;\ 657 sta %i1, [%g4 + %g1]asi_num ;\ 658 sta %i2, [%g4 + %g2]asi_num ;\ 659 sta %i3, [%g4 + %g3]asi_num ;\ 660 add %g4, 16, %g4 ;\ 661 sta %i4, [%g4 + %g0]asi_num ;\ 662 sta %i5, [%g4 + %g1]asi_num ;\ 663 sta %i6, [%g4 + %g2]asi_num ;\ 664 sta %i7, [%g4 + %g3]asi_num ;\ 665 TT_TRACE_L(trace_win) ;\ 666 b .spill_clean ;\ 667 mov WSTATE_USER32, %g7 ;\ 668 SKIP(31-25-TT_TRACE_L_INS) ;\ 669 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 670 .empty 671 672#define SPILL_64clean(asi_num, tail) \ 673 mov 0 + V9BIAS64, %g1 ;\ 674 stxa %l0, [%sp + %g1]asi_num ;\ 675 mov 8 + V9BIAS64, %g2 ;\ 676 stxa %l1, [%sp + %g2]asi_num ;\ 677 mov 16 + V9BIAS64, %g3 ;\ 678 stxa %l2, [%sp + %g3]asi_num ;\ 679 mov 24 + V9BIAS64, %g4 ;\ 680 stxa %l3, [%sp + %g4]asi_num ;\ 681 add %sp, 32, %g5 ;\ 682 stxa %l4, [%g5 + %g1]asi_num ;\ 683 stxa %l5, [%g5 + %g2]asi_num ;\ 684 stxa %l6, [%g5 + %g3]asi_num ;\ 685 stxa %l7, [%g5 + %g4]asi_num ;\ 686 add %g5, 32, %g5 ;\ 687 stxa %i0, [%g5 + %g1]asi_num ;\ 688 stxa %i1, [%g5 + %g2]asi_num ;\ 689 stxa %i2, [%g5 + %g3]asi_num ;\ 690 stxa %i3, [%g5 + %g4]asi_num ;\ 691 add %g5, 32, %g5 ;\ 692 stxa %i4, [%g5 + %g1]asi_num ;\ 693 stxa %i5, [%g5 + %g2]asi_num ;\ 694 stxa %i6, [%g5 + %g3]asi_num ;\ 695 stxa %i7, [%g5 + %g4]asi_num ;\ 696 TT_TRACE_L(trace_win) ;\ 697 b .spill_clean ;\ 698 mov WSTATE_USER64, %g7 ;\ 699 SKIP(31-25-TT_TRACE_L_INS) ;\ 700 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 701 .empty 702 703 704/* 705 * Floating point disabled. 706 */ 707#define FP_DISABLED_TRAP \ 708 TT_TRACE(trace_gen) ;\ 709 ba,pt %xcc,.fp_disabled ;\ 710 nop ;\ 711 .align 32 712 713/* 714 * Floating point exceptions. 715 */ 716#define FP_IEEE_TRAP \ 717 TT_TRACE(trace_gen) ;\ 718 ba,pt %xcc,.fp_ieee_exception ;\ 719 nop ;\ 720 .align 32 721 722#define FP_TRAP \ 723 TT_TRACE(trace_gen) ;\ 724 ba,pt %xcc,.fp_exception ;\ 725 nop ;\ 726 .align 32 727 728#if !defined(lint) 729 730/* 731 * ECACHE_ECC error traps at level 0 and level 1 732 */ 733#define ECACHE_ECC(table_name) \ 734 .global table_name ;\ 735table_name: ;\ 736 membar #Sync ;\ 737 set trap, %g1 ;\ 738 rdpr %tt, %g3 ;\ 739 ba,pt %xcc, sys_trap ;\ 740 sub %g0, 1, %g4 ;\ 741 .align 32 742 743#endif /* !lint */ 744 745/* 746 * illegal instruction trap 747 */ 748#define ILLTRAP_INSTR \ 749 membar #Sync ;\ 750 TT_TRACE(trace_gen) ;\ 751 or %g0, P_UTRAP4, %g2 ;\ 752 or %g0, T_UNIMP_INSTR, %g3 ;\ 753 sethi %hi(.check_v9utrap), %g4 ;\ 754 jmp %g4 + %lo(.check_v9utrap) ;\ 755 nop ;\ 756 .align 32 757 758/* 759 * tag overflow trap 760 */ 761#define TAG_OVERFLOW \ 762 TT_TRACE(trace_gen) ;\ 763 or %g0, P_UTRAP10, %g2 ;\ 764 or %g0, T_TAG_OVERFLOW, %g3 ;\ 765 sethi %hi(.check_v9utrap), %g4 ;\ 766 jmp %g4 + %lo(.check_v9utrap) ;\ 767 nop ;\ 768 .align 32 769 770/* 771 * divide by zero trap 772 */ 773#define DIV_BY_ZERO \ 774 TT_TRACE(trace_gen) ;\ 775 or %g0, P_UTRAP11, %g2 ;\ 776 or %g0, T_IDIV0, %g3 ;\ 777 sethi %hi(.check_v9utrap), %g4 ;\ 778 jmp %g4 + %lo(.check_v9utrap) ;\ 779 nop ;\ 780 .align 32 781 782/* 783 * trap instruction for V9 user trap handlers 784 */ 785#define TRAP_INSTR \ 786 TT_TRACE(trace_gen) ;\ 787 or %g0, T_SOFTWARE_TRAP, %g3 ;\ 788 sethi %hi(.check_v9utrap), %g4 ;\ 789 jmp %g4 + %lo(.check_v9utrap) ;\ 790 nop ;\ 791 .align 32 792#define TRP4 TRAP_INSTR; TRAP_INSTR; TRAP_INSTR; TRAP_INSTR 793 794/* 795 * LEVEL_INTERRUPT is for level N interrupts. 796 * VECTOR_INTERRUPT is for the vector trap. 797 */ 798#define LEVEL_INTERRUPT(level) \ 799 .global tt_pil/**/level ;\ 800tt_pil/**/level: ;\ 801 ba,pt %xcc, pil_interrupt ;\ 802 mov level, %g4 ;\ 803 .align 32 804 805#define LEVEL14_INTERRUPT \ 806 ba pil14_interrupt ;\ 807 mov PIL_14, %g4 ;\ 808 .align 32 809 810#define CPU_MONDO \ 811 ba,a,pt %xcc, cpu_mondo ;\ 812 .align 32 813 814#define DEV_MONDO \ 815 ba,a,pt %xcc, dev_mondo ;\ 816 .align 32 817 818/* 819 * We take over the rtba after we set our trap table and 820 * fault status area. The watchdog reset trap is now handled by the OS. 821 */ 822#define WATCHDOG_RESET \ 823 mov PTL1_BAD_WATCHDOG, %g1 ;\ 824 ba,a,pt %xcc, .watchdog_trap ;\ 825 .align 32 826 827/* 828 * RED is for traps that use the red mode handler. 829 * We should never see these either. 830 */ 831#define RED \ 832 mov PTL1_BAD_RED, %g1 ;\ 833 ba,a,pt %xcc, .watchdog_trap ;\ 834 .align 32 835 836 837/* 838 * MMU Trap Handlers. 839 */ 840 841/* 842 * synthesize for trap(): SFSR in %g3 843 */ 844#define IMMU_EXCEPTION \ 845 MMU_FAULT_STATUS_AREA(%g3) ;\ 846 rdpr %tpc, %g2 ;\ 847 ldx [%g3 + MMFSA_I_TYPE], %g1 ;\ 848 ldx [%g3 + MMFSA_I_CTX], %g3 ;\ 849 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 850 or %g3, %g1, %g3 ;\ 851 ba,pt %xcc, .mmu_exception_end ;\ 852 mov T_INSTR_EXCEPTION, %g1 ;\ 853 .align 32 854 855/* 856 * synthesize for trap(): TAG_ACCESS in %g2, SFSR in %g3 857 */ 858#define DMMU_EXCEPTION \ 859 ba,a,pt %xcc, .dmmu_exception ;\ 860 .align 32 861 862/* 863 * synthesize for trap(): SFAR in %g2, SFSR in %g3 864 */ 865#define DMMU_EXC_AG_PRIV \ 866 MMU_FAULT_STATUS_AREA(%g3) ;\ 867 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 868 /* Fault type not available in MMU fault status area */ ;\ 869 mov MMFSA_F_PRVACT, %g1 ;\ 870 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 871 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 872 ba,pt %xcc, .mmu_priv_exception ;\ 873 or %g3, %g1, %g3 ;\ 874 .align 32 875 876/* 877 * synthesize for trap(): SFAR in %g2, SFSR in %g3 878 */ 879#define DMMU_EXC_AG_NOT_ALIGNED \ 880 MMU_FAULT_STATUS_AREA(%g3) ;\ 881 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 882 /* Fault type not available in MMU fault status area */ ;\ 883 mov MMFSA_F_UNALIGN, %g1 ;\ 884 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 885 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 886 ba,pt %xcc, .mmu_exception_not_aligned ;\ 887 or %g3, %g1, %g3 /* SFSR */ ;\ 888 .align 32 889/* 890 * SPARC V9 IMPL. DEP. #109(1) and (2) and #110(1) and (2) 891 */ 892 893/* 894 * synthesize for trap(): SFAR in %g2, SFSR in %g3 895 */ 896#define DMMU_EXC_LDDF_NOT_ALIGNED \ 897 ba,a,pt %xcc, .dmmu_exc_lddf_not_aligned ;\ 898 .align 32 899/* 900 * synthesize for trap(): SFAR in %g2, SFSR in %g3 901 */ 902#define DMMU_EXC_STDF_NOT_ALIGNED \ 903 ba,a,pt %xcc, .dmmu_exc_stdf_not_aligned ;\ 904 .align 32 905 906#if defined(cscope) 907/* 908 * Define labels to direct cscope quickly to labels that 909 * are generated by macro expansion of DTLB_MISS(). 910 */ 911 .global tt0_dtlbmiss 912tt0_dtlbmiss: 913 .global tt1_dtlbmiss 914tt1_dtlbmiss: 915 nop 916#endif 917 918/* 919 * Data miss handler (must be exactly 32 instructions) 920 * 921 * This handler is invoked only if the hypervisor has been instructed 922 * not to do any TSB walk. 923 * 924 * Kernel and invalid context cases are handled by the sfmmu_kdtlb_miss 925 * handler. 926 * 927 * User TLB miss handling depends upon whether a user process has one or 928 * two TSBs. User TSB information (physical base and size code) is kept 929 * in two dedicated scratchpad registers. Absence of a user TSB (primarily 930 * second TSB) is indicated by a negative value (-1) in that register. 931 */ 932 933/* 934 * synthesize for miss handler: pseudo-tag access in %g2 (with context "type" 935 * (0=kernel, 1=invalid, or 2=user) rather than context ID) 936 */ 937#define DTLB_MISS(table_name) ;\ 938 .global table_name/**/_dtlbmiss ;\ 939table_name/**/_dtlbmiss: ;\ 940 GET_MMU_D_PTAGACC_CTXTYPE(%g2, %g3) /* 8 instr */ ;\ 941 cmp %g3, INVALID_CONTEXT ;\ 942 ble,pn %xcc, sfmmu_kdtlb_miss ;\ 943 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 944 mov SCRATCHPAD_UTSBREG2, %g1 ;\ 945 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\ 946 brgez,pn %g1, sfmmu_udtlb_slowpath /* branch if 2 TSBs */ ;\ 947 nop ;\ 948 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\ 949 ba,pt %xcc, sfmmu_udtlb_fastpath /* no 4M TSB, miss */ ;\ 950 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 951 .align 128 952 953 954#if defined(cscope) 955/* 956 * Define labels to direct cscope quickly to labels that 957 * are generated by macro expansion of ITLB_MISS(). 958 */ 959 .global tt0_itlbmiss 960tt0_itlbmiss: 961 .global tt1_itlbmiss 962tt1_itlbmiss: 963 nop 964#endif 965 966/* 967 * Instruction miss handler. 968 * 969 * This handler is invoked only if the hypervisor has been instructed 970 * not to do any TSB walk. 971 * 972 * ldda instructions will have their ASI patched 973 * by sfmmu_patch_ktsb at runtime. 974 * MUST be EXACTLY 32 instructions or we'll break. 975 */ 976 977/* 978 * synthesize for miss handler: TAG_ACCESS in %g2 (with context "type" 979 * (0=kernel, 1=invalid, or 2=user) rather than context ID) 980 */ 981#define ITLB_MISS(table_name) \ 982 .global table_name/**/_itlbmiss ;\ 983table_name/**/_itlbmiss: ;\ 984 GET_MMU_I_PTAGACC_CTXTYPE(%g2, %g3) /* 8 instr */ ;\ 985 cmp %g3, INVALID_CONTEXT ;\ 986 ble,pn %xcc, sfmmu_kitlb_miss ;\ 987 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 988 mov SCRATCHPAD_UTSBREG2, %g1 ;\ 989 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\ 990 brgez,pn %g1, sfmmu_uitlb_slowpath /* branch if 2 TSBs */ ;\ 991 nop ;\ 992 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\ 993 ba,pt %xcc, sfmmu_uitlb_fastpath /* no 4M TSB, miss */ ;\ 994 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 995 .align 128 996 997#define DTSB_MISS \ 998 GOTO_TT(sfmmu_slow_dmmu_miss,trace_dmmu) 999 1000#define ITSB_MISS \ 1001 GOTO_TT(sfmmu_slow_immu_miss,trace_immu) 1002 1003/* 1004 * This macro is the first level handler for fast protection faults. 1005 * It first demaps the tlb entry which generated the fault and then 1006 * attempts to set the modify bit on the hash. It needs to be 1007 * exactly 32 instructions. 1008 */ 1009/* 1010 * synthesize for miss handler: TAG_ACCESS in %g2 (with context "type" 1011 * (0=kernel, 1=invalid, or 2=user) rather than context ID) 1012 */ 1013#define DTLB_PROT \ 1014 GET_MMU_D_PTAGACC_CTXTYPE(%g2, %g3) /* 8 instr */ ;\ 1015 /* ;\ 1016 * g2 = pseudo-tag access register (ctx type rather than ctx ID) ;\ 1017 * g3 = ctx type (0, 1, or 2) ;\ 1018 */ ;\ 1019 TT_TRACE(trace_dataprot) /* 2 instr ifdef TRAPTRACE */ ;\ 1020 /* clobbers g1 and g6 XXXQ? */ ;\ 1021 brnz,pt %g3, sfmmu_uprot_trap /* user trap */ ;\ 1022 nop ;\ 1023 ba,a,pt %xcc, sfmmu_kprot_trap /* kernel trap */ ;\ 1024 .align 128 1025 1026#define DMMU_EXCEPTION_TL1 ;\ 1027 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1028 .align 32 1029 1030#define MISALIGN_ADDR_TL1 ;\ 1031 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1032 .align 32 1033 1034/* 1035 * Trace a tsb hit 1036 * g1 = tsbe pointer (in/clobbered) 1037 * g2 = tag access register (in) 1038 * g3 - g4 = scratch (clobbered) 1039 * g5 = tsbe data (in) 1040 * g6 = scratch (clobbered) 1041 * g7 = pc we jumped here from (in) 1042 * ttextra = value to OR in to trap type (%tt) (in) 1043 */ 1044#ifdef TRAPTRACE 1045#define TRACE_TSBHIT(ttextra) \ 1046 membar #Sync ;\ 1047 sethi %hi(FLUSH_ADDR), %g6 ;\ 1048 flush %g6 ;\ 1049 TRACE_PTR(%g3, %g6) ;\ 1050 GET_TRACE_TICK(%g6) ;\ 1051 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi ;\ 1052 stna %g2, [%g3 + TRAP_ENT_SP]%asi /* tag access */ ;\ 1053 stna %g5, [%g3 + TRAP_ENT_F1]%asi /* tsb data */ ;\ 1054 rdpr %tnpc, %g6 ;\ 1055 stna %g6, [%g3 + TRAP_ENT_F2]%asi ;\ 1056 stna %g1, [%g3 + TRAP_ENT_F3]%asi /* tsb pointer */ ;\ 1057 stna %g0, [%g3 + TRAP_ENT_F4]%asi ;\ 1058 rdpr %tpc, %g6 ;\ 1059 stna %g6, [%g3 + TRAP_ENT_TPC]%asi ;\ 1060 TRACE_SAVE_TL_GL_REGS(%g3, %g6) ;\ 1061 rdpr %tt, %g6 ;\ 1062 or %g6, (ttextra), %g1 ;\ 1063 stha %g1, [%g3 + TRAP_ENT_TT]%asi ;\ 1064 MMU_FAULT_STATUS_AREA(%g4) ;\ 1065 mov MMFSA_D_ADDR, %g1 ;\ 1066 cmp %g6, FAST_IMMU_MISS_TT ;\ 1067 move %xcc, MMFSA_I_ADDR, %g1 ;\ 1068 cmp %g6, T_INSTR_MMU_MISS ;\ 1069 move %xcc, MMFSA_I_ADDR, %g1 ;\ 1070 ldx [%g4 + %g1], %g1 ;\ 1071 stxa %g1, [%g3 + TRAP_ENT_TSTATE]%asi /* fault addr */ ;\ 1072 mov MMFSA_D_CTX, %g1 ;\ 1073 cmp %g6, FAST_IMMU_MISS_TT ;\ 1074 move %xcc, MMFSA_I_CTX, %g1 ;\ 1075 cmp %g6, T_INSTR_MMU_MISS ;\ 1076 move %xcc, MMFSA_I_CTX, %g1 ;\ 1077 ldx [%g4 + %g1], %g1 ;\ 1078 stna %g1, [%g3 + TRAP_ENT_TR]%asi ;\ 1079 TRACE_NEXT(%g3, %g4, %g6) 1080#else 1081#define TRACE_TSBHIT(ttextra) 1082#endif 1083 1084 1085#if defined(lint) 1086 1087struct scb trap_table; 1088struct scb scb; /* trap_table/scb are the same object */ 1089 1090#else /* lint */ 1091 1092/* 1093 * ======================================================================= 1094 * SPARC V9 TRAP TABLE 1095 * 1096 * The trap table is divided into two halves: the first half is used when 1097 * taking traps when TL=0; the second half is used when taking traps from 1098 * TL>0. Note that handlers in the second half of the table might not be able 1099 * to make the same assumptions as handlers in the first half of the table. 1100 * 1101 * Worst case trap nesting so far: 1102 * 1103 * at TL=0 client issues software trap requesting service 1104 * at TL=1 nucleus wants a register window 1105 * at TL=2 register window clean/spill/fill takes a TLB miss 1106 * at TL=3 processing TLB miss 1107 * at TL=4 handle asynchronous error 1108 * 1109 * Note that a trap from TL=4 to TL=5 places Spitfire in "RED mode". 1110 * 1111 * ======================================================================= 1112 */ 1113 .section ".text" 1114 .align 4 1115 .global trap_table, scb, trap_table0, trap_table1, etrap_table 1116 .type trap_table, #object 1117 .type trap_table0, #object 1118 .type trap_table1, #object 1119 .type scb, #object 1120trap_table: 1121scb: 1122trap_table0: 1123 /* hardware traps */ 1124 NOT; /* 000 reserved */ 1125 RED; /* 001 power on reset */ 1126 WATCHDOG_RESET; /* 002 watchdog reset */ 1127 RED; /* 003 externally initiated reset */ 1128 RED; /* 004 software initiated reset */ 1129 RED; /* 005 red mode exception */ 1130 NOT; NOT; /* 006 - 007 reserved */ 1131 IMMU_EXCEPTION; /* 008 instruction access exception */ 1132 ITSB_MISS; /* 009 instruction access MMU miss */ 1133 NOT; /* 00A reserved */ 1134 NOT; NOT4; /* 00B - 00F reserved */ 1135 ILLTRAP_INSTR; /* 010 illegal instruction */ 1136 TRAP(T_PRIV_INSTR); /* 011 privileged opcode */ 1137 TRAP(T_UNIMP_LDD); /* 012 unimplemented LDD */ 1138 TRAP(T_UNIMP_STD); /* 013 unimplemented STD */ 1139 NOT4; NOT4; NOT4; /* 014 - 01F reserved */ 1140 FP_DISABLED_TRAP; /* 020 fp disabled */ 1141 FP_IEEE_TRAP; /* 021 fp exception ieee 754 */ 1142 FP_TRAP; /* 022 fp exception other */ 1143 TAG_OVERFLOW; /* 023 tag overflow */ 1144 CLEAN_WINDOW; /* 024 - 027 clean window */ 1145 DIV_BY_ZERO; /* 028 division by zero */ 1146 NOT; /* 029 internal processor error */ 1147 NOT; NOT; NOT4; /* 02A - 02F reserved */ 1148 DMMU_EXCEPTION; /* 030 data access exception */ 1149 DTSB_MISS; /* 031 data access MMU miss */ 1150 NOT; /* 032 reserved */ 1151 NOT; /* 033 data access protection */ 1152 DMMU_EXC_AG_NOT_ALIGNED; /* 034 mem address not aligned */ 1153 DMMU_EXC_LDDF_NOT_ALIGNED; /* 035 LDDF mem address not aligned */ 1154 DMMU_EXC_STDF_NOT_ALIGNED; /* 036 STDF mem address not aligned */ 1155 DMMU_EXC_AG_PRIV; /* 037 privileged action */ 1156 NOT; /* 038 LDQF mem address not aligned */ 1157 NOT; /* 039 STQF mem address not aligned */ 1158 NOT; NOT; NOT4; /* 03A - 03F reserved */ 1159 NOT; /* 040 async data error */ 1160 LEVEL_INTERRUPT(1); /* 041 interrupt level 1 */ 1161 LEVEL_INTERRUPT(2); /* 042 interrupt level 2 */ 1162 LEVEL_INTERRUPT(3); /* 043 interrupt level 3 */ 1163 LEVEL_INTERRUPT(4); /* 044 interrupt level 4 */ 1164 LEVEL_INTERRUPT(5); /* 045 interrupt level 5 */ 1165 LEVEL_INTERRUPT(6); /* 046 interrupt level 6 */ 1166 LEVEL_INTERRUPT(7); /* 047 interrupt level 7 */ 1167 LEVEL_INTERRUPT(8); /* 048 interrupt level 8 */ 1168 LEVEL_INTERRUPT(9); /* 049 interrupt level 9 */ 1169 LEVEL_INTERRUPT(10); /* 04A interrupt level 10 */ 1170 LEVEL_INTERRUPT(11); /* 04B interrupt level 11 */ 1171 LEVEL_INTERRUPT(12); /* 04C interrupt level 12 */ 1172 LEVEL_INTERRUPT(13); /* 04D interrupt level 13 */ 1173 LEVEL14_INTERRUPT; /* 04E interrupt level 14 */ 1174 LEVEL_INTERRUPT(15); /* 04F interrupt level 15 */ 1175 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F reserved */ 1176 NOT; /* 060 interrupt vector */ 1177 GOTO(kmdb_trap); /* 061 PA watchpoint */ 1178 GOTO(kmdb_trap); /* 062 VA watchpoint */ 1179 NOT; /* 063 reserved */ 1180 ITLB_MISS(tt0); /* 064 instruction access MMU miss */ 1181 DTLB_MISS(tt0); /* 068 data access MMU miss */ 1182 DTLB_PROT; /* 06C data access protection */ 1183 NOT; /* 070 reserved */ 1184 NOT; /* 071 reserved */ 1185 NOT; /* 072 reserved */ 1186 NOT; /* 073 reserved */ 1187 NOT4; NOT4 /* 074 - 07B reserved */ 1188 CPU_MONDO; /* 07C cpu_mondo */ 1189 DEV_MONDO; /* 07D dev_mondo */ 1190 GOTO_TT(resumable_error, trace_gen); /* 07E resumable error */ 1191 GOTO_TT(nonresumable_error, trace_gen); /* 07F non-reasumable error */ 1192 NOT4; /* 080 spill 0 normal */ 1193 SPILL_32bit_asi(ASI_AIUP,sn0); /* 084 spill 1 normal */ 1194 SPILL_64bit_asi(ASI_AIUP,sn0); /* 088 spill 2 normal */ 1195 SPILL_32clean(ASI_AIUP,sn0); /* 08C spill 3 normal */ 1196 SPILL_64clean(ASI_AIUP,sn0); /* 090 spill 4 normal */ 1197 SPILL_32bit(not); /* 094 spill 5 normal */ 1198 SPILL_64bit(not); /* 098 spill 6 normal */ 1199 SPILL_mixed; /* 09C spill 7 normal */ 1200 NOT4; /* 0A0 spill 0 other */ 1201 SPILL_32bit_asi(ASI_AIUS,so0); /* 0A4 spill 1 other */ 1202 SPILL_64bit_asi(ASI_AIUS,so0); /* 0A8 spill 2 other */ 1203 SPILL_32bit_asi(ASI_AIUS,so0); /* 0AC spill 3 other */ 1204 SPILL_64bit_asi(ASI_AIUS,so0); /* 0B0 spill 4 other */ 1205 NOT4; /* 0B4 spill 5 other */ 1206 NOT4; /* 0B8 spill 6 other */ 1207 NOT4; /* 0BC spill 7 other */ 1208 NOT4; /* 0C0 fill 0 normal */ 1209 FILL_32bit_asi(ASI_AIUP,fn0); /* 0C4 fill 1 normal */ 1210 FILL_64bit_asi(ASI_AIUP,fn0); /* 0C8 fill 2 normal */ 1211 FILL_32bit_asi(ASI_AIUP,fn0); /* 0CC fill 3 normal */ 1212 FILL_64bit_asi(ASI_AIUP,fn0); /* 0D0 fill 4 normal */ 1213 FILL_32bit(not); /* 0D4 fill 5 normal */ 1214 FILL_64bit(not); /* 0D8 fill 6 normal */ 1215 FILL_mixed; /* 0DC fill 7 normal */ 1216 NOT4; /* 0E0 fill 0 other */ 1217 NOT4; /* 0E4 fill 1 other */ 1218 NOT4; /* 0E8 fill 2 other */ 1219 NOT4; /* 0EC fill 3 other */ 1220 NOT4; /* 0F0 fill 4 other */ 1221 NOT4; /* 0F4 fill 5 other */ 1222 NOT4; /* 0F8 fill 6 other */ 1223 NOT4; /* 0FC fill 7 other */ 1224 /* user traps */ 1225 GOTO(syscall_trap_4x); /* 100 old system call */ 1226 TRAP(T_BREAKPOINT); /* 101 user breakpoint */ 1227 TRAP(T_DIV0); /* 102 user divide by zero */ 1228 GOTO(.flushw); /* 103 flush windows */ 1229 GOTO(.clean_windows); /* 104 clean windows */ 1230 BAD; /* 105 range check ?? */ 1231 GOTO(.fix_alignment); /* 106 do unaligned references */ 1232 BAD; /* 107 unused */ 1233 SYSCALL_TRAP32; /* 108 ILP32 system call on LP64 */ 1234 GOTO(set_trap0_addr); /* 109 set trap0 address */ 1235 BAD; BAD; BAD4; /* 10A - 10F unused */ 1236 TRP4; TRP4; TRP4; TRP4; /* 110 - 11F V9 user trap handlers */ 1237 GOTO(.getcc); /* 120 get condition codes */ 1238 GOTO(.setcc); /* 121 set condition codes */ 1239 GOTO(.getpsr); /* 122 get psr */ 1240 GOTO(.setpsr); /* 123 set psr (some fields) */ 1241 GOTO(get_timestamp); /* 124 get timestamp */ 1242 GOTO(get_virtime); /* 125 get lwp virtual time */ 1243 PRIV(self_xcall); /* 126 self xcall */ 1244 GOTO(get_hrestime); /* 127 get hrestime */ 1245 BAD; /* 128 ST_SETV9STACK */ 1246 GOTO(.getlgrp); /* 129 get lgrpid */ 1247 BAD; BAD; BAD4; /* 12A - 12F unused */ 1248 BAD4; BAD4; /* 130 - 137 unused */ 1249 DTRACE_PID; /* 138 dtrace pid tracing provider */ 1250 BAD; /* 139 unused */ 1251 DTRACE_RETURN; /* 13A dtrace pid return probe */ 1252 BAD; BAD4; /* 13B - 13F unused */ 1253 SYSCALL_TRAP; /* 140 LP64 system call */ 1254 SYSCALL(nosys); /* 141 unused system call trap */ 1255#ifdef DEBUG_USER_TRAPTRACECTL 1256 GOTO(.traptrace_freeze); /* 142 freeze traptrace */ 1257 GOTO(.traptrace_unfreeze); /* 143 unfreeze traptrace */ 1258#else 1259 SYSCALL(nosys); /* 142 unused system call trap */ 1260 SYSCALL(nosys); /* 143 unused system call trap */ 1261#endif 1262 BAD4; BAD4; BAD4; /* 144 - 14F unused */ 1263 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1264 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1265 BAD; /* 170 - unused */ 1266 BAD; /* 171 - unused */ 1267 BAD; BAD; /* 172 - 173 unused */ 1268 BAD4; BAD4; /* 174 - 17B unused */ 1269#ifdef PTL1_PANIC_DEBUG 1270 mov PTL1_BAD_DEBUG, %g1; GOTO(ptl1_panic); 1271 /* 17C test ptl1_panic */ 1272#else 1273 BAD; /* 17C unused */ 1274#endif /* PTL1_PANIC_DEBUG */ 1275 PRIV(kmdb_trap); /* 17D kmdb enter (L1-A) */ 1276 PRIV(kmdb_trap); /* 17E kmdb breakpoint */ 1277 PRIV(obp_bpt); /* 17F obp breakpoint */ 1278 /* reserved */ 1279 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1280 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1281 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1282 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1283 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1284 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1285 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1286 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1287 .size trap_table0, (.-trap_table0) 1288trap_table1: 1289 NOT4; NOT4; /* 000 - 007 unused */ 1290 NOT; /* 008 instruction access exception */ 1291 ITSB_MISS; /* 009 instruction access MMU miss */ 1292 NOT; /* 00A reserved */ 1293 NOT; NOT4; /* 00B - 00F unused */ 1294 NOT4; NOT4; NOT4; NOT4; /* 010 - 01F unused */ 1295 NOT4; /* 020 - 023 unused */ 1296 CLEAN_WINDOW; /* 024 - 027 clean window */ 1297 NOT4; NOT4; /* 028 - 02F unused */ 1298 DMMU_EXCEPTION_TL1; /* 030 data access exception */ 1299 DTSB_MISS; /* 031 data access MMU miss */ 1300 NOT; /* 032 reserved */ 1301 NOT; /* 033 unused */ 1302 MISALIGN_ADDR_TL1; /* 034 mem address not aligned */ 1303 NOT; NOT; NOT; NOT4; NOT4 /* 035 - 03F unused */ 1304 NOT4; NOT4; NOT4; NOT4; /* 040 - 04F unused */ 1305 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F unused */ 1306 NOT; /* 060 unused */ 1307 GOTO(kmdb_trap_tl1); /* 061 PA watchpoint */ 1308 GOTO(kmdb_trap_tl1); /* 062 VA watchpoint */ 1309 NOT; /* 063 reserved */ 1310 ITLB_MISS(tt1); /* 064 instruction access MMU miss */ 1311 DTLB_MISS(tt1); /* 068 data access MMU miss */ 1312 DTLB_PROT; /* 06C data access protection */ 1313 NOT; /* 070 reserved */ 1314 NOT; /* 071 reserved */ 1315 NOT; /* 072 reserved */ 1316 NOT; /* 073 reserved */ 1317 NOT4; NOT4; /* 074 - 07B reserved */ 1318 NOT; /* 07C reserved */ 1319 NOT; /* 07D reserved */ 1320 NOT; /* 07E resumable error */ 1321 GOTO_TT(nonresumable_error, trace_gen); /* 07F nonresumable error */ 1322 NOTP4; /* 080 spill 0 normal */ 1323 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 084 spill 1 normal */ 1324 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 088 spill 2 normal */ 1325 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 08C spill 3 normal */ 1326 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 090 spill 4 normal */ 1327 NOTP4; /* 094 spill 5 normal */ 1328 SPILL_64bit_ktt1(sk); /* 098 spill 6 normal */ 1329 SPILL_mixed_ktt1(sk); /* 09C spill 7 normal */ 1330 NOTP4; /* 0A0 spill 0 other */ 1331 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0A4 spill 1 other */ 1332 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0A8 spill 2 other */ 1333 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0AC spill 3 other */ 1334 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0B0 spill 4 other */ 1335 NOTP4; /* 0B4 spill 5 other */ 1336 NOTP4; /* 0B8 spill 6 other */ 1337 NOTP4; /* 0BC spill 7 other */ 1338 NOT4; /* 0C0 fill 0 normal */ 1339 NOT4; /* 0C4 fill 1 normal */ 1340 NOT4; /* 0C8 fill 2 normal */ 1341 NOT4; /* 0CC fill 3 normal */ 1342 NOT4; /* 0D0 fill 4 normal */ 1343 NOT4; /* 0D4 fill 5 normal */ 1344 NOT4; /* 0D8 fill 6 normal */ 1345 NOT4; /* 0DC fill 7 normal */ 1346 NOT4; NOT4; NOT4; NOT4; /* 0E0 - 0EF unused */ 1347 NOT4; NOT4; NOT4; NOT4; /* 0F0 - 0FF unused */ 1348/* 1349 * Code running at TL>0 does not use soft traps, so 1350 * we can truncate the table here. 1351 * However: 1352 * sun4v uses (hypervisor) ta instructions at TL > 0, so 1353 * provide a safety net for now. 1354 */ 1355 /* soft traps */ 1356 BAD4; BAD4; BAD4; BAD4; /* 100 - 10F unused */ 1357 BAD4; BAD4; BAD4; BAD4; /* 110 - 11F unused */ 1358 BAD4; BAD4; BAD4; BAD4; /* 120 - 12F unused */ 1359 BAD4; BAD4; BAD4; BAD4; /* 130 - 13F unused */ 1360 BAD4; BAD4; BAD4; BAD4; /* 140 - 14F unused */ 1361 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1362 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1363 BAD4; BAD4; BAD4; BAD4; /* 170 - 17F unused */ 1364 /* reserved */ 1365 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1366 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1367 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1368 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1369 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1370 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1371 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1372 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1373etrap_table: 1374 .size trap_table1, (.-trap_table1) 1375 .size trap_table, (.-trap_table) 1376 .size scb, (.-scb) 1377 1378/* 1379 * We get to exec_fault in the case of an instruction miss and tte 1380 * has no execute bit set. We go to tl0 to handle it. 1381 * 1382 * g1 = tsbe pointer (in/clobbered) 1383 * g2 = tag access register (in) 1384 * g3 - g4 = scratch (clobbered) 1385 * g5 = tsbe data (in) 1386 * g6 = scratch (clobbered) 1387 * g7 = pc we jumped here from (in) 1388 */ 1389/* 1390 * synthesize for miss handler: TAG_ACCESS in %g2 (with context "type" 1391 * (0=kernel, 1=invalid, or 2=user) rather than context ID) 1392 */ 1393 ALTENTRY(exec_fault) 1394 set icache_is_coherent, %g6 /* check soft exec mode */ 1395 ld [%g6], %g6 1396 brz,pn %g6, sfmmu_slow_immu_miss 1397 nop 1398 TRACE_TSBHIT(TT_MMU_EXEC) 1399 MMU_FAULT_STATUS_AREA(%g4) 1400 ldx [%g4 + MMFSA_I_ADDR], %g2 /* g2 = address */ 1401 ldx [%g4 + MMFSA_I_CTX], %g3 /* g3 = ctx */ 1402 srlx %g2, MMU_PAGESHIFT, %g2 ! align address to page boundry 1403 cmp %g3, USER_CONTEXT_TYPE 1404 sllx %g2, MMU_PAGESHIFT, %g2 1405 movgu %icc, USER_CONTEXT_TYPE, %g3 1406 or %g2, %g3, %g2 /* TAG_ACCESS */ 1407 mov T_INSTR_MMU_MISS, %g3 ! arg2 = traptype 1408 set trap, %g1 1409 ba,pt %xcc, sys_trap 1410 mov -1, %g4 1411 1412.mmu_exception_not_aligned: 1413 /* %g2 = sfar, %g3 = sfsr */ 1414 rdpr %tstate, %g1 1415 btst TSTATE_PRIV, %g1 1416 bnz,pn %icc, 2f 1417 nop 1418 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1419 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1420 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1421 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1422 brz,pt %g5, 2f 1423 nop 1424 ldn [%g5 + P_UTRAP15], %g5 ! unaligned utrap? 1425 brz,pn %g5, 2f 1426 nop 1427 btst 1, %sp 1428 bz,pt %xcc, 1f ! 32 bit user program 1429 nop 1430 ba,pt %xcc, .setup_v9utrap ! 64 bit user program 1431 nop 14321: 1433 ba,pt %xcc, .setup_utrap 1434 or %g2, %g0, %g7 14352: 1436 ba,pt %xcc, .mmu_exception_end 1437 mov T_ALIGNMENT, %g1 1438 1439.mmu_priv_exception: 1440 rdpr %tstate, %g1 1441 btst TSTATE_PRIV, %g1 1442 bnz,pn %icc, 1f 1443 nop 1444 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1445 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1446 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1447 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1448 brz,pt %g5, 1f 1449 nop 1450 ldn [%g5 + P_UTRAP16], %g5 1451 brnz,pt %g5, .setup_v9utrap 1452 nop 14531: 1454 mov T_PRIV_INSTR, %g1 1455 1456.mmu_exception_end: 1457 CPU_INDEX(%g4, %g5) 1458 set cpu_core, %g5 1459 sllx %g4, CPU_CORE_SHIFT, %g4 1460 add %g4, %g5, %g4 1461 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5 1462 andcc %g5, CPU_DTRACE_NOFAULT, %g0 1463 bz 1f 1464 or %g5, CPU_DTRACE_BADADDR, %g5 1465 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS] 1466 done 1467 14681: 1469 sllx %g3, 32, %g3 1470 or %g3, %g1, %g3 1471 set trap, %g1 1472 ba,pt %xcc, sys_trap 1473 sub %g0, 1, %g4 1474 1475.fp_disabled: 1476 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1477 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1478 rdpr %tstate, %g4 1479 btst TSTATE_PRIV, %g4 1480 bnz,a,pn %icc, ptl1_panic 1481 mov PTL1_BAD_FPTRAP, %g1 1482 1483 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1484 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1485 brz,a,pt %g5, 2f 1486 nop 1487 ldn [%g5 + P_UTRAP7], %g5 ! fp_disabled utrap? 1488 brz,a,pn %g5, 2f 1489 nop 1490 btst 1, %sp 1491 bz,a,pt %xcc, 1f ! 32 bit user program 1492 nop 1493 ba,a,pt %xcc, .setup_v9utrap ! 64 bit user program 1494 nop 14951: 1496 ba,pt %xcc, .setup_utrap 1497 or %g0, %g0, %g7 14982: 1499 set fp_disabled, %g1 1500 ba,pt %xcc, sys_trap 1501 sub %g0, 1, %g4 1502 1503.fp_ieee_exception: 1504 rdpr %tstate, %g1 1505 btst TSTATE_PRIV, %g1 1506 bnz,a,pn %icc, ptl1_panic 1507 mov PTL1_BAD_FPTRAP, %g1 1508 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1509 stx %fsr, [%g1 + CPU_TMP1] 1510 ldx [%g1 + CPU_TMP1], %g2 1511 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1512 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1513 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1514 brz,a,pt %g5, 1f 1515 nop 1516 ldn [%g5 + P_UTRAP8], %g5 1517 brnz,a,pt %g5, .setup_v9utrap 1518 nop 15191: 1520 set _fp_ieee_exception, %g1 1521 ba,pt %xcc, sys_trap 1522 sub %g0, 1, %g4 1523 1524/* 1525 * Register Inputs: 1526 * %g5 user trap handler 1527 * %g7 misaligned addr - for alignment traps only 1528 */ 1529.setup_utrap: 1530 set trap, %g1 ! setup in case we go 1531 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1532 sub %g0, 1, %g4 ! the save instruction below 1533 1534 /* 1535 * If the DTrace pid provider is single stepping a copied-out 1536 * instruction, t->t_dtrace_step will be set. In that case we need 1537 * to abort the single-stepping (since execution of the instruction 1538 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1539 */ 1540 save %sp, -SA(MINFRAME32), %sp ! window for trap handler 1541 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1542 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1543 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1544 rdpr %tnpc, %l2 ! arg1 == tnpc 1545 brz,pt %g2, 1f 1546 rdpr %tpc, %l1 ! arg0 == tpc 1547 1548 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1549 ldn [%g1 + T_DTRACE_NPC], %l2 ! arg1 = t->t_dtrace_npc (step) 1550 brz,pt %g2, 1f 1551 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1552 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 15531: 1554 mov %g7, %l3 ! arg2 == misaligned address 1555 1556 rdpr %tstate, %g1 ! cwp for trap handler 1557 rdpr %cwp, %g4 1558 bclr TSTATE_CWP_MASK, %g1 1559 wrpr %g1, %g4, %tstate 1560 wrpr %g0, %g5, %tnpc ! trap handler address 1561 FAST_TRAP_DONE 1562 /* NOTREACHED */ 1563 1564.check_v9utrap: 1565 rdpr %tstate, %g1 1566 btst TSTATE_PRIV, %g1 1567 bnz,a,pn %icc, 3f 1568 nop 1569 CPU_ADDR(%g4, %g1) ! load CPU struct addr 1570 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer 1571 ldn [%g5 + T_PROCP], %g5 ! load proc pointer 1572 ldn [%g5 + P_UTRAPS], %g5 ! are there utraps? 1573 1574 cmp %g3, T_SOFTWARE_TRAP 1575 bne,a,pt %icc, 1f 1576 nop 1577 1578 brz,pt %g5, 3f ! if p_utraps == NULL goto trap() 1579 rdpr %tt, %g3 ! delay - get actual hw trap type 1580 1581 sub %g3, 254, %g1 ! UT_TRAP_INSTRUCTION_16 = p_utraps[18] 1582 ba,pt %icc, 2f 1583 smul %g1, CPTRSIZE, %g2 15841: 1585 brz,a,pt %g5, 3f ! if p_utraps == NULL goto trap() 1586 nop 1587 1588 cmp %g3, T_UNIMP_INSTR 1589 bne,a,pt %icc, 2f 1590 nop 1591 1592 mov 1, %g1 1593 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR 1594 rdpr %tpc, %g1 ! ld trapping instruction using 1595 lduwa [%g1]ASI_AIUP, %g1 ! "AS IF USER" ASI which could fault 1596 st %g0, [%g4 + CPU_TL1_HDLR] ! clr CPU_TL1_HDLR 1597 1598 sethi %hi(0xc1c00000), %g4 ! setup mask for illtrap instruction 1599 andcc %g1, %g4, %g4 ! and instruction with mask 1600 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP 1601 nop ! fall thru to setup 16022: 1603 ldn [%g5 + %g2], %g5 1604 brnz,a,pt %g5, .setup_v9utrap 1605 nop 16063: 1607 set trap, %g1 1608 ba,pt %xcc, sys_trap 1609 sub %g0, 1, %g4 1610 /* NOTREACHED */ 1611 1612/* 1613 * Register Inputs: 1614 * %g5 user trap handler 1615 */ 1616.setup_v9utrap: 1617 set trap, %g1 ! setup in case we go 1618 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1619 sub %g0, 1, %g4 ! the save instruction below 1620 1621 /* 1622 * If the DTrace pid provider is single stepping a copied-out 1623 * instruction, t->t_dtrace_step will be set. In that case we need 1624 * to abort the single-stepping (since execution of the instruction 1625 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1626 */ 1627 save %sp, -SA(MINFRAME64), %sp ! window for trap handler 1628 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1629 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1630 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1631 rdpr %tnpc, %l7 ! arg1 == tnpc 1632 brz,pt %g2, 1f 1633 rdpr %tpc, %l6 ! arg0 == tpc 1634 1635 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1636 ldn [%g1 + T_DTRACE_NPC], %l7 ! arg1 == t->t_dtrace_npc (step) 1637 brz,pt %g2, 1f 1638 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1639 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 16401: 1641 rdpr %tstate, %g2 ! cwp for trap handler 1642 rdpr %cwp, %g4 1643 bclr TSTATE_CWP_MASK, %g2 1644 wrpr %g2, %g4, %tstate 1645 1646 ldn [%g1 + T_PROCP], %g4 ! load proc pointer 1647 ldn [%g4 + P_AS], %g4 ! load as pointer 1648 ldn [%g4 + A_USERLIMIT], %g4 ! load as userlimit 1649 cmp %l7, %g4 ! check for single-step set 1650 bne,pt %xcc, 4f 1651 nop 1652 ldn [%g1 + T_LWP], %g1 ! load klwp pointer 1653 ld [%g1 + PCB_STEP], %g4 ! load single-step flag 1654 cmp %g4, STEP_ACTIVE ! step flags set in pcb? 1655 bne,pt %icc, 4f 1656 nop 1657 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb 1658 mov %l7, %g4 ! on entry to precise user trap 1659 add %l6, 4, %l7 ! handler, %l6 == pc, %l7 == npc 1660 ! at time of trap 1661 wrpr %g0, %g4, %tnpc ! generate FLTBOUNDS, 1662 ! %g4 == userlimit 1663 FAST_TRAP_DONE 1664 /* NOTREACHED */ 16654: 1666 wrpr %g0, %g5, %tnpc ! trap handler address 1667 FAST_TRAP_DONE_CHK_INTR 1668 /* NOTREACHED */ 1669 1670.fp_exception: 1671 CPU_ADDR(%g1, %g4) 1672 stx %fsr, [%g1 + CPU_TMP1] 1673 ldx [%g1 + CPU_TMP1], %g2 1674 1675 /* 1676 * Cheetah takes unfinished_FPop trap for certain range of operands 1677 * to the "fitos" instruction. Instead of going through the slow 1678 * software emulation path, we try to simulate the "fitos" instruction 1679 * via "fitod" and "fdtos" provided the following conditions are met: 1680 * 1681 * fpu_exists is set (if DEBUG) 1682 * not in privileged mode 1683 * ftt is unfinished_FPop 1684 * NXM IEEE trap is not enabled 1685 * instruction at %tpc is "fitos" 1686 * 1687 * Usage: 1688 * %g1 per cpu address 1689 * %g2 %fsr 1690 * %g6 user instruction 1691 * 1692 * Note that we can take a memory access related trap while trying 1693 * to fetch the user instruction. Therefore, we set CPU_TL1_HDLR 1694 * flag to catch those traps and let the SFMMU code deal with page 1695 * fault and data access exception. 1696 */ 1697#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 1698 sethi %hi(fpu_exists), %g7 1699 ld [%g7 + %lo(fpu_exists)], %g7 1700 brz,pn %g7, .fp_exception_cont 1701 nop 1702#endif 1703 rdpr %tstate, %g7 ! branch if in privileged mode 1704 btst TSTATE_PRIV, %g7 1705 bnz,pn %xcc, .fp_exception_cont 1706 srl %g2, FSR_FTT_SHIFT, %g7 ! extract ftt from %fsr 1707 and %g7, (FSR_FTT>>FSR_FTT_SHIFT), %g7 1708 cmp %g7, FTT_UNFIN 1709 set FSR_TEM_NX, %g5 1710 bne,pn %xcc, .fp_exception_cont ! branch if NOT unfinished_FPop 1711 andcc %g2, %g5, %g0 1712 bne,pn %xcc, .fp_exception_cont ! branch if FSR_TEM_NX enabled 1713 rdpr %tpc, %g5 ! get faulting PC 1714 1715 or %g0, 1, %g7 1716 st %g7, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 1717 lda [%g5]ASI_USER, %g6 ! get user's instruction 1718 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 1719 1720 set FITOS_INSTR_MASK, %g7 1721 and %g6, %g7, %g7 1722 set FITOS_INSTR, %g5 1723 cmp %g7, %g5 1724 bne,pn %xcc, .fp_exception_cont ! branch if not FITOS_INSTR 1725 nop 1726 1727 /* 1728 * This is unfinished FPops trap for "fitos" instruction. We 1729 * need to simulate "fitos" via "fitod" and "fdtos" instruction 1730 * sequence. 1731 * 1732 * We need a temporary FP register to do the conversion. Since 1733 * both source and destination operands for the "fitos" instruction 1734 * have to be within %f0-%f31, we use an FP register from the upper 1735 * half to guarantee that it won't collide with the source or the 1736 * dest operand. However, we do have to save and restore its value. 1737 * 1738 * We use %d62 as a temporary FP register for the conversion and 1739 * branch to appropriate instruction within the conversion tables 1740 * based upon the rs2 and rd values. 1741 */ 1742 1743 std %d62, [%g1 + CPU_TMP1] ! save original value 1744 1745 srl %g6, FITOS_RS2_SHIFT, %g7 1746 and %g7, FITOS_REG_MASK, %g7 1747 set _fitos_fitod_table, %g4 1748 sllx %g7, 2, %g7 1749 jmp %g4 + %g7 1750 ba,pt %xcc, _fitos_fitod_done 1751 .empty 1752 1753_fitos_fitod_table: 1754 fitod %f0, %d62 1755 fitod %f1, %d62 1756 fitod %f2, %d62 1757 fitod %f3, %d62 1758 fitod %f4, %d62 1759 fitod %f5, %d62 1760 fitod %f6, %d62 1761 fitod %f7, %d62 1762 fitod %f8, %d62 1763 fitod %f9, %d62 1764 fitod %f10, %d62 1765 fitod %f11, %d62 1766 fitod %f12, %d62 1767 fitod %f13, %d62 1768 fitod %f14, %d62 1769 fitod %f15, %d62 1770 fitod %f16, %d62 1771 fitod %f17, %d62 1772 fitod %f18, %d62 1773 fitod %f19, %d62 1774 fitod %f20, %d62 1775 fitod %f21, %d62 1776 fitod %f22, %d62 1777 fitod %f23, %d62 1778 fitod %f24, %d62 1779 fitod %f25, %d62 1780 fitod %f26, %d62 1781 fitod %f27, %d62 1782 fitod %f28, %d62 1783 fitod %f29, %d62 1784 fitod %f30, %d62 1785 fitod %f31, %d62 1786_fitos_fitod_done: 1787 1788 /* 1789 * Now convert data back into single precision 1790 */ 1791 srl %g6, FITOS_RD_SHIFT, %g7 1792 and %g7, FITOS_REG_MASK, %g7 1793 set _fitos_fdtos_table, %g4 1794 sllx %g7, 2, %g7 1795 jmp %g4 + %g7 1796 ba,pt %xcc, _fitos_fdtos_done 1797 .empty 1798 1799_fitos_fdtos_table: 1800 fdtos %d62, %f0 1801 fdtos %d62, %f1 1802 fdtos %d62, %f2 1803 fdtos %d62, %f3 1804 fdtos %d62, %f4 1805 fdtos %d62, %f5 1806 fdtos %d62, %f6 1807 fdtos %d62, %f7 1808 fdtos %d62, %f8 1809 fdtos %d62, %f9 1810 fdtos %d62, %f10 1811 fdtos %d62, %f11 1812 fdtos %d62, %f12 1813 fdtos %d62, %f13 1814 fdtos %d62, %f14 1815 fdtos %d62, %f15 1816 fdtos %d62, %f16 1817 fdtos %d62, %f17 1818 fdtos %d62, %f18 1819 fdtos %d62, %f19 1820 fdtos %d62, %f20 1821 fdtos %d62, %f21 1822 fdtos %d62, %f22 1823 fdtos %d62, %f23 1824 fdtos %d62, %f24 1825 fdtos %d62, %f25 1826 fdtos %d62, %f26 1827 fdtos %d62, %f27 1828 fdtos %d62, %f28 1829 fdtos %d62, %f29 1830 fdtos %d62, %f30 1831 fdtos %d62, %f31 1832_fitos_fdtos_done: 1833 1834 ldd [%g1 + CPU_TMP1], %d62 ! restore %d62 1835 1836#if DEBUG 1837 /* 1838 * Update FPop_unfinished trap kstat 1839 */ 1840 set fpustat+FPUSTAT_UNFIN_KSTAT, %g7 1841 ldx [%g7], %g5 18421: 1843 add %g5, 1, %g6 1844 1845 casxa [%g7] ASI_N, %g5, %g6 1846 cmp %g5, %g6 1847 bne,a,pn %xcc, 1b 1848 or %g0, %g6, %g5 1849 1850 /* 1851 * Update fpu_sim_fitos kstat 1852 */ 1853 set fpuinfo+FPUINFO_FITOS_KSTAT, %g7 1854 ldx [%g7], %g5 18551: 1856 add %g5, 1, %g6 1857 1858 casxa [%g7] ASI_N, %g5, %g6 1859 cmp %g5, %g6 1860 bne,a,pn %xcc, 1b 1861 or %g0, %g6, %g5 1862#endif /* DEBUG */ 1863 1864 FAST_TRAP_DONE 1865 1866.fp_exception_cont: 1867 /* 1868 * Let _fp_exception deal with simulating FPop instruction. 1869 * Note that we need to pass %fsr in %g2 (already read above). 1870 */ 1871 1872 set _fp_exception, %g1 1873 ba,pt %xcc, sys_trap 1874 sub %g0, 1, %g4 1875 1876 1877/* 1878 * Register windows 1879 */ 1880.flushw: 1881.clean_windows: 1882 rdpr %tnpc, %g1 1883 wrpr %g1, %tpc 1884 add %g1, 4, %g1 1885 wrpr %g1, %tnpc 1886 set trap, %g1 1887 mov T_FLUSH_PCB, %g3 1888 ba,pt %xcc, sys_trap 1889 sub %g0, 1, %g4 1890 1891/* 1892 * .spill_clean: clean the previous window, restore the wstate, and 1893 * "done". 1894 * 1895 * Entry: %g7 contains new wstate 1896 */ 1897.spill_clean: 1898 sethi %hi(nwin_minus_one), %g5 1899 ld [%g5 + %lo(nwin_minus_one)], %g5 ! %g5 = nwin - 1 1900 rdpr %cwp, %g6 ! %g6 = %cwp 1901 deccc %g6 ! %g6-- 1902 movneg %xcc, %g5, %g6 ! if (%g6<0) %g6 = nwin-1 1903 wrpr %g6, %cwp 1904 TT_TRACE_L(trace_win) 1905 clr %l0 1906 clr %l1 1907 clr %l2 1908 clr %l3 1909 clr %l4 1910 clr %l5 1911 clr %l6 1912 clr %l7 1913 wrpr %g0, %g7, %wstate 1914 saved 1915 retry ! restores correct %cwp 1916 1917.fix_alignment: 1918 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 1919 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1920 ldn [%g1 + T_PROCP], %g1 1921 mov 1, %g2 1922 stb %g2, [%g1 + P_FIXALIGNMENT] 1923 FAST_TRAP_DONE 1924 1925#define STDF_REG(REG, ADDR, TMP) \ 1926 sll REG, 3, REG ;\ 1927mark1: set start1, TMP ;\ 1928 jmp REG + TMP ;\ 1929 nop ;\ 1930start1: ba,pt %xcc, done1 ;\ 1931 std %f0, [ADDR + CPU_TMP1] ;\ 1932 ba,pt %xcc, done1 ;\ 1933 std %f32, [ADDR + CPU_TMP1] ;\ 1934 ba,pt %xcc, done1 ;\ 1935 std %f2, [ADDR + CPU_TMP1] ;\ 1936 ba,pt %xcc, done1 ;\ 1937 std %f34, [ADDR + CPU_TMP1] ;\ 1938 ba,pt %xcc, done1 ;\ 1939 std %f4, [ADDR + CPU_TMP1] ;\ 1940 ba,pt %xcc, done1 ;\ 1941 std %f36, [ADDR + CPU_TMP1] ;\ 1942 ba,pt %xcc, done1 ;\ 1943 std %f6, [ADDR + CPU_TMP1] ;\ 1944 ba,pt %xcc, done1 ;\ 1945 std %f38, [ADDR + CPU_TMP1] ;\ 1946 ba,pt %xcc, done1 ;\ 1947 std %f8, [ADDR + CPU_TMP1] ;\ 1948 ba,pt %xcc, done1 ;\ 1949 std %f40, [ADDR + CPU_TMP1] ;\ 1950 ba,pt %xcc, done1 ;\ 1951 std %f10, [ADDR + CPU_TMP1] ;\ 1952 ba,pt %xcc, done1 ;\ 1953 std %f42, [ADDR + CPU_TMP1] ;\ 1954 ba,pt %xcc, done1 ;\ 1955 std %f12, [ADDR + CPU_TMP1] ;\ 1956 ba,pt %xcc, done1 ;\ 1957 std %f44, [ADDR + CPU_TMP1] ;\ 1958 ba,pt %xcc, done1 ;\ 1959 std %f14, [ADDR + CPU_TMP1] ;\ 1960 ba,pt %xcc, done1 ;\ 1961 std %f46, [ADDR + CPU_TMP1] ;\ 1962 ba,pt %xcc, done1 ;\ 1963 std %f16, [ADDR + CPU_TMP1] ;\ 1964 ba,pt %xcc, done1 ;\ 1965 std %f48, [ADDR + CPU_TMP1] ;\ 1966 ba,pt %xcc, done1 ;\ 1967 std %f18, [ADDR + CPU_TMP1] ;\ 1968 ba,pt %xcc, done1 ;\ 1969 std %f50, [ADDR + CPU_TMP1] ;\ 1970 ba,pt %xcc, done1 ;\ 1971 std %f20, [ADDR + CPU_TMP1] ;\ 1972 ba,pt %xcc, done1 ;\ 1973 std %f52, [ADDR + CPU_TMP1] ;\ 1974 ba,pt %xcc, done1 ;\ 1975 std %f22, [ADDR + CPU_TMP1] ;\ 1976 ba,pt %xcc, done1 ;\ 1977 std %f54, [ADDR + CPU_TMP1] ;\ 1978 ba,pt %xcc, done1 ;\ 1979 std %f24, [ADDR + CPU_TMP1] ;\ 1980 ba,pt %xcc, done1 ;\ 1981 std %f56, [ADDR + CPU_TMP1] ;\ 1982 ba,pt %xcc, done1 ;\ 1983 std %f26, [ADDR + CPU_TMP1] ;\ 1984 ba,pt %xcc, done1 ;\ 1985 std %f58, [ADDR + CPU_TMP1] ;\ 1986 ba,pt %xcc, done1 ;\ 1987 std %f28, [ADDR + CPU_TMP1] ;\ 1988 ba,pt %xcc, done1 ;\ 1989 std %f60, [ADDR + CPU_TMP1] ;\ 1990 ba,pt %xcc, done1 ;\ 1991 std %f30, [ADDR + CPU_TMP1] ;\ 1992 ba,pt %xcc, done1 ;\ 1993 std %f62, [ADDR + CPU_TMP1] ;\ 1994done1: 1995 1996#define LDDF_REG(REG, ADDR, TMP) \ 1997 sll REG, 3, REG ;\ 1998mark2: set start2, TMP ;\ 1999 jmp REG + TMP ;\ 2000 nop ;\ 2001start2: ba,pt %xcc, done2 ;\ 2002 ldd [ADDR + CPU_TMP1], %f0 ;\ 2003 ba,pt %xcc, done2 ;\ 2004 ldd [ADDR + CPU_TMP1], %f32 ;\ 2005 ba,pt %xcc, done2 ;\ 2006 ldd [ADDR + CPU_TMP1], %f2 ;\ 2007 ba,pt %xcc, done2 ;\ 2008 ldd [ADDR + CPU_TMP1], %f34 ;\ 2009 ba,pt %xcc, done2 ;\ 2010 ldd [ADDR + CPU_TMP1], %f4 ;\ 2011 ba,pt %xcc, done2 ;\ 2012 ldd [ADDR + CPU_TMP1], %f36 ;\ 2013 ba,pt %xcc, done2 ;\ 2014 ldd [ADDR + CPU_TMP1], %f6 ;\ 2015 ba,pt %xcc, done2 ;\ 2016 ldd [ADDR + CPU_TMP1], %f38 ;\ 2017 ba,pt %xcc, done2 ;\ 2018 ldd [ADDR + CPU_TMP1], %f8 ;\ 2019 ba,pt %xcc, done2 ;\ 2020 ldd [ADDR + CPU_TMP1], %f40 ;\ 2021 ba,pt %xcc, done2 ;\ 2022 ldd [ADDR + CPU_TMP1], %f10 ;\ 2023 ba,pt %xcc, done2 ;\ 2024 ldd [ADDR + CPU_TMP1], %f42 ;\ 2025 ba,pt %xcc, done2 ;\ 2026 ldd [ADDR + CPU_TMP1], %f12 ;\ 2027 ba,pt %xcc, done2 ;\ 2028 ldd [ADDR + CPU_TMP1], %f44 ;\ 2029 ba,pt %xcc, done2 ;\ 2030 ldd [ADDR + CPU_TMP1], %f14 ;\ 2031 ba,pt %xcc, done2 ;\ 2032 ldd [ADDR + CPU_TMP1], %f46 ;\ 2033 ba,pt %xcc, done2 ;\ 2034 ldd [ADDR + CPU_TMP1], %f16 ;\ 2035 ba,pt %xcc, done2 ;\ 2036 ldd [ADDR + CPU_TMP1], %f48 ;\ 2037 ba,pt %xcc, done2 ;\ 2038 ldd [ADDR + CPU_TMP1], %f18 ;\ 2039 ba,pt %xcc, done2 ;\ 2040 ldd [ADDR + CPU_TMP1], %f50 ;\ 2041 ba,pt %xcc, done2 ;\ 2042 ldd [ADDR + CPU_TMP1], %f20 ;\ 2043 ba,pt %xcc, done2 ;\ 2044 ldd [ADDR + CPU_TMP1], %f52 ;\ 2045 ba,pt %xcc, done2 ;\ 2046 ldd [ADDR + CPU_TMP1], %f22 ;\ 2047 ba,pt %xcc, done2 ;\ 2048 ldd [ADDR + CPU_TMP1], %f54 ;\ 2049 ba,pt %xcc, done2 ;\ 2050 ldd [ADDR + CPU_TMP1], %f24 ;\ 2051 ba,pt %xcc, done2 ;\ 2052 ldd [ADDR + CPU_TMP1], %f56 ;\ 2053 ba,pt %xcc, done2 ;\ 2054 ldd [ADDR + CPU_TMP1], %f26 ;\ 2055 ba,pt %xcc, done2 ;\ 2056 ldd [ADDR + CPU_TMP1], %f58 ;\ 2057 ba,pt %xcc, done2 ;\ 2058 ldd [ADDR + CPU_TMP1], %f28 ;\ 2059 ba,pt %xcc, done2 ;\ 2060 ldd [ADDR + CPU_TMP1], %f60 ;\ 2061 ba,pt %xcc, done2 ;\ 2062 ldd [ADDR + CPU_TMP1], %f30 ;\ 2063 ba,pt %xcc, done2 ;\ 2064 ldd [ADDR + CPU_TMP1], %f62 ;\ 2065done2: 2066 2067.lddf_exception_not_aligned: 2068 /* %g2 = sfar, %g3 = sfsr */ 2069 mov %g2, %g5 ! stash sfar 2070#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2071 sethi %hi(fpu_exists), %g2 ! check fpu_exists 2072 ld [%g2 + %lo(fpu_exists)], %g2 2073 brz,a,pn %g2, 4f 2074 nop 2075#endif 2076 CPU_ADDR(%g1, %g4) 2077 or %g0, 1, %g4 2078 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2079 2080 rdpr %tpc, %g2 2081 lda [%g2]ASI_AIUP, %g6 ! get the user's lddf instruction 2082 srl %g6, 23, %g1 ! using ldda or not? 2083 and %g1, 1, %g1 2084 brz,a,pt %g1, 2f ! check for ldda instruction 2085 nop 2086 srl %g6, 13, %g1 ! check immflag 2087 and %g1, 1, %g1 2088 rdpr %tstate, %g2 ! %tstate in %g2 2089 brnz,a,pn %g1, 1f 2090 srl %g2, 31, %g1 ! get asi from %tstate 2091 srl %g6, 5, %g1 ! get asi from instruction 2092 and %g1, 0xFF, %g1 ! imm_asi field 20931: 2094 cmp %g1, ASI_P ! primary address space 2095 be,a,pt %icc, 2f 2096 nop 2097 cmp %g1, ASI_PNF ! primary no fault address space 2098 be,a,pt %icc, 2f 2099 nop 2100 cmp %g1, ASI_S ! secondary address space 2101 be,a,pt %icc, 2f 2102 nop 2103 cmp %g1, ASI_SNF ! secondary no fault address space 2104 bne,a,pn %icc, 3f 2105 nop 21062: 2107 lduwa [%g5]ASI_USER, %g7 ! get first half of misaligned data 2108 add %g5, 4, %g5 ! increment misaligned data address 2109 lduwa [%g5]ASI_USER, %g5 ! get second half of misaligned data 2110 2111 sllx %g7, 32, %g7 2112 or %g5, %g7, %g5 ! combine data 2113 CPU_ADDR(%g7, %g1) ! save data on a per-cpu basis 2114 stx %g5, [%g7 + CPU_TMP1] ! save in cpu_tmp1 2115 2116 srl %g6, 25, %g3 ! %g6 has the instruction 2117 and %g3, 0x1F, %g3 ! %g3 has rd 2118 LDDF_REG(%g3, %g7, %g4) 2119 2120 CPU_ADDR(%g1, %g4) 2121 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2122 FAST_TRAP_DONE 21233: 2124 CPU_ADDR(%g1, %g4) 2125 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 21264: 2127 set T_USER, %g3 ! trap type in %g3 2128 or %g3, T_LDDF_ALIGN, %g3 2129 mov %g5, %g2 ! misaligned vaddr in %g2 2130 set fpu_trap, %g1 ! goto C for the little and 2131 ba,pt %xcc, sys_trap ! no fault little asi's 2132 sub %g0, 1, %g4 2133 2134.stdf_exception_not_aligned: 2135 /* %g2 = sfar, %g3 = sfsr */ 2136 mov %g2, %g5 2137 2138#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2139 sethi %hi(fpu_exists), %g7 ! check fpu_exists 2140 ld [%g7 + %lo(fpu_exists)], %g3 2141 brz,a,pn %g3, 4f 2142 nop 2143#endif 2144 CPU_ADDR(%g1, %g4) 2145 or %g0, 1, %g4 2146 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2147 2148 rdpr %tpc, %g2 2149 lda [%g2]ASI_AIUP, %g6 ! get the user's stdf instruction 2150 2151 srl %g6, 23, %g1 ! using stda or not? 2152 and %g1, 1, %g1 2153 brz,a,pt %g1, 2f ! check for stda instruction 2154 nop 2155 srl %g6, 13, %g1 ! check immflag 2156 and %g1, 1, %g1 2157 rdpr %tstate, %g2 ! %tstate in %g2 2158 brnz,a,pn %g1, 1f 2159 srl %g2, 31, %g1 ! get asi from %tstate 2160 srl %g6, 5, %g1 ! get asi from instruction 2161 and %g1, 0xff, %g1 ! imm_asi field 21621: 2163 cmp %g1, ASI_P ! primary address space 2164 be,a,pt %icc, 2f 2165 nop 2166 cmp %g1, ASI_S ! secondary address space 2167 bne,a,pn %icc, 3f 2168 nop 21692: 2170 srl %g6, 25, %g6 2171 and %g6, 0x1F, %g6 ! %g6 has rd 2172 CPU_ADDR(%g7, %g1) 2173 STDF_REG(%g6, %g7, %g4) ! STDF_REG(REG, ADDR, TMP) 2174 2175 ldx [%g7 + CPU_TMP1], %g6 2176 srlx %g6, 32, %g7 2177 stuwa %g7, [%g5]ASI_USER ! first half 2178 add %g5, 4, %g5 ! increment misaligned data address 2179 stuwa %g6, [%g5]ASI_USER ! second half 2180 2181 CPU_ADDR(%g1, %g4) 2182 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2183 FAST_TRAP_DONE 21843: 2185 CPU_ADDR(%g1, %g4) 2186 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 21874: 2188 set T_USER, %g3 ! trap type in %g3 2189 or %g3, T_STDF_ALIGN, %g3 2190 mov %g5, %g2 ! misaligned vaddr in %g2 2191 set fpu_trap, %g1 ! goto C for the little and 2192 ba,pt %xcc, sys_trap ! nofault little asi's 2193 sub %g0, 1, %g4 2194 2195#ifdef DEBUG_USER_TRAPTRACECTL 2196 2197.traptrace_freeze: 2198 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2199 TT_TRACE_L(trace_win) 2200 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2201 set trap_freeze, %g1 2202 mov 1, %g2 2203 st %g2, [%g1] 2204 FAST_TRAP_DONE 2205 2206.traptrace_unfreeze: 2207 set trap_freeze, %g1 2208 st %g0, [%g1] 2209 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2210 TT_TRACE_L(trace_win) 2211 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2212 FAST_TRAP_DONE 2213 2214#endif /* DEBUG_USER_TRAPTRACECTL */ 2215 2216.getcc: 2217 CPU_ADDR(%g1, %g2) 2218 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2219 rdpr %tstate, %g3 ! get tstate 2220 srlx %g3, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2221 set PSR_ICC, %g2 2222 and %o0, %g2, %o0 ! mask out the rest 2223 srl %o0, PSR_ICC_SHIFT, %o0 ! right justify 2224 wrpr %g0, 0, %gl 2225 mov %o0, %g1 ! move ccr to normal %g1 2226 wrpr %g0, 1, %gl 2227 ! cannot assume globals retained their values after increasing %gl 2228 CPU_ADDR(%g1, %g2) 2229 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2230 FAST_TRAP_DONE 2231 2232.setcc: 2233 CPU_ADDR(%g1, %g2) 2234 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2235 wrpr %g0, 0, %gl 2236 mov %g1, %o0 2237 wrpr %g0, 1, %gl 2238 ! cannot assume globals retained their values after increasing %gl 2239 CPU_ADDR(%g1, %g2) 2240 sll %o0, PSR_ICC_SHIFT, %g2 2241 set PSR_ICC, %g3 2242 and %g2, %g3, %g2 ! mask out rest 2243 sllx %g2, PSR_TSTATE_CC_SHIFT, %g2 2244 rdpr %tstate, %g3 ! get tstate 2245 srl %g3, 0, %g3 ! clear upper word 2246 or %g3, %g2, %g3 ! or in new bits 2247 wrpr %g3, %tstate 2248 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2249 FAST_TRAP_DONE 2250 2251/* 2252 * getpsr(void) 2253 * Note that the xcc part of the ccr is not provided. 2254 * The V8 code shows why the V9 trap is not faster: 2255 * #define GETPSR_TRAP() \ 2256 * mov %psr, %i0; jmp %l2; rett %l2+4; nop; 2257 */ 2258 2259 .type .getpsr, #function 2260.getpsr: 2261 rdpr %tstate, %g1 ! get tstate 2262 srlx %g1, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2263 set PSR_ICC, %g2 2264 and %o0, %g2, %o0 ! mask out the rest 2265 2266 rd %fprs, %g1 ! get fprs 2267 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower 2268 sllx %g2, PSR_FPRS_FEF_SHIFT, %g2 ! shift fef to V8 psr.ef 2269 or %o0, %g2, %o0 ! or result into psr.ef 2270 2271 set V9_PSR_IMPLVER, %g2 ! SI assigned impl/ver: 0xef 2272 or %o0, %g2, %o0 ! or psr.impl/ver 2273 FAST_TRAP_DONE 2274 SET_SIZE(.getpsr) 2275 2276/* 2277 * setpsr(newpsr) 2278 * Note that there is no support for ccr.xcc in the V9 code. 2279 */ 2280 2281 .type .setpsr, #function 2282.setpsr: 2283 rdpr %tstate, %g1 ! get tstate 2284! setx TSTATE_V8_UBITS, %g2 2285 or %g0, CCR_ICC, %g3 2286 sllx %g3, TSTATE_CCR_SHIFT, %g2 2287 2288 andn %g1, %g2, %g1 ! zero current user bits 2289 set PSR_ICC, %g2 2290 and %g2, %o0, %g2 ! clear all but psr.icc bits 2291 sllx %g2, PSR_TSTATE_CC_SHIFT, %g3 ! shift to tstate.ccr.icc 2292 wrpr %g1, %g3, %tstate ! write tstate 2293 2294 set PSR_EF, %g2 2295 and %g2, %o0, %g2 ! clear all but fp enable bit 2296 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef 2297 wr %g0, %g4, %fprs ! write fprs 2298 2299 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 2300 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2301 ldn [%g2 + T_LWP], %g3 ! load klwp pointer 2302 ldn [%g3 + LWP_FPU], %g2 ! get lwp_fpu pointer 2303 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs 2304 srlx %g4, 2, %g4 ! shift fef value to bit 0 2305 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en 2306 FAST_TRAP_DONE 2307 SET_SIZE(.setpsr) 2308 2309/* 2310 * getlgrp 2311 * get home lgrpid on which the calling thread is currently executing. 2312 */ 2313 .type .getlgrp, #function 2314.getlgrp: 2315 ! Thanks for the incredibly helpful comments 2316 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2317 ld [%g1 + CPU_ID], %o0 ! load cpu_id 2318 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2319 ldn [%g2 + T_LPL], %g2 ! load lpl pointer 2320 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid 2321 sra %g1, 0, %o1 2322 FAST_TRAP_DONE 2323 SET_SIZE(.getlgrp) 2324 2325/* 2326 * Entry for old 4.x trap (trap 0). 2327 */ 2328 ENTRY_NP(syscall_trap_4x) 2329 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2330 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2331 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2332 ld [%g2 + PCB_TRAP0], %g2 ! lwp->lwp_pcb.pcb_trap0addr 2333 brz,pn %g2, 1f ! has it been set? 2334 st %l0, [%g1 + CPU_TMP1] ! delay - save some locals 2335 st %l1, [%g1 + CPU_TMP2] 2336 rdpr %tnpc, %l1 ! save old tnpc 2337 wrpr %g0, %g2, %tnpc ! setup tnpc 2338 2339 mov %g1, %l0 ! save CPU struct addr 2340 wrpr %g0, 0, %gl 2341 mov %l1, %g6 ! pass tnpc to user code in %g6 2342 wrpr %g0, 1, %gl 2343 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2344 ld [%l0 + CPU_TMP1], %l0 2345 FAST_TRAP_DONE_CHK_INTR 23461: 2347 ! 2348 ! check for old syscall mmap which is the only different one which 2349 ! must be the same. Others are handled in the compatibility library. 2350 ! 2351 mov %g1, %l0 ! save CPU struct addr 2352 wrpr %g0, 0, %gl 2353 cmp %g1, OSYS_mmap ! compare to old 4.x mmap 2354 movz %icc, SYS_mmap, %g1 2355 wrpr %g0, 1, %gl 2356 ld [%l0 + CPU_TMP1], %l0 2357 SYSCALL(syscall_trap32) 2358 SET_SIZE(syscall_trap_4x) 2359 2360/* 2361 * Handler for software trap 9. 2362 * Set trap0 emulation address for old 4.x system call trap. 2363 * XXX - this should be a system call. 2364 */ 2365 ENTRY_NP(set_trap0_addr) 2366 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2367 st %l0, [%g1 + CPU_TMP1] ! save some locals 2368 st %l1, [%g1 + CPU_TMP2] 2369 mov %g1, %l0 ! preserve CPU addr 2370 wrpr %g0, 0, %gl 2371 mov %g1, %l1 2372 wrpr %g0, 1, %gl 2373 ! cannot assume globals retained their values after increasing %gl 2374 ldn [%l0 + CPU_THREAD], %g2 ! load thread pointer 2375 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2376 andn %l1, 3, %l1 ! force alignment 2377 st %l1, [%g2 + PCB_TRAP0] ! lwp->lwp_pcb.pcb_trap0addr 2378 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2379 ld [%l0 + CPU_TMP1], %l0 2380 FAST_TRAP_DONE 2381 SET_SIZE(set_trap0_addr) 2382 2383/* 2384 * mmu_trap_tl1 2385 * trap handler for unexpected mmu traps. 2386 * simply checks if the trap was a user lddf/stdf alignment trap, in which 2387 * case we go to fpu_trap or a user trap from the window handler, in which 2388 * case we go save the state on the pcb. Otherwise, we go to ptl1_panic. 2389 */ 2390 .type mmu_trap_tl1, #function 2391mmu_trap_tl1: 2392#ifdef TRAPTRACE 2393 TRACE_PTR(%g5, %g6) 2394 GET_TRACE_TICK(%g6) 2395 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2396 TRACE_SAVE_TL_GL_REGS(%g5, %g6) 2397 rdpr %tt, %g6 2398 stha %g6, [%g5 + TRAP_ENT_TT]%asi 2399 rdpr %tstate, %g6 2400 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi 2401 stna %sp, [%g5 + TRAP_ENT_SP]%asi 2402 stna %g0, [%g5 + TRAP_ENT_TR]%asi 2403 rdpr %tpc, %g6 2404 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2405 MMU_FAULT_STATUS_AREA(%g6) 2406 ldx [%g6 + MMFSA_D_ADDR], %g6 2407 stna %g6, [%g5 + TRAP_ENT_F1]%asi ! MMU fault address 2408 CPU_PADDR(%g7, %g6); 2409 add %g7, CPU_TL1_HDLR, %g7 2410 lda [%g7]ASI_MEM, %g6 2411 stna %g6, [%g5 + TRAP_ENT_F2]%asi 2412 MMU_FAULT_STATUS_AREA(%g6) 2413 ldx [%g6 + MMFSA_D_TYPE], %g7 ! XXXQ should be a MMFSA_F_ constant? 2414 ldx [%g6 + MMFSA_D_CTX], %g6 2415 sllx %g6, SFSR_CTX_SHIFT, %g6 2416 or %g6, %g7, %g6 2417 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! MMU context/type 2418 set 0xdeadbeef, %g6 2419 stna %g6, [%g5 + TRAP_ENT_F4]%asi 2420 TRACE_NEXT(%g5, %g6, %g7) 2421#endif /* TRAPTRACE */ 2422 CPU_PADDR(%g7, %g6); 2423 add %g7, CPU_TL1_HDLR, %g7 ! %g7 = &cpu_m.tl1_hdlr (PA) 2424 lda [%g7]ASI_MEM, %g6 2425 brz,a,pt %g6, 1f 2426 nop 2427 sta %g0, [%g7]ASI_MEM 2428 ! XXXQ need to setup registers for sfmmu_mmu_trap? 2429 ba,a,pt %xcc, sfmmu_mmu_trap ! handle page faults 24301: 2431 rdpr %tpc, %g7 2432 /* in user_rtt? */ 2433 set rtt_fill_start, %g6 2434 cmp %g7, %g6 2435 blu,pn %xcc, 6f 2436 .empty 2437 set rtt_fill_end, %g6 2438 cmp %g7, %g6 2439 bgeu,pn %xcc, 6f 2440 nop 2441 set fault_rtt_fn1, %g7 2442 ba,a 7f 24436: 2444 ! check to see if the trap pc is in a window spill/fill handling 2445 rdpr %tpc, %g7 2446 /* tpc should be in the trap table */ 2447 set trap_table, %g6 2448 cmp %g7, %g6 2449 blu,a,pn %xcc, ptl1_panic 2450 mov PTL1_BAD_MMUTRAP, %g1 2451 set etrap_table, %g6 2452 cmp %g7, %g6 2453 bgeu,a,pn %xcc, ptl1_panic 2454 mov PTL1_BAD_MMUTRAP, %g1 2455 ! pc is inside the trap table, convert to trap type 2456 srl %g7, 5, %g6 ! XXXQ need #define 2457 and %g6, 0x1ff, %g6 ! XXXQ need #define 2458 ! and check for a window trap type 2459 and %g6, WTRAP_TTMASK, %g6 2460 cmp %g6, WTRAP_TYPE 2461 bne,a,pn %xcc, ptl1_panic 2462 mov PTL1_BAD_MMUTRAP, %g1 2463 andn %g7, WTRAP_ALIGN, %g7 /* 128 byte aligned */ 2464 add %g7, WTRAP_FAULTOFF, %g7 2465 24667: 2467 ! Arguments are passed in the global set active after the 2468 ! 'done' instruction. Before switching sets, must save 2469 ! the calculated next pc 2470 wrpr %g0, %g7, %tnpc 2471 wrpr %g0, 1, %gl 2472 rdpr %tt, %g5 2473 MMU_FAULT_STATUS_AREA(%g7) 2474 cmp %g5, T_ALIGNMENT 2475 be,pn %xcc, 1f 2476 ldx [%g7 + MMFSA_D_ADDR], %g6 2477 ldx [%g7 + MMFSA_D_CTX], %g7 2478 srlx %g6, MMU_PAGESHIFT, %g6 /* align address */ 2479 cmp %g7, USER_CONTEXT_TYPE 2480 sllx %g6, MMU_PAGESHIFT, %g6 2481 movgu %icc, USER_CONTEXT_TYPE, %g7 2482 or %g6, %g7, %g6 /* TAG_ACCESS */ 24831: 2484 done 2485 SET_SIZE(mmu_trap_tl1) 2486 2487/* 2488 * Several traps use kmdb_trap and kmdb_trap_tl1 as their handlers. These 2489 * traps are valid only when kmdb is loaded. When the debugger is active, 2490 * the code below is rewritten to transfer control to the appropriate 2491 * debugger entry points. 2492 */ 2493 .global kmdb_trap 2494 .align 8 2495kmdb_trap: 2496 ba,a trap_table0 2497 jmp %g1 + 0 2498 nop 2499 2500 .global kmdb_trap_tl1 2501 .align 8 2502kmdb_trap_tl1: 2503 ba,a trap_table0 2504 jmp %g1 + 0 2505 nop 2506 2507/* 2508 * This entry is copied from OBP's trap table during boot. 2509 */ 2510 .global obp_bpt 2511 .align 8 2512obp_bpt: 2513 NOT 2514 2515 2516 2517#ifdef TRAPTRACE 2518/* 2519 * TRAPTRACE support. 2520 * labels here are branched to with "rd %pc, %g7" in the delay slot. 2521 * Return is done by "jmp %g7 + 4". 2522 */ 2523 2524trace_dmmu: 2525 TRACE_PTR(%g3, %g6) 2526 GET_TRACE_TICK(%g6) 2527 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2528 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2529 rdpr %tt, %g6 2530 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2531 rdpr %tstate, %g6 2532 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2533 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2534 rdpr %tpc, %g6 2535 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2536 MMU_FAULT_STATUS_AREA(%g6) 2537 ldx [%g6 + MMFSA_D_ADDR], %g4 2538 stxa %g4, [%g3 + TRAP_ENT_TR]%asi 2539 ldx [%g6 + MMFSA_D_CTX], %g4 2540 stxa %g4, [%g3 + TRAP_ENT_F1]%asi 2541 ldx [%g6 + MMFSA_D_TYPE], %g4 2542 stxa %g4, [%g3 + TRAP_ENT_F2]%asi 2543 stxa %g6, [%g3 + TRAP_ENT_F3]%asi 2544 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2545 TRACE_NEXT(%g3, %g4, %g5) 2546 jmp %g7 + 4 2547 nop 2548 2549trace_immu: 2550 TRACE_PTR(%g3, %g6) 2551 GET_TRACE_TICK(%g6) 2552 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2553 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2554 rdpr %tt, %g6 2555 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2556 rdpr %tstate, %g6 2557 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2558 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2559 rdpr %tpc, %g6 2560 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2561 MMU_FAULT_STATUS_AREA(%g6) 2562 ldx [%g6 + MMFSA_I_ADDR], %g4 2563 stxa %g4, [%g3 + TRAP_ENT_TR]%asi 2564 ldx [%g6 + MMFSA_I_CTX], %g4 2565 stxa %g4, [%g3 + TRAP_ENT_F1]%asi 2566 ldx [%g6 + MMFSA_I_TYPE], %g4 2567 stxa %g4, [%g3 + TRAP_ENT_F2]%asi 2568 stxa %g6, [%g3 + TRAP_ENT_F3]%asi 2569 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2570 TRACE_NEXT(%g3, %g4, %g5) 2571 jmp %g7 + 4 2572 nop 2573 2574trace_gen: 2575 TRACE_PTR(%g3, %g6) 2576 GET_TRACE_TICK(%g6) 2577 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2578 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2579 rdpr %tt, %g6 2580 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2581 rdpr %tstate, %g6 2582 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2583 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2584 rdpr %tpc, %g6 2585 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2586 stna %g0, [%g3 + TRAP_ENT_TR]%asi 2587 stna %g0, [%g3 + TRAP_ENT_F1]%asi 2588 stna %g0, [%g3 + TRAP_ENT_F2]%asi 2589 stna %g0, [%g3 + TRAP_ENT_F3]%asi 2590 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2591 TRACE_NEXT(%g3, %g4, %g5) 2592 jmp %g7 + 4 2593 nop 2594 2595trace_win: 2596 TRACE_WIN_INFO(0, %l0, %l1, %l2) 2597 ! Keep the locals as clean as possible, caller cleans %l4 2598 clr %l2 2599 clr %l1 2600 jmp %l4 + 4 2601 clr %l0 2602 2603/* 2604 * Trace a tsb hit 2605 * g1 = tsbe pointer (in/clobbered) 2606 * g2 = tag access register (in) 2607 * g3 - g4 = scratch (clobbered) 2608 * g5 = tsbe data (in) 2609 * g6 = scratch (clobbered) 2610 * g7 = pc we jumped here from (in) 2611 */ 2612 2613 ! Do not disturb %g5, it will be used after the trace 2614 ALTENTRY(trace_tsbhit) 2615 TRACE_TSBHIT(0) 2616 jmp %g7 + 4 2617 nop 2618 2619/* 2620 * Trace a TSB miss 2621 * 2622 * g1 = tsb8k pointer (in) 2623 * g2 = tag access register (in) 2624 * g3 = tsb4m pointer (in) 2625 * g4 = tsbe tag (in/clobbered) 2626 * g5 - g6 = scratch (clobbered) 2627 * g7 = pc we jumped here from (in) 2628 */ 2629 .global trace_tsbmiss 2630trace_tsbmiss: 2631 membar #Sync 2632 sethi %hi(FLUSH_ADDR), %g6 2633 flush %g6 2634 TRACE_PTR(%g5, %g6) 2635 GET_TRACE_TICK(%g6) 2636 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2637 stna %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access 2638 stna %g4, [%g5 + TRAP_ENT_F1]%asi ! XXX? tsb tag 2639 rdpr %tnpc, %g6 2640 stna %g6, [%g5 + TRAP_ENT_F2]%asi 2641 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer 2642 rdpr %tpc, %g6 2643 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2644 TRACE_SAVE_TL_GL_REGS(%g5, %g6) 2645 rdpr %tt, %g6 2646 or %g6, TT_MMU_MISS, %g4 2647 stha %g4, [%g5 + TRAP_ENT_TT]%asi 2648 mov MMFSA_D_ADDR, %g4 2649 cmp %g6, FAST_IMMU_MISS_TT 2650 move %xcc, MMFSA_I_ADDR, %g4 2651 cmp %g6, T_INSTR_MMU_MISS 2652 move %xcc, MMFSA_I_ADDR, %g4 2653 MMU_FAULT_STATUS_AREA(%g6) 2654 ldx [%g6 + %g4], %g6 2655 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! tag target 2656 cmp %g4, MMFSA_D_ADDR 2657 move %xcc, MMFSA_D_CTX, %g4 2658 movne %xcc, MMFSA_I_CTX, %g4 2659 MMU_FAULT_STATUS_AREA(%g6) 2660 ldx [%g6 + %g4], %g6 2661 stxa %g6, [%g5 + TRAP_ENT_F4]%asi ! context ID 2662 stna %g3, [%g5 + TRAP_ENT_TR]%asi ! tsb4m pointer 2663 TRACE_NEXT(%g5, %g4, %g6) 2664 jmp %g7 + 4 2665 nop 2666 2667/* 2668 * g2 = tag access register (in) 2669 * g3 = ctx type (0, 1 or 2) (in) (not used) 2670 */ 2671trace_dataprot: 2672 membar #Sync 2673 sethi %hi(FLUSH_ADDR), %g6 2674 flush %g6 2675 TRACE_PTR(%g1, %g6) 2676 GET_TRACE_TICK(%g6) 2677 stxa %g6, [%g1 + TRAP_ENT_TICK]%asi 2678 rdpr %tpc, %g6 2679 stna %g6, [%g1 + TRAP_ENT_TPC]%asi 2680 rdpr %tstate, %g6 2681 stxa %g6, [%g1 + TRAP_ENT_TSTATE]%asi 2682 stna %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg 2683 stna %g0, [%g1 + TRAP_ENT_F1]%asi 2684 stna %g0, [%g1 + TRAP_ENT_F2]%asi 2685 stna %g0, [%g1 + TRAP_ENT_F3]%asi 2686 stna %g0, [%g1 + TRAP_ENT_F4]%asi 2687 TRACE_SAVE_TL_GL_REGS(%g1, %g6) 2688 rdpr %tt, %g6 2689 stha %g6, [%g1 + TRAP_ENT_TT]%asi 2690 mov MMFSA_D_CTX, %g4 2691 cmp %g6, FAST_IMMU_MISS_TT 2692 move %xcc, MMFSA_I_CTX, %g4 2693 cmp %g6, T_INSTR_MMU_MISS 2694 move %xcc, MMFSA_I_CTX, %g4 2695 MMU_FAULT_STATUS_AREA(%g6) 2696 ldx [%g6 + %g4], %g6 2697 stxa %g6, [%g1 + TRAP_ENT_TR]%asi ! context ID 2698 TRACE_NEXT(%g1, %g4, %g5) 2699 jmp %g7 + 4 2700 nop 2701 2702#endif /* TRAPTRACE */ 2703 2704/* 2705 * Handle watchdog reset trap. Enable the MMU using the MMU_ENABLE 2706 * HV service, which requires the return target to be specified as a VA 2707 * since we are enabling the MMU. We set the target to ptl1_panic. 2708 */ 2709 2710 .type .watchdog_trap, #function 2711.watchdog_trap: 2712 mov 1, %o0 2713 setx ptl1_panic, %g2, %o1 2714 mov MMU_ENABLE, %o5 2715 ta FAST_TRAP 2716 done 2717 SET_SIZE(.watchdog_trap) 2718/* 2719 * synthesize for trap(): SFAR in %g2, SFSR in %g3 2720 */ 2721 .type .dmmu_exc_lddf_not_aligned, #function 2722.dmmu_exc_lddf_not_aligned: 2723 MMU_FAULT_STATUS_AREA(%g3) 2724 ldx [%g3 + MMFSA_D_ADDR], %g2 2725 /* Fault type not available in MMU fault status area */ 2726 mov MMFSA_F_UNALIGN, %g1 2727 ldx [%g3 + MMFSA_D_CTX], %g3 2728 sllx %g3, SFSR_CTX_SHIFT, %g3 2729 btst 1, %sp 2730 bnz,pt %xcc, .lddf_exception_not_aligned 2731 or %g3, %g1, %g3 /* SFSR */ 2732 ba,a,pt %xcc, .mmu_exception_not_aligned 2733 SET_SIZE(.dmmu_exc_lddf_not_aligned) 2734 2735/* 2736 * synthesize for trap(): SFAR in %g2, SFSR in %g3 2737 */ 2738 .type .dmmu_exc_stdf_not_aligned, #function 2739.dmmu_exc_stdf_not_aligned: 2740 MMU_FAULT_STATUS_AREA(%g3) 2741 ldx [%g3 + MMFSA_D_ADDR], %g2 2742 /* Fault type not available in MMU fault status area */ 2743 mov MMFSA_F_UNALIGN, %g1 2744 ldx [%g3 + MMFSA_D_CTX], %g3 2745 sllx %g3, SFSR_CTX_SHIFT, %g3 2746 btst 1, %sp 2747 bnz,pt %xcc, .stdf_exception_not_aligned 2748 or %g3, %g1, %g3 /* SFSR */ 2749 ba,a,pt %xcc, .mmu_exception_not_aligned 2750 SET_SIZE(.dmmu_exc_stdf_not_aligned) 2751 2752 .type .dmmu_exception, #function 2753.dmmu_exception: 2754 MMU_FAULT_STATUS_AREA(%g3) 2755 ldx [%g3 + MMFSA_D_ADDR], %g2 2756 ldx [%g3 + MMFSA_D_TYPE], %g1 2757 ldx [%g3 + MMFSA_D_CTX], %g4 2758 srlx %g2, MMU_PAGESHIFT, %g2 /* align address */ 2759 sllx %g2, MMU_PAGESHIFT, %g2 2760 sllx %g4, SFSR_CTX_SHIFT, %g3 2761 or %g3, %g1, %g3 /* SFSR */ 2762 cmp %g4, USER_CONTEXT_TYPE 2763 movgeu %icc, USER_CONTEXT_TYPE, %g4 2764 or %g2, %g4, %g2 /* TAG_ACCESS */ 2765 ba,pt %xcc, .mmu_exception_end 2766 mov T_DATA_EXCEPTION, %g1 2767 SET_SIZE(.dmmu_exception) 2768 2769/* 2770 * fast_trap_done, fast_trap_done_chk_intr: 2771 * 2772 * Due to the design of UltraSPARC pipeline, pending interrupts are not 2773 * taken immediately after a RETRY or DONE instruction which causes IE to 2774 * go from 0 to 1. Instead, the instruction at %tpc or %tnpc is allowed 2775 * to execute first before taking any interrupts. If that instruction 2776 * results in other traps, and if the corresponding trap handler runs 2777 * entirely at TL=1 with interrupts disabled, then pending interrupts 2778 * won't be taken until after yet another instruction following the %tpc 2779 * or %tnpc. 2780 * 2781 * A malicious user program can use this feature to block out interrupts 2782 * for extended durations, which can result in send_mondo_timeout kernel 2783 * panic. 2784 * 2785 * This problem is addressed by servicing any pending interrupts via 2786 * sys_trap before returning back to the user mode from a fast trap 2787 * handler. The "done" instruction within a fast trap handler, which 2788 * runs entirely at TL=1 with interrupts disabled, is replaced with the 2789 * FAST_TRAP_DONE macro, which branches control to this fast_trap_done 2790 * entry point. 2791 * 2792 * We check for any pending interrupts here and force a sys_trap to 2793 * service those interrupts, if any. To minimize overhead, pending 2794 * interrupts are checked if the %tpc happens to be at 16K boundary, 2795 * which allows a malicious program to execute at most 4K consecutive 2796 * instructions before we service any pending interrupts. If a worst 2797 * case fast trap handler takes about 2 usec, then interrupts will be 2798 * blocked for at most 8 msec, less than a clock tick. 2799 * 2800 * For the cases where we don't know if the %tpc will cross a 16K 2801 * boundary, we can't use the above optimization and always process 2802 * any pending interrupts via fast_frap_done_chk_intr entry point. 2803 * 2804 * Entry Conditions: 2805 * %pstate am:0 priv:1 ie:0 2806 * globals are AG (not normal globals) 2807 */ 2808 2809 .global fast_trap_done, fast_trap_done_chk_intr 2810fast_trap_done: 2811 rdpr %tpc, %g5 2812 sethi %hi(0xffffc000), %g6 ! 1's complement of 0x3fff 2813 andncc %g5, %g6, %g0 ! check lower 14 bits of %tpc 2814 bz,pn %icc, 1f ! branch if zero (lower 32 bits only) 2815 nop 2816 done 2817 2818fast_trap_done_chk_intr: 28191: rd SOFTINT, %g6 2820 brnz,pn %g6, 2f ! branch if any pending intr 2821 nop 2822 done 2823 28242: 2825 /* 2826 * We get here if there are any pending interrupts. 2827 * Adjust %tpc/%tnpc as we'll be resuming via "retry" 2828 * instruction. 2829 */ 2830 rdpr %tnpc, %g5 2831 wrpr %g0, %g5, %tpc 2832 add %g5, 4, %g5 2833 wrpr %g0, %g5, %tnpc 2834 2835 /* 2836 * Force a dummy sys_trap call so that interrupts can be serviced. 2837 */ 2838 set fast_trap_dummy_call, %g1 2839 ba,pt %xcc, sys_trap 2840 mov -1, %g4 2841 2842fast_trap_dummy_call: 2843 retl 2844 nop 2845 2846/* 2847 * Currently the brand syscall interposition code is not enabled by 2848 * default. Instead, when a branded zone is first booted the brand 2849 * infrastructure will patch the trap table so that the syscall 2850 * entry points are redirected to syscall_wrapper32 and syscall_wrapper 2851 * for ILP32 and LP64 syscalls respectively. this is done in 2852 * brand_plat_interposition_enable(). Note that the syscall wrappers 2853 * below do not collect any trap trace data since the syscall hot patch 2854 * points are reached after trap trace data has already been collected. 2855 */ 2856#define BRAND_CALLBACK(callback_id) \ 2857 CPU_ADDR(%g2, %g1) /* load CPU struct addr to %g2 */ ;\ 2858 ldn [%g2 + CPU_THREAD], %g3 /* load thread pointer */ ;\ 2859 ldn [%g3 + T_PROCP], %g3 /* get proc pointer */ ;\ 2860 ldn [%g3 + P_BRAND], %g3 /* get brand pointer */ ;\ 2861 brz %g3, 1f /* No brand? No callback. */ ;\ 2862 nop ;\ 2863 ldn [%g3 + B_MACHOPS], %g3 /* get machops list */ ;\ 2864 ldn [%g3 + (callback_id << 3)], %g3 ;\ 2865 brz %g3, 1f ;\ 2866 /* \ 2867 * This isn't pretty. We want a low-latency way for the callback \ 2868 * routine to decline to do anything. We just pass in an address \ 2869 * the routine can directly jmp back to, pretending that nothing \ 2870 * has happened. \ 2871 * \ 2872 * %g1: return address (where the brand handler jumps back to) \ 2873 * %g2: address of CPU structure \ 2874 * %g3: address of brand handler (where we will jump to) \ 2875 */ \ 2876 mov %pc, %g1 ;\ 2877 add %g1, 16, %g1 ;\ 2878 jmp %g3 ;\ 2879 nop ;\ 28801: 2881 2882 ENTRY_NP(syscall_wrapper32) 2883 BRAND_CALLBACK(BRAND_CB_SYSCALL32) 2884 SYSCALL_NOTT(syscall_trap32) 2885 SET_SIZE(syscall_wrapper32) 2886 2887 ENTRY_NP(syscall_wrapper) 2888 BRAND_CALLBACK(BRAND_CB_SYSCALL) 2889 SYSCALL_NOTT(syscall_trap) 2890 SET_SIZE(syscall_wrapper) 2891 2892#endif /* lint */ 2893