1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Hypervisor calls 29 */ 30 31#include <sys/asm_linkage.h> 32#include <sys/machasi.h> 33#include <sys/machparam.h> 34#include <sys/hypervisor_api.h> 35 36#if defined(lint) || defined(__lint) 37 38/*ARGSUSED*/ 39uint64_t 40hv_mach_exit(uint64_t exit_code) 41{ return (0); } 42 43uint64_t 44hv_mach_sir(void) 45{ return (0); } 46 47/*ARGSUSED*/ 48uint64_t 49hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 50{ return (0); } 51 52/*ARGSUSED*/ 53uint64_t 54hv_cpu_stop(uint64_t cpuid) 55{ return (0); } 56 57/*ARGSUSED*/ 58uint64_t 59hv_cpu_set_rtba(uint64_t *rtba) 60{ return (0); } 61 62/*ARGSUSED*/ 63int64_t 64hv_cnputchar(uint8_t ch) 65{ return (0); } 66 67/*ARGSUSED*/ 68int64_t 69hv_cngetchar(uint8_t *ch) 70{ return (0); } 71 72/*ARGSUSED*/ 73uint64_t 74hv_tod_get(uint64_t *seconds) 75{ return (0); } 76 77/*ARGSUSED*/ 78uint64_t 79hv_tod_set(uint64_t seconds) 80{ return (0);} 81 82/*ARGSUSED*/ 83uint64_t 84hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 85{ return (0); } 86 87/*ARGSUSED */ 88uint64_t 89hv_mmu_fault_area_conf(void *raddr) 90{ return (0); } 91 92/*ARGSUSED*/ 93uint64_t 94hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 95{ return (0); } 96 97/*ARGSUSED*/ 98uint64_t 99hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 100{ return (0); } 101 102/*ARGSUSED*/ 103uint64_t 104hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 105{ return (0); } 106 107#ifdef SET_MMU_STATS 108/*ARGSUSED*/ 109uint64_t 110hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 111{ return (0); } 112#endif /* SET_MMU_STATS */ 113 114/*ARGSUSED*/ 115uint64_t 116hv_cpu_qconf(int queue, uint64_t paddr, int size) 117{ return (0); } 118 119/*ARGSUSED*/ 120uint64_t 121hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 122{ return (0); } 123 124/*ARGSUSED*/ 125uint64_t 126hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 127{ return (0); } 128 129/*ARGSUSED*/ 130uint64_t 131hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 132{ return (0); } 133 134/*ARGSUSED*/ 135uint64_t 136hvio_intr_getstate(uint64_t sysino, int *intr_state) 137{ return (0); } 138 139/*ARGSUSED*/ 140uint64_t 141hvio_intr_setstate(uint64_t sysino, int intr_state) 142{ return (0); } 143 144/*ARGSUSED*/ 145uint64_t 146hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 147{ return (0); } 148 149/*ARGSUSED*/ 150uint64_t 151hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 152{ return (0); } 153 154uint64_t 155hv_cpu_yield(void) 156{ return (0); } 157 158/*ARGSUSED*/ 159uint64_t 160hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 161{ return (0); } 162 163/*ARGSUSED*/ 164uint64_t 165hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 166{ return (0); } 167 168/*ARGSUSED*/ 169uint64_t 170hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 171{ return (0); } 172 173/*ARGSUSED*/ 174uint64_t 175hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 176{ return (0); } 177 178/*ARGSUSED*/ 179uint64_t 180hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 181{ return (0); } 182 183/*ARGSUSED*/ 184uint64_t 185hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 186{ return (0); } 187 188/*ARGSUSED*/ 189uint64_t 190hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 191{ return (0); } 192 193/*ARGSUSED*/ 194uint64_t 195hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 196{ return (0); } 197 198/*ARGSUSED*/ 199uint64_t 200hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 201{ return (0); } 202 203/*ARGSUSED*/ 204uint64_t 205hv_ra2pa(uint64_t ra) 206{ return (0); } 207 208/*ARGSUSED*/ 209uint64_t 210hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 211{ return (0); } 212 213/*ARGSUSED*/ 214uint64_t 215hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 216{ return (0); } 217 218/*ARGSUSED*/ 219uint64_t 220hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 221{ return (0); } 222 223/*ARGSUSED*/ 224uint64_t 225hv_ldc_tx_get_state(uint64_t channel, 226 uint64_t *headp, uint64_t *tailp, uint64_t *state) 227{ return (0); } 228 229/*ARGSUSED*/ 230uint64_t 231hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 232{ return (0); } 233 234/*ARGSUSED*/ 235uint64_t 236hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 237{ return (0); } 238 239/*ARGSUSED*/ 240uint64_t 241hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 242{ return (0); } 243 244/*ARGSUSED*/ 245uint64_t 246hv_ldc_rx_get_state(uint64_t channel, 247 uint64_t *headp, uint64_t *tailp, uint64_t *state) 248{ return (0); } 249 250/*ARGSUSED*/ 251uint64_t 252hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 253{ return (0); } 254 255/*ARGSUSED*/ 256uint64_t 257hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 258{ return (0); } 259 260/*ARGSUSED*/ 261uint64_t 262hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 263{ return (0); } 264 265/*ARGSUSED*/ 266uint64_t 267hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 268 uint64_t raddr, uint64_t length, uint64_t *lengthp) 269{ return (0); } 270 271/*ARGSUSED*/ 272uint64_t 273hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 274{ return (0); } 275 276/*ARGSUSED*/ 277uint64_t 278hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 279{ return (0); } 280 281/*ARGSUSED*/ 282uint64_t 283hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 284{ return (0); } 285 286/*ARGSUSED*/ 287uint64_t 288hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 289{ return (0); } 290 291/*ARGSUSED*/ 292uint64_t 293hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 294{ return (0); } 295 296/*ARGSUSED*/ 297uint64_t 298hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 299{ return (0); } 300 301/*ARGSUSED*/ 302uint64_t 303hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 304{ return (0); } 305 306/*ARGSUSED*/ 307uint64_t 308hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 309{ return (0); } 310 311/*ARGSUSED*/ 312uint64_t 313hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 314{ return (0); } 315 316/*ARGSUSED*/ 317uint64_t 318hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 319 uint64_t *supported_minor) 320{ return (0); } 321 322/*ARGSUSED*/ 323uint64_t 324hv_tm_enable(uint64_t enable) 325{ return (0); } 326 327/*ARGSUSED*/ 328uint64_t 329hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 330{ return (0); } 331 332/*ARGSUSED*/ 333int64_t 334hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount) 335{ return (0); } 336 337/*ARGSUSED*/ 338int64_t 339hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount) 340{ return (0); } 341 342/*ARGSUSED*/ 343uint64_t 344hv_soft_state_set(uint64_t state, uint64_t string) 345{ return (0); } 346 347/*ARGSUSED*/ 348uint64_t 349hv_soft_state_get(uint64_t string, uint64_t *state) 350{ return (0); }uint64_t 351hv_guest_suspend(void) 352{ return (0); } 353 354/*ARGSUSED*/ 355uint64_t 356hv_tick_set_npt(uint64_t npt) 357{ return (0); } 358 359/*ARGSUSED*/ 360uint64_t 361hv_stick_set_npt(uint64_t npt) 362{ return (0); } 363 364/*ARGSUSED*/ 365uint64_t 366hv_reboot_data_set(uint64_t buffer_ra, uint64_t buffer_len) 367{ return (0); } 368 369#else /* lint || __lint */ 370 371 /* 372 * int hv_mach_exit(uint64_t exit_code) 373 */ 374 ENTRY(hv_mach_exit) 375 mov HV_MACH_EXIT, %o5 376 ta FAST_TRAP 377 retl 378 nop 379 SET_SIZE(hv_mach_exit) 380 381 /* 382 * uint64_t hv_mach_sir(void) 383 */ 384 ENTRY(hv_mach_sir) 385 mov HV_MACH_SIR, %o5 386 ta FAST_TRAP 387 retl 388 nop 389 SET_SIZE(hv_mach_sir) 390 391 /* 392 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 393 * uint64_t arg) 394 */ 395 ENTRY(hv_cpu_start) 396 mov HV_CPU_START, %o5 397 ta FAST_TRAP 398 retl 399 nop 400 SET_SIZE(hv_cpu_start) 401 402 /* 403 * hv_cpu_stop(uint64_t cpuid) 404 */ 405 ENTRY(hv_cpu_stop) 406 mov HV_CPU_STOP, %o5 407 ta FAST_TRAP 408 retl 409 nop 410 SET_SIZE(hv_cpu_stop) 411 412 /* 413 * hv_cpu_set_rtba(uint64_t *rtba) 414 */ 415 ENTRY(hv_cpu_set_rtba) 416 mov %o0, %o2 417 ldx [%o2], %o0 418 mov HV_CPU_SET_RTBA, %o5 419 ta FAST_TRAP 420 stx %o1, [%o2] 421 retl 422 nop 423 SET_SIZE(hv_cpu_set_rtba) 424 425 /* 426 * int64_t hv_cnputchar(uint8_t ch) 427 */ 428 ENTRY(hv_cnputchar) 429 mov CONS_PUTCHAR, %o5 430 ta FAST_TRAP 431 retl 432 nop 433 SET_SIZE(hv_cnputchar) 434 435 /* 436 * int64_t hv_cngetchar(uint8_t *ch) 437 */ 438 ENTRY(hv_cngetchar) 439 mov %o0, %o2 440 mov CONS_GETCHAR, %o5 441 ta FAST_TRAP 442 brnz,a %o0, 1f ! failure, just return error 443 nop 444 445 cmp %o1, H_BREAK 446 be 1f 447 mov %o1, %o0 448 449 cmp %o1, H_HUP 450 be 1f 451 mov %o1, %o0 452 453 stb %o1, [%o2] ! success, save character and return 0 454 mov 0, %o0 4551: 456 retl 457 nop 458 SET_SIZE(hv_cngetchar) 459 460 ENTRY(hv_tod_get) 461 mov %o0, %o4 462 mov TOD_GET, %o5 463 ta FAST_TRAP 464 retl 465 stx %o1, [%o4] 466 SET_SIZE(hv_tod_get) 467 468 ENTRY(hv_tod_set) 469 mov TOD_SET, %o5 470 ta FAST_TRAP 471 retl 472 nop 473 SET_SIZE(hv_tod_set) 474 475 /* 476 * Map permanent address 477 * arg0 vaddr (%o0) 478 * arg1 context (%o1) 479 * arg2 tte (%o2) 480 * arg3 flags (%o3) 0x1=d 0x2=i 481 */ 482 ENTRY(hv_mmu_map_perm_addr) 483 mov MAP_PERM_ADDR, %o5 484 ta FAST_TRAP 485 retl 486 nop 487 SET_SIZE(hv_mmu_map_perm_addr) 488 489 /* 490 * hv_mmu_fault_area_conf(void *raddr) 491 */ 492 ENTRY(hv_mmu_fault_area_conf) 493 mov %o0, %o2 494 ldx [%o2], %o0 495 mov MMU_SET_INFOPTR, %o5 496 ta FAST_TRAP 497 stx %o1, [%o2] 498 retl 499 nop 500 SET_SIZE(hv_mmu_fault_area_conf) 501 502 /* 503 * Unmap permanent address 504 * arg0 vaddr (%o0) 505 * arg1 context (%o1) 506 * arg2 flags (%o2) 0x1=d 0x2=i 507 */ 508 ENTRY(hv_mmu_unmap_perm_addr) 509 mov UNMAP_PERM_ADDR, %o5 510 ta FAST_TRAP 511 retl 512 nop 513 SET_SIZE(hv_mmu_unmap_perm_addr) 514 515 /* 516 * Set TSB for context 0 517 * arg0 ntsb_descriptor (%o0) 518 * arg1 desc_ra (%o1) 519 */ 520 ENTRY(hv_set_ctx0) 521 mov MMU_TSB_CTX0, %o5 522 ta FAST_TRAP 523 retl 524 nop 525 SET_SIZE(hv_set_ctx0) 526 527 /* 528 * Set TSB for context non0 529 * arg0 ntsb_descriptor (%o0) 530 * arg1 desc_ra (%o1) 531 */ 532 ENTRY(hv_set_ctxnon0) 533 mov MMU_TSB_CTXNON0, %o5 534 ta FAST_TRAP 535 retl 536 nop 537 SET_SIZE(hv_set_ctxnon0) 538 539#ifdef SET_MMU_STATS 540 /* 541 * Returns old stat area on success 542 */ 543 ENTRY(hv_mmu_set_stat_area) 544 mov MMU_STAT_AREA, %o5 545 ta FAST_TRAP 546 retl 547 nop 548 SET_SIZE(hv_mmu_set_stat_area) 549#endif /* SET_MMU_STATS */ 550 551 /* 552 * CPU Q Configure 553 * arg0 queue (%o0) 554 * arg1 Base address RA (%o1) 555 * arg2 Size (%o2) 556 */ 557 ENTRY(hv_cpu_qconf) 558 mov HV_CPU_QCONF, %o5 559 ta FAST_TRAP 560 retl 561 nop 562 SET_SIZE(hv_cpu_qconf) 563 564 /* 565 * arg0 - devhandle 566 * arg1 - devino 567 * 568 * ret0 - status 569 * ret1 - sysino 570 */ 571 ENTRY(hvio_intr_devino_to_sysino) 572 mov HVIO_INTR_DEVINO2SYSINO, %o5 573 ta FAST_TRAP 574 brz,a %o0, 1f 575 stx %o1, [%o2] 5761: retl 577 nop 578 SET_SIZE(hvio_intr_devino_to_sysino) 579 580 /* 581 * arg0 - sysino 582 * 583 * ret0 - status 584 * ret1 - intr_valid_state 585 */ 586 ENTRY(hvio_intr_getvalid) 587 mov %o1, %o2 588 mov HVIO_INTR_GETVALID, %o5 589 ta FAST_TRAP 590 brz,a %o0, 1f 591 stuw %o1, [%o2] 5921: retl 593 nop 594 SET_SIZE(hvio_intr_getvalid) 595 596 /* 597 * arg0 - sysino 598 * arg1 - intr_valid_state 599 * 600 * ret0 - status 601 */ 602 ENTRY(hvio_intr_setvalid) 603 mov HVIO_INTR_SETVALID, %o5 604 ta FAST_TRAP 605 retl 606 nop 607 SET_SIZE(hvio_intr_setvalid) 608 609 /* 610 * arg0 - sysino 611 * 612 * ret0 - status 613 * ret1 - intr_state 614 */ 615 ENTRY(hvio_intr_getstate) 616 mov %o1, %o2 617 mov HVIO_INTR_GETSTATE, %o5 618 ta FAST_TRAP 619 brz,a %o0, 1f 620 stuw %o1, [%o2] 6211: retl 622 nop 623 SET_SIZE(hvio_intr_getstate) 624 625 /* 626 * arg0 - sysino 627 * arg1 - intr_state 628 * 629 * ret0 - status 630 */ 631 ENTRY(hvio_intr_setstate) 632 mov HVIO_INTR_SETSTATE, %o5 633 ta FAST_TRAP 634 retl 635 nop 636 SET_SIZE(hvio_intr_setstate) 637 638 /* 639 * arg0 - sysino 640 * 641 * ret0 - status 642 * ret1 - cpu_id 643 */ 644 ENTRY(hvio_intr_gettarget) 645 mov %o1, %o2 646 mov HVIO_INTR_GETTARGET, %o5 647 ta FAST_TRAP 648 brz,a %o0, 1f 649 stuw %o1, [%o2] 6501: retl 651 nop 652 SET_SIZE(hvio_intr_gettarget) 653 654 /* 655 * arg0 - sysino 656 * arg1 - cpu_id 657 * 658 * ret0 - status 659 */ 660 ENTRY(hvio_intr_settarget) 661 mov HVIO_INTR_SETTARGET, %o5 662 ta FAST_TRAP 663 retl 664 nop 665 SET_SIZE(hvio_intr_settarget) 666 667 /* 668 * hv_cpu_yield(void) 669 */ 670 ENTRY(hv_cpu_yield) 671 mov HV_CPU_YIELD, %o5 672 ta FAST_TRAP 673 retl 674 nop 675 SET_SIZE(hv_cpu_yield) 676 677 /* 678 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 679 */ 680 ENTRY(hv_cpu_state) 681 mov %o1, %o4 ! save datap 682 mov HV_CPU_STATE, %o5 683 ta FAST_TRAP 684 brz,a %o0, 1f 685 stx %o1, [%o4] 6861: 687 retl 688 nop 689 SET_SIZE(hv_cpu_state) 690 691 /* 692 * HV state dump zone Configure 693 * arg0 real adrs of dump buffer (%o0) 694 * arg1 size of dump buffer (%o1) 695 * ret0 status (%o0) 696 * ret1 size of buffer on success and min size on EINVAL (%o1) 697 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 698 */ 699 ENTRY(hv_dump_buf_update) 700 mov DUMP_BUF_UPDATE, %o5 701 ta FAST_TRAP 702 retl 703 stx %o1, [%o2] 704 SET_SIZE(hv_dump_buf_update) 705 706 /* 707 * arg0 - timeout value (%o0) 708 * 709 * ret0 - status (%o0) 710 * ret1 - time_remaining (%o1) 711 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 712 */ 713 ENTRY(hv_mach_set_watchdog) 714 mov %o1, %o2 715 mov MACH_SET_WATCHDOG, %o5 716 ta FAST_TRAP 717 retl 718 stx %o1, [%o2] 719 SET_SIZE(hv_mach_set_watchdog) 720 721 /* 722 * For memory scrub 723 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 724 * uint64_t *scrubbed_len); 725 * Retun %o0 -- status 726 * %o1 -- bytes scrubbed 727 */ 728 ENTRY(hv_mem_scrub) 729 mov %o2, %o4 730 mov HV_MEM_SCRUB, %o5 731 ta FAST_TRAP 732 retl 733 stx %o1, [%o4] 734 SET_SIZE(hv_mem_scrub) 735 736 /* 737 * Flush ecache 738 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 739 * uint64_t *flushed_len); 740 * Retun %o0 -- status 741 * %o1 -- bytes flushed 742 */ 743 ENTRY(hv_mem_sync) 744 mov %o2, %o4 745 mov HV_MEM_SYNC, %o5 746 ta FAST_TRAP 747 retl 748 stx %o1, [%o4] 749 SET_SIZE(hv_mem_sync) 750 751 /* 752 * uint64_t hv_tm_enable(uint64_t enable) 753 */ 754 ENTRY(hv_tm_enable) 755 mov HV_TM_ENABLE, %o5 756 ta FAST_TRAP 757 retl 758 nop 759 SET_SIZE(hv_tm_enable) 760 761 /* 762 * TTRACE_BUF_CONF Configure 763 * arg0 RA base of buffer (%o0) 764 * arg1 buf size in no. of entries (%o1) 765 * ret0 status (%o0) 766 * ret1 minimum size in no. of entries on failure, 767 * actual size in no. of entries on success (%o1) 768 */ 769 ENTRY(hv_ttrace_buf_conf) 770 mov TTRACE_BUF_CONF, %o5 771 ta FAST_TRAP 772 retl 773 stx %o1, [%o2] 774 SET_SIZE(hv_ttrace_buf_conf) 775 776 /* 777 * TTRACE_BUF_INFO 778 * ret0 status (%o0) 779 * ret1 RA base of buffer (%o1) 780 * ret2 size in no. of entries (%o2) 781 */ 782 ENTRY(hv_ttrace_buf_info) 783 mov %o0, %o3 784 mov %o1, %o4 785 mov TTRACE_BUF_INFO, %o5 786 ta FAST_TRAP 787 stx %o1, [%o3] 788 retl 789 stx %o2, [%o4] 790 SET_SIZE(hv_ttrace_buf_info) 791 792 /* 793 * TTRACE_ENABLE 794 * arg0 enable/ disable (%o0) 795 * ret0 status (%o0) 796 * ret1 previous enable state (%o1) 797 */ 798 ENTRY(hv_ttrace_enable) 799 mov %o1, %o2 800 mov TTRACE_ENABLE, %o5 801 ta FAST_TRAP 802 retl 803 stx %o1, [%o2] 804 SET_SIZE(hv_ttrace_enable) 805 806 /* 807 * TTRACE_FREEZE 808 * arg0 enable/ freeze (%o0) 809 * ret0 status (%o0) 810 * ret1 previous freeze state (%o1) 811 */ 812 ENTRY(hv_ttrace_freeze) 813 mov %o1, %o2 814 mov TTRACE_FREEZE, %o5 815 ta FAST_TRAP 816 retl 817 stx %o1, [%o2] 818 SET_SIZE(hv_ttrace_freeze) 819 820 /* 821 * MACH_DESC 822 * arg0 buffer real address 823 * arg1 pointer to uint64_t for size of buffer 824 * ret0 status 825 * ret1 return required size of buffer / returned data size 826 */ 827 ENTRY(hv_mach_desc) 828 mov %o1, %o4 ! save datap 829 ldx [%o1], %o1 830 mov HV_MACH_DESC, %o5 831 ta FAST_TRAP 832 retl 833 stx %o1, [%o4] 834 SET_SIZE(hv_mach_desc) 835 836 /* 837 * hv_ra2pa(uint64_t ra) 838 * 839 * MACH_DESC 840 * arg0 Real address to convert 841 * ret0 Returned physical address or -1 on error 842 */ 843 ENTRY(hv_ra2pa) 844 mov HV_RA2PA, %o5 845 ta FAST_TRAP 846 cmp %o0, 0 847 move %xcc, %o1, %o0 848 movne %xcc, -1, %o0 849 retl 850 nop 851 SET_SIZE(hv_ra2pa) 852 853 /* 854 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 855 * 856 * MACH_DESC 857 * arg0 OS function to call 858 * arg1 First arg to OS function 859 * arg2 Second arg to OS function 860 * arg3 Third arg to OS function 861 * ret0 Returned value from function 862 */ 863 864 ENTRY(hv_hpriv) 865 mov HV_HPRIV, %o5 866 ta FAST_TRAP 867 retl 868 nop 869 SET_SIZE(hv_hpriv) 870 871 /* 872 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 873 * uint64_t nentries); 874 */ 875 ENTRY(hv_ldc_tx_qconf) 876 mov LDC_TX_QCONF, %o5 877 ta FAST_TRAP 878 retl 879 nop 880 SET_SIZE(hv_ldc_tx_qconf) 881 882 883 /* 884 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 885 * uint64_t *nentries); 886 */ 887 ENTRY(hv_ldc_tx_qinfo) 888 mov %o1, %g1 889 mov %o2, %g2 890 mov LDC_TX_QINFO, %o5 891 ta FAST_TRAP 892 stx %o1, [%g1] 893 retl 894 stx %o2, [%g2] 895 SET_SIZE(hv_ldc_tx_qinfo) 896 897 898 /* 899 * hv_ldc_tx_get_state(uint64_t channel, 900 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 901 */ 902 ENTRY(hv_ldc_tx_get_state) 903 mov LDC_TX_GET_STATE, %o5 904 mov %o1, %g1 905 mov %o2, %g2 906 mov %o3, %g3 907 ta FAST_TRAP 908 stx %o1, [%g1] 909 stx %o2, [%g2] 910 retl 911 stx %o3, [%g3] 912 SET_SIZE(hv_ldc_tx_get_state) 913 914 915 /* 916 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 917 */ 918 ENTRY(hv_ldc_tx_set_qtail) 919 mov LDC_TX_SET_QTAIL, %o5 920 ta FAST_TRAP 921 retl 922 SET_SIZE(hv_ldc_tx_set_qtail) 923 924 925 /* 926 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 927 * uint64_t nentries); 928 */ 929 ENTRY(hv_ldc_rx_qconf) 930 mov LDC_RX_QCONF, %o5 931 ta FAST_TRAP 932 retl 933 nop 934 SET_SIZE(hv_ldc_rx_qconf) 935 936 937 /* 938 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 939 * uint64_t *nentries); 940 */ 941 ENTRY(hv_ldc_rx_qinfo) 942 mov %o1, %g1 943 mov %o2, %g2 944 mov LDC_RX_QINFO, %o5 945 ta FAST_TRAP 946 stx %o1, [%g1] 947 retl 948 stx %o2, [%g2] 949 SET_SIZE(hv_ldc_rx_qinfo) 950 951 952 /* 953 * hv_ldc_rx_get_state(uint64_t channel, 954 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 955 */ 956 ENTRY(hv_ldc_rx_get_state) 957 mov LDC_RX_GET_STATE, %o5 958 mov %o1, %g1 959 mov %o2, %g2 960 mov %o3, %g3 961 ta FAST_TRAP 962 stx %o1, [%g1] 963 stx %o2, [%g2] 964 retl 965 stx %o3, [%g3] 966 SET_SIZE(hv_ldc_rx_get_state) 967 968 969 /* 970 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 971 */ 972 ENTRY(hv_ldc_rx_set_qhead) 973 mov LDC_RX_SET_QHEAD, %o5 974 ta FAST_TRAP 975 retl 976 SET_SIZE(hv_ldc_rx_set_qhead) 977 978 /* 979 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 980 * uint64_t tbl_entries) 981 */ 982 ENTRY(hv_ldc_set_map_table) 983 mov LDC_SET_MAP_TABLE, %o5 984 ta FAST_TRAP 985 retl 986 nop 987 SET_SIZE(hv_ldc_set_map_table) 988 989 990 /* 991 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 992 * uint64_t *tbl_entries) 993 */ 994 ENTRY(hv_ldc_get_map_table) 995 mov %o1, %g1 996 mov %o2, %g2 997 mov LDC_GET_MAP_TABLE, %o5 998 ta FAST_TRAP 999 stx %o1, [%g1] 1000 retl 1001 stx %o2, [%g2] 1002 SET_SIZE(hv_ldc_get_map_table) 1003 1004 1005 /* 1006 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 1007 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 1008 */ 1009 ENTRY(hv_ldc_copy) 1010 mov %o5, %g1 1011 mov LDC_COPY, %o5 1012 ta FAST_TRAP 1013 retl 1014 stx %o1, [%g1] 1015 SET_SIZE(hv_ldc_copy) 1016 1017 1018 /* 1019 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 1020 * uint64_t *perm) 1021 */ 1022 ENTRY(hv_ldc_mapin) 1023 mov %o2, %g1 1024 mov %o3, %g2 1025 mov LDC_MAPIN, %o5 1026 ta FAST_TRAP 1027 stx %o1, [%g1] 1028 retl 1029 stx %o2, [%g2] 1030 SET_SIZE(hv_ldc_mapin) 1031 1032 1033 /* 1034 * hv_ldc_unmap(uint64_t raddr) 1035 */ 1036 ENTRY(hv_ldc_unmap) 1037 mov LDC_UNMAP, %o5 1038 ta FAST_TRAP 1039 retl 1040 nop 1041 SET_SIZE(hv_ldc_unmap) 1042 1043 1044 /* 1045 * hv_ldc_revoke(uint64_t channel, uint64_t cookie, 1046 * uint64_t revoke_cookie 1047 */ 1048 ENTRY(hv_ldc_revoke) 1049 mov LDC_REVOKE, %o5 1050 ta FAST_TRAP 1051 retl 1052 nop 1053 SET_SIZE(hv_ldc_revoke) 1054 1055 1056 /* 1057 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 1058 * uint64_t *cookie); 1059 */ 1060 ENTRY(hvldc_intr_getcookie) 1061 mov %o2, %g1 1062 mov VINTR_GET_COOKIE, %o5 1063 ta FAST_TRAP 1064 retl 1065 stx %o1, [%g1] 1066 SET_SIZE(hvldc_intr_getcookie) 1067 1068 /* 1069 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1070 * uint64_t cookie); 1071 */ 1072 ENTRY(hvldc_intr_setcookie) 1073 mov VINTR_SET_COOKIE, %o5 1074 ta FAST_TRAP 1075 retl 1076 nop 1077 SET_SIZE(hvldc_intr_setcookie) 1078 1079 1080 /* 1081 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1082 * int *intr_valid_state); 1083 */ 1084 ENTRY(hvldc_intr_getvalid) 1085 mov %o2, %g1 1086 mov VINTR_GET_VALID, %o5 1087 ta FAST_TRAP 1088 retl 1089 stuw %o1, [%g1] 1090 SET_SIZE(hvldc_intr_getvalid) 1091 1092 /* 1093 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1094 * int intr_valid_state); 1095 */ 1096 ENTRY(hvldc_intr_setvalid) 1097 mov VINTR_SET_VALID, %o5 1098 ta FAST_TRAP 1099 retl 1100 nop 1101 SET_SIZE(hvldc_intr_setvalid) 1102 1103 /* 1104 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1105 * int *intr_state); 1106 */ 1107 ENTRY(hvldc_intr_getstate) 1108 mov %o2, %g1 1109 mov VINTR_GET_STATE, %o5 1110 ta FAST_TRAP 1111 retl 1112 stuw %o1, [%g1] 1113 SET_SIZE(hvldc_intr_getstate) 1114 1115 /* 1116 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1117 * int intr_state); 1118 */ 1119 ENTRY(hvldc_intr_setstate) 1120 mov VINTR_SET_STATE, %o5 1121 ta FAST_TRAP 1122 retl 1123 nop 1124 SET_SIZE(hvldc_intr_setstate) 1125 1126 /* 1127 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1128 * uint32_t *cpuid); 1129 */ 1130 ENTRY(hvldc_intr_gettarget) 1131 mov %o2, %g1 1132 mov VINTR_GET_TARGET, %o5 1133 ta FAST_TRAP 1134 retl 1135 stuw %o1, [%g1] 1136 SET_SIZE(hvldc_intr_gettarget) 1137 1138 /* 1139 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1140 * uint32_t cpuid); 1141 */ 1142 ENTRY(hvldc_intr_settarget) 1143 mov VINTR_SET_TARGET, %o5 1144 ta FAST_TRAP 1145 retl 1146 nop 1147 SET_SIZE(hvldc_intr_settarget) 1148 1149 /* 1150 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1151 * uint64_t *minorp) 1152 * 1153 * API_GET_VERSION 1154 * arg0 API group 1155 * ret0 status 1156 * ret1 major number 1157 * ret2 minor number 1158 */ 1159 ENTRY(hv_api_get_version) 1160 mov %o1, %o3 1161 mov %o2, %o4 1162 mov API_GET_VERSION, %o5 1163 ta CORE_TRAP 1164 stx %o1, [%o3] 1165 retl 1166 stx %o2, [%o4] 1167 SET_SIZE(hv_api_get_version) 1168 1169 /* 1170 * hv_api_set_version(uint64_t api_group, uint64_t major, 1171 * uint64_t minor, uint64_t *supported_minor) 1172 * 1173 * API_SET_VERSION 1174 * arg0 API group 1175 * arg1 major number 1176 * arg2 requested minor number 1177 * ret0 status 1178 * ret1 actual minor number 1179 */ 1180 ENTRY(hv_api_set_version) 1181 mov %o3, %o4 1182 mov API_SET_VERSION, %o5 1183 ta CORE_TRAP 1184 retl 1185 stx %o1, [%o4] 1186 SET_SIZE(hv_api_set_version) 1187 1188 /* 1189 * %o0 - buffer real address 1190 * %o1 - buffer size 1191 * %o2 - &characters written 1192 * returns 1193 * status 1194 */ 1195 ENTRY(hv_cnwrite) 1196 mov CONS_WRITE, %o5 1197 ta FAST_TRAP 1198 retl 1199 stx %o1, [%o2] 1200 SET_SIZE(hv_cnwrite) 1201 1202 /* 1203 * %o0 character buffer ra 1204 * %o1 buffer size 1205 * %o2 pointer to returned size 1206 * return values: 1207 * 0 success 1208 * hv_errno failure 1209 */ 1210 ENTRY(hv_cnread) 1211 mov CONS_READ, %o5 1212 ta FAST_TRAP 1213 brnz,a %o0, 1f ! failure, just return error 1214 nop 1215 1216 cmp %o1, H_BREAK 1217 be 1f 1218 mov %o1, %o0 1219 1220 cmp %o1, H_HUP 1221 be 1f 1222 mov %o1, %o0 1223 1224 stx %o1, [%o2] ! success, save count and return 0 1225 mov 0, %o0 12261: 1227 retl 1228 nop 1229 SET_SIZE(hv_cnread) 1230 1231 /* 1232 * SOFT_STATE_SET 1233 * arg0 state (%o0) 1234 * arg1 string (%o1) 1235 * ret0 status (%o0) 1236 */ 1237 ENTRY(hv_soft_state_set) 1238 mov SOFT_STATE_SET, %o5 1239 ta FAST_TRAP 1240 retl 1241 nop 1242 SET_SIZE(hv_soft_state_set) 1243 1244 /* 1245 * SOFT_STATE_GET 1246 * arg0 string buffer (%o0) 1247 * ret0 status (%o0) 1248 * ret1 current state (%o1) 1249 */ 1250 ENTRY(hv_soft_state_get) 1251 mov %o1, %o2 1252 mov SOFT_STATE_GET, %o5 1253 ta FAST_TRAP 1254 retl 1255 stx %o1, [%o2] 1256 SET_SIZE(hv_soft_state_get) 1257 1258 ENTRY(hv_guest_suspend) 1259 mov GUEST_SUSPEND, %o5 1260 ta FAST_TRAP 1261 retl 1262 nop 1263 SET_SIZE(hv_guest_suspend) 1264 1265 ENTRY(hv_tick_set_npt) 1266 mov TICK_SET_NPT, %o5 1267 ta FAST_TRAP 1268 retl 1269 nop 1270 SET_SIZE(hv_tick_set_npt) 1271 1272 ENTRY(hv_stick_set_npt) 1273 mov STICK_SET_NPT, %o5 1274 ta FAST_TRAP 1275 retl 1276 nop 1277 SET_SIZE(hv_stick_set_npt) 1278 1279 /* 1280 * REBOOT_DATA_SET 1281 * arg0 buffer real address 1282 * arg1 buffer length 1283 * ret0 status 1284 */ 1285 ENTRY(hv_reboot_data_set) 1286 mov HV_REBOOT_DATA_SET, %o5 1287 ta FAST_TRAP 1288 retl 1289 nop 1290 SET_SIZE(hv_reboot_data_set) 1291 1292#endif /* lint || __lint */ 1293