1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Hypervisor calls 31 */ 32 33#include <sys/asm_linkage.h> 34#include <sys/machasi.h> 35#include <sys/machparam.h> 36#include <sys/hypervisor_api.h> 37#include <io/px/px_ioapi.h> 38 39#if defined(lint) || defined(__lint) 40 41/*ARGSUSED*/ 42int64_t 43hv_cnputchar(uint8_t ch) 44{ return (0); } 45 46/*ARGSUSED*/ 47int64_t 48hv_cngetchar(uint8_t *ch) 49{ return (0); } 50 51/*ARGSUSED*/ 52uint64_t 53hv_tod_get(uint64_t *seconds) 54{ return (0); } 55 56/*ARGSUSED*/ 57uint64_t 58hv_tod_set(uint64_t seconds) 59{ return (0);} 60 61/*ARGSUSED*/ 62uint64_t 63hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 64{ return (0); } 65 66/*ARGSUSED*/ 67uint64_t 68hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 69{ return (0); } 70 71/*ARGSUSED*/ 72uint64_t 73hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 74{ return (0); } 75 76/*ARGSUSED*/ 77uint64_t 78hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 79{ return (0); } 80 81#ifdef SET_MMU_STATS 82/*ARGSUSED*/ 83uint64_t 84hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 85{ return (0); } 86#endif /* SET_MMU_STATS */ 87 88/*ARGSUSED*/ 89uint64_t 90hv_cpu_qconf(int queue, uint64_t paddr, int size) 91{ return (0); } 92 93/*ARGSUSED*/ 94uint64_t 95hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, 96 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t *data_p) 97{ return (0); } 98 99/*ARGSUSED*/ 100uint64_t 101hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, 102 pci_config_offset_t off, pci_config_size_t size, pci_cfg_data_t data) 103{ return (0); } 104 105/*ARGSUSED*/ 106uint64_t 107hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 108{ return (0); } 109 110/*ARGSUSED*/ 111uint64_t 112hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 113{ return (0); } 114 115/*ARGSUSED*/ 116uint64_t 117hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 118{ return (0); } 119 120/*ARGSUSED*/ 121uint64_t 122hvio_intr_getstate(uint64_t sysino, int *intr_state) 123{ return (0); } 124 125/*ARGSUSED*/ 126uint64_t 127hvio_intr_setstate(uint64_t sysino, int intr_state) 128{ return (0); } 129 130/*ARGSUSED*/ 131uint64_t 132hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 133{ return (0); } 134 135/*ARGSUSED*/ 136uint64_t 137hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 138{ return (0); } 139 140/*ARGSUSED*/ 141uint64_t 142hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 143 pages_t pages, io_attributes_t io_attributes, 144 io_page_list_t *io_page_list_p, pages_t *pages_mapped) 145{ return (0); } 146 147/*ARGSUSED*/ 148uint64_t 149hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 150 pages_t pages, pages_t *pages_demapped) 151{ return (0); } 152 153/*ARGSUSED*/ 154uint64_t 155hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 156 io_attributes_t *attributes_p, r_addr_t *r_addr_p) 157{ return (0); } 158 159/*ARGSUSED*/ 160uint64_t 161hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 162 io_attributes_t io_attributes, io_addr_t *io_addr_p) 163{ return (0); } 164 165/*ARGSUSED*/ 166uint64_t 167hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, 168 uint64_t *data_p) 169{ return (0); } 170 171/*ARGSUSED*/ 172uint64_t 173hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, 174 r_addr_t ra2, uint32_t *rdbk_status) 175{ return (0); } 176 177/*ARGSUSED*/ 178uint64_t 179hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, 180 int io_sync_direction, size_t *bytes_synched) 181{ return (0); } 182 183/*ARGSUSED*/ 184uint64_t 185hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, 186 uint_t msiq_rec_cnt) 187{ return (0); } 188 189/*ARGSUSED*/ 190uint64_t 191hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, 192 uint_t *msiq_rec_cnt_p) 193{ return (0); } 194 195/*ARGSUSED*/ 196uint64_t 197hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 198 pci_msiq_valid_state_t *msiq_valid_state) 199{ return (0); } 200 201/*ARGSUSED*/ 202uint64_t 203hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 204 pci_msiq_valid_state_t msiq_valid_state) 205{ return (0); } 206 207/*ARGSUSED*/ 208uint64_t 209hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 210 pci_msiq_state_t *msiq_state) 211{ return (0); } 212 213/*ARGSUSED*/ 214uint64_t 215hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 216 pci_msiq_state_t msiq_state) 217{ return (0); } 218 219/*ARGSUSED*/ 220uint64_t 221hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 222 msiqhead_t *msiq_head) 223{ return (0); } 224 225/*ARGSUSED*/ 226uint64_t 227hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 228 msiqhead_t msiq_head) 229{ return (0); } 230 231/*ARGSUSED*/ 232uint64_t 233hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 234 msiqtail_t *msiq_tail) 235{ return (0); } 236 237/*ARGSUSED*/ 238uint64_t 239hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 240 msiqid_t *msiq_id) 241{ return (0); } 242 243/*ARGSUSED*/ 244uint64_t 245hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 246 msiqid_t msiq_id, msi_type_t msitype) 247{ return (0); } 248 249/*ARGSUSED*/ 250uint64_t 251hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 252 pci_msi_valid_state_t *msi_valid_state) 253{ return (0); } 254 255/*ARGSUSED*/ 256uint64_t 257hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 258 pci_msi_valid_state_t msi_valid_state) 259{ return (0); } 260 261/*ARGSUSED*/ 262uint64_t 263hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 264 pci_msi_state_t *msi_state) 265{ return (0); } 266 267/*ARGSUSED*/ 268uint64_t 269hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 270 pci_msi_state_t msi_state) 271{ return (0); } 272 273/*ARGSUSED*/ 274uint64_t 275hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 276 msiqid_t *msiq_id) 277{ return (0); } 278 279/*ARGSUSED*/ 280uint64_t 281hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 282 msiqid_t msiq_id) 283{ return (0); } 284 285/*ARGSUSED*/ 286uint64_t 287hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 288 pcie_msg_valid_state_t *msg_valid_state) 289{ return (0); } 290 291/*ARGSUSED*/ 292uint64_t 293hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 294 pcie_msg_valid_state_t msg_valid_state) 295{ return (0); } 296 297uint64_t 298hv_cpu_yield(void) 299{ return (0); } 300 301/*ARGSUSED*/ 302uint64_t 303hv_service_recv(uint64_t s_id, uint64_t buf_pa, uint64_t size, 304 uint64_t *recv_bytes) 305{ return (0); } 306 307/*ARGSUSED*/ 308uint64_t 309hv_service_send(uint64_t s_id, uint64_t buf_pa, uint64_t size, 310 uint64_t *send_bytes) 311{ return (0); } 312 313/*ARGSUSED*/ 314uint64_t 315hv_service_getstatus(uint64_t s_id, uint64_t *vreg) 316{ return (0); } 317 318/*ARGSUSED*/ 319uint64_t 320hv_service_setstatus(uint64_t s_id, uint64_t bits) 321{ return (0); } 322 323/*ARGSUSED*/ 324uint64_t 325hv_service_clrstatus(uint64_t s_id, uint64_t bits) 326{ return (0); } 327 328/*ARGSUSED*/ 329uint64_t 330hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 331{ return (0); } 332 333/*ARGSUSED*/ 334uint64_t 335hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 336{ return (0); } 337 338/*ARGSUSED*/ 339uint64_t 340hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 341{ return (0); } 342 343/*ARGSUSED*/ 344uint64_t 345hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 346{ return (0); } 347 348/*ARGSUSED*/ 349uint64_t 350hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 351{ return (0); } 352 353/*ARGSUSED*/ 354uint64_t 355hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 356{ return (0); } 357 358/*ARGSUSED*/ 359uint64_t 360hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 361{ return (0); } 362 363/*ARGSUSED*/ 364uint64_t 365hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 366{ return (0); } 367 368/*ARGSUSED*/ 369uint64_t 370hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 371{ return (0); } 372 373/*ARGSUSED*/ 374uint64_t 375hv_ncs_request(int cmd, uint64_t realaddr, size_t sz) 376{ return (0); } 377 378/*ARGSUSED*/ 379uint64_t 380hv_ra2pa(uint64_t ra) 381{ return (0); } 382 383/*ARGSUSED*/ 384uint64_t 385hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 386{ return (0); } 387 388#else /* lint || __lint */ 389 390 /* 391 * %o0 - character 392 */ 393 ENTRY(hv_cnputchar) 394 mov CONS_WRITE, %o5 395 ta FAST_TRAP 396 tst %o0 397 retl 398 movnz %xcc, -1, %o0 399 SET_SIZE(hv_cnputchar) 400 401 /* 402 * %o0 pointer to character buffer 403 * return values: 404 * 0 success 405 * hv_errno failure 406 */ 407 ENTRY(hv_cngetchar) 408 mov %o0, %o2 409 mov CONS_READ, %o5 410 ta FAST_TRAP 411 brnz,a %o0, 1f ! failure, just return error 412 mov 1, %o0 413 414 cmp %o1, H_BREAK 415 be 1f 416 mov %o1, %o0 417 418 cmp %o1, H_HUP 419 be 1f 420 mov %o1, %o0 421 422 stb %o1, [%o2] ! success, save character and return 0 423 mov 0, %o0 4241: 425 retl 426 nop 427 SET_SIZE(hv_cngetchar) 428 429 ENTRY(hv_tod_get) 430 mov %o0, %o4 431 mov TOD_GET, %o5 432 ta FAST_TRAP 433 retl 434 stx %o1, [%o4] 435 SET_SIZE(hv_tod_get) 436 437 ENTRY(hv_tod_set) 438 mov TOD_SET, %o5 439 ta FAST_TRAP 440 retl 441 nop 442 SET_SIZE(hv_tod_set) 443 444 /* 445 * Map permanent address 446 * arg0 vaddr (%o0) 447 * arg1 context (%o1) 448 * arg2 tte (%o2) 449 * arg3 flags (%o3) 0x1=d 0x2=i 450 */ 451 ENTRY(hv_mmu_map_perm_addr) 452 mov MAP_PERM_ADDR, %o5 453 ta FAST_TRAP 454 retl 455 nop 456 SET_SIZE(hv_mmu_map_perm_addr) 457 458 /* 459 * Unmap permanent address 460 * arg0 vaddr (%o0) 461 * arg1 context (%o1) 462 * arg2 flags (%o2) 0x1=d 0x2=i 463 */ 464 ENTRY(hv_mmu_unmap_perm_addr) 465 mov UNMAP_PERM_ADDR, %o5 466 ta FAST_TRAP 467 retl 468 nop 469 SET_SIZE(hv_mmu_unmap_perm_addr) 470 471 /* 472 * Set TSB for context 0 473 * arg0 ntsb_descriptor (%o0) 474 * arg1 desc_ra (%o1) 475 */ 476 ENTRY(hv_set_ctx0) 477 mov MMU_TSB_CTX0, %o5 478 ta FAST_TRAP 479 retl 480 nop 481 SET_SIZE(hv_set_ctx0) 482 483 /* 484 * Set TSB for context non0 485 * arg0 ntsb_descriptor (%o0) 486 * arg1 desc_ra (%o1) 487 */ 488 ENTRY(hv_set_ctxnon0) 489 mov MMU_TSB_CTXNON0, %o5 490 ta FAST_TRAP 491 retl 492 nop 493 SET_SIZE(hv_set_ctxnon0) 494 495#ifdef SET_MMU_STATS 496 /* 497 * Returns old stat area on success 498 */ 499 ENTRY(hv_mmu_set_stat_area) 500 mov MMU_STAT_AREA, %o5 501 ta FAST_TRAP 502 retl 503 nop 504 SET_SIZE(hv_mmu_set_stat_area) 505#endif /* SET_MMU_STATS */ 506 507 /* 508 * CPU Q Configure 509 * arg0 queue (%o0) 510 * arg1 Base address RA (%o1) 511 * arg2 Size (%o2) 512 */ 513 ENTRY(hv_cpu_qconf) 514 mov CPU_QCONF, %o5 515 ta FAST_TRAP 516 retl 517 nop 518 SET_SIZE(hv_cpu_qconf) 519 520 /* 521 * arg0 - devhandle 522 * arg1 - pci_device 523 * arg2 - pci_config_offset 524 * arg3 - pci_config_size 525 * 526 * ret0 - status 527 * ret1 - error_flag 528 * ret2 - pci_cfg_data 529 */ 530 ENTRY(hvio_config_get) 531 mov HVIO_CONFIG_GET, %o5 532 ta FAST_TRAP 533 brnz %o0, 1f 534 movrnz %o1, -1, %o2 535 brz,a %o1, 1f 536 stuw %o2, [%o4] 5371: retl 538 nop 539 SET_SIZE(hvio_config_get) 540 541 /* 542 * arg0 - devhandle 543 * arg1 - pci_device 544 * arg2 - pci_config_offset 545 * arg3 - pci_config_size 546 * arg4 - pci_cfg_data 547 * 548 * ret0 - status 549 * ret1 - error_flag 550 */ 551 ENTRY(hvio_config_put) 552 mov HVIO_CONFIG_PUT, %o5 553 ta FAST_TRAP 554 retl 555 nop 556 SET_SIZE(hvio_config_put) 557 558 /* 559 * arg0 - devhandle 560 * arg1 - devino 561 * 562 * ret0 - status 563 * ret1 - sysino 564 */ 565 ENTRY(hvio_intr_devino_to_sysino) 566 mov HVIO_INTR_DEVINO2SYSINO, %o5 567 ta FAST_TRAP 568 brz,a %o0, 1f 569 stx %o1, [%o2] 5701: retl 571 nop 572 SET_SIZE(hvio_intr_devino_to_sysino) 573 574 /* 575 * arg0 - sysino 576 * 577 * ret0 - status 578 * ret1 - intr_valid_state 579 */ 580 ENTRY(hvio_intr_getvalid) 581 mov %o1, %o2 582 mov HVIO_INTR_GETVALID, %o5 583 ta FAST_TRAP 584 brz,a %o0, 1f 585 stuw %o1, [%o2] 5861: retl 587 nop 588 SET_SIZE(hvio_intr_getvalid) 589 590 /* 591 * arg0 - sysino 592 * arg1 - intr_valid_state 593 * 594 * ret0 - status 595 */ 596 ENTRY(hvio_intr_setvalid) 597 mov HVIO_INTR_SETVALID, %o5 598 ta FAST_TRAP 599 retl 600 nop 601 SET_SIZE(hvio_intr_setvalid) 602 603 /* 604 * arg0 - sysino 605 * 606 * ret0 - status 607 * ret1 - intr_state 608 */ 609 ENTRY(hvio_intr_getstate) 610 mov %o1, %o2 611 mov HVIO_INTR_GETSTATE, %o5 612 ta FAST_TRAP 613 brz,a %o0, 1f 614 stuw %o1, [%o2] 6151: retl 616 nop 617 SET_SIZE(hvio_intr_getstate) 618 619 /* 620 * arg0 - sysino 621 * arg1 - intr_state 622 * 623 * ret0 - status 624 */ 625 ENTRY(hvio_intr_setstate) 626 mov HVIO_INTR_SETSTATE, %o5 627 ta FAST_TRAP 628 retl 629 nop 630 SET_SIZE(hvio_intr_setstate) 631 632 /* 633 * arg0 - sysino 634 * 635 * ret0 - status 636 * ret1 - cpu_id 637 */ 638 ENTRY(hvio_intr_gettarget) 639 mov %o1, %o2 640 mov HVIO_INTR_GETTARGET, %o5 641 ta FAST_TRAP 642 brz,a %o0, 1f 643 stuw %o1, [%o2] 6441: retl 645 nop 646 SET_SIZE(hvio_intr_gettarget) 647 648 /* 649 * arg0 - sysino 650 * arg1 - cpu_id 651 * 652 * ret0 - status 653 */ 654 ENTRY(hvio_intr_settarget) 655 mov HVIO_INTR_SETTARGET, %o5 656 ta FAST_TRAP 657 retl 658 nop 659 SET_SIZE(hvio_intr_settarget) 660 661 /* 662 * arg0 - devhandle 663 * arg1 - tsbid 664 * arg2 - pages 665 * arg3 - io_attributes 666 * arg4 - io_page_list_p 667 * 668 * ret1 - pages_mapped 669 */ 670 ENTRY(hvio_iommu_map) 671 save %sp, -SA(MINFRAME64), %sp 672 mov %i0, %o0 673 mov %i1, %o1 674 mov %i2, %o2 675 mov %i3, %o3 676 mov %i4, %o4 677 mov HVIO_IOMMU_MAP, %o5 678 ta FAST_TRAP 679 brnz %o0, 1f 680 mov %o0, %i0 681 stuw %o1, [%i5] 6821: 683 ret 684 restore 685 SET_SIZE(hvio_iommu_map) 686 687 /* 688 * arg0 - devhandle 689 * arg1 - tsbid 690 * arg2 - pages 691 * 692 * ret1 - pages_demapped 693 */ 694 ENTRY(hvio_iommu_demap) 695 mov HVIO_IOMMU_DEMAP, %o5 696 ta FAST_TRAP 697 brz,a %o0, 1f 698 stuw %o1, [%o3] 6991: retl 700 nop 701 SET_SIZE(hvio_iommu_demap) 702 703 /* 704 * arg0 - devhandle 705 * arg1 - tsbid 706 * 707 * 708 * ret0 - status 709 * ret1 - io_attributes 710 * ret2 - r_addr 711 */ 712 ENTRY(hvio_iommu_getmap) 713 mov %o2, %o4 714 mov HVIO_IOMMU_GETMAP, %o5 715 ta FAST_TRAP 716 brnz %o0, 1f 717 nop 718 stx %o2, [%o3] 719 st %o1, [%o4] 7201: 721 retl 722 nop 723 SET_SIZE(hvio_iommu_getmap) 724 725 /* 726 * arg0 - devhandle 727 * arg1 - r_addr 728 * arg2 - io_attributes 729 * 730 * 731 * ret0 - status 732 * ret1 - io_addr 733 */ 734 ENTRY(hvio_iommu_getbypass) 735 mov HVIO_IOMMU_GETBYPASS, %o5 736 ta FAST_TRAP 737 brz,a %o0, 1f 738 stx %o1, [%o3] 7391: retl 740 nop 741 SET_SIZE(hvio_iommu_getbypass) 742 743 /* 744 * arg0 - devhandle 745 * arg1 - r_addr 746 * arg2 - size 747 * 748 * ret1 - error_flag 749 * ret2 - data 750 */ 751 ENTRY(hvio_peek) 752 mov HVIO_PEEK, %o5 753 ta FAST_TRAP 754 brnz %o0, 1f 755 nop 756 stx %o2, [%o4] 757 st %o1, [%o3] 7581: 759 retl 760 nop 761 SET_SIZE(hvio_peek) 762 763 /* 764 * arg0 - devhandle 765 * arg1 - r_addr 766 * arg2 - sizes 767 * arg3 - data 768 * arg4 - r_addr2 769 * 770 * ret1 - error_flag 771 */ 772 ENTRY(hvio_poke) 773 save %sp, -SA(MINFRAME64), %sp 774 mov %i0, %o0 775 mov %i1, %o1 776 mov %i2, %o2 777 mov %i3, %o3 778 mov %i4, %o4 779 mov HVIO_POKE, %o5 780 ta FAST_TRAP 781 brnz %o0, 1f 782 mov %o0, %i0 783 stuw %o1, [%i5] 7841: 785 ret 786 restore 787 SET_SIZE(hvio_poke) 788 789 /* 790 * arg0 - devhandle 791 * arg1 - r_addr 792 * arg2 - num_bytes 793 * arg3 - io_sync_direction 794 * 795 * ret0 - status 796 * ret1 - bytes_synched 797 */ 798 ENTRY(hvio_dma_sync) 799 mov HVIO_DMA_SYNC, %o5 800 ta FAST_TRAP 801 brz,a %o0, 1f 802 stx %o1, [%o4] 8031: retl 804 nop 805 SET_SIZE(hvio_dma_sync) 806 807 /* 808 * arg0 - devhandle 809 * arg1 - msiq_id 810 * arg2 - r_addr 811 * arg3 - nentries 812 * 813 * ret0 - status 814 */ 815 ENTRY(hvio_msiq_conf) 816 mov HVIO_MSIQ_CONF, %o5 817 ta FAST_TRAP 818 retl 819 nop 820 SET_SIZE(hvio_msiq_conf) 821 822 /* 823 * arg0 - devhandle 824 * arg1 - msiq_id 825 * 826 * ret0 - status 827 * ret1 - r_addr 828 * ret1 - nentries 829 */ 830 ENTRY(hvio_msiq_info) 831 mov %o2, %o4 832 mov HVIO_MSIQ_INFO, %o5 833 ta FAST_TRAP 834 brnz 1f 835 nop 836 stx %o1, [%o4] 837 stuw %o2, [%o3] 8381: retl 839 nop 840 SET_SIZE(hvio_msiq_info) 841 842 /* 843 * arg0 - devhandle 844 * arg1 - msiq_id 845 * 846 * ret0 - status 847 * ret1 - msiq_valid_state 848 */ 849 ENTRY(hvio_msiq_getvalid) 850 mov HVIO_MSIQ_GETVALID, %o5 851 ta FAST_TRAP 852 brz,a %o0, 1f 853 stuw %o1, [%o2] 8541: retl 855 nop 856 SET_SIZE(hvio_msiq_getvalid) 857 858 /* 859 * arg0 - devhandle 860 * arg1 - msiq_id 861 * arg2 - msiq_valid_state 862 * 863 * ret0 - status 864 */ 865 ENTRY(hvio_msiq_setvalid) 866 mov HVIO_MSIQ_SETVALID, %o5 867 ta FAST_TRAP 868 retl 869 nop 870 SET_SIZE(hvio_msiq_setvalid) 871 872 /* 873 * arg0 - devhandle 874 * arg1 - msiq_id 875 * 876 * ret0 - status 877 * ret1 - msiq_state 878 */ 879 ENTRY(hvio_msiq_getstate) 880 mov HVIO_MSIQ_GETSTATE, %o5 881 ta FAST_TRAP 882 brz,a %o0, 1f 883 stuw %o1, [%o2] 8841: retl 885 nop 886 SET_SIZE(hvio_msiq_getstate) 887 888 /* 889 * arg0 - devhandle 890 * arg1 - msiq_id 891 * arg2 - msiq_state 892 * 893 * ret0 - status 894 */ 895 ENTRY(hvio_msiq_setstate) 896 mov HVIO_MSIQ_SETSTATE, %o5 897 ta FAST_TRAP 898 retl 899 nop 900 SET_SIZE(hvio_msiq_setstate) 901 902 /* 903 * arg0 - devhandle 904 * arg1 - msiq_id 905 * 906 * ret0 - status 907 * ret1 - msiq_head 908 */ 909 ENTRY(hvio_msiq_gethead) 910 mov HVIO_MSIQ_GETHEAD, %o5 911 ta FAST_TRAP 912 brz,a %o0, 1f 913 stx %o1, [%o2] 9141: retl 915 nop 916 SET_SIZE(hvio_msiq_gethead) 917 918 /* 919 * arg0 - devhandle 920 * arg1 - msiq_id 921 * arg2 - msiq_head 922 * 923 * ret0 - status 924 */ 925 ENTRY(hvio_msiq_sethead) 926 mov HVIO_MSIQ_SETHEAD, %o5 927 ta FAST_TRAP 928 retl 929 nop 930 SET_SIZE(hvio_msiq_sethead) 931 932 /* 933 * arg0 - devhandle 934 * arg1 - msiq_id 935 * 936 * ret0 - status 937 * ret1 - msiq_tail 938 */ 939 ENTRY(hvio_msiq_gettail) 940 mov HVIO_MSIQ_GETTAIL, %o5 941 ta FAST_TRAP 942 brz,a %o0, 1f 943 stx %o1, [%o2] 9441: retl 945 nop 946 SET_SIZE(hvio_msiq_gettail) 947 948 /* 949 * arg0 - devhandle 950 * arg1 - msi_num 951 * 952 * ret0 - status 953 * ret1 - msiq_id 954 */ 955 ENTRY(hvio_msi_getmsiq) 956 mov HVIO_MSI_GETMSIQ, %o5 957 ta FAST_TRAP 958 brz,a %o0, 1f 959 stuw %o1, [%o2] 9601: retl 961 nop 962 SET_SIZE(hvio_msi_getmsiq) 963 964 /* 965 * arg0 - devhandle 966 * arg1 - msi_num 967 * arg2 - msiq_id 968 * arg2 - msitype 969 * 970 * ret0 - status 971 */ 972 ENTRY(hvio_msi_setmsiq) 973 mov HVIO_MSI_SETMSIQ, %o5 974 ta FAST_TRAP 975 retl 976 nop 977 SET_SIZE(hvio_msi_setmsiq) 978 979 /* 980 * arg0 - devhandle 981 * arg1 - msi_num 982 * 983 * ret0 - status 984 * ret1 - msi_valid_state 985 */ 986 ENTRY(hvio_msi_getvalid) 987 mov HVIO_MSI_GETVALID, %o5 988 ta FAST_TRAP 989 brz,a %o0, 1f 990 stuw %o1, [%o2] 9911: retl 992 nop 993 SET_SIZE(hvio_msi_getvalid) 994 995 /* 996 * arg0 - devhandle 997 * arg1 - msi_num 998 * arg2 - msi_valid_state 999 * 1000 * ret0 - status 1001 */ 1002 ENTRY(hvio_msi_setvalid) 1003 mov HVIO_MSI_SETVALID, %o5 1004 ta FAST_TRAP 1005 retl 1006 nop 1007 SET_SIZE(hvio_msi_setvalid) 1008 1009 /* 1010 * arg0 - devhandle 1011 * arg1 - msi_num 1012 * 1013 * ret0 - status 1014 * ret1 - msi_state 1015 */ 1016 ENTRY(hvio_msi_getstate) 1017 mov HVIO_MSI_GETSTATE, %o5 1018 ta FAST_TRAP 1019 brz,a %o0, 1f 1020 stuw %o1, [%o2] 10211: retl 1022 nop 1023 SET_SIZE(hvio_msi_getstate) 1024 1025 /* 1026 * arg0 - devhandle 1027 * arg1 - msi_num 1028 * arg2 - msi_state 1029 * 1030 * ret0 - status 1031 */ 1032 ENTRY(hvio_msi_setstate) 1033 mov HVIO_MSI_SETSTATE, %o5 1034 ta FAST_TRAP 1035 retl 1036 nop 1037 SET_SIZE(hvio_msi_setstate) 1038 1039 /* 1040 * arg0 - devhandle 1041 * arg1 - msg_type 1042 * 1043 * ret0 - status 1044 * ret1 - msiq_id 1045 */ 1046 ENTRY(hvio_msg_getmsiq) 1047 mov HVIO_MSG_GETMSIQ, %o5 1048 ta FAST_TRAP 1049 brz,a %o0, 1f 1050 stuw %o1, [%o2] 10511: retl 1052 nop 1053 SET_SIZE(hvio_msg_getmsiq) 1054 1055 /* 1056 * arg0 - devhandle 1057 * arg1 - msg_type 1058 * arg2 - msiq_id 1059 * 1060 * ret0 - status 1061 */ 1062 ENTRY(hvio_msg_setmsiq) 1063 mov HVIO_MSG_SETMSIQ, %o5 1064 ta FAST_TRAP 1065 retl 1066 nop 1067 SET_SIZE(hvio_msg_setmsiq) 1068 1069 /* 1070 * arg0 - devhandle 1071 * arg1 - msg_type 1072 * 1073 * ret0 - status 1074 * ret1 - msg_valid_state 1075 */ 1076 ENTRY(hvio_msg_getvalid) 1077 mov HVIO_MSG_GETVALID, %o5 1078 ta FAST_TRAP 1079 brz,a %o0, 1f 1080 stuw %o1, [%o2] 10811: retl 1082 nop 1083 SET_SIZE(hvio_msg_getvalid) 1084 1085 /* 1086 * arg0 - devhandle 1087 * arg1 - msg_type 1088 * arg2 - msg_valid_state 1089 * 1090 * ret0 - status 1091 */ 1092 ENTRY(hvio_msg_setvalid) 1093 mov HVIO_MSG_SETVALID, %o5 1094 ta FAST_TRAP 1095 retl 1096 nop 1097 SET_SIZE(hvio_msg_setvalid) 1098 1099 /* 1100 * hv_cpu_yield(void) 1101 */ 1102 ENTRY(hv_cpu_yield) 1103 mov HV_CPU_YIELD, %o5 1104 ta FAST_TRAP 1105 retl 1106 nop 1107 SET_SIZE(hv_cpu_yield) 1108 1109 /* 1110 * hv_service_recv(uint64_t s_id, uint64_t buf_pa, 1111 * uint64_t size, uint64_t *recv_bytes); 1112 */ 1113 ENTRY(hv_service_recv) 1114 save %sp, -SA(MINFRAME), %sp 1115 mov %i0, %o0 1116 mov %i1, %o1 1117 mov %i2, %o2 1118 mov %i3, %o3 1119 mov SVC_RECV, %o5 1120 ta FAST_TRAP 1121 brnz %o0, 1f 1122 mov %o0, %i0 1123 stx %o1, [%i3] 11241: 1125 ret 1126 restore 1127 SET_SIZE(hv_service_recv) 1128 1129 /* 1130 * hv_service_send(uint64_t s_id, uint64_t buf_pa, 1131 * uint64_t size, uint64_t *recv_bytes); 1132 */ 1133 ENTRY(hv_service_send) 1134 save %sp, -SA(MINFRAME), %sp 1135 mov %i0, %o0 1136 mov %i1, %o1 1137 mov %i2, %o2 1138 mov %i3, %o3 1139 mov SVC_SEND, %o5 1140 ta FAST_TRAP 1141 brnz %o0, 1f 1142 mov %o0, %i0 1143 stx %o1, [%i3] 11441: 1145 ret 1146 restore 1147 SET_SIZE(hv_service_send) 1148 1149 /* 1150 * hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 1151 */ 1152 ENTRY(hv_service_getstatus) 1153 mov %o1, %o4 ! save datap 1154 mov SVC_GETSTATUS, %o5 1155 ta FAST_TRAP 1156 brz,a %o0, 1f 1157 stx %o1, [%o4] 11581: 1159 retl 1160 nop 1161 SET_SIZE(hv_service_getstatus) 1162 1163 /* 1164 * hv_service_setstatus(uint64_t s_id, uint64_t bits); 1165 */ 1166 ENTRY(hv_service_setstatus) 1167 mov SVC_SETSTATUS, %o5 1168 ta FAST_TRAP 1169 retl 1170 nop 1171 SET_SIZE(hv_service_setstatus) 1172 1173 /* 1174 * hv_service_clrstatus(uint64_t s_id, uint64_t bits); 1175 */ 1176 ENTRY(hv_service_clrstatus) 1177 mov SVC_CLRSTATUS, %o5 1178 ta FAST_TRAP 1179 retl 1180 nop 1181 SET_SIZE(hv_service_clrstatus) 1182 1183 /* 1184 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 1185 */ 1186 ENTRY(hv_cpu_state) 1187 mov %o1, %o4 ! save datap 1188 mov HV_CPU_STATE, %o5 1189 ta FAST_TRAP 1190 brz,a %o0, 1f 1191 stx %o1, [%o4] 11921: 1193 retl 1194 nop 1195 SET_SIZE(hv_cpu_state) 1196 1197 /* 1198 * HV state dump zone Configure 1199 * arg0 real adrs of dump buffer (%o0) 1200 * arg1 size of dump buffer (%o1) 1201 * ret0 status (%o0) 1202 * ret1 size of buffer on success and min size on EINVAL (%o1) 1203 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 1204 */ 1205 ENTRY(hv_dump_buf_update) 1206 mov DUMP_BUF_UPDATE, %o5 1207 ta FAST_TRAP 1208 retl 1209 stx %o1, [%o2] 1210 SET_SIZE(hv_dump_buf_update) 1211 1212 1213 /* 1214 * For memory scrub 1215 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 1216 * uint64_t *scrubbed_len); 1217 * Retun %o0 -- status 1218 * %o1 -- bytes scrubbed 1219 */ 1220 ENTRY(hv_mem_scrub) 1221 mov %o2, %o4 1222 mov HV_MEM_SCRUB, %o5 1223 ta FAST_TRAP 1224 retl 1225 stx %o1, [%o4] 1226 SET_SIZE(hv_mem_scrub) 1227 1228 /* 1229 * Flush ecache 1230 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 1231 * uint64_t *flushed_len); 1232 * Retun %o0 -- status 1233 * %o1 -- bytes flushed 1234 */ 1235 ENTRY(hv_mem_sync) 1236 mov %o2, %o4 1237 mov HV_MEM_SYNC, %o5 1238 ta FAST_TRAP 1239 retl 1240 stx %o1, [%o4] 1241 SET_SIZE(hv_mem_sync) 1242 1243 /* 1244 * TTRACE_BUF_CONF Configure 1245 * arg0 RA base of buffer (%o0) 1246 * arg1 buf size in no. of entries (%o1) 1247 * ret0 status (%o0) 1248 * ret1 minimum size in no. of entries on failure, 1249 * actual size in no. of entries on success (%o1) 1250 */ 1251 ENTRY(hv_ttrace_buf_conf) 1252 mov TTRACE_BUF_CONF, %o5 1253 ta FAST_TRAP 1254 retl 1255 stx %o1, [%o2] 1256 SET_SIZE(hv_ttrace_buf_conf) 1257 1258 /* 1259 * TTRACE_BUF_INFO 1260 * ret0 status (%o0) 1261 * ret1 RA base of buffer (%o1) 1262 * ret2 size in no. of entries (%o2) 1263 */ 1264 ENTRY(hv_ttrace_buf_info) 1265 mov %o0, %o3 1266 mov %o1, %o4 1267 mov TTRACE_BUF_INFO, %o5 1268 ta FAST_TRAP 1269 stx %o1, [%o3] 1270 retl 1271 stx %o2, [%o4] 1272 SET_SIZE(hv_ttrace_buf_info) 1273 1274 /* 1275 * TTRACE_ENABLE 1276 * arg0 enable/ disable (%o0) 1277 * ret0 status (%o0) 1278 * ret1 previous enable state (%o1) 1279 */ 1280 ENTRY(hv_ttrace_enable) 1281 mov %o1, %o2 1282 mov TTRACE_ENABLE, %o5 1283 ta FAST_TRAP 1284 retl 1285 stx %o1, [%o2] 1286 SET_SIZE(hv_ttrace_enable) 1287 1288 /* 1289 * TTRACE_FREEZE 1290 * arg0 enable/ freeze (%o0) 1291 * ret0 status (%o0) 1292 * ret1 previous freeze state (%o1) 1293 */ 1294 ENTRY(hv_ttrace_freeze) 1295 mov %o1, %o2 1296 mov TTRACE_FREEZE, %o5 1297 ta FAST_TRAP 1298 retl 1299 stx %o1, [%o2] 1300 SET_SIZE(hv_ttrace_freeze) 1301 1302 /* 1303 * MACH_DESC 1304 * arg0 buffer real address 1305 * arg1 pointer to uint64_t for size of buffer 1306 * ret0 status 1307 * ret1 return required size of buffer / returned data size 1308 */ 1309 ENTRY(hv_mach_desc) 1310 mov %o1, %o4 ! save datap 1311 ldx [%o1], %o1 1312 mov HV_MACH_DESC, %o5 1313 ta FAST_TRAP 1314 retl 1315 stx %o1, [%o4] 1316 SET_SIZE(hv_mach_desc) 1317 1318 /* 1319 * hv_ncs_request(int cmd, uint64_t realaddr, size_t sz) 1320 */ 1321 ENTRY(hv_ncs_request) 1322 mov HV_NCS_REQUEST, %o5 1323 ta FAST_TRAP 1324 retl 1325 nop 1326 SET_SIZE(hv_ncs_request) 1327 1328 /* 1329 * hv_ra2pa(uint64_t ra) 1330 * 1331 * MACH_DESC 1332 * arg0 Real address to convert 1333 * ret0 Returned physical address or -1 on error 1334 */ 1335 ENTRY(hv_ra2pa) 1336 mov HV_RA2PA, %o5 1337 ta FAST_TRAP 1338 cmp %o0, 0 1339 move %xcc, %o1, %o0 1340 movne %xcc, -1, %o0 1341 retl 1342 nop 1343 SET_SIZE(hv_ra2pa) 1344 1345 /* 1346 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 1347 * 1348 * MACH_DESC 1349 * arg0 OS function to call 1350 * arg1 First arg to OS function 1351 * arg2 Second arg to OS function 1352 * arg3 Third arg to OS function 1353 * ret0 Returned value from function 1354 */ 1355 1356 ENTRY(hv_hpriv) 1357 mov HV_HPRIV, %o5 1358 ta FAST_TRAP 1359 retl 1360 nop 1361 SET_SIZE(hv_hpriv) 1362 1363#endif /* lint || __lint */ 1364