1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ib_ino_info_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 /* 326 * If HV VPCI version is 1.1 and higher, pass the BDF, phantom 327 * function, and relax ordering information. Otherwise, justp pass 328 * read or write attribute information. 329 */ 330 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 331 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 332 333 while ((ttes_mapped = pfn_p - pfns) < pages) { 334 uintptr_t ra = va_to_pa(pfn_p); 335 pages_t ttes2map; 336 uint64_t ret; 337 338 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 339 ra = MMU_PTOB(MMU_BTOP(ra)); 340 341 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 342 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 343 344 ttes_mapped = 0; 345 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 346 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 347 ttes2map, attr, (io_page_list_t *)(ra | 348 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 349 &ttes_mapped)) != H_EOK) { 350 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 351 "ret 0x%lx\n", ret); 352 353 ttes_mapped = pfn_p - pfns; 354 err = DDI_FAILURE; 355 goto cleanup; 356 } 357 358 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 359 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 360 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 361 tsb_index + (pfn_p - pfns), ttes2map, attr, 362 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 363 ttes_mapped); 364 } 365 } 366 367 cleanup: 368 if ((err == DDI_FAILURE) && ttes_mapped) 369 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 370 371 kmem_free(pfns, pages * sizeof (io_page_list_t)); 372 return (err); 373 } 374 375 /*ARGSUSED*/ 376 int 377 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 378 { 379 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 380 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 381 pages_t ttes2demap, ttes_demapped = 0; 382 uint64_t ret; 383 384 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 385 "pages 0x%x\n", dip, tsbid, pages); 386 387 for (ttes2demap = pages; ttes2demap; 388 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 389 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 390 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 391 &ttes_demapped)) != H_EOK) { 392 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 393 "ret 0x%lx\n", ret); 394 395 return (DDI_FAILURE); 396 } 397 398 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 399 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 400 tsb_num, tsb_index, ttes2demap, ttes_demapped); 401 } 402 403 return (DDI_SUCCESS); 404 } 405 406 /*ARGSUSED*/ 407 int 408 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 409 r_addr_t *r_addr_p) 410 { 411 uint64_t ret; 412 413 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 414 dip, tsbid); 415 416 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 417 attr_p, r_addr_p)) != H_EOK) { 418 DBG(DBG_LIB_DMA, dip, 419 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 420 421 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 422 } 423 424 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 425 *attr_p, *r_addr_p); 426 427 return (DDI_SUCCESS); 428 } 429 430 /*ARGSUSED*/ 431 uint64_t 432 px_get_rng_parent_hi_mask(px_t *px_p) 433 { 434 return (PX_RANGE_PROP_MASK); 435 } 436 437 /* 438 * Checks dma attributes against system bypass ranges 439 * A sun4v device must be capable of generating the entire 64-bit 440 * address in order to perform bypass DMA. 441 */ 442 /*ARGSUSED*/ 443 int 444 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 445 uint64_t *lo_p, uint64_t *hi_p) 446 { 447 if ((attr_p->dma_attr_addr_lo != 0ull) || 448 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 449 450 return (DDI_DMA_BADATTR); 451 } 452 453 *lo_p = 0ull; 454 *hi_p = UINT64_MAX; 455 456 return (DDI_SUCCESS); 457 } 458 459 460 /*ARGSUSED*/ 461 int 462 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 463 io_addr_t *io_addr_p) 464 { 465 uint64_t ret; 466 467 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 468 "attr 0x%x\n", dip, ra, attr); 469 470 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 471 attr, io_addr_p)) != H_EOK) { 472 DBG(DBG_LIB_DMA, dip, 473 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 474 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 475 } 476 477 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 478 *io_addr_p); 479 480 return (DDI_SUCCESS); 481 } 482 483 /*ARGSUSED*/ 484 int 485 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 486 off_t off, size_t len, uint_t cache_flags) 487 { 488 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 489 uint64_t sync_dir; 490 px_dvma_addr_t dvma_addr, pg_off; 491 size_t num_sync; 492 uint64_t status = H_EOK; 493 494 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 495 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 496 dip, rdip, handle, off, len, cache_flags); 497 498 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 499 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 500 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 501 return (DDI_FAILURE); 502 } 503 504 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 505 return (DDI_SUCCESS); 506 507 if (!len) 508 len = mp->dmai_size; 509 510 pg_off = mp->dmai_offset; /* start min */ 511 dvma_addr = MAX(off, pg_off); /* lo */ 512 pg_off += mp->dmai_size; /* end max */ 513 pg_off = MIN(off + len, pg_off); /* hi */ 514 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 515 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 516 ddi_driver_name(rdip), ddi_get_instance(rdip), 517 off, len, mp->dmai_offset, 518 mp->dmai_offset + mp->dmai_size); 519 return (DDI_FAILURE); 520 } 521 522 len = pg_off - dvma_addr; /* sz = hi - lo */ 523 dvma_addr += mp->dmai_mapping; /* start addr */ 524 525 if (mp->dmai_rflags & DDI_DMA_READ) 526 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 527 else 528 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 529 530 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 531 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 532 sync_dir, &num_sync); 533 dvma_addr += num_sync; 534 } 535 536 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 537 } 538 539 540 /* 541 * MSIQ Functions: 542 */ 543 544 /*ARGSUSED*/ 545 int 546 px_lib_msiq_init(dev_info_t *dip) 547 { 548 px_t *px_p = DIP_TO_STATE(dip); 549 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 550 uint64_t *msiq_addr, ra; 551 size_t msiq_size; 552 uint_t rec_cnt; 553 int i, err = DDI_SUCCESS; 554 uint64_t ret; 555 556 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 557 558 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 559 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 560 561 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 562 563 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 564 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 565 566 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 567 (i + msiq_state_p->msiq_1st_msiq_id), 568 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 569 DBG(DBG_LIB_MSIQ, dip, 570 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 571 err = DDI_FAILURE; 572 break; 573 } 574 575 if ((err = px_lib_msiq_info(dip, 576 (i + msiq_state_p->msiq_1st_msiq_id), 577 &ra, &rec_cnt)) != DDI_SUCCESS) { 578 DBG(DBG_LIB_MSIQ, dip, 579 "px_lib_msiq_info failed, ret 0x%x\n", err); 580 err = DDI_FAILURE; 581 break; 582 } 583 584 DBG(DBG_LIB_MSIQ, dip, 585 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 586 } 587 588 return (err); 589 } 590 591 /*ARGSUSED*/ 592 int 593 px_lib_msiq_fini(dev_info_t *dip) 594 { 595 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 596 597 return (DDI_SUCCESS); 598 } 599 600 /*ARGSUSED*/ 601 int 602 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 603 uint_t *msiq_rec_cnt_p) 604 { 605 uint64_t ret; 606 607 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 608 dip, msiq_id); 609 610 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 611 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 612 DBG(DBG_LIB_MSIQ, dip, 613 "hvio_msiq_info failed, ret 0x%lx\n", ret); 614 return (DDI_FAILURE); 615 } 616 617 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 618 ra_p, *msiq_rec_cnt_p); 619 620 return (DDI_SUCCESS); 621 } 622 623 /*ARGSUSED*/ 624 int 625 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 626 pci_msiq_valid_state_t *msiq_valid_state) 627 { 628 uint64_t ret; 629 630 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 631 dip, msiq_id); 632 633 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 634 msiq_id, msiq_valid_state)) != H_EOK) { 635 DBG(DBG_LIB_MSIQ, dip, 636 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 637 return (DDI_FAILURE); 638 } 639 640 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 641 *msiq_valid_state); 642 643 return (DDI_SUCCESS); 644 } 645 646 /*ARGSUSED*/ 647 int 648 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 649 pci_msiq_valid_state_t msiq_valid_state) 650 { 651 uint64_t ret; 652 653 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 654 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 655 656 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 657 msiq_id, msiq_valid_state)) != H_EOK) { 658 DBG(DBG_LIB_MSIQ, dip, 659 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 660 return (DDI_FAILURE); 661 } 662 663 return (DDI_SUCCESS); 664 } 665 666 /*ARGSUSED*/ 667 int 668 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 669 pci_msiq_state_t *msiq_state) 670 { 671 uint64_t ret; 672 673 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 674 dip, msiq_id); 675 676 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 677 msiq_id, msiq_state)) != H_EOK) { 678 DBG(DBG_LIB_MSIQ, dip, 679 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 680 return (DDI_FAILURE); 681 } 682 683 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 684 *msiq_state); 685 686 return (DDI_SUCCESS); 687 } 688 689 /*ARGSUSED*/ 690 int 691 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 692 pci_msiq_state_t msiq_state) 693 { 694 uint64_t ret; 695 696 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 697 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 698 699 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 700 msiq_id, msiq_state)) != H_EOK) { 701 DBG(DBG_LIB_MSIQ, dip, 702 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 703 return (DDI_FAILURE); 704 } 705 706 return (DDI_SUCCESS); 707 } 708 709 /*ARGSUSED*/ 710 int 711 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 712 msiqhead_t *msiq_head_p) 713 { 714 uint64_t ret; 715 716 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 717 dip, msiq_id); 718 719 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 720 msiq_id, msiq_head_p)) != H_EOK) { 721 DBG(DBG_LIB_MSIQ, dip, 722 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 723 return (DDI_FAILURE); 724 } 725 726 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 727 728 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 729 *msiq_head_p); 730 731 return (DDI_SUCCESS); 732 } 733 734 /*ARGSUSED*/ 735 int 736 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 737 msiqhead_t msiq_head) 738 { 739 uint64_t ret; 740 741 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 742 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 743 744 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 745 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 746 DBG(DBG_LIB_MSIQ, dip, 747 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 748 return (DDI_FAILURE); 749 } 750 751 return (DDI_SUCCESS); 752 } 753 754 /*ARGSUSED*/ 755 int 756 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 757 msiqtail_t *msiq_tail_p) 758 { 759 uint64_t ret; 760 761 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 762 dip, msiq_id); 763 764 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 765 msiq_id, msiq_tail_p)) != H_EOK) { 766 DBG(DBG_LIB_MSIQ, dip, 767 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 768 return (DDI_FAILURE); 769 } 770 771 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 772 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 773 *msiq_tail_p); 774 775 return (DDI_SUCCESS); 776 } 777 778 /*ARGSUSED*/ 779 void 780 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 781 msiq_rec_t *msiq_rec_p) 782 { 783 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 784 785 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 786 787 if (!curr_msiq_rec_p->msiq_rec_type) 788 return; 789 790 *msiq_rec_p = *curr_msiq_rec_p; 791 792 /* Zero out msiq_rec_type field */ 793 curr_msiq_rec_p->msiq_rec_type = 0; 794 } 795 796 /* 797 * MSI Functions: 798 */ 799 800 /*ARGSUSED*/ 801 int 802 px_lib_msi_init(dev_info_t *dip) 803 { 804 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 805 806 /* Noop */ 807 return (DDI_SUCCESS); 808 } 809 810 /*ARGSUSED*/ 811 int 812 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 813 msiqid_t *msiq_id) 814 { 815 uint64_t ret; 816 817 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 818 dip, msi_num); 819 820 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 821 msi_num, msiq_id)) != H_EOK) { 822 DBG(DBG_LIB_MSI, dip, 823 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 824 return (DDI_FAILURE); 825 } 826 827 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 828 *msiq_id); 829 830 return (DDI_SUCCESS); 831 } 832 833 /*ARGSUSED*/ 834 int 835 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 836 msiqid_t msiq_id, msi_type_t msitype) 837 { 838 uint64_t ret; 839 840 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 841 "msq_id 0x%x\n", dip, msi_num, msiq_id); 842 843 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 844 msi_num, msiq_id, msitype)) != H_EOK) { 845 DBG(DBG_LIB_MSI, dip, 846 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 847 return (DDI_FAILURE); 848 } 849 850 return (DDI_SUCCESS); 851 } 852 853 /*ARGSUSED*/ 854 int 855 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 856 pci_msi_valid_state_t *msi_valid_state) 857 { 858 uint64_t ret; 859 860 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 861 dip, msi_num); 862 863 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 864 msi_num, msi_valid_state)) != H_EOK) { 865 DBG(DBG_LIB_MSI, dip, 866 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 867 return (DDI_FAILURE); 868 } 869 870 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 871 *msi_valid_state); 872 873 return (DDI_SUCCESS); 874 } 875 876 /*ARGSUSED*/ 877 int 878 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 879 pci_msi_valid_state_t msi_valid_state) 880 { 881 uint64_t ret; 882 883 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 884 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 885 886 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 887 msi_num, msi_valid_state)) != H_EOK) { 888 DBG(DBG_LIB_MSI, dip, 889 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 890 return (DDI_FAILURE); 891 } 892 893 return (DDI_SUCCESS); 894 } 895 896 /*ARGSUSED*/ 897 int 898 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 899 pci_msi_state_t *msi_state) 900 { 901 uint64_t ret; 902 903 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 904 dip, msi_num); 905 906 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 907 msi_num, msi_state)) != H_EOK) { 908 DBG(DBG_LIB_MSI, dip, 909 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 910 return (DDI_FAILURE); 911 } 912 913 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 914 *msi_state); 915 916 return (DDI_SUCCESS); 917 } 918 919 /*ARGSUSED*/ 920 int 921 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 922 pci_msi_state_t msi_state) 923 { 924 uint64_t ret; 925 926 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 927 "msi_state 0x%x\n", dip, msi_num, msi_state); 928 929 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 930 msi_num, msi_state)) != H_EOK) { 931 DBG(DBG_LIB_MSI, dip, 932 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 933 return (DDI_FAILURE); 934 } 935 936 return (DDI_SUCCESS); 937 } 938 939 /* 940 * MSG Functions: 941 */ 942 943 /*ARGSUSED*/ 944 int 945 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 946 msiqid_t *msiq_id) 947 { 948 uint64_t ret; 949 950 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 951 dip, msg_type); 952 953 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 954 msg_type, msiq_id)) != H_EOK) { 955 DBG(DBG_LIB_MSG, dip, 956 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 957 return (DDI_FAILURE); 958 } 959 960 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 961 *msiq_id); 962 963 return (DDI_SUCCESS); 964 } 965 966 /*ARGSUSED*/ 967 int 968 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 969 msiqid_t msiq_id) 970 { 971 uint64_t ret; 972 973 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 974 "msq_id 0x%x\n", dip, msg_type, msiq_id); 975 976 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 977 msg_type, msiq_id)) != H_EOK) { 978 DBG(DBG_LIB_MSG, dip, 979 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 980 return (DDI_FAILURE); 981 } 982 983 return (DDI_SUCCESS); 984 } 985 986 /*ARGSUSED*/ 987 int 988 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 989 pcie_msg_valid_state_t *msg_valid_state) 990 { 991 uint64_t ret; 992 993 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 994 dip, msg_type); 995 996 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 997 msg_valid_state)) != H_EOK) { 998 DBG(DBG_LIB_MSG, dip, 999 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1000 return (DDI_FAILURE); 1001 } 1002 1003 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1004 *msg_valid_state); 1005 1006 return (DDI_SUCCESS); 1007 } 1008 1009 /*ARGSUSED*/ 1010 int 1011 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1012 pcie_msg_valid_state_t msg_valid_state) 1013 { 1014 uint64_t ret; 1015 1016 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1017 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1018 1019 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1020 msg_valid_state)) != H_EOK) { 1021 DBG(DBG_LIB_MSG, dip, 1022 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1023 return (DDI_FAILURE); 1024 } 1025 1026 return (DDI_SUCCESS); 1027 } 1028 1029 /* 1030 * Suspend/Resume Functions: 1031 * Currently unsupported by hypervisor and all functions are noops. 1032 */ 1033 /*ARGSUSED*/ 1034 int 1035 px_lib_suspend(dev_info_t *dip) 1036 { 1037 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1038 1039 /* Not supported */ 1040 return (DDI_FAILURE); 1041 } 1042 1043 /*ARGSUSED*/ 1044 void 1045 px_lib_resume(dev_info_t *dip) 1046 { 1047 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1048 1049 /* Noop */ 1050 } 1051 1052 /* 1053 * Misc Functions: 1054 * Currently unsupported by hypervisor and all functions are noops. 1055 */ 1056 /*ARGSUSED*/ 1057 static int 1058 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1059 uint8_t size, pci_cfg_data_t *data_p) 1060 { 1061 uint64_t ret; 1062 1063 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1064 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1065 1066 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1067 size, data_p)) != H_EOK) { 1068 DBG(DBG_LIB_CFG, dip, 1069 "hvio_config_get failed, ret 0x%lx\n", ret); 1070 return (DDI_FAILURE); 1071 } 1072 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1073 1074 return (DDI_SUCCESS); 1075 } 1076 1077 /*ARGSUSED*/ 1078 static int 1079 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1080 uint8_t size, pci_cfg_data_t data) 1081 { 1082 uint64_t ret; 1083 1084 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1085 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1086 1087 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1088 size, data)) != H_EOK) { 1089 DBG(DBG_LIB_CFG, dip, 1090 "hvio_config_put failed, ret 0x%lx\n", ret); 1091 return (DDI_FAILURE); 1092 } 1093 1094 return (DDI_SUCCESS); 1095 } 1096 1097 static uint32_t 1098 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1099 { 1100 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1101 handle->ahi_common.ah_bus_private; 1102 uint32_t pci_dev_addr = px_pvt->raddr; 1103 uint32_t vaddr = px_pvt->vaddr; 1104 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1105 uint32_t rdata = 0; 1106 1107 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1108 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1109 /* XXX update error kstats */ 1110 return (0xffffffff); 1111 return (rdata); 1112 } 1113 1114 static void 1115 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1116 int size, pci_cfg_data_t wdata) 1117 { 1118 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1119 handle->ahi_common.ah_bus_private; 1120 uint32_t pci_dev_addr = px_pvt->raddr; 1121 uint32_t vaddr = px_pvt->vaddr; 1122 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1123 1124 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1125 size, wdata) != DDI_SUCCESS) { 1126 /*EMPTY*/ 1127 /* XXX update error kstats */ 1128 } 1129 } 1130 1131 static uint8_t 1132 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1133 { 1134 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1135 } 1136 1137 static uint16_t 1138 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1139 { 1140 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1141 } 1142 1143 static uint32_t 1144 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1145 { 1146 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1147 } 1148 1149 static uint64_t 1150 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1151 { 1152 uint32_t rdatah, rdatal; 1153 1154 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1155 rdatah = (uint32_t)px_pci_config_get(handle, 1156 (uint32_t *)((char *)addr+4), 4); 1157 return (((uint64_t)rdatah << 32) | rdatal); 1158 } 1159 1160 static void 1161 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1162 { 1163 pci_cfg_data_t wdata = { 0 }; 1164 1165 wdata.qw = (uint8_t)data; 1166 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1167 } 1168 1169 static void 1170 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1171 { 1172 pci_cfg_data_t wdata = { 0 }; 1173 1174 wdata.qw = (uint16_t)data; 1175 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1176 } 1177 1178 static void 1179 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1180 { 1181 pci_cfg_data_t wdata = { 0 }; 1182 1183 wdata.qw = (uint32_t)data; 1184 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1185 } 1186 1187 static void 1188 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1189 { 1190 pci_cfg_data_t wdata = { 0 }; 1191 1192 wdata.qw = (uint32_t)(data & 0xffffffff); 1193 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1194 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1195 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1196 } 1197 1198 static void 1199 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1200 uint8_t *dev_addr, size_t repcount, uint_t flags) 1201 { 1202 if (flags == DDI_DEV_AUTOINCR) 1203 for (; repcount; repcount--) 1204 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1205 else 1206 for (; repcount; repcount--) 1207 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1208 } 1209 1210 /* 1211 * Function to rep read 16 bit data off the PCI configuration space behind 1212 * the 21554's host interface. 1213 */ 1214 static void 1215 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1216 uint16_t *dev_addr, size_t repcount, uint_t flags) 1217 { 1218 if (flags == DDI_DEV_AUTOINCR) 1219 for (; repcount; repcount--) 1220 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1221 else 1222 for (; repcount; repcount--) 1223 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1224 } 1225 1226 /* 1227 * Function to rep read 32 bit data off the PCI configuration space behind 1228 * the 21554's host interface. 1229 */ 1230 static void 1231 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1232 uint32_t *dev_addr, size_t repcount, uint_t flags) 1233 { 1234 if (flags == DDI_DEV_AUTOINCR) 1235 for (; repcount; repcount--) 1236 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1237 else 1238 for (; repcount; repcount--) 1239 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1240 } 1241 1242 /* 1243 * Function to rep read 64 bit data off the PCI configuration space behind 1244 * the 21554's host interface. 1245 */ 1246 static void 1247 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1248 uint64_t *dev_addr, size_t repcount, uint_t flags) 1249 { 1250 if (flags == DDI_DEV_AUTOINCR) 1251 for (; repcount; repcount--) 1252 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1253 else 1254 for (; repcount; repcount--) 1255 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1256 } 1257 1258 /* 1259 * Function to rep write 8 bit data into the PCI configuration space behind 1260 * the 21554's host interface. 1261 */ 1262 static void 1263 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1264 uint8_t *dev_addr, size_t repcount, uint_t flags) 1265 { 1266 if (flags == DDI_DEV_AUTOINCR) 1267 for (; repcount; repcount--) 1268 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1269 else 1270 for (; repcount; repcount--) 1271 px_pci_config_put8(handle, dev_addr, *host_addr++); 1272 } 1273 1274 /* 1275 * Function to rep write 16 bit data into the PCI configuration space behind 1276 * the 21554's host interface. 1277 */ 1278 static void 1279 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1280 uint16_t *dev_addr, size_t repcount, uint_t flags) 1281 { 1282 if (flags == DDI_DEV_AUTOINCR) 1283 for (; repcount; repcount--) 1284 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1285 else 1286 for (; repcount; repcount--) 1287 px_pci_config_put16(handle, dev_addr, *host_addr++); 1288 } 1289 1290 /* 1291 * Function to rep write 32 bit data into the PCI configuration space behind 1292 * the 21554's host interface. 1293 */ 1294 static void 1295 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1296 uint32_t *dev_addr, size_t repcount, uint_t flags) 1297 { 1298 if (flags == DDI_DEV_AUTOINCR) 1299 for (; repcount; repcount--) 1300 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1301 else 1302 for (; repcount; repcount--) 1303 px_pci_config_put32(handle, dev_addr, *host_addr++); 1304 } 1305 1306 /* 1307 * Function to rep write 64 bit data into the PCI configuration space behind 1308 * the 21554's host interface. 1309 */ 1310 static void 1311 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1312 uint64_t *dev_addr, size_t repcount, uint_t flags) 1313 { 1314 if (flags == DDI_DEV_AUTOINCR) 1315 for (; repcount; repcount--) 1316 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1317 else 1318 for (; repcount; repcount--) 1319 px_pci_config_put64(handle, dev_addr, *host_addr++); 1320 } 1321 1322 /* 1323 * Provide a private access handle to route config access calls to Hypervisor. 1324 * Beware: Do all error checking for config space accesses before calling 1325 * this function. ie. do error checking from the calling function. 1326 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1327 * DDI_SUCCESS from here makes the code organization readable/easier from 1328 * the generic code. 1329 */ 1330 /*ARGSUSED*/ 1331 int 1332 px_lib_map_vconfig(dev_info_t *dip, 1333 ddi_map_req_t *mp, pci_config_offset_t off, 1334 pci_regspec_t *rp, caddr_t *addrp) 1335 { 1336 ddi_acc_hdl_t *hp; 1337 ddi_acc_impl_t *ap; 1338 uchar_t busnum; /* bus number */ 1339 uchar_t devnum; /* device number */ 1340 uchar_t funcnum; /* function number */ 1341 px_config_acc_pvt_t *px_pvt; 1342 1343 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1344 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1345 1346 /* Check for mapping teardown operation */ 1347 if ((mp->map_op == DDI_MO_UNMAP) || 1348 (mp->map_op == DDI_MO_UNLOCK)) { 1349 /* free up memory allocated for the private access handle. */ 1350 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1351 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1352 1353 /* unmap operation of PCI IO/config space. */ 1354 return (DDI_SUCCESS); 1355 } 1356 1357 ap->ahi_get8 = px_pci_config_get8; 1358 ap->ahi_get16 = px_pci_config_get16; 1359 ap->ahi_get32 = px_pci_config_get32; 1360 ap->ahi_get64 = px_pci_config_get64; 1361 ap->ahi_put8 = px_pci_config_put8; 1362 ap->ahi_put16 = px_pci_config_put16; 1363 ap->ahi_put32 = px_pci_config_put32; 1364 ap->ahi_put64 = px_pci_config_put64; 1365 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1366 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1367 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1368 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1369 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1370 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1371 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1372 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1373 1374 /* Initialize to default check/notify functions */ 1375 ap->ahi_fault = 0; 1376 ap->ahi_fault_check = i_ddi_acc_fault_check; 1377 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1378 1379 /* allocate memory for our private handle */ 1380 px_pvt = (px_config_acc_pvt_t *) 1381 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1382 hp->ah_bus_private = (void *)px_pvt; 1383 1384 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1385 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1386 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1387 1388 /* set up private data for use during IO routines */ 1389 1390 /* addr needed by the HV APIs */ 1391 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1392 /* 1393 * Address that specifies the actual offset into the 256MB 1394 * memory mapped configuration space, 4K per device. 1395 * First 12bits form the offset into 4K config space. 1396 * This address is only used during the IO routines to calculate 1397 * the offset at which the transaction must be performed. 1398 * Drivers bypassing DDI functions to access PCI config space will 1399 * panic the system since the following is a bogus virtual address. 1400 */ 1401 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1402 px_pvt->dip = dip; 1403 1404 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1405 px_pvt->raddr, px_pvt->vaddr); 1406 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1407 return (DDI_SUCCESS); 1408 } 1409 1410 /*ARGSUSED*/ 1411 void 1412 px_lib_map_attr_check(ddi_map_req_t *mp) 1413 { 1414 } 1415 1416 /* 1417 * px_lib_log_safeacc_err: 1418 * Imitate a cpu/mem trap call when a peek/poke fails. 1419 * This will initiate something similar to px_fm_callback. 1420 */ 1421 static void 1422 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1423 { 1424 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1425 ddi_fm_error_t derr; 1426 1427 derr.fme_status = DDI_FM_NONFATAL; 1428 derr.fme_version = DDI_FME_VERSION; 1429 derr.fme_flag = fme_flag; 1430 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1431 derr.fme_acc_handle = handle; 1432 if (hp) 1433 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1434 1435 mutex_enter(&px_p->px_fm_mutex); 1436 1437 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1438 1439 mutex_exit(&px_p->px_fm_mutex); 1440 } 1441 1442 1443 #ifdef DEBUG 1444 int px_peekfault_cnt = 0; 1445 int px_pokefault_cnt = 0; 1446 #endif /* DEBUG */ 1447 1448 static int 1449 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1450 { 1451 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1452 pci_regspec_t regspec_array[8]; 1453 pci_regspec_t *regspec = regspec_array; 1454 int buflen = sizeof (regspec_array); 1455 boolean_t kmalloced = B_FALSE; 1456 int status; 1457 1458 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1459 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1460 1461 /* If need more space, fallback to kmem_alloc. */ 1462 if (status == DDI_PROP_BUF_TOO_SMALL) { 1463 regspec = kmem_alloc(buflen, KM_SLEEP); 1464 1465 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1466 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1467 1468 kmalloced = B_TRUE; 1469 } 1470 1471 /* Get phys_hi from first element. All have same bdf. */ 1472 if (status == DDI_PROP_SUCCESS) 1473 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1474 1475 if (kmalloced) 1476 kmem_free(regspec, buflen); 1477 1478 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1479 } 1480 1481 /* 1482 * Do a safe write to a device. 1483 * 1484 * When this function is given a handle (cautious access), all errors are 1485 * suppressed. 1486 * 1487 * When this function is not given a handle (poke), only Unsupported Request 1488 * and Completer Abort errors are suppressed. 1489 * 1490 * In all cases, all errors are returned in the function return status. 1491 */ 1492 1493 int 1494 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1495 peekpoke_ctlops_t *in_args) 1496 { 1497 px_t *px_p = DIP_TO_STATE(dip); 1498 px_pec_t *pec_p = px_p->px_pec_p; 1499 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1500 1501 size_t repcount = in_args->repcount; 1502 size_t size = in_args->size; 1503 uintptr_t dev_addr = in_args->dev_addr; 1504 uintptr_t host_addr = in_args->host_addr; 1505 1506 int err = DDI_SUCCESS; 1507 uint64_t hvio_poke_status; 1508 uint32_t bdf; 1509 uint32_t wrt_stat; 1510 1511 r_addr_t ra; 1512 uint64_t pokeval; 1513 1514 /* 1515 * Used only to notify error handling peek/poke is occuring 1516 * One scenario is when a fabric err as a result of peek/poke. 1517 * However there is no way to guarantee that the fabric error 1518 * handler will occur in the window where otd is set. 1519 */ 1520 on_trap_data_t otd; 1521 1522 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1523 DBG(DBG_LIB_DMA, px_p->px_dip, 1524 "poke: px_lib_bdf_from_dip failed\n"); 1525 err = DDI_FAILURE; 1526 goto done; 1527 } 1528 1529 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1530 for (; repcount; repcount--) { 1531 1532 switch (size) { 1533 case sizeof (uint8_t): 1534 pokeval = *(uint8_t *)host_addr; 1535 break; 1536 case sizeof (uint16_t): 1537 pokeval = *(uint16_t *)host_addr; 1538 break; 1539 case sizeof (uint32_t): 1540 pokeval = *(uint32_t *)host_addr; 1541 break; 1542 case sizeof (uint64_t): 1543 pokeval = *(uint64_t *)host_addr; 1544 break; 1545 default: 1546 DBG(DBG_MAP, px_p->px_dip, 1547 "poke: invalid size %d passed\n", size); 1548 err = DDI_FAILURE; 1549 goto done; 1550 } 1551 1552 /* 1553 * Grab pokefault mutex since hypervisor does not guarantee 1554 * poke serialization. 1555 */ 1556 if (hp) { 1557 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1558 (ddi_acc_handle_t)hp); 1559 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1560 } else { 1561 mutex_enter(&pec_p->pec_pokefault_mutex); 1562 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1563 } 1564 pec_p->pec_ontrap_data = &otd; 1565 1566 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1567 pokeval, bdf, &wrt_stat); 1568 1569 if (otd.ot_trap & OT_DATA_ACCESS) 1570 err = DDI_FAILURE; 1571 1572 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1573 err = DDI_FAILURE; 1574 #ifdef DEBUG 1575 px_pokefault_cnt++; 1576 #endif 1577 /* 1578 * For CAUTIOUS and POKE access, notify FMA to 1579 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1580 */ 1581 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1582 (hp ? DDI_FM_ERR_EXPECTED : 1583 DDI_FM_ERR_POKE)); 1584 1585 pec_p->pec_ontrap_data = NULL; 1586 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1587 if (hp) { 1588 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1589 (ddi_acc_handle_t)hp); 1590 } else { 1591 mutex_exit(&pec_p->pec_pokefault_mutex); 1592 } 1593 goto done; 1594 } 1595 1596 pec_p->pec_ontrap_data = NULL; 1597 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1598 if (hp) { 1599 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1600 (ddi_acc_handle_t)hp); 1601 } else { 1602 mutex_exit(&pec_p->pec_pokefault_mutex); 1603 } 1604 1605 host_addr += size; 1606 1607 if (in_args->flags == DDI_DEV_AUTOINCR) { 1608 dev_addr += size; 1609 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1610 } 1611 } 1612 1613 done: 1614 return (err); 1615 } 1616 1617 1618 /*ARGSUSED*/ 1619 int 1620 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1621 peekpoke_ctlops_t *in_args, void *result) 1622 { 1623 px_t *px_p = DIP_TO_STATE(dip); 1624 px_pec_t *pec_p = px_p->px_pec_p; 1625 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1626 1627 size_t repcount = in_args->repcount; 1628 uintptr_t dev_addr = in_args->dev_addr; 1629 uintptr_t host_addr = in_args->host_addr; 1630 1631 r_addr_t ra; 1632 uint32_t read_status; 1633 uint64_t hvio_peek_status; 1634 uint64_t peekval; 1635 int err = DDI_SUCCESS; 1636 1637 /* 1638 * Used only to notify error handling peek/poke is occuring 1639 * One scenario is when a fabric err as a result of peek/poke. 1640 * However there is no way to guarantee that the fabric error 1641 * handler will occur in the window where otd is set. 1642 */ 1643 on_trap_data_t otd; 1644 1645 result = (void *)in_args->host_addr; 1646 1647 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1648 for (; repcount; repcount--) { 1649 1650 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1651 if (hp) { 1652 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1653 (ddi_acc_handle_t)hp); 1654 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1655 } else { 1656 mutex_enter(&pec_p->pec_pokefault_mutex); 1657 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1658 } 1659 pec_p->pec_ontrap_data = &otd; 1660 1661 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1662 in_args->size, &read_status, &peekval); 1663 1664 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1665 err = DDI_FAILURE; 1666 1667 /* 1668 * For CAUTIOUS and PEEK access, notify FMA to 1669 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1670 */ 1671 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1672 (hp ? DDI_FM_ERR_EXPECTED : 1673 DDI_FM_ERR_PEEK)); 1674 1675 /* Stuff FFs in host addr if peek. */ 1676 if (hp == NULL) { 1677 int i; 1678 uint8_t *ff_addr = (uint8_t *)host_addr; 1679 for (i = 0; i < in_args->size; i++) 1680 *ff_addr++ = 0xff; 1681 } 1682 #ifdef DEBUG 1683 px_peekfault_cnt++; 1684 #endif 1685 pec_p->pec_ontrap_data = NULL; 1686 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1687 if (hp) { 1688 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1689 (ddi_acc_handle_t)hp); 1690 } else { 1691 mutex_exit(&pec_p->pec_pokefault_mutex); 1692 } 1693 goto done; 1694 1695 } 1696 pec_p->pec_ontrap_data = NULL; 1697 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1698 if (hp) { 1699 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1700 (ddi_acc_handle_t)hp); 1701 } else { 1702 mutex_exit(&pec_p->pec_pokefault_mutex); 1703 } 1704 1705 switch (in_args->size) { 1706 case sizeof (uint8_t): 1707 *(uint8_t *)host_addr = (uint8_t)peekval; 1708 break; 1709 case sizeof (uint16_t): 1710 *(uint16_t *)host_addr = (uint16_t)peekval; 1711 break; 1712 case sizeof (uint32_t): 1713 *(uint32_t *)host_addr = (uint32_t)peekval; 1714 break; 1715 case sizeof (uint64_t): 1716 *(uint64_t *)host_addr = (uint64_t)peekval; 1717 break; 1718 default: 1719 DBG(DBG_MAP, px_p->px_dip, 1720 "peek: invalid size %d passed\n", 1721 in_args->size); 1722 err = DDI_FAILURE; 1723 goto done; 1724 } 1725 1726 host_addr += in_args->size; 1727 1728 if (in_args->flags == DDI_DEV_AUTOINCR) { 1729 dev_addr += in_args->size; 1730 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1731 } 1732 } 1733 done: 1734 return (err); 1735 } 1736 1737 1738 /* add interrupt vector */ 1739 int 1740 px_err_add_intr(px_fault_t *px_fault_p) 1741 { 1742 int ret; 1743 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1744 1745 DBG(DBG_LIB_INT, px_p->px_dip, 1746 "px_err_add_intr: calling add_ivintr"); 1747 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1748 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1749 (caddr_t)&px_fault_p->px_intr_payload[0]); 1750 1751 if (ret != DDI_SUCCESS) { 1752 DBG(DBG_LIB_INT, px_p->px_dip, 1753 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1754 1755 return (ret); 1756 } 1757 DBG(DBG_LIB_INT, px_p->px_dip, 1758 "px_err_add_intr: ib_intr_enable "); 1759 1760 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1761 1762 return (ret); 1763 } 1764 1765 /* remove interrupt vector */ 1766 void 1767 px_err_rem_intr(px_fault_t *px_fault_p) 1768 { 1769 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1770 1771 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1772 IB_INTR_WAIT); 1773 1774 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1775 } 1776 1777 int 1778 px_cb_add_intr(px_fault_t *f_p) 1779 { 1780 return (px_err_add_intr(f_p)); 1781 } 1782 1783 void 1784 px_cb_rem_intr(px_fault_t *f_p) 1785 { 1786 px_err_rem_intr(f_p); 1787 } 1788 1789 void 1790 px_cb_intr_redist(px_t *px_p) 1791 { 1792 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1793 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1794 } 1795 1796 #ifdef FMA 1797 void 1798 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1799 { 1800 px_pec_err_t *err_pkt; 1801 1802 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1803 1804 /* initialise all the structure members */ 1805 rc_status->status_valid = 0; 1806 1807 if (err_pkt->pec_descr.P) { 1808 /* PCI Status Register */ 1809 rc_status->pci_err_status = err_pkt->pci_err_status; 1810 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1811 } 1812 1813 if (err_pkt->pec_descr.E) { 1814 /* PCIe Status Register */ 1815 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1816 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1817 } 1818 1819 if (err_pkt->pec_descr.U) { 1820 rc_status->ue_status = err_pkt->ue_reg_status; 1821 rc_status->status_valid |= UE_STATUS_VALID; 1822 } 1823 1824 if (err_pkt->pec_descr.H) { 1825 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1826 rc_status->status_valid |= UE_HDR1_VALID; 1827 } 1828 1829 if (err_pkt->pec_descr.I) { 1830 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1831 rc_status->status_valid |= UE_HDR2_VALID; 1832 } 1833 1834 /* ue_fst_err_ptr - not available for sun4v?? */ 1835 1836 1837 if (err_pkt->pec_descr.S) { 1838 rc_status->source_id = err_pkt->err_src_reg; 1839 rc_status->status_valid |= SOURCE_ID_VALID; 1840 } 1841 1842 if (err_pkt->pec_descr.R) { 1843 rc_status->root_err_status = err_pkt->root_err_status; 1844 rc_status->status_valid |= CE_STATUS_VALID; 1845 } 1846 } 1847 #endif 1848 1849 /*ARGSUSED*/ 1850 int 1851 px_lib_pmctl(int cmd, px_t *px_p) 1852 { 1853 return (DDI_FAILURE); 1854 } 1855 1856 /*ARGSUSED*/ 1857 uint_t 1858 px_pmeq_intr(caddr_t arg) 1859 { 1860 return (DDI_INTR_CLAIMED); 1861 } 1862 1863 /* 1864 * Unprotected raw reads/writes of fabric device's config space. 1865 * Only used for temporary PCI-E Fabric Error Handling. 1866 */ 1867 uint32_t 1868 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1869 uint32_t data = 0; 1870 1871 (void) hvio_config_get(px_p->px_dev_hdl, 1872 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1873 (pci_cfg_data_t *)&data); 1874 1875 return (data); 1876 } 1877 1878 void 1879 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1880 uint32_t val) { 1881 pci_cfg_data_t wdata = { 0 }; 1882 1883 wdata.qw = (uint32_t)val; 1884 (void) hvio_config_put(px_p->px_dev_hdl, 1885 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1886 } 1887 1888 /*ARGSUSED*/ 1889 int 1890 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1891 { 1892 return (DDI_ENOTSUP); 1893 } 1894 1895 /*ARGSUSED*/ 1896 void 1897 px_lib_hotplug_uninit(dev_info_t *dip) 1898 { 1899 } 1900 1901 /* Dummy cpr add callback */ 1902 /*ARGSUSED*/ 1903 void 1904 px_cpr_add_callb(px_t *px_p) 1905 { 1906 } 1907 1908 /* Dummy cpr rem callback */ 1909 /*ARGSUSED*/ 1910 void 1911 px_cpr_rem_callb(px_t *px_p) 1912 { 1913 } 1914 1915 /*ARGSUSED*/ 1916 boolean_t 1917 px_lib_is_in_drain_state(px_t *px_p) 1918 { 1919 return (B_FALSE); 1920 } 1921