1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ino_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 /* 326 * If HV VPCI version is 1.1 and higher, pass the BDF, phantom 327 * function, and relax ordering information. Otherwise, justp pass 328 * read or write attribute information. 329 */ 330 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 331 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 332 333 while ((ttes_mapped = pfn_p - pfns) < pages) { 334 uintptr_t ra = va_to_pa(pfn_p); 335 pages_t ttes2map; 336 uint64_t ret; 337 338 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 339 ra = MMU_PTOB(MMU_BTOP(ra)); 340 341 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 342 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 343 344 ttes_mapped = 0; 345 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 346 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 347 ttes2map, attr, (io_page_list_t *)(ra | 348 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 349 &ttes_mapped)) != H_EOK) { 350 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 351 "ret 0x%lx\n", ret); 352 353 ttes_mapped = pfn_p - pfns; 354 err = DDI_FAILURE; 355 goto cleanup; 356 } 357 358 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 359 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 360 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 361 tsb_index + (pfn_p - pfns), ttes2map, attr, 362 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 363 ttes_mapped); 364 } 365 } 366 367 cleanup: 368 if ((err == DDI_FAILURE) && ttes_mapped) 369 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 370 371 kmem_free(pfns, pages * sizeof (io_page_list_t)); 372 return (err); 373 } 374 375 /*ARGSUSED*/ 376 int 377 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 378 { 379 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 380 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 381 pages_t ttes2demap, ttes_demapped = 0; 382 uint64_t ret; 383 384 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 385 "pages 0x%x\n", dip, tsbid, pages); 386 387 for (ttes2demap = pages; ttes2demap; 388 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 389 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 390 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 391 &ttes_demapped)) != H_EOK) { 392 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 393 "ret 0x%lx\n", ret); 394 395 return (DDI_FAILURE); 396 } 397 398 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 399 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 400 tsb_num, tsb_index, ttes2demap, ttes_demapped); 401 } 402 403 return (DDI_SUCCESS); 404 } 405 406 /*ARGSUSED*/ 407 int 408 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 409 r_addr_t *r_addr_p) 410 { 411 uint64_t ret; 412 413 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 414 dip, tsbid); 415 416 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 417 attr_p, r_addr_p)) != H_EOK) { 418 DBG(DBG_LIB_DMA, dip, 419 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 420 421 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 422 } 423 424 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 425 *attr_p, *r_addr_p); 426 427 return (DDI_SUCCESS); 428 } 429 430 /*ARGSUSED*/ 431 uint64_t 432 px_get_rng_parent_hi_mask(px_t *px_p) 433 { 434 return (PX_RANGE_PROP_MASK); 435 } 436 437 /* 438 * Checks dma attributes against system bypass ranges 439 * A sun4v device must be capable of generating the entire 64-bit 440 * address in order to perform bypass DMA. 441 */ 442 /*ARGSUSED*/ 443 int 444 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 445 uint64_t *lo_p, uint64_t *hi_p) 446 { 447 if ((attr_p->dma_attr_addr_lo != 0ull) || 448 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 449 450 return (DDI_DMA_BADATTR); 451 } 452 453 *lo_p = 0ull; 454 *hi_p = UINT64_MAX; 455 456 return (DDI_SUCCESS); 457 } 458 459 460 /*ARGSUSED*/ 461 int 462 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 463 io_addr_t *io_addr_p) 464 { 465 uint64_t ret; 466 467 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 468 "attr 0x%x\n", dip, ra, attr); 469 470 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 471 attr, io_addr_p)) != H_EOK) { 472 DBG(DBG_LIB_DMA, dip, 473 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 474 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 475 } 476 477 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 478 *io_addr_p); 479 480 return (DDI_SUCCESS); 481 } 482 483 /*ARGSUSED*/ 484 int 485 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 486 off_t off, size_t len, uint_t cache_flags) 487 { 488 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 489 uint64_t sync_dir; 490 px_dvma_addr_t dvma_addr, pg_off; 491 size_t num_sync; 492 uint64_t status = H_EOK; 493 494 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 495 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 496 dip, rdip, handle, off, len, cache_flags); 497 498 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 499 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 500 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 501 return (DDI_FAILURE); 502 } 503 504 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 505 return (DDI_SUCCESS); 506 507 if (!len) 508 len = mp->dmai_size; 509 510 pg_off = mp->dmai_offset; /* start min */ 511 dvma_addr = MAX(off, pg_off); /* lo */ 512 pg_off += mp->dmai_size; /* end max */ 513 pg_off = MIN(off + len, pg_off); /* hi */ 514 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 515 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 516 ddi_driver_name(rdip), ddi_get_instance(rdip), 517 off, len, mp->dmai_offset, 518 mp->dmai_offset + mp->dmai_size); 519 return (DDI_FAILURE); 520 } 521 522 len = pg_off - dvma_addr; /* sz = hi - lo */ 523 dvma_addr += mp->dmai_mapping; /* start addr */ 524 525 if (mp->dmai_rflags & DDI_DMA_READ) 526 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 527 else 528 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 529 530 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 531 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 532 sync_dir, &num_sync); 533 dvma_addr += num_sync; 534 } 535 536 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 537 } 538 539 540 /* 541 * MSIQ Functions: 542 */ 543 544 /*ARGSUSED*/ 545 int 546 px_lib_msiq_init(dev_info_t *dip) 547 { 548 px_t *px_p = DIP_TO_STATE(dip); 549 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 550 r_addr_t ra; 551 size_t msiq_size; 552 uint_t rec_cnt; 553 int i, err = DDI_SUCCESS; 554 uint64_t ret; 555 556 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 557 558 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 559 560 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 561 ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p + 562 (i * msiq_size)); 563 564 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 565 (i + msiq_state_p->msiq_1st_msiq_id), 566 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 567 DBG(DBG_LIB_MSIQ, dip, 568 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 569 err = DDI_FAILURE; 570 break; 571 } 572 573 if ((err = px_lib_msiq_info(dip, 574 (i + msiq_state_p->msiq_1st_msiq_id), 575 &ra, &rec_cnt)) != DDI_SUCCESS) { 576 DBG(DBG_LIB_MSIQ, dip, 577 "px_lib_msiq_info failed, ret 0x%x\n", err); 578 err = DDI_FAILURE; 579 break; 580 } 581 582 DBG(DBG_LIB_MSIQ, dip, 583 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 584 } 585 586 return (err); 587 } 588 589 /*ARGSUSED*/ 590 int 591 px_lib_msiq_fini(dev_info_t *dip) 592 { 593 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 594 595 return (DDI_SUCCESS); 596 } 597 598 /*ARGSUSED*/ 599 int 600 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 601 uint_t *msiq_rec_cnt_p) 602 { 603 uint64_t ret; 604 605 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 606 dip, msiq_id); 607 608 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 609 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 610 DBG(DBG_LIB_MSIQ, dip, 611 "hvio_msiq_info failed, ret 0x%lx\n", ret); 612 return (DDI_FAILURE); 613 } 614 615 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 616 ra_p, *msiq_rec_cnt_p); 617 618 return (DDI_SUCCESS); 619 } 620 621 /*ARGSUSED*/ 622 int 623 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 624 pci_msiq_valid_state_t *msiq_valid_state) 625 { 626 uint64_t ret; 627 628 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 629 dip, msiq_id); 630 631 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 632 msiq_id, msiq_valid_state)) != H_EOK) { 633 DBG(DBG_LIB_MSIQ, dip, 634 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 635 return (DDI_FAILURE); 636 } 637 638 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 639 *msiq_valid_state); 640 641 return (DDI_SUCCESS); 642 } 643 644 /*ARGSUSED*/ 645 int 646 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 647 pci_msiq_valid_state_t msiq_valid_state) 648 { 649 uint64_t ret; 650 651 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 652 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 653 654 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 655 msiq_id, msiq_valid_state)) != H_EOK) { 656 DBG(DBG_LIB_MSIQ, dip, 657 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 658 return (DDI_FAILURE); 659 } 660 661 return (DDI_SUCCESS); 662 } 663 664 /*ARGSUSED*/ 665 int 666 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 667 pci_msiq_state_t *msiq_state) 668 { 669 uint64_t ret; 670 671 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 672 dip, msiq_id); 673 674 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 675 msiq_id, msiq_state)) != H_EOK) { 676 DBG(DBG_LIB_MSIQ, dip, 677 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 678 return (DDI_FAILURE); 679 } 680 681 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 682 *msiq_state); 683 684 return (DDI_SUCCESS); 685 } 686 687 /*ARGSUSED*/ 688 int 689 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 690 pci_msiq_state_t msiq_state) 691 { 692 uint64_t ret; 693 694 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 695 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 696 697 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 698 msiq_id, msiq_state)) != H_EOK) { 699 DBG(DBG_LIB_MSIQ, dip, 700 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 701 return (DDI_FAILURE); 702 } 703 704 return (DDI_SUCCESS); 705 } 706 707 /*ARGSUSED*/ 708 int 709 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 710 msiqhead_t *msiq_head_p) 711 { 712 uint64_t ret; 713 714 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 715 dip, msiq_id); 716 717 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 718 msiq_id, msiq_head_p)) != H_EOK) { 719 DBG(DBG_LIB_MSIQ, dip, 720 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 721 return (DDI_FAILURE); 722 } 723 724 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 725 726 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 727 *msiq_head_p); 728 729 return (DDI_SUCCESS); 730 } 731 732 /*ARGSUSED*/ 733 int 734 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 735 msiqhead_t msiq_head) 736 { 737 uint64_t ret; 738 739 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 740 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 741 742 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 743 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 744 DBG(DBG_LIB_MSIQ, dip, 745 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 746 return (DDI_FAILURE); 747 } 748 749 return (DDI_SUCCESS); 750 } 751 752 /*ARGSUSED*/ 753 int 754 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 755 msiqtail_t *msiq_tail_p) 756 { 757 uint64_t ret; 758 759 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 760 dip, msiq_id); 761 762 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 763 msiq_id, msiq_tail_p)) != H_EOK) { 764 DBG(DBG_LIB_MSIQ, dip, 765 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 766 return (DDI_FAILURE); 767 } 768 769 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 770 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 771 *msiq_tail_p); 772 773 return (DDI_SUCCESS); 774 } 775 776 /*ARGSUSED*/ 777 void 778 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 779 msiq_rec_t *msiq_rec_p) 780 { 781 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 782 783 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 784 785 if (!curr_msiq_rec_p->msiq_rec_type) { 786 /* Set msiq_rec_type to zero */ 787 msiq_rec_p->msiq_rec_type = 0; 788 789 return; 790 } 791 792 *msiq_rec_p = *curr_msiq_rec_p; 793 } 794 795 /*ARGSUSED*/ 796 void 797 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 798 { 799 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 800 801 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p\n", dip); 802 803 /* Zero out msiq_rec_type field */ 804 curr_msiq_rec_p->msiq_rec_type = 0; 805 } 806 807 /* 808 * MSI Functions: 809 */ 810 811 /*ARGSUSED*/ 812 int 813 px_lib_msi_init(dev_info_t *dip) 814 { 815 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 816 817 /* Noop */ 818 return (DDI_SUCCESS); 819 } 820 821 /*ARGSUSED*/ 822 int 823 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 824 msiqid_t *msiq_id) 825 { 826 uint64_t ret; 827 828 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 829 dip, msi_num); 830 831 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 832 msi_num, msiq_id)) != H_EOK) { 833 DBG(DBG_LIB_MSI, dip, 834 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 835 return (DDI_FAILURE); 836 } 837 838 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 839 *msiq_id); 840 841 return (DDI_SUCCESS); 842 } 843 844 /*ARGSUSED*/ 845 int 846 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 847 msiqid_t msiq_id, msi_type_t msitype) 848 { 849 uint64_t ret; 850 851 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 852 "msq_id 0x%x\n", dip, msi_num, msiq_id); 853 854 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 855 msi_num, msiq_id, msitype)) != H_EOK) { 856 DBG(DBG_LIB_MSI, dip, 857 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 858 return (DDI_FAILURE); 859 } 860 861 return (DDI_SUCCESS); 862 } 863 864 /*ARGSUSED*/ 865 int 866 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 867 pci_msi_valid_state_t *msi_valid_state) 868 { 869 uint64_t ret; 870 871 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 872 dip, msi_num); 873 874 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 875 msi_num, msi_valid_state)) != H_EOK) { 876 DBG(DBG_LIB_MSI, dip, 877 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 878 return (DDI_FAILURE); 879 } 880 881 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 882 *msi_valid_state); 883 884 return (DDI_SUCCESS); 885 } 886 887 /*ARGSUSED*/ 888 int 889 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 890 pci_msi_valid_state_t msi_valid_state) 891 { 892 uint64_t ret; 893 894 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 895 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 896 897 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 898 msi_num, msi_valid_state)) != H_EOK) { 899 DBG(DBG_LIB_MSI, dip, 900 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 901 return (DDI_FAILURE); 902 } 903 904 return (DDI_SUCCESS); 905 } 906 907 /*ARGSUSED*/ 908 int 909 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 910 pci_msi_state_t *msi_state) 911 { 912 uint64_t ret; 913 914 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 915 dip, msi_num); 916 917 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 918 msi_num, msi_state)) != H_EOK) { 919 DBG(DBG_LIB_MSI, dip, 920 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 921 return (DDI_FAILURE); 922 } 923 924 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 925 *msi_state); 926 927 return (DDI_SUCCESS); 928 } 929 930 /*ARGSUSED*/ 931 int 932 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 933 pci_msi_state_t msi_state) 934 { 935 uint64_t ret; 936 937 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 938 "msi_state 0x%x\n", dip, msi_num, msi_state); 939 940 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 941 msi_num, msi_state)) != H_EOK) { 942 DBG(DBG_LIB_MSI, dip, 943 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 944 return (DDI_FAILURE); 945 } 946 947 return (DDI_SUCCESS); 948 } 949 950 /* 951 * MSG Functions: 952 */ 953 954 /*ARGSUSED*/ 955 int 956 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 957 msiqid_t *msiq_id) 958 { 959 uint64_t ret; 960 961 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 962 dip, msg_type); 963 964 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 965 msg_type, msiq_id)) != H_EOK) { 966 DBG(DBG_LIB_MSG, dip, 967 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 968 return (DDI_FAILURE); 969 } 970 971 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 972 *msiq_id); 973 974 return (DDI_SUCCESS); 975 } 976 977 /*ARGSUSED*/ 978 int 979 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 980 msiqid_t msiq_id) 981 { 982 uint64_t ret; 983 984 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 985 "msq_id 0x%x\n", dip, msg_type, msiq_id); 986 987 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 988 msg_type, msiq_id)) != H_EOK) { 989 DBG(DBG_LIB_MSG, dip, 990 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 991 return (DDI_FAILURE); 992 } 993 994 return (DDI_SUCCESS); 995 } 996 997 /*ARGSUSED*/ 998 int 999 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1000 pcie_msg_valid_state_t *msg_valid_state) 1001 { 1002 uint64_t ret; 1003 1004 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1005 dip, msg_type); 1006 1007 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1008 msg_valid_state)) != H_EOK) { 1009 DBG(DBG_LIB_MSG, dip, 1010 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1011 return (DDI_FAILURE); 1012 } 1013 1014 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1015 *msg_valid_state); 1016 1017 return (DDI_SUCCESS); 1018 } 1019 1020 /*ARGSUSED*/ 1021 int 1022 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1023 pcie_msg_valid_state_t msg_valid_state) 1024 { 1025 uint64_t ret; 1026 1027 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1028 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1029 1030 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1031 msg_valid_state)) != H_EOK) { 1032 DBG(DBG_LIB_MSG, dip, 1033 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1034 return (DDI_FAILURE); 1035 } 1036 1037 return (DDI_SUCCESS); 1038 } 1039 1040 /* 1041 * Suspend/Resume Functions: 1042 * Currently unsupported by hypervisor and all functions are noops. 1043 */ 1044 /*ARGSUSED*/ 1045 int 1046 px_lib_suspend(dev_info_t *dip) 1047 { 1048 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1049 1050 /* Not supported */ 1051 return (DDI_FAILURE); 1052 } 1053 1054 /*ARGSUSED*/ 1055 void 1056 px_lib_resume(dev_info_t *dip) 1057 { 1058 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1059 1060 /* Noop */ 1061 } 1062 1063 /* 1064 * Misc Functions: 1065 * Currently unsupported by hypervisor and all functions are noops. 1066 */ 1067 /*ARGSUSED*/ 1068 static int 1069 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1070 uint8_t size, pci_cfg_data_t *data_p) 1071 { 1072 uint64_t ret; 1073 1074 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1075 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1076 1077 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1078 size, data_p)) != H_EOK) { 1079 DBG(DBG_LIB_CFG, dip, 1080 "hvio_config_get failed, ret 0x%lx\n", ret); 1081 return (DDI_FAILURE); 1082 } 1083 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1084 1085 return (DDI_SUCCESS); 1086 } 1087 1088 /*ARGSUSED*/ 1089 static int 1090 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1091 uint8_t size, pci_cfg_data_t data) 1092 { 1093 uint64_t ret; 1094 1095 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1096 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1097 1098 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1099 size, data)) != H_EOK) { 1100 DBG(DBG_LIB_CFG, dip, 1101 "hvio_config_put failed, ret 0x%lx\n", ret); 1102 return (DDI_FAILURE); 1103 } 1104 1105 return (DDI_SUCCESS); 1106 } 1107 1108 static uint32_t 1109 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1110 { 1111 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1112 handle->ahi_common.ah_bus_private; 1113 uint32_t pci_dev_addr = px_pvt->raddr; 1114 uint32_t vaddr = px_pvt->vaddr; 1115 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1116 uint32_t rdata = 0; 1117 1118 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1119 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1120 /* XXX update error kstats */ 1121 return (0xffffffff); 1122 return (rdata); 1123 } 1124 1125 static void 1126 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1127 int size, pci_cfg_data_t wdata) 1128 { 1129 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1130 handle->ahi_common.ah_bus_private; 1131 uint32_t pci_dev_addr = px_pvt->raddr; 1132 uint32_t vaddr = px_pvt->vaddr; 1133 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1134 1135 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1136 size, wdata) != DDI_SUCCESS) { 1137 /*EMPTY*/ 1138 /* XXX update error kstats */ 1139 } 1140 } 1141 1142 static uint8_t 1143 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1144 { 1145 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1146 } 1147 1148 static uint16_t 1149 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1150 { 1151 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1152 } 1153 1154 static uint32_t 1155 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1156 { 1157 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1158 } 1159 1160 static uint64_t 1161 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1162 { 1163 uint32_t rdatah, rdatal; 1164 1165 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1166 rdatah = (uint32_t)px_pci_config_get(handle, 1167 (uint32_t *)((char *)addr+4), 4); 1168 return (((uint64_t)rdatah << 32) | rdatal); 1169 } 1170 1171 static void 1172 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1173 { 1174 pci_cfg_data_t wdata = { 0 }; 1175 1176 wdata.qw = (uint8_t)data; 1177 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1178 } 1179 1180 static void 1181 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1182 { 1183 pci_cfg_data_t wdata = { 0 }; 1184 1185 wdata.qw = (uint16_t)data; 1186 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1187 } 1188 1189 static void 1190 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1191 { 1192 pci_cfg_data_t wdata = { 0 }; 1193 1194 wdata.qw = (uint32_t)data; 1195 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1196 } 1197 1198 static void 1199 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1200 { 1201 pci_cfg_data_t wdata = { 0 }; 1202 1203 wdata.qw = (uint32_t)(data & 0xffffffff); 1204 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1205 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1206 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1207 } 1208 1209 static void 1210 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1211 uint8_t *dev_addr, size_t repcount, uint_t flags) 1212 { 1213 if (flags == DDI_DEV_AUTOINCR) 1214 for (; repcount; repcount--) 1215 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1216 else 1217 for (; repcount; repcount--) 1218 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1219 } 1220 1221 /* 1222 * Function to rep read 16 bit data off the PCI configuration space behind 1223 * the 21554's host interface. 1224 */ 1225 static void 1226 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1227 uint16_t *dev_addr, size_t repcount, uint_t flags) 1228 { 1229 if (flags == DDI_DEV_AUTOINCR) 1230 for (; repcount; repcount--) 1231 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1232 else 1233 for (; repcount; repcount--) 1234 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1235 } 1236 1237 /* 1238 * Function to rep read 32 bit data off the PCI configuration space behind 1239 * the 21554's host interface. 1240 */ 1241 static void 1242 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1243 uint32_t *dev_addr, size_t repcount, uint_t flags) 1244 { 1245 if (flags == DDI_DEV_AUTOINCR) 1246 for (; repcount; repcount--) 1247 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1248 else 1249 for (; repcount; repcount--) 1250 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1251 } 1252 1253 /* 1254 * Function to rep read 64 bit data off the PCI configuration space behind 1255 * the 21554's host interface. 1256 */ 1257 static void 1258 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1259 uint64_t *dev_addr, size_t repcount, uint_t flags) 1260 { 1261 if (flags == DDI_DEV_AUTOINCR) 1262 for (; repcount; repcount--) 1263 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1264 else 1265 for (; repcount; repcount--) 1266 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1267 } 1268 1269 /* 1270 * Function to rep write 8 bit data into the PCI configuration space behind 1271 * the 21554's host interface. 1272 */ 1273 static void 1274 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1275 uint8_t *dev_addr, size_t repcount, uint_t flags) 1276 { 1277 if (flags == DDI_DEV_AUTOINCR) 1278 for (; repcount; repcount--) 1279 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1280 else 1281 for (; repcount; repcount--) 1282 px_pci_config_put8(handle, dev_addr, *host_addr++); 1283 } 1284 1285 /* 1286 * Function to rep write 16 bit data into the PCI configuration space behind 1287 * the 21554's host interface. 1288 */ 1289 static void 1290 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1291 uint16_t *dev_addr, size_t repcount, uint_t flags) 1292 { 1293 if (flags == DDI_DEV_AUTOINCR) 1294 for (; repcount; repcount--) 1295 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1296 else 1297 for (; repcount; repcount--) 1298 px_pci_config_put16(handle, dev_addr, *host_addr++); 1299 } 1300 1301 /* 1302 * Function to rep write 32 bit data into the PCI configuration space behind 1303 * the 21554's host interface. 1304 */ 1305 static void 1306 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1307 uint32_t *dev_addr, size_t repcount, uint_t flags) 1308 { 1309 if (flags == DDI_DEV_AUTOINCR) 1310 for (; repcount; repcount--) 1311 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1312 else 1313 for (; repcount; repcount--) 1314 px_pci_config_put32(handle, dev_addr, *host_addr++); 1315 } 1316 1317 /* 1318 * Function to rep write 64 bit data into the PCI configuration space behind 1319 * the 21554's host interface. 1320 */ 1321 static void 1322 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1323 uint64_t *dev_addr, size_t repcount, uint_t flags) 1324 { 1325 if (flags == DDI_DEV_AUTOINCR) 1326 for (; repcount; repcount--) 1327 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1328 else 1329 for (; repcount; repcount--) 1330 px_pci_config_put64(handle, dev_addr, *host_addr++); 1331 } 1332 1333 /* 1334 * Provide a private access handle to route config access calls to Hypervisor. 1335 * Beware: Do all error checking for config space accesses before calling 1336 * this function. ie. do error checking from the calling function. 1337 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1338 * DDI_SUCCESS from here makes the code organization readable/easier from 1339 * the generic code. 1340 */ 1341 /*ARGSUSED*/ 1342 int 1343 px_lib_map_vconfig(dev_info_t *dip, 1344 ddi_map_req_t *mp, pci_config_offset_t off, 1345 pci_regspec_t *rp, caddr_t *addrp) 1346 { 1347 ddi_acc_hdl_t *hp; 1348 ddi_acc_impl_t *ap; 1349 uchar_t busnum; /* bus number */ 1350 uchar_t devnum; /* device number */ 1351 uchar_t funcnum; /* function number */ 1352 px_config_acc_pvt_t *px_pvt; 1353 1354 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1355 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1356 1357 /* Check for mapping teardown operation */ 1358 if ((mp->map_op == DDI_MO_UNMAP) || 1359 (mp->map_op == DDI_MO_UNLOCK)) { 1360 /* free up memory allocated for the private access handle. */ 1361 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1362 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1363 1364 /* unmap operation of PCI IO/config space. */ 1365 return (DDI_SUCCESS); 1366 } 1367 1368 ap->ahi_get8 = px_pci_config_get8; 1369 ap->ahi_get16 = px_pci_config_get16; 1370 ap->ahi_get32 = px_pci_config_get32; 1371 ap->ahi_get64 = px_pci_config_get64; 1372 ap->ahi_put8 = px_pci_config_put8; 1373 ap->ahi_put16 = px_pci_config_put16; 1374 ap->ahi_put32 = px_pci_config_put32; 1375 ap->ahi_put64 = px_pci_config_put64; 1376 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1377 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1378 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1379 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1380 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1381 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1382 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1383 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1384 1385 /* Initialize to default check/notify functions */ 1386 ap->ahi_fault = 0; 1387 ap->ahi_fault_check = i_ddi_acc_fault_check; 1388 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1389 1390 /* allocate memory for our private handle */ 1391 px_pvt = (px_config_acc_pvt_t *) 1392 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1393 hp->ah_bus_private = (void *)px_pvt; 1394 1395 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1396 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1397 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1398 1399 /* set up private data for use during IO routines */ 1400 1401 /* addr needed by the HV APIs */ 1402 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1403 /* 1404 * Address that specifies the actual offset into the 256MB 1405 * memory mapped configuration space, 4K per device. 1406 * First 12bits form the offset into 4K config space. 1407 * This address is only used during the IO routines to calculate 1408 * the offset at which the transaction must be performed. 1409 * Drivers bypassing DDI functions to access PCI config space will 1410 * panic the system since the following is a bogus virtual address. 1411 */ 1412 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1413 px_pvt->dip = dip; 1414 1415 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1416 px_pvt->raddr, px_pvt->vaddr); 1417 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1418 return (DDI_SUCCESS); 1419 } 1420 1421 /*ARGSUSED*/ 1422 void 1423 px_lib_map_attr_check(ddi_map_req_t *mp) 1424 { 1425 } 1426 1427 /* 1428 * px_lib_log_safeacc_err: 1429 * Imitate a cpu/mem trap call when a peek/poke fails. 1430 * This will initiate something similar to px_fm_callback. 1431 */ 1432 static void 1433 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1434 { 1435 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1436 ddi_fm_error_t derr; 1437 1438 derr.fme_status = DDI_FM_NONFATAL; 1439 derr.fme_version = DDI_FME_VERSION; 1440 derr.fme_flag = fme_flag; 1441 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1442 derr.fme_acc_handle = handle; 1443 if (hp) 1444 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1445 1446 mutex_enter(&px_p->px_fm_mutex); 1447 1448 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1449 1450 mutex_exit(&px_p->px_fm_mutex); 1451 } 1452 1453 1454 #ifdef DEBUG 1455 int px_peekfault_cnt = 0; 1456 int px_pokefault_cnt = 0; 1457 #endif /* DEBUG */ 1458 1459 static int 1460 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1461 { 1462 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1463 pci_regspec_t regspec_array[8]; 1464 pci_regspec_t *regspec = regspec_array; 1465 int buflen = sizeof (regspec_array); 1466 boolean_t kmalloced = B_FALSE; 1467 int status; 1468 1469 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1470 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1471 1472 /* If need more space, fallback to kmem_alloc. */ 1473 if (status == DDI_PROP_BUF_TOO_SMALL) { 1474 regspec = kmem_alloc(buflen, KM_SLEEP); 1475 1476 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1477 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1478 1479 kmalloced = B_TRUE; 1480 } 1481 1482 /* Get phys_hi from first element. All have same bdf. */ 1483 if (status == DDI_PROP_SUCCESS) 1484 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1485 1486 if (kmalloced) 1487 kmem_free(regspec, buflen); 1488 1489 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1490 } 1491 1492 /* 1493 * Do a safe write to a device. 1494 * 1495 * When this function is given a handle (cautious access), all errors are 1496 * suppressed. 1497 * 1498 * When this function is not given a handle (poke), only Unsupported Request 1499 * and Completer Abort errors are suppressed. 1500 * 1501 * In all cases, all errors are returned in the function return status. 1502 */ 1503 1504 int 1505 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1506 peekpoke_ctlops_t *in_args) 1507 { 1508 px_t *px_p = DIP_TO_STATE(dip); 1509 px_pec_t *pec_p = px_p->px_pec_p; 1510 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1511 1512 size_t repcount = in_args->repcount; 1513 size_t size = in_args->size; 1514 uintptr_t dev_addr = in_args->dev_addr; 1515 uintptr_t host_addr = in_args->host_addr; 1516 1517 int err = DDI_SUCCESS; 1518 uint64_t hvio_poke_status; 1519 uint32_t bdf; 1520 uint32_t wrt_stat; 1521 1522 r_addr_t ra; 1523 uint64_t pokeval; 1524 1525 /* 1526 * Used only to notify error handling peek/poke is occuring 1527 * One scenario is when a fabric err as a result of peek/poke. 1528 * However there is no way to guarantee that the fabric error 1529 * handler will occur in the window where otd is set. 1530 */ 1531 on_trap_data_t otd; 1532 1533 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1534 DBG(DBG_LIB_DMA, px_p->px_dip, 1535 "poke: px_lib_bdf_from_dip failed\n"); 1536 err = DDI_FAILURE; 1537 goto done; 1538 } 1539 1540 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1541 for (; repcount; repcount--) { 1542 1543 switch (size) { 1544 case sizeof (uint8_t): 1545 pokeval = *(uint8_t *)host_addr; 1546 break; 1547 case sizeof (uint16_t): 1548 pokeval = *(uint16_t *)host_addr; 1549 break; 1550 case sizeof (uint32_t): 1551 pokeval = *(uint32_t *)host_addr; 1552 break; 1553 case sizeof (uint64_t): 1554 pokeval = *(uint64_t *)host_addr; 1555 break; 1556 default: 1557 DBG(DBG_MAP, px_p->px_dip, 1558 "poke: invalid size %d passed\n", size); 1559 err = DDI_FAILURE; 1560 goto done; 1561 } 1562 1563 /* 1564 * Grab pokefault mutex since hypervisor does not guarantee 1565 * poke serialization. 1566 */ 1567 if (hp) { 1568 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1569 (ddi_acc_handle_t)hp); 1570 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1571 } else { 1572 mutex_enter(&pec_p->pec_pokefault_mutex); 1573 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1574 } 1575 pec_p->pec_ontrap_data = &otd; 1576 1577 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1578 pokeval, bdf, &wrt_stat); 1579 1580 if (otd.ot_trap & OT_DATA_ACCESS) 1581 err = DDI_FAILURE; 1582 1583 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1584 err = DDI_FAILURE; 1585 #ifdef DEBUG 1586 px_pokefault_cnt++; 1587 #endif 1588 /* 1589 * For CAUTIOUS and POKE access, notify FMA to 1590 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1591 */ 1592 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1593 (hp ? DDI_FM_ERR_EXPECTED : 1594 DDI_FM_ERR_POKE)); 1595 1596 pec_p->pec_ontrap_data = NULL; 1597 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1598 if (hp) { 1599 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1600 (ddi_acc_handle_t)hp); 1601 } else { 1602 mutex_exit(&pec_p->pec_pokefault_mutex); 1603 } 1604 goto done; 1605 } 1606 1607 pec_p->pec_ontrap_data = NULL; 1608 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1609 if (hp) { 1610 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1611 (ddi_acc_handle_t)hp); 1612 } else { 1613 mutex_exit(&pec_p->pec_pokefault_mutex); 1614 } 1615 1616 host_addr += size; 1617 1618 if (in_args->flags == DDI_DEV_AUTOINCR) { 1619 dev_addr += size; 1620 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1621 } 1622 } 1623 1624 done: 1625 return (err); 1626 } 1627 1628 1629 /*ARGSUSED*/ 1630 int 1631 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1632 peekpoke_ctlops_t *in_args, void *result) 1633 { 1634 px_t *px_p = DIP_TO_STATE(dip); 1635 px_pec_t *pec_p = px_p->px_pec_p; 1636 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1637 1638 size_t repcount = in_args->repcount; 1639 uintptr_t dev_addr = in_args->dev_addr; 1640 uintptr_t host_addr = in_args->host_addr; 1641 1642 r_addr_t ra; 1643 uint32_t read_status; 1644 uint64_t hvio_peek_status; 1645 uint64_t peekval; 1646 int err = DDI_SUCCESS; 1647 1648 /* 1649 * Used only to notify error handling peek/poke is occuring 1650 * One scenario is when a fabric err as a result of peek/poke. 1651 * However there is no way to guarantee that the fabric error 1652 * handler will occur in the window where otd is set. 1653 */ 1654 on_trap_data_t otd; 1655 1656 result = (void *)in_args->host_addr; 1657 1658 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1659 for (; repcount; repcount--) { 1660 1661 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1662 if (hp) { 1663 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1664 (ddi_acc_handle_t)hp); 1665 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1666 } else { 1667 mutex_enter(&pec_p->pec_pokefault_mutex); 1668 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1669 } 1670 pec_p->pec_ontrap_data = &otd; 1671 1672 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1673 in_args->size, &read_status, &peekval); 1674 1675 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1676 err = DDI_FAILURE; 1677 1678 /* 1679 * For CAUTIOUS and PEEK access, notify FMA to 1680 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1681 */ 1682 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1683 (hp ? DDI_FM_ERR_EXPECTED : 1684 DDI_FM_ERR_PEEK)); 1685 1686 /* Stuff FFs in host addr if peek. */ 1687 if (hp == NULL) { 1688 int i; 1689 uint8_t *ff_addr = (uint8_t *)host_addr; 1690 for (i = 0; i < in_args->size; i++) 1691 *ff_addr++ = 0xff; 1692 } 1693 #ifdef DEBUG 1694 px_peekfault_cnt++; 1695 #endif 1696 pec_p->pec_ontrap_data = NULL; 1697 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1698 if (hp) { 1699 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1700 (ddi_acc_handle_t)hp); 1701 } else { 1702 mutex_exit(&pec_p->pec_pokefault_mutex); 1703 } 1704 goto done; 1705 1706 } 1707 pec_p->pec_ontrap_data = NULL; 1708 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1709 if (hp) { 1710 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1711 (ddi_acc_handle_t)hp); 1712 } else { 1713 mutex_exit(&pec_p->pec_pokefault_mutex); 1714 } 1715 1716 switch (in_args->size) { 1717 case sizeof (uint8_t): 1718 *(uint8_t *)host_addr = (uint8_t)peekval; 1719 break; 1720 case sizeof (uint16_t): 1721 *(uint16_t *)host_addr = (uint16_t)peekval; 1722 break; 1723 case sizeof (uint32_t): 1724 *(uint32_t *)host_addr = (uint32_t)peekval; 1725 break; 1726 case sizeof (uint64_t): 1727 *(uint64_t *)host_addr = (uint64_t)peekval; 1728 break; 1729 default: 1730 DBG(DBG_MAP, px_p->px_dip, 1731 "peek: invalid size %d passed\n", 1732 in_args->size); 1733 err = DDI_FAILURE; 1734 goto done; 1735 } 1736 1737 host_addr += in_args->size; 1738 1739 if (in_args->flags == DDI_DEV_AUTOINCR) { 1740 dev_addr += in_args->size; 1741 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1742 } 1743 } 1744 done: 1745 return (err); 1746 } 1747 1748 1749 /* add interrupt vector */ 1750 int 1751 px_err_add_intr(px_fault_t *px_fault_p) 1752 { 1753 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1754 1755 DBG(DBG_LIB_INT, px_p->px_dip, 1756 "px_err_add_intr: calling add_ivintr"); 1757 1758 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1759 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL, 1760 (caddr_t)&px_fault_p->px_intr_payload[0]) == 0); 1761 1762 DBG(DBG_LIB_INT, px_p->px_dip, 1763 "px_err_add_intr: ib_intr_enable "); 1764 1765 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1766 1767 return (DDI_SUCCESS); 1768 } 1769 1770 /* remove interrupt vector */ 1771 void 1772 px_err_rem_intr(px_fault_t *px_fault_p) 1773 { 1774 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1775 1776 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1777 IB_INTR_WAIT); 1778 1779 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 1780 } 1781 1782 int 1783 px_cb_add_intr(px_fault_t *f_p) 1784 { 1785 return (px_err_add_intr(f_p)); 1786 } 1787 1788 void 1789 px_cb_rem_intr(px_fault_t *f_p) 1790 { 1791 px_err_rem_intr(f_p); 1792 } 1793 1794 void 1795 px_cb_intr_redist(px_t *px_p) 1796 { 1797 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1798 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1799 } 1800 1801 #ifdef FMA 1802 void 1803 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1804 { 1805 px_pec_err_t *err_pkt; 1806 1807 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1808 1809 /* initialise all the structure members */ 1810 rc_status->status_valid = 0; 1811 1812 if (err_pkt->pec_descr.P) { 1813 /* PCI Status Register */ 1814 rc_status->pci_err_status = err_pkt->pci_err_status; 1815 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1816 } 1817 1818 if (err_pkt->pec_descr.E) { 1819 /* PCIe Status Register */ 1820 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1821 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1822 } 1823 1824 if (err_pkt->pec_descr.U) { 1825 rc_status->ue_status = err_pkt->ue_reg_status; 1826 rc_status->status_valid |= UE_STATUS_VALID; 1827 } 1828 1829 if (err_pkt->pec_descr.H) { 1830 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1831 rc_status->status_valid |= UE_HDR1_VALID; 1832 } 1833 1834 if (err_pkt->pec_descr.I) { 1835 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1836 rc_status->status_valid |= UE_HDR2_VALID; 1837 } 1838 1839 /* ue_fst_err_ptr - not available for sun4v?? */ 1840 1841 1842 if (err_pkt->pec_descr.S) { 1843 rc_status->source_id = err_pkt->err_src_reg; 1844 rc_status->status_valid |= SOURCE_ID_VALID; 1845 } 1846 1847 if (err_pkt->pec_descr.R) { 1848 rc_status->root_err_status = err_pkt->root_err_status; 1849 rc_status->status_valid |= CE_STATUS_VALID; 1850 } 1851 } 1852 #endif 1853 1854 /*ARGSUSED*/ 1855 int 1856 px_lib_pmctl(int cmd, px_t *px_p) 1857 { 1858 return (DDI_FAILURE); 1859 } 1860 1861 /*ARGSUSED*/ 1862 uint_t 1863 px_pmeq_intr(caddr_t arg) 1864 { 1865 return (DDI_INTR_CLAIMED); 1866 } 1867 1868 /* 1869 * Unprotected raw reads/writes of fabric device's config space. 1870 * Only used for temporary PCI-E Fabric Error Handling. 1871 */ 1872 uint32_t 1873 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1874 uint32_t data = 0; 1875 1876 (void) hvio_config_get(px_p->px_dev_hdl, 1877 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1878 (pci_cfg_data_t *)&data); 1879 1880 return (data); 1881 } 1882 1883 void 1884 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1885 uint32_t val) { 1886 pci_cfg_data_t wdata = { 0 }; 1887 1888 wdata.qw = (uint32_t)val; 1889 (void) hvio_config_put(px_p->px_dev_hdl, 1890 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1891 } 1892 1893 /*ARGSUSED*/ 1894 int 1895 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1896 { 1897 return (DDI_ENOTSUP); 1898 } 1899 1900 /*ARGSUSED*/ 1901 void 1902 px_lib_hotplug_uninit(dev_info_t *dip) 1903 { 1904 } 1905 1906 /* Dummy cpr add callback */ 1907 /*ARGSUSED*/ 1908 void 1909 px_cpr_add_callb(px_t *px_p) 1910 { 1911 } 1912 1913 /* Dummy cpr rem callback */ 1914 /*ARGSUSED*/ 1915 void 1916 px_cpr_rem_callb(px_t *px_p) 1917 { 1918 } 1919 1920 /*ARGSUSED*/ 1921 boolean_t 1922 px_lib_is_in_drain_state(px_t *px_p) 1923 { 1924 return (B_FALSE); 1925 } 1926