1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/sysmacros.h> 28 #include <sys/ddi.h> 29 #include <sys/async.h> 30 #include <sys/sunddi.h> 31 #include <sys/ddifm.h> 32 #include <sys/fm/protocol.h> 33 #include <sys/vmem.h> 34 #include <sys/intr.h> 35 #include <sys/ivintr.h> 36 #include <sys/errno.h> 37 #include <sys/hypervisor_api.h> 38 #include <sys/hsvc.h> 39 #include <px_obj.h> 40 #include <sys/machsystm.h> 41 #include <sys/sunndi.h> 42 #include <sys/pcie_impl.h> 43 #include "px_lib4v.h" 44 #include "px_err.h" 45 #include <sys/pci_cfgacc.h> 46 #include <sys/pci_cfgacc_4v.h> 47 48 49 /* mask for the ranges property in calculating the real PFN range */ 50 uint_t px_ranges_phi_mask = ((1 << 28) -1); 51 52 /* 53 * Hypervisor VPCI services information for the px nexus driver. 54 */ 55 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 56 static uint_t px_vpci_users = 0; /* VPCI API users */ 57 static hsvc_info_t px_hsvc_vpci = { 58 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 59 PX_VPCI_MINOR_VER, "PX" 60 }; 61 62 /* 63 * Hypervisor SDIO services information for the px nexus driver. 64 */ 65 static uint64_t px_sdio_min_ver; /* Negotiated SDIO API minor version */ 66 static uint_t px_sdio_users = 0; /* SDIO API users */ 67 static hsvc_info_t px_hsvc_sdio = { 68 HSVC_REV_1, NULL, HSVC_GROUP_SDIO, PX_SDIO_MAJOR_VER, 69 PX_SDIO_MINOR_VER, "PX" 70 }; 71 72 /* 73 * Hypervisor SDIO ERR services information for the px nexus driver. 74 */ 75 static uint64_t px_sdio_err_min_ver; /* Negotiated SDIO ERR API */ 76 /* minor version */ 77 static uint_t px_sdio_err_users = 0; /* SDIO ERR API users */ 78 static hsvc_info_t px_hsvc_sdio_err = { 79 HSVC_REV_1, NULL, HSVC_GROUP_SDIO_ERR, PX_SDIO_ERR_MAJOR_VER, 80 PX_SDIO_ERR_MINOR_VER, "PX" 81 }; 82 83 #define CHILD_LOANED "child_loaned" 84 static int px_lib_count_waiting_dev(dev_info_t *); 85 86 int 87 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 88 { 89 px_nexus_regspec_t *rp; 90 uint_t reglen; 91 int ret; 92 px_t *px_p = DIP_TO_STATE(dip); 93 uint64_t mjrnum; 94 uint64_t mnrnum; 95 96 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 97 98 /* 99 * Check HV intr group api versioning. 100 * This driver uses the old interrupt routines which are supported 101 * in old firmware in the CORE API group and in newer firmware in 102 * the INTR API group. Support for these calls will be dropped 103 * once the INTR API group major goes to 2. 104 */ 105 if ((hsvc_version(HSVC_GROUP_INTR, &mjrnum, &mnrnum) == 0) && 106 (mjrnum > 1)) { 107 cmn_err(CE_WARN, "px: unsupported intr api group: " 108 "maj:0x%lx, min:0x%lx", mjrnum, mnrnum); 109 return (ENOTSUP); 110 } 111 112 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 113 "reg", (uchar_t **)&rp, ®len); 114 if (ret != DDI_PROP_SUCCESS) { 115 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 116 return (DDI_FAILURE); 117 } 118 119 /* 120 * Initilize device handle. The device handle uniquely identifies 121 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 122 * of the first entry of the SUN4V device's "reg" property as 123 * defined by the SUN4V Bus Binding to Open Firmware. 124 */ 125 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 126 ddi_prop_free(rp); 127 128 /* 129 * hotplug implementation requires this property to be associated with 130 * any indirect PCI config access services 131 */ 132 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 133 PCI_MINOR_NUM(ddi_get_instance(dip), PCI_DEVCTL_MINOR)), dip, 134 PCI_BUS_CONF_MAP_PROP, 1); 135 136 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 137 138 /* 139 * If a /pci node has a pci-intx-not-supported property, this property 140 * represents that the fabric doesn't support fixed interrupt. 141 */ 142 if (!ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 143 "pci-intx-not-supported")) { 144 DBG(DBG_ATTACH, dip, "px_lib_dev_init: " 145 "pci-intx-not-supported is not found, dip=0x%p\n", dip); 146 px_p->px_supp_intr_types |= DDI_INTR_TYPE_FIXED; 147 } 148 149 /* 150 * Negotiate the API version for VPCI hypervisor services. 151 */ 152 if ((px_vpci_users == 0) && 153 ((ret = hsvc_register(&px_hsvc_vpci, &px_vpci_min_ver)) != 0)) { 154 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 155 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 156 px_hsvc_vpci.hsvc_modname, px_hsvc_vpci.hsvc_group, 157 px_hsvc_vpci.hsvc_major, px_hsvc_vpci.hsvc_minor, ret); 158 return (DDI_FAILURE); 159 } 160 px_vpci_users++; 161 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 162 "major 0x%lx minor 0x%lx\n", px_hsvc_vpci.hsvc_major, 163 px_vpci_min_ver); 164 165 /* 166 * Negotiate the API version for SDIO hypervisor services. 167 */ 168 if ((px_sdio_users == 0) && 169 ((ret = hsvc_register(&px_hsvc_sdio, &px_sdio_min_ver)) != 0)) { 170 DBG(DBG_ATTACH, dip, "%s: cannot negotiate hypervisor " 171 "services group: 0x%lx major: 0x%lx minor: 0x%lx " 172 "errno: %d\n", px_hsvc_sdio.hsvc_modname, 173 px_hsvc_sdio.hsvc_group, px_hsvc_sdio.hsvc_major, 174 px_hsvc_sdio.hsvc_minor, ret); 175 } else { 176 px_sdio_users++; 177 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated SDIO API" 178 "version, major 0x%lx minor 0x%lx\n", 179 px_hsvc_sdio.hsvc_major, px_sdio_min_ver); 180 } 181 182 /* 183 * Negotiate the API version for SDIO ERR hypervisor services. 184 */ 185 if ((px_sdio_err_users == 0) && 186 ((ret = hsvc_register(&px_hsvc_sdio_err, 187 &px_sdio_err_min_ver)) != 0)) { 188 DBG(DBG_ATTACH, dip, "%s: cannot negotiate SDIO ERR hypervisor " 189 "services group: 0x%lx major: 0x%lx minor: 0x%lx " 190 "errno: %d\n", px_hsvc_sdio_err.hsvc_modname, 191 px_hsvc_sdio_err.hsvc_group, px_hsvc_sdio_err.hsvc_major, 192 px_hsvc_sdio_err.hsvc_minor, ret); 193 } else { 194 px_sdio_err_users++; 195 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated SDIO ERR API " 196 "version, major 0x%lx minor 0x%lx\n", 197 px_hsvc_sdio_err.hsvc_major, px_sdio_err_min_ver); 198 } 199 200 /* 201 * Find out the number of dev we need to wait under this RC 202 * before we issue fabric sync hypercall 203 */ 204 px_p->px_plat_p = (void *)(uintptr_t)px_lib_count_waiting_dev(dip); 205 DBG(DBG_ATTACH, dip, "Found %d bridges need waiting under RC %p", 206 (int)(uintptr_t)px_p->px_plat_p, dip); 207 return (DDI_SUCCESS); 208 } 209 210 /*ARGSUSED*/ 211 int 212 px_lib_dev_fini(dev_info_t *dip) 213 { 214 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 215 216 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 217 PCI_MINOR_NUM(ddi_get_instance(dip), PCI_DEVCTL_MINOR)), dip, 218 PCI_BUS_CONF_MAP_PROP); 219 220 if (--px_vpci_users == 0) 221 (void) hsvc_unregister(&px_hsvc_vpci); 222 223 if (--px_sdio_users == 0) 224 (void) hsvc_unregister(&px_hsvc_sdio); 225 226 if (--px_sdio_err_users == 0) 227 (void) hsvc_unregister(&px_hsvc_sdio_err); 228 229 return (DDI_SUCCESS); 230 } 231 232 /*ARGSUSED*/ 233 int 234 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 235 sysino_t *sysino) 236 { 237 uint64_t ret; 238 239 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 240 "devino 0x%x\n", dip, devino); 241 242 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 243 devino, sysino)) != H_EOK) { 244 DBG(DBG_LIB_INT, dip, 245 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 246 return (DDI_FAILURE); 247 } 248 249 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 250 *sysino); 251 252 return (DDI_SUCCESS); 253 } 254 255 /*ARGSUSED*/ 256 int 257 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 258 intr_valid_state_t *intr_valid_state) 259 { 260 uint64_t ret; 261 262 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 263 dip, sysino); 264 265 if ((ret = hvio_intr_getvalid(sysino, 266 (int *)intr_valid_state)) != H_EOK) { 267 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 268 ret); 269 return (DDI_FAILURE); 270 } 271 272 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 273 *intr_valid_state); 274 275 return (DDI_SUCCESS); 276 } 277 278 /*ARGSUSED*/ 279 int 280 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 281 intr_valid_state_t intr_valid_state) 282 { 283 uint64_t ret; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 286 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 287 288 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 289 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 290 ret); 291 return (DDI_FAILURE); 292 } 293 294 return (DDI_SUCCESS); 295 } 296 297 /*ARGSUSED*/ 298 int 299 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 300 intr_state_t *intr_state) 301 { 302 uint64_t ret; 303 304 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 305 dip, sysino); 306 307 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 308 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 309 ret); 310 return (DDI_FAILURE); 311 } 312 313 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 314 *intr_state); 315 316 return (DDI_SUCCESS); 317 } 318 319 /*ARGSUSED*/ 320 int 321 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 322 intr_state_t intr_state) 323 { 324 uint64_t ret; 325 326 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 327 "intr_state 0x%x\n", dip, sysino, intr_state); 328 329 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 330 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 331 ret); 332 return (DDI_FAILURE); 333 } 334 335 return (DDI_SUCCESS); 336 } 337 338 /*ARGSUSED*/ 339 int 340 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 341 { 342 uint64_t ret; 343 344 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 345 dip, sysino); 346 347 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 348 DBG(DBG_LIB_INT, dip, 349 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 350 return (DDI_FAILURE); 351 } 352 353 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", *cpuid); 354 355 return (DDI_SUCCESS); 356 } 357 358 /*ARGSUSED*/ 359 int 360 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 361 { 362 uint64_t ret; 363 364 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 365 "cpuid 0x%x\n", dip, sysino, cpuid); 366 367 ret = hvio_intr_settarget(sysino, cpuid); 368 if (ret == H_ECPUERROR) { 369 cmn_err(CE_PANIC, 370 "px_lib_intr_settarget: hvio_intr_settarget failed, " 371 "ret = 0x%lx, cpuid = 0x%x, sysino = 0x%lx\n", ret, 372 cpuid, sysino); 373 } else if (ret != H_EOK) { 374 DBG(DBG_LIB_INT, dip, 375 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 376 return (DDI_FAILURE); 377 } 378 379 return (DDI_SUCCESS); 380 } 381 382 /*ARGSUSED*/ 383 int 384 px_lib_intr_reset(dev_info_t *dip) 385 { 386 px_t *px_p = DIP_TO_STATE(dip); 387 px_ib_t *ib_p = px_p->px_ib_p; 388 px_ino_t *ino_p; 389 390 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 391 392 mutex_enter(&ib_p->ib_ino_lst_mutex); 393 394 /* Reset all Interrupts */ 395 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) { 396 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 397 INTR_IDLE_STATE) != DDI_SUCCESS) 398 return (BF_FATAL); 399 } 400 401 mutex_exit(&ib_p->ib_ino_lst_mutex); 402 403 return (BF_NONE); 404 } 405 406 /*ARGSUSED*/ 407 int 408 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 409 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 410 { 411 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 412 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 413 io_page_list_t *pfns, *pfn_p; 414 pages_t ttes_mapped = 0; 415 int i, err = DDI_SUCCESS; 416 417 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 418 "pages 0x%x attr 0x%llx addr 0x%p pfn_index 0x%llx flags 0x%x\n", 419 dip, tsbid, pages, attr, addr, pfn_index, flags); 420 421 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 422 KM_NOSLEEP)) == NULL) { 423 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 424 return (DDI_FAILURE); 425 } 426 427 for (i = 0; i < pages; i++) 428 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 429 430 /* 431 * If HV VPCI version is 1.1 and higher, pass BDF, phantom function, 432 * and relaxed ordering attributes. Otherwise, pass only read or write 433 * attribute. 434 */ 435 if (px_vpci_min_ver == PX_HSVC_MINOR_VER_0) 436 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 437 438 while ((ttes_mapped = pfn_p - pfns) < pages) { 439 uintptr_t ra = va_to_pa(pfn_p); 440 pages_t ttes2map; 441 uint64_t ret; 442 443 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 444 ra = MMU_PTOB(MMU_BTOP(ra)); 445 446 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 447 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 448 449 ttes_mapped = 0; 450 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 451 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 452 ttes2map, attr, (io_page_list_t *)(ra | 453 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 454 &ttes_mapped)) != H_EOK) { 455 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 456 "ret 0x%lx\n", ret); 457 458 ttes_mapped = pfn_p - pfns; 459 err = DDI_FAILURE; 460 goto cleanup; 461 } 462 463 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 464 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%llx " 465 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 466 tsb_index + (pfn_p - pfns), ttes2map, attr, 467 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 468 ttes_mapped); 469 } 470 } 471 472 cleanup: 473 if ((err == DDI_FAILURE) && ttes_mapped) 474 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 475 476 kmem_free(pfns, pages * sizeof (io_page_list_t)); 477 return (err); 478 } 479 480 /*ARGSUSED*/ 481 int 482 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 483 { 484 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 485 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 486 pages_t ttes2demap, ttes_demapped = 0; 487 uint64_t ret; 488 489 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 490 "pages 0x%x\n", dip, tsbid, pages); 491 492 for (ttes2demap = pages; ttes2demap; 493 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 494 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 495 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 496 &ttes_demapped)) != H_EOK) { 497 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 498 "ret 0x%lx\n", ret); 499 500 return (DDI_FAILURE); 501 } 502 503 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 504 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 505 tsb_num, tsb_index, ttes2demap, ttes_demapped); 506 } 507 508 return (DDI_SUCCESS); 509 } 510 511 /*ARGSUSED*/ 512 int 513 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 514 r_addr_t *r_addr_p) 515 { 516 uint64_t ret; 517 518 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 519 dip, tsbid); 520 521 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 522 attr_p, r_addr_p)) != H_EOK) { 523 DBG(DBG_LIB_DMA, dip, 524 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 525 526 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 527 } 528 529 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%llx " 530 "r_addr 0x%llx\n", *attr_p, *r_addr_p); 531 532 return (DDI_SUCCESS); 533 } 534 535 /*ARGSUSED*/ 536 uint64_t 537 px_get_rng_parent_hi_mask(px_t *px_p) 538 { 539 return (PX_RANGE_PROP_MASK); 540 } 541 542 /* 543 * Checks dma attributes against system bypass ranges 544 * A sun4v device must be capable of generating the entire 64-bit 545 * address in order to perform bypass DMA. 546 */ 547 /*ARGSUSED*/ 548 int 549 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 550 uint64_t *lo_p, uint64_t *hi_p) 551 { 552 if ((attr_p->dma_attr_addr_lo != 0ull) || 553 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 554 555 return (DDI_DMA_BADATTR); 556 } 557 558 *lo_p = 0ull; 559 *hi_p = UINT64_MAX; 560 561 return (DDI_SUCCESS); 562 } 563 564 565 /*ARGSUSED*/ 566 int 567 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 568 io_addr_t *io_addr_p) 569 { 570 uint64_t ret; 571 572 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 573 "attr 0x%llx\n", dip, ra, attr); 574 575 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 576 attr, io_addr_p)) != H_EOK) { 577 DBG(DBG_LIB_DMA, dip, 578 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 579 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 580 } 581 582 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 583 *io_addr_p); 584 585 return (DDI_SUCCESS); 586 } 587 588 /* 589 * Returns any needed IO address bit(s) for relaxed ordering in IOMMU 590 * bypass mode. 591 */ 592 /* ARGSUSED */ 593 uint64_t 594 px_lib_ro_bypass(dev_info_t *dip, io_attributes_t attr, uint64_t ioaddr) 595 { 596 return (ioaddr); 597 } 598 599 /*ARGSUSED*/ 600 int 601 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 602 off_t off, size_t len, uint_t cache_flags) 603 { 604 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 605 uint64_t sync_dir; 606 size_t bytes_synced; 607 int end, idx; 608 off_t pg_off; 609 devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */ 610 611 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 612 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 613 dip, rdip, handle, off, len, cache_flags); 614 615 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 616 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 617 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 618 return (DDI_FAILURE); 619 } 620 621 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 622 return (DDI_SUCCESS); 623 624 if (!len) 625 len = mp->dmai_size; 626 627 if (mp->dmai_rflags & DDI_DMA_READ) 628 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 629 else 630 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 631 632 off += mp->dmai_offset; 633 pg_off = off & MMU_PAGEOFFSET; 634 635 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: page offset %x size %x\n", 636 pg_off, len); 637 638 /* sync on page basis */ 639 end = MMU_BTOPR(off + len - 1); 640 for (idx = MMU_BTOP(off); idx < end; idx++, 641 len -= bytes_synced, pg_off = 0) { 642 size_t bytes_to_sync = bytes_to_sync = 643 MIN(len, MMU_PAGESIZE - pg_off); 644 645 if (hvio_dma_sync(hdl, MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + 646 pg_off, bytes_to_sync, sync_dir, &bytes_synced) != H_EOK) 647 break; 648 649 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: Called hvio_dma_sync " 650 "ra = %p bytes to sync = %x bytes synced %x\n", 651 MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + pg_off, bytes_to_sync, 652 bytes_synced); 653 654 if (bytes_to_sync != bytes_synced) 655 break; 656 } 657 658 return (len ? DDI_FAILURE : DDI_SUCCESS); 659 } 660 661 662 /* 663 * MSIQ Functions: 664 */ 665 666 /*ARGSUSED*/ 667 int 668 px_lib_msiq_init(dev_info_t *dip) 669 { 670 px_t *px_p = DIP_TO_STATE(dip); 671 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 672 r_addr_t ra; 673 size_t msiq_size; 674 uint_t rec_cnt; 675 int i, err = DDI_SUCCESS; 676 uint64_t ret; 677 678 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 679 680 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 681 682 /* sun4v requires all EQ allocation to be on q size boundary */ 683 if ((msiq_state_p->msiq_buf_p = contig_mem_alloc_align( 684 msiq_state_p->msiq_cnt * msiq_size, msiq_size)) == NULL) { 685 DBG(DBG_LIB_MSIQ, dip, 686 "px_lib_msiq_init: Contig alloc failed\n"); 687 688 return (DDI_FAILURE); 689 } 690 691 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 692 msiq_state_p->msiq_p[i].msiq_base_p = (msiqhead_t *) 693 ((caddr_t)msiq_state_p->msiq_buf_p + (i * msiq_size)); 694 695 ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p + 696 (i * msiq_size)); 697 698 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 699 (i + msiq_state_p->msiq_1st_msiq_id), 700 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 701 DBG(DBG_LIB_MSIQ, dip, 702 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 703 err = DDI_FAILURE; 704 break; 705 } 706 707 if ((err = px_lib_msiq_info(dip, 708 (i + msiq_state_p->msiq_1st_msiq_id), 709 &ra, &rec_cnt)) != DDI_SUCCESS) { 710 DBG(DBG_LIB_MSIQ, dip, 711 "px_lib_msiq_info failed, ret 0x%x\n", err); 712 err = DDI_FAILURE; 713 break; 714 } 715 716 DBG(DBG_LIB_MSIQ, dip, 717 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 718 } 719 720 return (err); 721 } 722 723 /*ARGSUSED*/ 724 int 725 px_lib_msiq_fini(dev_info_t *dip) 726 { 727 px_t *px_p = DIP_TO_STATE(dip); 728 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 729 size_t msiq_size; 730 731 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 732 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 733 734 if (msiq_state_p->msiq_buf_p != NULL) 735 contig_mem_free(msiq_state_p->msiq_buf_p, 736 msiq_state_p->msiq_cnt * msiq_size); 737 738 return (DDI_SUCCESS); 739 } 740 741 /*ARGSUSED*/ 742 int 743 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 744 uint_t *msiq_rec_cnt_p) 745 { 746 uint64_t ret; 747 748 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 749 dip, msiq_id); 750 751 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 752 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 753 DBG(DBG_LIB_MSIQ, dip, 754 "hvio_msiq_info failed, ret 0x%lx\n", ret); 755 return (DDI_FAILURE); 756 } 757 758 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 759 ra_p, *msiq_rec_cnt_p); 760 761 return (DDI_SUCCESS); 762 } 763 764 /*ARGSUSED*/ 765 int 766 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 767 pci_msiq_valid_state_t *msiq_valid_state) 768 { 769 uint64_t ret; 770 771 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 772 dip, msiq_id); 773 774 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 775 msiq_id, msiq_valid_state)) != H_EOK) { 776 DBG(DBG_LIB_MSIQ, dip, 777 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 778 return (DDI_FAILURE); 779 } 780 781 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 782 *msiq_valid_state); 783 784 return (DDI_SUCCESS); 785 } 786 787 /*ARGSUSED*/ 788 int 789 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 790 pci_msiq_valid_state_t msiq_valid_state) 791 { 792 uint64_t ret; 793 794 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 795 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 796 797 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 798 msiq_id, msiq_valid_state)) != H_EOK) { 799 DBG(DBG_LIB_MSIQ, dip, 800 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 801 return (DDI_FAILURE); 802 } 803 804 return (DDI_SUCCESS); 805 } 806 807 /*ARGSUSED*/ 808 int 809 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 810 pci_msiq_state_t *msiq_state) 811 { 812 uint64_t ret; 813 814 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 815 dip, msiq_id); 816 817 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 818 msiq_id, msiq_state)) != H_EOK) { 819 DBG(DBG_LIB_MSIQ, dip, 820 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 821 return (DDI_FAILURE); 822 } 823 824 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 825 *msiq_state); 826 827 return (DDI_SUCCESS); 828 } 829 830 /*ARGSUSED*/ 831 int 832 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 833 pci_msiq_state_t msiq_state) 834 { 835 uint64_t ret; 836 837 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 838 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 839 840 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 841 msiq_id, msiq_state)) != H_EOK) { 842 DBG(DBG_LIB_MSIQ, dip, 843 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 844 return (DDI_FAILURE); 845 } 846 847 return (DDI_SUCCESS); 848 } 849 850 /*ARGSUSED*/ 851 int 852 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 853 msiqhead_t *msiq_head_p) 854 { 855 uint64_t ret; 856 857 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 858 dip, msiq_id); 859 860 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 861 msiq_id, msiq_head_p)) != H_EOK) { 862 DBG(DBG_LIB_MSIQ, dip, 863 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 864 return (DDI_FAILURE); 865 } 866 867 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 868 869 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 870 *msiq_head_p); 871 872 return (DDI_SUCCESS); 873 } 874 875 /*ARGSUSED*/ 876 int 877 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 878 msiqhead_t msiq_head) 879 { 880 uint64_t ret; 881 882 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 883 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 884 885 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 886 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 887 DBG(DBG_LIB_MSIQ, dip, 888 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 889 return (DDI_FAILURE); 890 } 891 892 return (DDI_SUCCESS); 893 } 894 895 /*ARGSUSED*/ 896 int 897 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 898 msiqtail_t *msiq_tail_p) 899 { 900 uint64_t ret; 901 902 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 903 dip, msiq_id); 904 905 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 906 msiq_id, msiq_tail_p)) != H_EOK) { 907 DBG(DBG_LIB_MSIQ, dip, 908 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 909 return (DDI_FAILURE); 910 } 911 912 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 913 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 914 *msiq_tail_p); 915 916 return (DDI_SUCCESS); 917 } 918 919 /*ARGSUSED*/ 920 void 921 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 922 msiq_rec_t *msiq_rec_p) 923 { 924 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 925 926 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 927 928 if (!curr_msiq_rec_p->msiq_rec_type) { 929 /* Set msiq_rec_type to zero */ 930 msiq_rec_p->msiq_rec_type = 0; 931 932 return; 933 } 934 935 *msiq_rec_p = *curr_msiq_rec_p; 936 } 937 938 /*ARGSUSED*/ 939 void 940 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 941 { 942 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 943 944 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p\n", dip); 945 946 /* Zero out msiq_rec_type field */ 947 curr_msiq_rec_p->msiq_rec_type = 0; 948 } 949 950 /* 951 * MSI Functions: 952 */ 953 954 /*ARGSUSED*/ 955 int 956 px_lib_msi_init(dev_info_t *dip) 957 { 958 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 959 960 /* Noop */ 961 return (DDI_SUCCESS); 962 } 963 964 /*ARGSUSED*/ 965 int 966 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 967 msiqid_t *msiq_id) 968 { 969 uint64_t ret; 970 971 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 972 dip, msi_num); 973 974 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 975 msi_num, msiq_id)) != H_EOK) { 976 DBG(DBG_LIB_MSI, dip, 977 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 978 return (DDI_FAILURE); 979 } 980 981 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 982 *msiq_id); 983 984 return (DDI_SUCCESS); 985 } 986 987 /*ARGSUSED*/ 988 int 989 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 990 msiqid_t msiq_id, msi_type_t msitype) 991 { 992 uint64_t ret; 993 994 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 995 "msq_id 0x%x\n", dip, msi_num, msiq_id); 996 997 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 998 msi_num, msiq_id, msitype)) != H_EOK) { 999 DBG(DBG_LIB_MSI, dip, 1000 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 1001 return (DDI_FAILURE); 1002 } 1003 1004 return (DDI_SUCCESS); 1005 } 1006 1007 /*ARGSUSED*/ 1008 int 1009 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 1010 pci_msi_valid_state_t *msi_valid_state) 1011 { 1012 uint64_t ret; 1013 1014 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 1015 dip, msi_num); 1016 1017 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 1018 msi_num, msi_valid_state)) != H_EOK) { 1019 DBG(DBG_LIB_MSI, dip, 1020 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 1021 return (DDI_FAILURE); 1022 } 1023 1024 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 1025 *msi_valid_state); 1026 1027 return (DDI_SUCCESS); 1028 } 1029 1030 /*ARGSUSED*/ 1031 int 1032 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 1033 pci_msi_valid_state_t msi_valid_state) 1034 { 1035 uint64_t ret; 1036 1037 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 1038 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 1039 1040 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 1041 msi_num, msi_valid_state)) != H_EOK) { 1042 DBG(DBG_LIB_MSI, dip, 1043 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 1044 return (DDI_FAILURE); 1045 } 1046 1047 return (DDI_SUCCESS); 1048 } 1049 1050 /*ARGSUSED*/ 1051 int 1052 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 1053 pci_msi_state_t *msi_state) 1054 { 1055 uint64_t ret; 1056 1057 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 1058 dip, msi_num); 1059 1060 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 1061 msi_num, msi_state)) != H_EOK) { 1062 DBG(DBG_LIB_MSI, dip, 1063 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 1064 return (DDI_FAILURE); 1065 } 1066 1067 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 1068 *msi_state); 1069 1070 return (DDI_SUCCESS); 1071 } 1072 1073 /*ARGSUSED*/ 1074 int 1075 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 1076 pci_msi_state_t msi_state) 1077 { 1078 uint64_t ret; 1079 1080 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 1081 "msi_state 0x%x\n", dip, msi_num, msi_state); 1082 1083 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 1084 msi_num, msi_state)) != H_EOK) { 1085 DBG(DBG_LIB_MSI, dip, 1086 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 1087 return (DDI_FAILURE); 1088 } 1089 1090 return (DDI_SUCCESS); 1091 } 1092 1093 /* 1094 * MSG Functions: 1095 */ 1096 1097 /*ARGSUSED*/ 1098 int 1099 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1100 msiqid_t *msiq_id) 1101 { 1102 uint64_t ret; 1103 1104 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 1105 dip, msg_type); 1106 1107 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 1108 msg_type, msiq_id)) != H_EOK) { 1109 DBG(DBG_LIB_MSG, dip, 1110 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 1111 return (DDI_FAILURE); 1112 } 1113 1114 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1115 *msiq_id); 1116 1117 return (DDI_SUCCESS); 1118 } 1119 1120 /*ARGSUSED*/ 1121 int 1122 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1123 msiqid_t msiq_id) 1124 { 1125 uint64_t ret; 1126 1127 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 1128 "msq_id 0x%x\n", dip, msg_type, msiq_id); 1129 1130 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1131 msg_type, msiq_id)) != H_EOK) { 1132 DBG(DBG_LIB_MSG, dip, 1133 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1134 return (DDI_FAILURE); 1135 } 1136 1137 return (DDI_SUCCESS); 1138 } 1139 1140 /*ARGSUSED*/ 1141 int 1142 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1143 pcie_msg_valid_state_t *msg_valid_state) 1144 { 1145 uint64_t ret; 1146 1147 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1148 dip, msg_type); 1149 1150 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1151 msg_valid_state)) != H_EOK) { 1152 DBG(DBG_LIB_MSG, dip, 1153 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1154 return (DDI_FAILURE); 1155 } 1156 1157 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1158 *msg_valid_state); 1159 1160 return (DDI_SUCCESS); 1161 } 1162 1163 /*ARGSUSED*/ 1164 int 1165 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1166 pcie_msg_valid_state_t msg_valid_state) 1167 { 1168 uint64_t ret; 1169 1170 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1171 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1172 1173 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1174 msg_valid_state)) != H_EOK) { 1175 DBG(DBG_LIB_MSG, dip, 1176 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1177 return (DDI_FAILURE); 1178 } 1179 1180 return (DDI_SUCCESS); 1181 } 1182 1183 /* 1184 * Suspend/Resume Functions: 1185 * Currently unsupported by hypervisor and all functions are noops. 1186 */ 1187 /*ARGSUSED*/ 1188 int 1189 px_lib_suspend(dev_info_t *dip) 1190 { 1191 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1192 1193 /* Not supported */ 1194 return (DDI_FAILURE); 1195 } 1196 1197 /*ARGSUSED*/ 1198 void 1199 px_lib_resume(dev_info_t *dip) 1200 { 1201 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1202 1203 /* Noop */ 1204 } 1205 1206 /* 1207 * Misc Functions: 1208 * Currently unsupported by hypervisor and all functions are noops. 1209 */ 1210 /*ARGSUSED*/ 1211 static int 1212 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1213 uint8_t size, pci_cfg_data_t *data_p) 1214 { 1215 uint64_t ret; 1216 1217 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1218 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1219 1220 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1221 size, data_p)) != H_EOK) { 1222 DBG(DBG_LIB_CFG, dip, 1223 "hvio_config_get failed, ret 0x%lx\n", ret); 1224 return (DDI_FAILURE); 1225 } 1226 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1227 1228 return (DDI_SUCCESS); 1229 } 1230 1231 /*ARGSUSED*/ 1232 static int 1233 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1234 uint8_t size, pci_cfg_data_t data) 1235 { 1236 uint64_t ret; 1237 1238 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1239 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1240 1241 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1242 size, data)) != H_EOK) { 1243 DBG(DBG_LIB_CFG, dip, 1244 "hvio_config_put failed, ret 0x%lx\n", ret); 1245 return (DDI_FAILURE); 1246 } 1247 1248 return (DDI_SUCCESS); 1249 } 1250 1251 static uint32_t 1252 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1253 { 1254 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1255 handle->ahi_common.ah_bus_private; 1256 pcie_bus_t *busp = NULL; 1257 dev_info_t *cdip = NULL; 1258 uint32_t pci_dev_addr = px_pvt->raddr; 1259 uint32_t vaddr = px_pvt->vaddr; 1260 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1261 uint64_t rdata = 0; 1262 1263 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1264 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1265 /* XXX update error kstats */ 1266 return (0xffffffff); 1267 1268 if (cdip = pcie_find_dip_by_bdf(px_pvt->dip, pci_dev_addr >> 8)) 1269 busp = PCIE_DIP2BUS(cdip); 1270 /* 1271 * This can be called early, before busp or busp->bus_dom has 1272 * been initialized, so check both before invoking 1273 * PCIE_IS_ASSIGNED. 1274 */ 1275 if (busp && PCIE_BUS2DOM(busp) && PCIE_IS_ASSIGNED(busp)) { 1276 if (off == PCI_CONF_VENID && size == 2) 1277 rdata = busp->bus_dev_ven_id & 0xffff; 1278 else if (off == PCI_CONF_DEVID && size == 2) 1279 rdata = busp->bus_dev_ven_id >> 16; 1280 else if (off == PCI_CONF_VENID && size == 4) 1281 rdata = busp->bus_dev_ven_id; 1282 } 1283 return ((uint32_t)rdata); 1284 } 1285 1286 static void 1287 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1288 int size, pci_cfg_data_t wdata) 1289 { 1290 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1291 handle->ahi_common.ah_bus_private; 1292 uint32_t pci_dev_addr = px_pvt->raddr; 1293 uint32_t vaddr = px_pvt->vaddr; 1294 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1295 1296 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1297 size, wdata) != DDI_SUCCESS) { 1298 /*EMPTY*/ 1299 /* XXX update error kstats */ 1300 } 1301 } 1302 1303 static uint8_t 1304 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1305 { 1306 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1307 } 1308 1309 static uint16_t 1310 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1311 { 1312 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1313 } 1314 1315 static uint32_t 1316 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1317 { 1318 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1319 } 1320 1321 static uint64_t 1322 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1323 { 1324 uint32_t rdatah, rdatal; 1325 1326 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1327 rdatah = (uint32_t)px_pci_config_get(handle, 1328 (uint32_t *)((char *)addr+4), 4); 1329 return (((uint64_t)rdatah << 32) | rdatal); 1330 } 1331 1332 static void 1333 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1334 { 1335 pci_cfg_data_t wdata = { 0 }; 1336 1337 wdata.qw = (uint8_t)data; 1338 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1339 } 1340 1341 static void 1342 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1343 { 1344 pci_cfg_data_t wdata = { 0 }; 1345 1346 wdata.qw = (uint16_t)data; 1347 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1348 } 1349 1350 static void 1351 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1352 { 1353 pci_cfg_data_t wdata = { 0 }; 1354 1355 wdata.qw = (uint32_t)data; 1356 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1357 } 1358 1359 static void 1360 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1361 { 1362 pci_cfg_data_t wdata = { 0 }; 1363 1364 wdata.qw = (uint32_t)(data & 0xffffffff); 1365 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1366 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1367 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1368 } 1369 1370 static void 1371 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1372 uint8_t *dev_addr, size_t repcount, uint_t flags) 1373 { 1374 if (flags == DDI_DEV_AUTOINCR) 1375 for (; repcount; repcount--) 1376 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1377 else 1378 for (; repcount; repcount--) 1379 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1380 } 1381 1382 /* 1383 * Function to rep read 16 bit data off the PCI configuration space behind 1384 * the 21554's host interface. 1385 */ 1386 static void 1387 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1388 uint16_t *dev_addr, size_t repcount, uint_t flags) 1389 { 1390 if (flags == DDI_DEV_AUTOINCR) 1391 for (; repcount; repcount--) 1392 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1393 else 1394 for (; repcount; repcount--) 1395 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1396 } 1397 1398 /* 1399 * Function to rep read 32 bit data off the PCI configuration space behind 1400 * the 21554's host interface. 1401 */ 1402 static void 1403 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1404 uint32_t *dev_addr, size_t repcount, uint_t flags) 1405 { 1406 if (flags == DDI_DEV_AUTOINCR) 1407 for (; repcount; repcount--) 1408 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1409 else 1410 for (; repcount; repcount--) 1411 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1412 } 1413 1414 /* 1415 * Function to rep read 64 bit data off the PCI configuration space behind 1416 * the 21554's host interface. 1417 */ 1418 static void 1419 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1420 uint64_t *dev_addr, size_t repcount, uint_t flags) 1421 { 1422 if (flags == DDI_DEV_AUTOINCR) 1423 for (; repcount; repcount--) 1424 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1425 else 1426 for (; repcount; repcount--) 1427 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1428 } 1429 1430 /* 1431 * Function to rep write 8 bit data into the PCI configuration space behind 1432 * the 21554's host interface. 1433 */ 1434 static void 1435 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1436 uint8_t *dev_addr, size_t repcount, uint_t flags) 1437 { 1438 if (flags == DDI_DEV_AUTOINCR) 1439 for (; repcount; repcount--) 1440 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1441 else 1442 for (; repcount; repcount--) 1443 px_pci_config_put8(handle, dev_addr, *host_addr++); 1444 } 1445 1446 /* 1447 * Function to rep write 16 bit data into the PCI configuration space behind 1448 * the 21554's host interface. 1449 */ 1450 static void 1451 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1452 uint16_t *dev_addr, size_t repcount, uint_t flags) 1453 { 1454 if (flags == DDI_DEV_AUTOINCR) 1455 for (; repcount; repcount--) 1456 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1457 else 1458 for (; repcount; repcount--) 1459 px_pci_config_put16(handle, dev_addr, *host_addr++); 1460 } 1461 1462 /* 1463 * Function to rep write 32 bit data into the PCI configuration space behind 1464 * the 21554's host interface. 1465 */ 1466 static void 1467 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1468 uint32_t *dev_addr, size_t repcount, uint_t flags) 1469 { 1470 if (flags == DDI_DEV_AUTOINCR) 1471 for (; repcount; repcount--) 1472 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1473 else 1474 for (; repcount; repcount--) 1475 px_pci_config_put32(handle, dev_addr, *host_addr++); 1476 } 1477 1478 /* 1479 * Function to rep write 64 bit data into the PCI configuration space behind 1480 * the 21554's host interface. 1481 */ 1482 static void 1483 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1484 uint64_t *dev_addr, size_t repcount, uint_t flags) 1485 { 1486 if (flags == DDI_DEV_AUTOINCR) 1487 for (; repcount; repcount--) 1488 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1489 else 1490 for (; repcount; repcount--) 1491 px_pci_config_put64(handle, dev_addr, *host_addr++); 1492 } 1493 1494 /* 1495 * Provide a private access handle to route config access calls to Hypervisor. 1496 * Beware: Do all error checking for config space accesses before calling 1497 * this function. ie. do error checking from the calling function. 1498 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1499 * DDI_SUCCESS from here makes the code organization readable/easier from 1500 * the generic code. 1501 */ 1502 /*ARGSUSED*/ 1503 int 1504 px_lib_map_vconfig(dev_info_t *dip, 1505 ddi_map_req_t *mp, pci_config_offset_t off, 1506 pci_regspec_t *rp, caddr_t *addrp) 1507 { 1508 int fmcap; 1509 ndi_err_t *errp; 1510 on_trap_data_t *otp; 1511 ddi_acc_hdl_t *hp; 1512 ddi_acc_impl_t *ap; 1513 uchar_t busnum; /* bus number */ 1514 uchar_t devnum; /* device number */ 1515 uchar_t funcnum; /* function number */ 1516 px_config_acc_pvt_t *px_pvt; 1517 1518 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1519 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1520 1521 /* Check for mapping teardown operation */ 1522 if ((mp->map_op == DDI_MO_UNMAP) || 1523 (mp->map_op == DDI_MO_UNLOCK)) { 1524 /* free up memory allocated for the private access handle. */ 1525 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1526 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1527 1528 /* unmap operation of PCI IO/config space. */ 1529 return (DDI_SUCCESS); 1530 } 1531 1532 fmcap = ddi_fm_capable(dip); 1533 if (DDI_FM_ACC_ERR_CAP(fmcap)) { 1534 errp = ((ddi_acc_impl_t *)hp)->ahi_err; 1535 otp = (on_trap_data_t *)errp->err_ontrap; 1536 otp->ot_handle = (void *)(hp); 1537 otp->ot_prot = OT_DATA_ACCESS; 1538 errp->err_status = DDI_FM_OK; 1539 errp->err_expected = DDI_FM_ERR_UNEXPECTED; 1540 errp->err_cf = px_err_cfg_hdl_check; 1541 } 1542 1543 ap->ahi_get8 = px_pci_config_get8; 1544 ap->ahi_get16 = px_pci_config_get16; 1545 ap->ahi_get32 = px_pci_config_get32; 1546 ap->ahi_get64 = px_pci_config_get64; 1547 ap->ahi_put8 = px_pci_config_put8; 1548 ap->ahi_put16 = px_pci_config_put16; 1549 ap->ahi_put32 = px_pci_config_put32; 1550 ap->ahi_put64 = px_pci_config_put64; 1551 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1552 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1553 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1554 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1555 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1556 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1557 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1558 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1559 1560 /* Initialize to default check/notify functions */ 1561 ap->ahi_fault = 0; 1562 ap->ahi_fault_check = i_ddi_acc_fault_check; 1563 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1564 1565 /* allocate memory for our private handle */ 1566 px_pvt = (px_config_acc_pvt_t *) 1567 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1568 hp->ah_bus_private = (void *)px_pvt; 1569 1570 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1571 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1572 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1573 1574 /* set up private data for use during IO routines */ 1575 1576 /* addr needed by the HV APIs */ 1577 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1578 /* 1579 * Address that specifies the actual offset into the 256MB 1580 * memory mapped configuration space, 4K per device. 1581 * First 12bits form the offset into 4K config space. 1582 * This address is only used during the IO routines to calculate 1583 * the offset at which the transaction must be performed. 1584 * Drivers bypassing DDI functions to access PCI config space will 1585 * panic the system since the following is a bogus virtual address. 1586 */ 1587 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1588 px_pvt->dip = dip; 1589 1590 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1591 px_pvt->raddr, px_pvt->vaddr); 1592 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1593 return (DDI_SUCCESS); 1594 } 1595 1596 /*ARGSUSED*/ 1597 void 1598 px_lib_map_attr_check(ddi_map_req_t *mp) 1599 { 1600 } 1601 1602 /* 1603 * px_lib_log_safeacc_err: 1604 * Imitate a cpu/mem trap call when a peek/poke fails. 1605 * This will initiate something similar to px_fm_callback. 1606 */ 1607 static void 1608 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag, 1609 r_addr_t addr) 1610 { 1611 uint32_t addr_high, addr_low; 1612 pcie_req_id_t bdf = PCIE_INVALID_BDF; 1613 pci_ranges_t *ranges_p; 1614 int range_len, i; 1615 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1616 ddi_fm_error_t derr; 1617 1618 if (px_fm_enter(px_p) != DDI_SUCCESS) 1619 return; 1620 1621 derr.fme_status = DDI_FM_NONFATAL; 1622 derr.fme_version = DDI_FME_VERSION; 1623 derr.fme_flag = fme_flag; 1624 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1625 derr.fme_acc_handle = handle; 1626 if (hp) 1627 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1628 1629 addr_high = (uint32_t)(addr >> 32); 1630 addr_low = (uint32_t)addr; 1631 1632 /* 1633 * Make sure this failed load came from this PCIe port. Check by 1634 * matching the upper 32 bits of the address with the ranges property. 1635 */ 1636 range_len = px_p->px_ranges_length / sizeof (pci_ranges_t); 1637 i = 0; 1638 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 1639 if (ranges_p->parent_high == addr_high) { 1640 switch (ranges_p->child_high & PCI_ADDR_MASK) { 1641 case PCI_ADDR_CONFIG: 1642 bdf = (pcie_req_id_t)(addr_low >> 12); 1643 break; 1644 default: 1645 bdf = PCIE_INVALID_BDF; 1646 break; 1647 } 1648 break; 1649 } 1650 } 1651 1652 (void) px_rp_en_q(px_p, bdf, addr, NULL); 1653 (void) px_scan_fabric(px_p, px_p->px_dip, &derr); 1654 px_fm_exit(px_p); 1655 } 1656 1657 1658 #ifdef DEBUG 1659 int px_peekfault_cnt = 0; 1660 int px_pokefault_cnt = 0; 1661 #endif /* DEBUG */ 1662 1663 /* 1664 * Do a safe write to a device. 1665 * 1666 * When this function is given a handle (cautious access), all errors are 1667 * suppressed. 1668 * 1669 * When this function is not given a handle (poke), only Unsupported Request 1670 * and Completer Abort errors are suppressed. 1671 * 1672 * In all cases, all errors are returned in the function return status. 1673 */ 1674 1675 int 1676 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1677 peekpoke_ctlops_t *in_args) 1678 { 1679 px_t *px_p = DIP_TO_STATE(dip); 1680 px_pec_t *pec_p = px_p->px_pec_p; 1681 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1682 1683 size_t repcount = in_args->repcount; 1684 size_t size = in_args->size; 1685 uintptr_t dev_addr = in_args->dev_addr; 1686 uintptr_t host_addr = in_args->host_addr; 1687 1688 int err = DDI_SUCCESS; 1689 uint64_t hvio_poke_status; 1690 uint32_t wrt_stat; 1691 1692 r_addr_t ra; 1693 uint64_t pokeval; 1694 pcie_req_id_t bdf; 1695 1696 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1697 for (; repcount; repcount--) { 1698 1699 switch (size) { 1700 case sizeof (uint8_t): 1701 pokeval = *(uint8_t *)host_addr; 1702 break; 1703 case sizeof (uint16_t): 1704 pokeval = *(uint16_t *)host_addr; 1705 break; 1706 case sizeof (uint32_t): 1707 pokeval = *(uint32_t *)host_addr; 1708 break; 1709 case sizeof (uint64_t): 1710 pokeval = *(uint64_t *)host_addr; 1711 break; 1712 default: 1713 DBG(DBG_MAP, px_p->px_dip, 1714 "poke: invalid size %d passed\n", size); 1715 err = DDI_FAILURE; 1716 goto done; 1717 } 1718 1719 /* 1720 * Grab pokefault mutex since hypervisor does not guarantee 1721 * poke serialization. 1722 */ 1723 if (hp) { 1724 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1725 (ddi_acc_handle_t)hp); 1726 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1727 } else { 1728 mutex_enter(&pec_p->pec_pokefault_mutex); 1729 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1730 } 1731 1732 if (pcie_get_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1733 err = DDI_FAILURE; 1734 goto done; 1735 } 1736 1737 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1738 pokeval, bdf << 8, &wrt_stat); 1739 1740 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1741 err = DDI_FAILURE; 1742 #ifdef DEBUG 1743 px_pokefault_cnt++; 1744 #endif 1745 /* 1746 * For CAUTIOUS and POKE access, notify FMA to 1747 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1748 */ 1749 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1750 (hp ? DDI_FM_ERR_EXPECTED : 1751 DDI_FM_ERR_POKE), ra); 1752 1753 pec_p->pec_ontrap_data = NULL; 1754 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1755 if (hp) { 1756 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1757 (ddi_acc_handle_t)hp); 1758 } else { 1759 mutex_exit(&pec_p->pec_pokefault_mutex); 1760 } 1761 goto done; 1762 } 1763 1764 pec_p->pec_ontrap_data = NULL; 1765 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1766 if (hp) { 1767 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1768 (ddi_acc_handle_t)hp); 1769 } else { 1770 mutex_exit(&pec_p->pec_pokefault_mutex); 1771 } 1772 1773 host_addr += size; 1774 1775 if (in_args->flags == DDI_DEV_AUTOINCR) { 1776 dev_addr += size; 1777 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1778 } 1779 } 1780 1781 done: 1782 return (err); 1783 } 1784 1785 1786 /*ARGSUSED*/ 1787 int 1788 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1789 peekpoke_ctlops_t *in_args, void *result) 1790 { 1791 px_t *px_p = DIP_TO_STATE(dip); 1792 px_pec_t *pec_p = px_p->px_pec_p; 1793 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1794 1795 size_t repcount = in_args->repcount; 1796 uintptr_t dev_addr = in_args->dev_addr; 1797 uintptr_t host_addr = in_args->host_addr; 1798 1799 r_addr_t ra; 1800 uint32_t read_status; 1801 uint64_t hvio_peek_status; 1802 uint64_t peekval; 1803 int err = DDI_SUCCESS; 1804 1805 result = (void *)in_args->host_addr; 1806 1807 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1808 for (; repcount; repcount--) { 1809 1810 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1811 if (hp) { 1812 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1813 (ddi_acc_handle_t)hp); 1814 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1815 } else { 1816 mutex_enter(&pec_p->pec_pokefault_mutex); 1817 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1818 } 1819 1820 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1821 in_args->size, &read_status, &peekval); 1822 1823 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1824 err = DDI_FAILURE; 1825 1826 /* 1827 * For CAUTIOUS and PEEK access, notify FMA to 1828 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1829 */ 1830 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1831 (hp ? DDI_FM_ERR_EXPECTED : 1832 DDI_FM_ERR_PEEK), ra); 1833 1834 /* Stuff FFs in host addr if peek. */ 1835 if (hp == NULL) { 1836 int i; 1837 uint8_t *ff_addr = (uint8_t *)host_addr; 1838 for (i = 0; i < in_args->size; i++) 1839 *ff_addr++ = 0xff; 1840 } 1841 #ifdef DEBUG 1842 px_peekfault_cnt++; 1843 #endif 1844 pec_p->pec_ontrap_data = NULL; 1845 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1846 if (hp) { 1847 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1848 (ddi_acc_handle_t)hp); 1849 } else { 1850 mutex_exit(&pec_p->pec_pokefault_mutex); 1851 } 1852 goto done; 1853 1854 } 1855 pec_p->pec_ontrap_data = NULL; 1856 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1857 if (hp) { 1858 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1859 (ddi_acc_handle_t)hp); 1860 } else { 1861 mutex_exit(&pec_p->pec_pokefault_mutex); 1862 } 1863 1864 switch (in_args->size) { 1865 case sizeof (uint8_t): 1866 *(uint8_t *)host_addr = (uint8_t)peekval; 1867 break; 1868 case sizeof (uint16_t): 1869 *(uint16_t *)host_addr = (uint16_t)peekval; 1870 break; 1871 case sizeof (uint32_t): 1872 *(uint32_t *)host_addr = (uint32_t)peekval; 1873 break; 1874 case sizeof (uint64_t): 1875 *(uint64_t *)host_addr = (uint64_t)peekval; 1876 break; 1877 default: 1878 DBG(DBG_MAP, px_p->px_dip, 1879 "peek: invalid size %d passed\n", 1880 in_args->size); 1881 err = DDI_FAILURE; 1882 goto done; 1883 } 1884 1885 host_addr += in_args->size; 1886 1887 if (in_args->flags == DDI_DEV_AUTOINCR) { 1888 dev_addr += in_args->size; 1889 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1890 } 1891 } 1892 done: 1893 return (err); 1894 } 1895 1896 1897 /* add interrupt vector */ 1898 int 1899 px_err_add_intr(px_fault_t *px_fault_p) 1900 { 1901 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1902 1903 DBG(DBG_LIB_INT, px_p->px_dip, 1904 "px_err_add_intr: calling add_ivintr"); 1905 1906 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1907 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL, 1908 (caddr_t)&px_fault_p->px_intr_payload[0]) == 0); 1909 1910 DBG(DBG_LIB_INT, px_p->px_dip, 1911 "px_err_add_intr: ib_intr_enable "); 1912 1913 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1914 1915 return (DDI_SUCCESS); 1916 } 1917 1918 /* remove interrupt vector */ 1919 void 1920 px_err_rem_intr(px_fault_t *px_fault_p) 1921 { 1922 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1923 1924 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1925 IB_INTR_WAIT); 1926 1927 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 1928 } 1929 1930 void 1931 px_cb_intr_redist(void *arg) 1932 { 1933 px_t *px_p = (px_t *)arg; 1934 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1935 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1936 } 1937 1938 int 1939 px_cb_add_intr(px_fault_t *f_p) 1940 { 1941 px_t *px_p = DIP_TO_STATE(f_p->px_fh_dip); 1942 1943 DBG(DBG_LIB_INT, px_p->px_dip, 1944 "px_err_add_intr: calling add_ivintr"); 1945 1946 VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL, 1947 (intrfunc)f_p->px_err_func, (caddr_t)f_p, NULL, 1948 (caddr_t)&f_p->px_intr_payload[0]) == 0); 1949 1950 intr_dist_add(px_cb_intr_redist, px_p); 1951 1952 DBG(DBG_LIB_INT, px_p->px_dip, 1953 "px_err_add_intr: ib_intr_enable "); 1954 1955 px_ib_intr_enable(px_p, intr_dist_cpuid(), f_p->px_intr_ino); 1956 1957 return (DDI_SUCCESS); 1958 } 1959 1960 void 1961 px_cb_rem_intr(px_fault_t *f_p) 1962 { 1963 intr_dist_rem(px_cb_intr_redist, DIP_TO_STATE(f_p->px_fh_dip)); 1964 px_err_rem_intr(f_p); 1965 } 1966 1967 #ifdef FMA 1968 void 1969 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1970 { 1971 px_pec_err_t *err_pkt; 1972 1973 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1974 1975 /* initialise all the structure members */ 1976 rc_status->status_valid = 0; 1977 1978 if (err_pkt->pec_descr.P) { 1979 /* PCI Status Register */ 1980 rc_status->pci_err_status = err_pkt->pci_err_status; 1981 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1982 } 1983 1984 if (err_pkt->pec_descr.E) { 1985 /* PCIe Status Register */ 1986 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1987 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1988 } 1989 1990 if (err_pkt->pec_descr.U) { 1991 rc_status->ue_status = err_pkt->ue_reg_status; 1992 rc_status->status_valid |= UE_STATUS_VALID; 1993 } 1994 1995 if (err_pkt->pec_descr.H) { 1996 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1997 rc_status->status_valid |= UE_HDR1_VALID; 1998 } 1999 2000 if (err_pkt->pec_descr.I) { 2001 rc_status->ue_hdr2 = err_pkt->hdr[1]; 2002 rc_status->status_valid |= UE_HDR2_VALID; 2003 } 2004 2005 /* ue_fst_err_ptr - not available for sun4v?? */ 2006 2007 2008 if (err_pkt->pec_descr.S) { 2009 rc_status->source_id = err_pkt->err_src_reg; 2010 rc_status->status_valid |= SOURCE_ID_VALID; 2011 } 2012 2013 if (err_pkt->pec_descr.R) { 2014 rc_status->root_err_status = err_pkt->root_err_status; 2015 rc_status->status_valid |= CE_STATUS_VALID; 2016 } 2017 } 2018 #endif 2019 2020 /*ARGSUSED*/ 2021 int 2022 px_lib_pmctl(int cmd, px_t *px_p) 2023 { 2024 return (DDI_FAILURE); 2025 } 2026 2027 /*ARGSUSED*/ 2028 uint_t 2029 px_pmeq_intr(caddr_t arg) 2030 { 2031 return (DDI_INTR_CLAIMED); 2032 } 2033 2034 /* 2035 * fetch the config space base addr of the root complex 2036 * note this depends on px structure being initialized 2037 */ 2038 uint64_t 2039 px_lib_get_cfgacc_base(dev_info_t *dip) 2040 { 2041 int instance = DIP_TO_INST(dip); 2042 px_t *px_p = INST_TO_STATE(instance); 2043 2044 return (px_p->px_dev_hdl); 2045 } 2046 2047 void 2048 px_panic_domain(px_t *px_p, pcie_req_id_t bdf) 2049 { 2050 uint64_t ret; 2051 dev_info_t *dip = px_p->px_dip; 2052 2053 DBG(DBG_ERR_INTR, dip, "px_panic_domain: handle 0x%lx, ino %d, " 2054 "bdf<<8 0x%lx\n", 2055 (uint64_t)DIP_TO_HANDLE(dip), px_p->px_cb_fault.px_intr_ino, 2056 (pci_device_t)bdf << 8); 2057 if ((ret = pci_error_send(DIP_TO_HANDLE(dip), 2058 px_p->px_cb_fault.px_intr_ino, (pci_device_t)bdf << 8)) != H_EOK) { 2059 DBG(DBG_ERR_INTR, dip, "pci_error_send failed, ret 0x%lx\n", 2060 ret); 2061 } else 2062 DBG(DBG_ERR_INTR, dip, "pci_error_send worked\n"); 2063 } 2064 2065 /*ARGSUSED*/ 2066 int 2067 px_lib_hotplug_init(dev_info_t *dip, void *arg) 2068 { 2069 return (DDI_ENOTSUP); 2070 } 2071 2072 /*ARGSUSED*/ 2073 void 2074 px_lib_hotplug_uninit(dev_info_t *dip) 2075 { 2076 } 2077 2078 /*ARGSUSED*/ 2079 void 2080 px_hp_intr_redist(px_t *px_p) 2081 { 2082 } 2083 2084 /* Dummy cpr add callback */ 2085 /*ARGSUSED*/ 2086 void 2087 px_cpr_add_callb(px_t *px_p) 2088 { 2089 } 2090 2091 /* Dummy cpr rem callback */ 2092 /*ARGSUSED*/ 2093 void 2094 px_cpr_rem_callb(px_t *px_p) 2095 { 2096 } 2097 2098 /*ARGSUSED*/ 2099 boolean_t 2100 px_lib_is_in_drain_state(px_t *px_p) 2101 { 2102 return (B_FALSE); 2103 } 2104 2105 /* 2106 * There is no IOAPI to get the BDF of the pcie root port nexus at this moment. 2107 * Assume it is 0x0000, until otherwise noted. For now, all sun4v platforms 2108 * have programmed the BDF to be 0x0000. 2109 */ 2110 /*ARGSUSED*/ 2111 pcie_req_id_t 2112 px_lib_get_bdf(px_t *px_p) 2113 { 2114 return (0x0000); 2115 } 2116 2117 int 2118 px_lib_get_root_complex_mps(px_t *px_p, dev_info_t *dip, int *mps) 2119 { 2120 pci_device_t bdf = px_lib_get_bdf(px_p); 2121 2122 if (hvio_get_rp_mps_cap(DIP_TO_HANDLE(dip), bdf, mps) == H_EOK) 2123 return (DDI_SUCCESS); 2124 else 2125 return (DDI_FAILURE); 2126 } 2127 2128 int 2129 px_lib_set_root_complex_mps(px_t *px_p, dev_info_t *dip, int mps) 2130 { 2131 pci_device_t bdf = px_lib_get_bdf(px_p); 2132 2133 if (hvio_set_rp_mps(DIP_TO_HANDLE(dip), bdf, mps) == H_EOK) 2134 return (DDI_SUCCESS); 2135 else 2136 return (DDI_FAILURE); 2137 } 2138 2139 static int 2140 px_lib_do_count_waiting_dev(dev_info_t *dip, void *arg) 2141 { 2142 int *count = (int *)arg; 2143 dev_info_t *cdip = ddi_get_child(dip); 2144 2145 while (cdip != NULL) { 2146 /* check if this is an assigned device */ 2147 if (ddi_prop_exists(DDI_DEV_T_NONE, cdip, DDI_PROP_DONTPASS, 2148 "ddi-assigned")) { 2149 DBG(DBG_ATTACH, dip, "px_lib_do_count_waiting_dev: " 2150 "Found an assigned dev %p, under bridge %p", 2151 cdip, dip); 2152 2153 /* 2154 * Mark this bridge as needing waiting for 2155 * CHILD_LOANED will be removed after bridge reports 2156 * its readyness back to px driver 2157 */ 2158 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 2159 CHILD_LOANED, 1) == DDI_PROP_SUCCESS) 2160 (*count)++; 2161 break; 2162 } 2163 cdip = ddi_get_next_sibling(cdip); 2164 } 2165 2166 return (DDI_WALK_CONTINUE); 2167 } 2168 2169 static int 2170 px_lib_count_waiting_dev(dev_info_t *dip) 2171 { 2172 int circular_count; 2173 int count = 0; 2174 2175 /* No need to continue if this system is not SDIO capable */ 2176 if (px_sdio_users == 0) 2177 return (0); 2178 2179 /* see if px iteslf has assigned children */ 2180 (void) px_lib_do_count_waiting_dev(dip, &count); 2181 2182 /* scan dev under this px */ 2183 ndi_devi_enter(dip, &circular_count); 2184 ddi_walk_devs(ddi_get_child(dip), px_lib_do_count_waiting_dev, &count); 2185 ndi_devi_exit(dip, circular_count); 2186 return (count); 2187 } 2188 2189 /* Called from px/bridge driver directly to report its readyness */ 2190 int 2191 px_lib_fabric_sync(dev_info_t *dip) 2192 { 2193 px_t *px; 2194 dev_info_t *rcdip; 2195 int waitdev; 2196 2197 /* No need to continue if this system is not SDIO capable */ 2198 if (px_sdio_users == 0) 2199 return (DDI_SUCCESS); 2200 2201 /* a valid bridge w/ assigned dev under it? */ 2202 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, CHILD_LOANED) != 2203 DDI_PROP_SUCCESS) 2204 return (DDI_FAILURE); 2205 2206 /* find out RC dip */ 2207 for (rcdip = dip; rcdip != NULL; rcdip = ddi_get_parent(rcdip)) { 2208 if (PCIE_DIP2BUS(rcdip) && PCIE_IS_RC(PCIE_DIP2BUS(rcdip))) 2209 break; 2210 } 2211 if ((rcdip == NULL) || ((px = (px_t *)DIP_TO_STATE(rcdip)) == NULL)) 2212 return (DDI_FAILURE); 2213 2214 /* are we ready? */ 2215 waitdev = (int)(uintptr_t)px->px_plat_p; 2216 ASSERT(waitdev); 2217 DBG(DBG_CTLOPS, rcdip, "px_lib_fabric_sync: " 2218 "Px/bridge %p is ready, %d left", rcdip, waitdev - 1); 2219 --waitdev; 2220 px->px_plat_p = (void *)(uintptr_t)waitdev; 2221 if (waitdev != 0) 2222 return (DDI_SUCCESS); 2223 2224 /* notify hpyervisor */ 2225 DBG(DBG_CTLOPS, rcdip, "px_lib_fabric_sync: " 2226 "Notifying HV that RC %p is ready users=%d", rcdip, px_sdio_users); 2227 2228 if (pci_iov_root_configured(px->px_dev_hdl) != H_EOK) 2229 return (DDI_FAILURE); 2230 2231 return (DDI_SUCCESS); 2232 } 2233