1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 uint64_t mjrnum; 69 uint64_t mnrnum; 70 71 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 72 73 /* 74 * Check HV intr group api versioning. 75 * This driver uses the old interrupt routines which are supported 76 * in old firmware in the CORE API group and in newer firmware in 77 * the INTR API group. Support for these calls will be dropped 78 * once the INTR API group major goes to 2. 79 */ 80 if ((hsvc_version(HSVC_GROUP_INTR, &mjrnum, &mnrnum) == 0) && 81 (mjrnum > 1)) { 82 cmn_err(CE_WARN, "niumx: unsupported intr api group: " 83 "maj:0x%lx, min:0x%lx", mjrnum, mnrnum); 84 return (ENOTSUP); 85 } 86 87 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 88 "reg", (uchar_t **)&rp, ®len); 89 if (ret != DDI_PROP_SUCCESS) { 90 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 91 return (DDI_FAILURE); 92 } 93 94 /* 95 * Initilize device handle. The device handle uniquely identifies 96 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 97 * of the first entry of the SUN4V device's "reg" property as 98 * defined by the SUN4V Bus Binding to Open Firmware. 99 */ 100 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 101 ddi_prop_free(rp); 102 103 /* 104 * hotplug implementation requires this property to be associated with 105 * any indirect PCI config access services 106 */ 107 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 108 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 109 PCI_BUS_CONF_MAP_PROP, 1); 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 112 113 /* 114 * Negotiate the API version for VPCI hypervisor services. 115 */ 116 if (px_vpci_users++) 117 return (DDI_SUCCESS); 118 119 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 120 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 121 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 122 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 123 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 124 125 return (DDI_FAILURE); 126 } 127 128 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 129 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 130 131 return (DDI_SUCCESS); 132 } 133 134 /*ARGSUSED*/ 135 int 136 px_lib_dev_fini(dev_info_t *dip) 137 { 138 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 139 140 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 141 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 142 PCI_BUS_CONF_MAP_PROP); 143 144 if (--px_vpci_users == 0) 145 (void) hsvc_unregister(&px_hsvc); 146 147 return (DDI_SUCCESS); 148 } 149 150 /*ARGSUSED*/ 151 int 152 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 153 sysino_t *sysino) 154 { 155 uint64_t ret; 156 157 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 158 "devino 0x%x\n", dip, devino); 159 160 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 161 devino, sysino)) != H_EOK) { 162 DBG(DBG_LIB_INT, dip, 163 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 164 return (DDI_FAILURE); 165 } 166 167 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 168 *sysino); 169 170 return (DDI_SUCCESS); 171 } 172 173 /*ARGSUSED*/ 174 int 175 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 176 intr_valid_state_t *intr_valid_state) 177 { 178 uint64_t ret; 179 180 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 181 dip, sysino); 182 183 if ((ret = hvio_intr_getvalid(sysino, 184 (int *)intr_valid_state)) != H_EOK) { 185 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 186 ret); 187 return (DDI_FAILURE); 188 } 189 190 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 191 *intr_valid_state); 192 193 return (DDI_SUCCESS); 194 } 195 196 /*ARGSUSED*/ 197 int 198 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 199 intr_valid_state_t intr_valid_state) 200 { 201 uint64_t ret; 202 203 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 204 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 205 206 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 207 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 208 ret); 209 return (DDI_FAILURE); 210 } 211 212 return (DDI_SUCCESS); 213 } 214 215 /*ARGSUSED*/ 216 int 217 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 218 intr_state_t *intr_state) 219 { 220 uint64_t ret; 221 222 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 223 dip, sysino); 224 225 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 226 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 227 ret); 228 return (DDI_FAILURE); 229 } 230 231 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 232 *intr_state); 233 234 return (DDI_SUCCESS); 235 } 236 237 /*ARGSUSED*/ 238 int 239 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 240 intr_state_t intr_state) 241 { 242 uint64_t ret; 243 244 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 245 "intr_state 0x%x\n", dip, sysino, intr_state); 246 247 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 248 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 249 ret); 250 return (DDI_FAILURE); 251 } 252 253 return (DDI_SUCCESS); 254 } 255 256 /*ARGSUSED*/ 257 int 258 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 259 { 260 uint64_t ret; 261 262 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 263 dip, sysino); 264 265 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 266 DBG(DBG_LIB_INT, dip, 267 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 268 return (DDI_FAILURE); 269 } 270 271 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 272 273 return (DDI_SUCCESS); 274 } 275 276 /*ARGSUSED*/ 277 int 278 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 279 { 280 uint64_t ret; 281 282 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 283 "cpuid 0x%x\n", dip, sysino, cpuid); 284 285 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 286 DBG(DBG_LIB_INT, dip, 287 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 288 return (DDI_FAILURE); 289 } 290 291 return (DDI_SUCCESS); 292 } 293 294 /*ARGSUSED*/ 295 int 296 px_lib_intr_reset(dev_info_t *dip) 297 { 298 px_t *px_p = DIP_TO_STATE(dip); 299 px_ib_t *ib_p = px_p->px_ib_p; 300 px_ino_t *ino_p; 301 302 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 303 304 mutex_enter(&ib_p->ib_ino_lst_mutex); 305 306 /* Reset all Interrupts */ 307 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next_p) { 308 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 309 INTR_IDLE_STATE) != DDI_SUCCESS) 310 return (BF_FATAL); 311 } 312 313 mutex_exit(&ib_p->ib_ino_lst_mutex); 314 315 return (BF_NONE); 316 } 317 318 /*ARGSUSED*/ 319 int 320 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 321 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 322 { 323 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 324 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 325 io_page_list_t *pfns, *pfn_p; 326 pages_t ttes_mapped = 0; 327 int i, err = DDI_SUCCESS; 328 329 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 330 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 331 dip, tsbid, pages, attr, addr, pfn_index, flags); 332 333 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 334 KM_NOSLEEP)) == NULL) { 335 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 336 return (DDI_FAILURE); 337 } 338 339 for (i = 0; i < pages; i++) 340 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 341 342 /* 343 * If HV VPCI version is 1.1 and higher, pass BDF, phantom function, 344 * and relaxed ordering attributes. Otherwise, pass only read or write 345 * attribute. 346 */ 347 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 348 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 349 350 while ((ttes_mapped = pfn_p - pfns) < pages) { 351 uintptr_t ra = va_to_pa(pfn_p); 352 pages_t ttes2map; 353 uint64_t ret; 354 355 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 356 ra = MMU_PTOB(MMU_BTOP(ra)); 357 358 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 359 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 360 361 ttes_mapped = 0; 362 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 363 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 364 ttes2map, attr, (io_page_list_t *)(ra | 365 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 366 &ttes_mapped)) != H_EOK) { 367 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 368 "ret 0x%lx\n", ret); 369 370 ttes_mapped = pfn_p - pfns; 371 err = DDI_FAILURE; 372 goto cleanup; 373 } 374 375 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 376 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 377 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 378 tsb_index + (pfn_p - pfns), ttes2map, attr, 379 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 380 ttes_mapped); 381 } 382 } 383 384 cleanup: 385 if ((err == DDI_FAILURE) && ttes_mapped) 386 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 387 388 kmem_free(pfns, pages * sizeof (io_page_list_t)); 389 return (err); 390 } 391 392 /*ARGSUSED*/ 393 int 394 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 395 { 396 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 397 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 398 pages_t ttes2demap, ttes_demapped = 0; 399 uint64_t ret; 400 401 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 402 "pages 0x%x\n", dip, tsbid, pages); 403 404 for (ttes2demap = pages; ttes2demap; 405 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 406 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 407 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 408 &ttes_demapped)) != H_EOK) { 409 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 410 "ret 0x%lx\n", ret); 411 412 return (DDI_FAILURE); 413 } 414 415 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 416 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 417 tsb_num, tsb_index, ttes2demap, ttes_demapped); 418 } 419 420 return (DDI_SUCCESS); 421 } 422 423 /*ARGSUSED*/ 424 int 425 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 426 r_addr_t *r_addr_p) 427 { 428 uint64_t ret; 429 430 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 431 dip, tsbid); 432 433 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 434 attr_p, r_addr_p)) != H_EOK) { 435 DBG(DBG_LIB_DMA, dip, 436 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 437 438 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 439 } 440 441 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 442 *attr_p, *r_addr_p); 443 444 return (DDI_SUCCESS); 445 } 446 447 /*ARGSUSED*/ 448 uint64_t 449 px_get_rng_parent_hi_mask(px_t *px_p) 450 { 451 return (PX_RANGE_PROP_MASK); 452 } 453 454 /* 455 * Checks dma attributes against system bypass ranges 456 * A sun4v device must be capable of generating the entire 64-bit 457 * address in order to perform bypass DMA. 458 */ 459 /*ARGSUSED*/ 460 int 461 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 462 uint64_t *lo_p, uint64_t *hi_p) 463 { 464 if ((attr_p->dma_attr_addr_lo != 0ull) || 465 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 466 467 return (DDI_DMA_BADATTR); 468 } 469 470 *lo_p = 0ull; 471 *hi_p = UINT64_MAX; 472 473 return (DDI_SUCCESS); 474 } 475 476 477 /*ARGSUSED*/ 478 int 479 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 480 io_addr_t *io_addr_p) 481 { 482 uint64_t ret; 483 484 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 485 "attr 0x%x\n", dip, ra, attr); 486 487 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 488 attr, io_addr_p)) != H_EOK) { 489 DBG(DBG_LIB_DMA, dip, 490 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 491 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 492 } 493 494 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 495 *io_addr_p); 496 497 return (DDI_SUCCESS); 498 } 499 500 /*ARGSUSED*/ 501 int 502 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 503 off_t off, size_t len, uint_t cache_flags) 504 { 505 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 506 uint64_t sync_dir; 507 size_t bytes_synced; 508 int end, idx; 509 off_t pg_off; 510 devhandle_t hdl = DIP_TO_HANDLE(dip); /* need to cache hdl */ 511 512 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 513 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 514 dip, rdip, handle, off, len, cache_flags); 515 516 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 517 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 518 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 519 return (DDI_FAILURE); 520 } 521 522 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 523 return (DDI_SUCCESS); 524 525 if (!len) 526 len = mp->dmai_size; 527 528 if (mp->dmai_rflags & DDI_DMA_READ) 529 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 530 else 531 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 532 533 off += mp->dmai_offset; 534 pg_off = off & MMU_PAGEOFFSET; 535 536 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: page offset %x size %x\n", 537 pg_off, len); 538 539 /* sync on page basis */ 540 end = MMU_BTOPR(off + len - 1); 541 for (idx = MMU_BTOP(off); idx < end; idx++, 542 len -= bytes_synced, pg_off = 0) { 543 size_t bytes_to_sync = bytes_to_sync = 544 MIN(len, MMU_PAGESIZE - pg_off); 545 546 if (hvio_dma_sync(hdl, MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + 547 pg_off, bytes_to_sync, sync_dir, &bytes_synced) != H_EOK) 548 break; 549 550 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: Called hvio_dma_sync " 551 "ra = %p bytes to sync = %x bytes synced %x\n", 552 MMU_PTOB(PX_GET_MP_PFN(mp, idx)) + pg_off, bytes_to_sync, 553 bytes_synced); 554 555 if (bytes_to_sync != bytes_synced) 556 break; 557 } 558 559 return (len ? DDI_FAILURE : DDI_SUCCESS); 560 } 561 562 563 /* 564 * MSIQ Functions: 565 */ 566 567 /*ARGSUSED*/ 568 int 569 px_lib_msiq_init(dev_info_t *dip) 570 { 571 px_t *px_p = DIP_TO_STATE(dip); 572 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 573 r_addr_t ra; 574 size_t msiq_size; 575 uint_t rec_cnt; 576 int i, err = DDI_SUCCESS; 577 uint64_t ret; 578 579 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 580 581 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 582 583 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 584 ra = (r_addr_t)va_to_pa((caddr_t)msiq_state_p->msiq_buf_p + 585 (i * msiq_size)); 586 587 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 588 (i + msiq_state_p->msiq_1st_msiq_id), 589 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 590 DBG(DBG_LIB_MSIQ, dip, 591 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 592 err = DDI_FAILURE; 593 break; 594 } 595 596 if ((err = px_lib_msiq_info(dip, 597 (i + msiq_state_p->msiq_1st_msiq_id), 598 &ra, &rec_cnt)) != DDI_SUCCESS) { 599 DBG(DBG_LIB_MSIQ, dip, 600 "px_lib_msiq_info failed, ret 0x%x\n", err); 601 err = DDI_FAILURE; 602 break; 603 } 604 605 DBG(DBG_LIB_MSIQ, dip, 606 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 607 } 608 609 return (err); 610 } 611 612 /*ARGSUSED*/ 613 int 614 px_lib_msiq_fini(dev_info_t *dip) 615 { 616 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 617 618 return (DDI_SUCCESS); 619 } 620 621 /*ARGSUSED*/ 622 int 623 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 624 uint_t *msiq_rec_cnt_p) 625 { 626 uint64_t ret; 627 628 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 629 dip, msiq_id); 630 631 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 632 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 633 DBG(DBG_LIB_MSIQ, dip, 634 "hvio_msiq_info failed, ret 0x%lx\n", ret); 635 return (DDI_FAILURE); 636 } 637 638 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 639 ra_p, *msiq_rec_cnt_p); 640 641 return (DDI_SUCCESS); 642 } 643 644 /*ARGSUSED*/ 645 int 646 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 647 pci_msiq_valid_state_t *msiq_valid_state) 648 { 649 uint64_t ret; 650 651 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 652 dip, msiq_id); 653 654 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 655 msiq_id, msiq_valid_state)) != H_EOK) { 656 DBG(DBG_LIB_MSIQ, dip, 657 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 658 return (DDI_FAILURE); 659 } 660 661 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 662 *msiq_valid_state); 663 664 return (DDI_SUCCESS); 665 } 666 667 /*ARGSUSED*/ 668 int 669 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 670 pci_msiq_valid_state_t msiq_valid_state) 671 { 672 uint64_t ret; 673 674 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 675 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 676 677 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 678 msiq_id, msiq_valid_state)) != H_EOK) { 679 DBG(DBG_LIB_MSIQ, dip, 680 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 681 return (DDI_FAILURE); 682 } 683 684 return (DDI_SUCCESS); 685 } 686 687 /*ARGSUSED*/ 688 int 689 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 690 pci_msiq_state_t *msiq_state) 691 { 692 uint64_t ret; 693 694 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 695 dip, msiq_id); 696 697 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 698 msiq_id, msiq_state)) != H_EOK) { 699 DBG(DBG_LIB_MSIQ, dip, 700 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 701 return (DDI_FAILURE); 702 } 703 704 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 705 *msiq_state); 706 707 return (DDI_SUCCESS); 708 } 709 710 /*ARGSUSED*/ 711 int 712 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 713 pci_msiq_state_t msiq_state) 714 { 715 uint64_t ret; 716 717 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 718 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 719 720 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 721 msiq_id, msiq_state)) != H_EOK) { 722 DBG(DBG_LIB_MSIQ, dip, 723 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 724 return (DDI_FAILURE); 725 } 726 727 return (DDI_SUCCESS); 728 } 729 730 /*ARGSUSED*/ 731 int 732 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 733 msiqhead_t *msiq_head_p) 734 { 735 uint64_t ret; 736 737 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 738 dip, msiq_id); 739 740 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 741 msiq_id, msiq_head_p)) != H_EOK) { 742 DBG(DBG_LIB_MSIQ, dip, 743 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 744 return (DDI_FAILURE); 745 } 746 747 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 748 749 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 750 *msiq_head_p); 751 752 return (DDI_SUCCESS); 753 } 754 755 /*ARGSUSED*/ 756 int 757 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 758 msiqhead_t msiq_head) 759 { 760 uint64_t ret; 761 762 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 763 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 764 765 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 766 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 767 DBG(DBG_LIB_MSIQ, dip, 768 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 769 return (DDI_FAILURE); 770 } 771 772 return (DDI_SUCCESS); 773 } 774 775 /*ARGSUSED*/ 776 int 777 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 778 msiqtail_t *msiq_tail_p) 779 { 780 uint64_t ret; 781 782 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 783 dip, msiq_id); 784 785 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 786 msiq_id, msiq_tail_p)) != H_EOK) { 787 DBG(DBG_LIB_MSIQ, dip, 788 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 789 return (DDI_FAILURE); 790 } 791 792 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 793 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 794 *msiq_tail_p); 795 796 return (DDI_SUCCESS); 797 } 798 799 /*ARGSUSED*/ 800 void 801 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 802 msiq_rec_t *msiq_rec_p) 803 { 804 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 805 806 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 807 808 if (!curr_msiq_rec_p->msiq_rec_type) { 809 /* Set msiq_rec_type to zero */ 810 msiq_rec_p->msiq_rec_type = 0; 811 812 return; 813 } 814 815 *msiq_rec_p = *curr_msiq_rec_p; 816 } 817 818 /*ARGSUSED*/ 819 void 820 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 821 { 822 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_head_p; 823 824 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p\n", dip); 825 826 /* Zero out msiq_rec_type field */ 827 curr_msiq_rec_p->msiq_rec_type = 0; 828 } 829 830 /* 831 * MSI Functions: 832 */ 833 834 /*ARGSUSED*/ 835 int 836 px_lib_msi_init(dev_info_t *dip) 837 { 838 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 839 840 /* Noop */ 841 return (DDI_SUCCESS); 842 } 843 844 /*ARGSUSED*/ 845 int 846 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 847 msiqid_t *msiq_id) 848 { 849 uint64_t ret; 850 851 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 852 dip, msi_num); 853 854 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 855 msi_num, msiq_id)) != H_EOK) { 856 DBG(DBG_LIB_MSI, dip, 857 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 858 return (DDI_FAILURE); 859 } 860 861 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 862 *msiq_id); 863 864 return (DDI_SUCCESS); 865 } 866 867 /*ARGSUSED*/ 868 int 869 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 870 msiqid_t msiq_id, msi_type_t msitype) 871 { 872 uint64_t ret; 873 874 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 875 "msq_id 0x%x\n", dip, msi_num, msiq_id); 876 877 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 878 msi_num, msiq_id, msitype)) != H_EOK) { 879 DBG(DBG_LIB_MSI, dip, 880 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 881 return (DDI_FAILURE); 882 } 883 884 return (DDI_SUCCESS); 885 } 886 887 /*ARGSUSED*/ 888 int 889 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 890 pci_msi_valid_state_t *msi_valid_state) 891 { 892 uint64_t ret; 893 894 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 895 dip, msi_num); 896 897 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 898 msi_num, msi_valid_state)) != H_EOK) { 899 DBG(DBG_LIB_MSI, dip, 900 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 901 return (DDI_FAILURE); 902 } 903 904 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 905 *msi_valid_state); 906 907 return (DDI_SUCCESS); 908 } 909 910 /*ARGSUSED*/ 911 int 912 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 913 pci_msi_valid_state_t msi_valid_state) 914 { 915 uint64_t ret; 916 917 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 918 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 919 920 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 921 msi_num, msi_valid_state)) != H_EOK) { 922 DBG(DBG_LIB_MSI, dip, 923 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 924 return (DDI_FAILURE); 925 } 926 927 return (DDI_SUCCESS); 928 } 929 930 /*ARGSUSED*/ 931 int 932 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 933 pci_msi_state_t *msi_state) 934 { 935 uint64_t ret; 936 937 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 938 dip, msi_num); 939 940 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 941 msi_num, msi_state)) != H_EOK) { 942 DBG(DBG_LIB_MSI, dip, 943 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 944 return (DDI_FAILURE); 945 } 946 947 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 948 *msi_state); 949 950 return (DDI_SUCCESS); 951 } 952 953 /*ARGSUSED*/ 954 int 955 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 956 pci_msi_state_t msi_state) 957 { 958 uint64_t ret; 959 960 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 961 "msi_state 0x%x\n", dip, msi_num, msi_state); 962 963 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 964 msi_num, msi_state)) != H_EOK) { 965 DBG(DBG_LIB_MSI, dip, 966 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 967 return (DDI_FAILURE); 968 } 969 970 return (DDI_SUCCESS); 971 } 972 973 /* 974 * MSG Functions: 975 */ 976 977 /*ARGSUSED*/ 978 int 979 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 980 msiqid_t *msiq_id) 981 { 982 uint64_t ret; 983 984 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 985 dip, msg_type); 986 987 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 988 msg_type, msiq_id)) != H_EOK) { 989 DBG(DBG_LIB_MSG, dip, 990 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 991 return (DDI_FAILURE); 992 } 993 994 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 995 *msiq_id); 996 997 return (DDI_SUCCESS); 998 } 999 1000 /*ARGSUSED*/ 1001 int 1002 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1003 msiqid_t msiq_id) 1004 { 1005 uint64_t ret; 1006 1007 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 1008 "msq_id 0x%x\n", dip, msg_type, msiq_id); 1009 1010 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1011 msg_type, msiq_id)) != H_EOK) { 1012 DBG(DBG_LIB_MSG, dip, 1013 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1014 return (DDI_FAILURE); 1015 } 1016 1017 return (DDI_SUCCESS); 1018 } 1019 1020 /*ARGSUSED*/ 1021 int 1022 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1023 pcie_msg_valid_state_t *msg_valid_state) 1024 { 1025 uint64_t ret; 1026 1027 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1028 dip, msg_type); 1029 1030 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1031 msg_valid_state)) != H_EOK) { 1032 DBG(DBG_LIB_MSG, dip, 1033 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1034 return (DDI_FAILURE); 1035 } 1036 1037 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1038 *msg_valid_state); 1039 1040 return (DDI_SUCCESS); 1041 } 1042 1043 /*ARGSUSED*/ 1044 int 1045 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1046 pcie_msg_valid_state_t msg_valid_state) 1047 { 1048 uint64_t ret; 1049 1050 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1051 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1052 1053 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1054 msg_valid_state)) != H_EOK) { 1055 DBG(DBG_LIB_MSG, dip, 1056 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1057 return (DDI_FAILURE); 1058 } 1059 1060 return (DDI_SUCCESS); 1061 } 1062 1063 /* 1064 * Suspend/Resume Functions: 1065 * Currently unsupported by hypervisor and all functions are noops. 1066 */ 1067 /*ARGSUSED*/ 1068 int 1069 px_lib_suspend(dev_info_t *dip) 1070 { 1071 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1072 1073 /* Not supported */ 1074 return (DDI_FAILURE); 1075 } 1076 1077 /*ARGSUSED*/ 1078 void 1079 px_lib_resume(dev_info_t *dip) 1080 { 1081 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1082 1083 /* Noop */ 1084 } 1085 1086 /* 1087 * Misc Functions: 1088 * Currently unsupported by hypervisor and all functions are noops. 1089 */ 1090 /*ARGSUSED*/ 1091 static int 1092 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1093 uint8_t size, pci_cfg_data_t *data_p) 1094 { 1095 uint64_t ret; 1096 1097 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1098 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1099 1100 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1101 size, data_p)) != H_EOK) { 1102 DBG(DBG_LIB_CFG, dip, 1103 "hvio_config_get failed, ret 0x%lx\n", ret); 1104 return (DDI_FAILURE); 1105 } 1106 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1107 1108 return (DDI_SUCCESS); 1109 } 1110 1111 /*ARGSUSED*/ 1112 static int 1113 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1114 uint8_t size, pci_cfg_data_t data) 1115 { 1116 uint64_t ret; 1117 1118 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1119 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1120 1121 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1122 size, data)) != H_EOK) { 1123 DBG(DBG_LIB_CFG, dip, 1124 "hvio_config_put failed, ret 0x%lx\n", ret); 1125 return (DDI_FAILURE); 1126 } 1127 1128 return (DDI_SUCCESS); 1129 } 1130 1131 static uint32_t 1132 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1133 { 1134 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1135 handle->ahi_common.ah_bus_private; 1136 uint32_t pci_dev_addr = px_pvt->raddr; 1137 uint32_t vaddr = px_pvt->vaddr; 1138 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1139 uint32_t rdata = 0; 1140 1141 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1142 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1143 /* XXX update error kstats */ 1144 return (0xffffffff); 1145 return (rdata); 1146 } 1147 1148 static void 1149 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1150 int size, pci_cfg_data_t wdata) 1151 { 1152 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1153 handle->ahi_common.ah_bus_private; 1154 uint32_t pci_dev_addr = px_pvt->raddr; 1155 uint32_t vaddr = px_pvt->vaddr; 1156 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1157 1158 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1159 size, wdata) != DDI_SUCCESS) { 1160 /*EMPTY*/ 1161 /* XXX update error kstats */ 1162 } 1163 } 1164 1165 static uint8_t 1166 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1167 { 1168 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1169 } 1170 1171 static uint16_t 1172 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1173 { 1174 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1175 } 1176 1177 static uint32_t 1178 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1179 { 1180 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1181 } 1182 1183 static uint64_t 1184 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1185 { 1186 uint32_t rdatah, rdatal; 1187 1188 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1189 rdatah = (uint32_t)px_pci_config_get(handle, 1190 (uint32_t *)((char *)addr+4), 4); 1191 return (((uint64_t)rdatah << 32) | rdatal); 1192 } 1193 1194 static void 1195 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1196 { 1197 pci_cfg_data_t wdata = { 0 }; 1198 1199 wdata.qw = (uint8_t)data; 1200 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1201 } 1202 1203 static void 1204 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1205 { 1206 pci_cfg_data_t wdata = { 0 }; 1207 1208 wdata.qw = (uint16_t)data; 1209 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1210 } 1211 1212 static void 1213 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1214 { 1215 pci_cfg_data_t wdata = { 0 }; 1216 1217 wdata.qw = (uint32_t)data; 1218 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1219 } 1220 1221 static void 1222 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1223 { 1224 pci_cfg_data_t wdata = { 0 }; 1225 1226 wdata.qw = (uint32_t)(data & 0xffffffff); 1227 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1228 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1229 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1230 } 1231 1232 static void 1233 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1234 uint8_t *dev_addr, size_t repcount, uint_t flags) 1235 { 1236 if (flags == DDI_DEV_AUTOINCR) 1237 for (; repcount; repcount--) 1238 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1239 else 1240 for (; repcount; repcount--) 1241 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1242 } 1243 1244 /* 1245 * Function to rep read 16 bit data off the PCI configuration space behind 1246 * the 21554's host interface. 1247 */ 1248 static void 1249 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1250 uint16_t *dev_addr, size_t repcount, uint_t flags) 1251 { 1252 if (flags == DDI_DEV_AUTOINCR) 1253 for (; repcount; repcount--) 1254 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1255 else 1256 for (; repcount; repcount--) 1257 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1258 } 1259 1260 /* 1261 * Function to rep read 32 bit data off the PCI configuration space behind 1262 * the 21554's host interface. 1263 */ 1264 static void 1265 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1266 uint32_t *dev_addr, size_t repcount, uint_t flags) 1267 { 1268 if (flags == DDI_DEV_AUTOINCR) 1269 for (; repcount; repcount--) 1270 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1271 else 1272 for (; repcount; repcount--) 1273 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1274 } 1275 1276 /* 1277 * Function to rep read 64 bit data off the PCI configuration space behind 1278 * the 21554's host interface. 1279 */ 1280 static void 1281 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1282 uint64_t *dev_addr, size_t repcount, uint_t flags) 1283 { 1284 if (flags == DDI_DEV_AUTOINCR) 1285 for (; repcount; repcount--) 1286 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1287 else 1288 for (; repcount; repcount--) 1289 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1290 } 1291 1292 /* 1293 * Function to rep write 8 bit data into the PCI configuration space behind 1294 * the 21554's host interface. 1295 */ 1296 static void 1297 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1298 uint8_t *dev_addr, size_t repcount, uint_t flags) 1299 { 1300 if (flags == DDI_DEV_AUTOINCR) 1301 for (; repcount; repcount--) 1302 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1303 else 1304 for (; repcount; repcount--) 1305 px_pci_config_put8(handle, dev_addr, *host_addr++); 1306 } 1307 1308 /* 1309 * Function to rep write 16 bit data into the PCI configuration space behind 1310 * the 21554's host interface. 1311 */ 1312 static void 1313 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1314 uint16_t *dev_addr, size_t repcount, uint_t flags) 1315 { 1316 if (flags == DDI_DEV_AUTOINCR) 1317 for (; repcount; repcount--) 1318 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1319 else 1320 for (; repcount; repcount--) 1321 px_pci_config_put16(handle, dev_addr, *host_addr++); 1322 } 1323 1324 /* 1325 * Function to rep write 32 bit data into the PCI configuration space behind 1326 * the 21554's host interface. 1327 */ 1328 static void 1329 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1330 uint32_t *dev_addr, size_t repcount, uint_t flags) 1331 { 1332 if (flags == DDI_DEV_AUTOINCR) 1333 for (; repcount; repcount--) 1334 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1335 else 1336 for (; repcount; repcount--) 1337 px_pci_config_put32(handle, dev_addr, *host_addr++); 1338 } 1339 1340 /* 1341 * Function to rep write 64 bit data into the PCI configuration space behind 1342 * the 21554's host interface. 1343 */ 1344 static void 1345 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1346 uint64_t *dev_addr, size_t repcount, uint_t flags) 1347 { 1348 if (flags == DDI_DEV_AUTOINCR) 1349 for (; repcount; repcount--) 1350 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1351 else 1352 for (; repcount; repcount--) 1353 px_pci_config_put64(handle, dev_addr, *host_addr++); 1354 } 1355 1356 /* 1357 * Provide a private access handle to route config access calls to Hypervisor. 1358 * Beware: Do all error checking for config space accesses before calling 1359 * this function. ie. do error checking from the calling function. 1360 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1361 * DDI_SUCCESS from here makes the code organization readable/easier from 1362 * the generic code. 1363 */ 1364 /*ARGSUSED*/ 1365 int 1366 px_lib_map_vconfig(dev_info_t *dip, 1367 ddi_map_req_t *mp, pci_config_offset_t off, 1368 pci_regspec_t *rp, caddr_t *addrp) 1369 { 1370 ddi_acc_hdl_t *hp; 1371 ddi_acc_impl_t *ap; 1372 uchar_t busnum; /* bus number */ 1373 uchar_t devnum; /* device number */ 1374 uchar_t funcnum; /* function number */ 1375 px_config_acc_pvt_t *px_pvt; 1376 1377 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1378 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1379 1380 /* Check for mapping teardown operation */ 1381 if ((mp->map_op == DDI_MO_UNMAP) || 1382 (mp->map_op == DDI_MO_UNLOCK)) { 1383 /* free up memory allocated for the private access handle. */ 1384 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1385 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1386 1387 /* unmap operation of PCI IO/config space. */ 1388 return (DDI_SUCCESS); 1389 } 1390 1391 ap->ahi_get8 = px_pci_config_get8; 1392 ap->ahi_get16 = px_pci_config_get16; 1393 ap->ahi_get32 = px_pci_config_get32; 1394 ap->ahi_get64 = px_pci_config_get64; 1395 ap->ahi_put8 = px_pci_config_put8; 1396 ap->ahi_put16 = px_pci_config_put16; 1397 ap->ahi_put32 = px_pci_config_put32; 1398 ap->ahi_put64 = px_pci_config_put64; 1399 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1400 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1401 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1402 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1403 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1404 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1405 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1406 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1407 1408 /* Initialize to default check/notify functions */ 1409 ap->ahi_fault = 0; 1410 ap->ahi_fault_check = i_ddi_acc_fault_check; 1411 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1412 1413 /* allocate memory for our private handle */ 1414 px_pvt = (px_config_acc_pvt_t *) 1415 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1416 hp->ah_bus_private = (void *)px_pvt; 1417 1418 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1419 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1420 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1421 1422 /* set up private data for use during IO routines */ 1423 1424 /* addr needed by the HV APIs */ 1425 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1426 /* 1427 * Address that specifies the actual offset into the 256MB 1428 * memory mapped configuration space, 4K per device. 1429 * First 12bits form the offset into 4K config space. 1430 * This address is only used during the IO routines to calculate 1431 * the offset at which the transaction must be performed. 1432 * Drivers bypassing DDI functions to access PCI config space will 1433 * panic the system since the following is a bogus virtual address. 1434 */ 1435 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1436 px_pvt->dip = dip; 1437 1438 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1439 px_pvt->raddr, px_pvt->vaddr); 1440 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1441 return (DDI_SUCCESS); 1442 } 1443 1444 /*ARGSUSED*/ 1445 void 1446 px_lib_map_attr_check(ddi_map_req_t *mp) 1447 { 1448 } 1449 1450 /* 1451 * px_lib_log_safeacc_err: 1452 * Imitate a cpu/mem trap call when a peek/poke fails. 1453 * This will initiate something similar to px_fm_callback. 1454 */ 1455 static void 1456 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag, 1457 r_addr_t addr) 1458 { 1459 uint32_t addr_high, addr_low; 1460 pcie_req_id_t bdf; 1461 px_ranges_t *ranges_p; 1462 int range_len, i; 1463 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1464 ddi_fm_error_t derr; 1465 1466 derr.fme_status = DDI_FM_NONFATAL; 1467 derr.fme_version = DDI_FME_VERSION; 1468 derr.fme_flag = fme_flag; 1469 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1470 derr.fme_acc_handle = handle; 1471 if (hp) 1472 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1473 1474 addr_high = (uint32_t)(addr >> 32); 1475 addr_low = (uint32_t)addr; 1476 1477 /* 1478 * Make sure this failed load came from this PCIe port. Check by 1479 * matching the upper 32 bits of the address with the ranges property. 1480 */ 1481 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 1482 i = 0; 1483 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 1484 if (ranges_p->parent_high == addr_high) { 1485 switch (ranges_p->child_high & PCI_ADDR_MASK) { 1486 case PCI_ADDR_CONFIG: 1487 bdf = (pcie_req_id_t)(addr_low >> 12); 1488 break; 1489 default: 1490 bdf = NULL; 1491 break; 1492 } 1493 break; 1494 } 1495 } 1496 1497 mutex_enter(&px_p->px_fm_mutex); 1498 1499 if (!px_lib_is_in_drain_state(px_p)) { 1500 /* 1501 * This is to ensure that device corresponding to the addr of 1502 * the failed PIO/CFG load gets scanned. 1503 */ 1504 px_rp_en_q(px_p, bdf, addr, 1505 (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)); 1506 (void) pf_scan_fabric(px_p->px_dip, &derr, 1507 px_p->px_dq_p, &px_p->px_dq_tail); 1508 } 1509 1510 mutex_exit(&px_p->px_fm_mutex); 1511 } 1512 1513 1514 #ifdef DEBUG 1515 int px_peekfault_cnt = 0; 1516 int px_pokefault_cnt = 0; 1517 #endif /* DEBUG */ 1518 1519 /* 1520 * Do a safe write to a device. 1521 * 1522 * When this function is given a handle (cautious access), all errors are 1523 * suppressed. 1524 * 1525 * When this function is not given a handle (poke), only Unsupported Request 1526 * and Completer Abort errors are suppressed. 1527 * 1528 * In all cases, all errors are returned in the function return status. 1529 */ 1530 1531 int 1532 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1533 peekpoke_ctlops_t *in_args) 1534 { 1535 px_t *px_p = DIP_TO_STATE(dip); 1536 px_pec_t *pec_p = px_p->px_pec_p; 1537 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1538 1539 size_t repcount = in_args->repcount; 1540 size_t size = in_args->size; 1541 uintptr_t dev_addr = in_args->dev_addr; 1542 uintptr_t host_addr = in_args->host_addr; 1543 1544 int err = DDI_SUCCESS; 1545 uint64_t hvio_poke_status; 1546 uint32_t wrt_stat; 1547 1548 r_addr_t ra; 1549 uint64_t pokeval; 1550 pcie_req_id_t bdf; 1551 1552 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1553 for (; repcount; repcount--) { 1554 1555 switch (size) { 1556 case sizeof (uint8_t): 1557 pokeval = *(uint8_t *)host_addr; 1558 break; 1559 case sizeof (uint16_t): 1560 pokeval = *(uint16_t *)host_addr; 1561 break; 1562 case sizeof (uint32_t): 1563 pokeval = *(uint32_t *)host_addr; 1564 break; 1565 case sizeof (uint64_t): 1566 pokeval = *(uint64_t *)host_addr; 1567 break; 1568 default: 1569 DBG(DBG_MAP, px_p->px_dip, 1570 "poke: invalid size %d passed\n", size); 1571 err = DDI_FAILURE; 1572 goto done; 1573 } 1574 1575 /* 1576 * Grab pokefault mutex since hypervisor does not guarantee 1577 * poke serialization. 1578 */ 1579 if (hp) { 1580 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1581 (ddi_acc_handle_t)hp); 1582 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1583 } else { 1584 mutex_enter(&pec_p->pec_pokefault_mutex); 1585 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1586 } 1587 1588 if (pcie_get_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1589 err = DDI_FAILURE; 1590 goto done; 1591 } 1592 1593 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1594 pokeval, bdf << 8, &wrt_stat); 1595 1596 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1597 err = DDI_FAILURE; 1598 #ifdef DEBUG 1599 px_pokefault_cnt++; 1600 #endif 1601 /* 1602 * For CAUTIOUS and POKE access, notify FMA to 1603 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1604 */ 1605 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1606 (hp ? DDI_FM_ERR_EXPECTED : 1607 DDI_FM_ERR_POKE), ra); 1608 1609 pec_p->pec_ontrap_data = NULL; 1610 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1611 if (hp) { 1612 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1613 (ddi_acc_handle_t)hp); 1614 } else { 1615 mutex_exit(&pec_p->pec_pokefault_mutex); 1616 } 1617 goto done; 1618 } 1619 1620 pec_p->pec_ontrap_data = NULL; 1621 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1622 if (hp) { 1623 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1624 (ddi_acc_handle_t)hp); 1625 } else { 1626 mutex_exit(&pec_p->pec_pokefault_mutex); 1627 } 1628 1629 host_addr += size; 1630 1631 if (in_args->flags == DDI_DEV_AUTOINCR) { 1632 dev_addr += size; 1633 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1634 } 1635 } 1636 1637 done: 1638 return (err); 1639 } 1640 1641 1642 /*ARGSUSED*/ 1643 int 1644 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1645 peekpoke_ctlops_t *in_args, void *result) 1646 { 1647 px_t *px_p = DIP_TO_STATE(dip); 1648 px_pec_t *pec_p = px_p->px_pec_p; 1649 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1650 1651 size_t repcount = in_args->repcount; 1652 uintptr_t dev_addr = in_args->dev_addr; 1653 uintptr_t host_addr = in_args->host_addr; 1654 1655 r_addr_t ra; 1656 uint32_t read_status; 1657 uint64_t hvio_peek_status; 1658 uint64_t peekval; 1659 int err = DDI_SUCCESS; 1660 1661 result = (void *)in_args->host_addr; 1662 1663 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1664 for (; repcount; repcount--) { 1665 1666 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1667 if (hp) { 1668 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1669 (ddi_acc_handle_t)hp); 1670 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1671 } else { 1672 mutex_enter(&pec_p->pec_pokefault_mutex); 1673 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1674 } 1675 1676 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1677 in_args->size, &read_status, &peekval); 1678 1679 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1680 err = DDI_FAILURE; 1681 1682 /* 1683 * For CAUTIOUS and PEEK access, notify FMA to 1684 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1685 */ 1686 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1687 (hp ? DDI_FM_ERR_EXPECTED : 1688 DDI_FM_ERR_PEEK), ra); 1689 1690 /* Stuff FFs in host addr if peek. */ 1691 if (hp == NULL) { 1692 int i; 1693 uint8_t *ff_addr = (uint8_t *)host_addr; 1694 for (i = 0; i < in_args->size; i++) 1695 *ff_addr++ = 0xff; 1696 } 1697 #ifdef DEBUG 1698 px_peekfault_cnt++; 1699 #endif 1700 pec_p->pec_ontrap_data = NULL; 1701 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1702 if (hp) { 1703 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1704 (ddi_acc_handle_t)hp); 1705 } else { 1706 mutex_exit(&pec_p->pec_pokefault_mutex); 1707 } 1708 goto done; 1709 1710 } 1711 pec_p->pec_ontrap_data = NULL; 1712 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1713 if (hp) { 1714 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1715 (ddi_acc_handle_t)hp); 1716 } else { 1717 mutex_exit(&pec_p->pec_pokefault_mutex); 1718 } 1719 1720 switch (in_args->size) { 1721 case sizeof (uint8_t): 1722 *(uint8_t *)host_addr = (uint8_t)peekval; 1723 break; 1724 case sizeof (uint16_t): 1725 *(uint16_t *)host_addr = (uint16_t)peekval; 1726 break; 1727 case sizeof (uint32_t): 1728 *(uint32_t *)host_addr = (uint32_t)peekval; 1729 break; 1730 case sizeof (uint64_t): 1731 *(uint64_t *)host_addr = (uint64_t)peekval; 1732 break; 1733 default: 1734 DBG(DBG_MAP, px_p->px_dip, 1735 "peek: invalid size %d passed\n", 1736 in_args->size); 1737 err = DDI_FAILURE; 1738 goto done; 1739 } 1740 1741 host_addr += in_args->size; 1742 1743 if (in_args->flags == DDI_DEV_AUTOINCR) { 1744 dev_addr += in_args->size; 1745 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1746 } 1747 } 1748 done: 1749 return (err); 1750 } 1751 1752 1753 /* add interrupt vector */ 1754 int 1755 px_err_add_intr(px_fault_t *px_fault_p) 1756 { 1757 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1758 1759 DBG(DBG_LIB_INT, px_p->px_dip, 1760 "px_err_add_intr: calling add_ivintr"); 1761 1762 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1763 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, NULL, 1764 (caddr_t)&px_fault_p->px_intr_payload[0]) == 0); 1765 1766 DBG(DBG_LIB_INT, px_p->px_dip, 1767 "px_err_add_intr: ib_intr_enable "); 1768 1769 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1770 1771 return (DDI_SUCCESS); 1772 } 1773 1774 /* remove interrupt vector */ 1775 void 1776 px_err_rem_intr(px_fault_t *px_fault_p) 1777 { 1778 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1779 1780 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1781 IB_INTR_WAIT); 1782 1783 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 1784 } 1785 1786 void 1787 px_cb_intr_redist(void *arg) 1788 { 1789 px_t *px_p = (px_t *)arg; 1790 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1791 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1792 } 1793 1794 int 1795 px_cb_add_intr(px_fault_t *f_p) 1796 { 1797 px_t *px_p = DIP_TO_STATE(f_p->px_fh_dip); 1798 1799 DBG(DBG_LIB_INT, px_p->px_dip, 1800 "px_err_add_intr: calling add_ivintr"); 1801 1802 VERIFY(add_ivintr(f_p->px_fh_sysino, PX_ERR_PIL, 1803 (intrfunc)f_p->px_err_func, (caddr_t)f_p, NULL, 1804 (caddr_t)&f_p->px_intr_payload[0]) == 0); 1805 1806 intr_dist_add(px_cb_intr_redist, px_p); 1807 1808 DBG(DBG_LIB_INT, px_p->px_dip, 1809 "px_err_add_intr: ib_intr_enable "); 1810 1811 px_ib_intr_enable(px_p, intr_dist_cpuid(), f_p->px_intr_ino); 1812 1813 return (DDI_SUCCESS); 1814 } 1815 1816 void 1817 px_cb_rem_intr(px_fault_t *f_p) 1818 { 1819 intr_dist_rem(px_cb_intr_redist, DIP_TO_STATE(f_p->px_fh_dip)); 1820 px_err_rem_intr(f_p); 1821 } 1822 1823 #ifdef FMA 1824 void 1825 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1826 { 1827 px_pec_err_t *err_pkt; 1828 1829 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1830 1831 /* initialise all the structure members */ 1832 rc_status->status_valid = 0; 1833 1834 if (err_pkt->pec_descr.P) { 1835 /* PCI Status Register */ 1836 rc_status->pci_err_status = err_pkt->pci_err_status; 1837 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1838 } 1839 1840 if (err_pkt->pec_descr.E) { 1841 /* PCIe Status Register */ 1842 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1843 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1844 } 1845 1846 if (err_pkt->pec_descr.U) { 1847 rc_status->ue_status = err_pkt->ue_reg_status; 1848 rc_status->status_valid |= UE_STATUS_VALID; 1849 } 1850 1851 if (err_pkt->pec_descr.H) { 1852 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1853 rc_status->status_valid |= UE_HDR1_VALID; 1854 } 1855 1856 if (err_pkt->pec_descr.I) { 1857 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1858 rc_status->status_valid |= UE_HDR2_VALID; 1859 } 1860 1861 /* ue_fst_err_ptr - not available for sun4v?? */ 1862 1863 1864 if (err_pkt->pec_descr.S) { 1865 rc_status->source_id = err_pkt->err_src_reg; 1866 rc_status->status_valid |= SOURCE_ID_VALID; 1867 } 1868 1869 if (err_pkt->pec_descr.R) { 1870 rc_status->root_err_status = err_pkt->root_err_status; 1871 rc_status->status_valid |= CE_STATUS_VALID; 1872 } 1873 } 1874 #endif 1875 1876 /*ARGSUSED*/ 1877 int 1878 px_lib_pmctl(int cmd, px_t *px_p) 1879 { 1880 return (DDI_FAILURE); 1881 } 1882 1883 /*ARGSUSED*/ 1884 uint_t 1885 px_pmeq_intr(caddr_t arg) 1886 { 1887 return (DDI_INTR_CLAIMED); 1888 } 1889 1890 /* 1891 * Unprotected raw reads/writes of fabric device's config space. 1892 * Only used for temporary PCI-E Fabric Error Handling. 1893 */ 1894 uint32_t 1895 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1896 uint32_t data = 0; 1897 1898 (void) hvio_config_get(px_p->px_dev_hdl, 1899 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1900 (pci_cfg_data_t *)&data); 1901 1902 return (data); 1903 } 1904 1905 void 1906 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1907 uint32_t val) { 1908 pci_cfg_data_t wdata = { 0 }; 1909 1910 wdata.qw = (uint32_t)val; 1911 (void) hvio_config_put(px_p->px_dev_hdl, 1912 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1913 } 1914 1915 /*ARGSUSED*/ 1916 int 1917 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1918 { 1919 return (DDI_ENOTSUP); 1920 } 1921 1922 /*ARGSUSED*/ 1923 void 1924 px_lib_hotplug_uninit(dev_info_t *dip) 1925 { 1926 } 1927 1928 /*ARGSUSED*/ 1929 void 1930 px_hp_intr_redist(px_t *px_p) 1931 { 1932 } 1933 1934 /* Dummy cpr add callback */ 1935 /*ARGSUSED*/ 1936 void 1937 px_cpr_add_callb(px_t *px_p) 1938 { 1939 } 1940 1941 /* Dummy cpr rem callback */ 1942 /*ARGSUSED*/ 1943 void 1944 px_cpr_rem_callb(px_t *px_p) 1945 { 1946 } 1947 1948 /*ARGSUSED*/ 1949 boolean_t 1950 px_lib_is_in_drain_state(px_t *px_p) 1951 { 1952 return (B_FALSE); 1953 } 1954 1955 /* 1956 * There is no IOAPI to get the BDF of the pcie root port nexus at this moment. 1957 * Assume it is 0x0000, until otherwise noted. For now, all sun4v platforms 1958 * have programmed the BDF to be 0x0000. 1959 */ 1960 /*ARGSUSED*/ 1961 pcie_req_id_t 1962 px_lib_get_bdf(px_t *px_p) 1963 { 1964 return (0x0000); 1965 } 1966