1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <vm/vm_dep.h> 39 #include <sys/cpuvar.h> 40 #include <sys/async.h> 41 #include <sys/cmn_err.h> 42 #include <sys/debug.h> 43 #include <sys/dditypes.h> 44 #include <sys/sunddi.h> 45 #include <sys/cpu_module.h> 46 #include <sys/prom_debug.h> 47 #include <sys/vmsystm.h> 48 #include <sys/prom_plat.h> 49 #include <sys/sysmacros.h> 50 #include <sys/intreg.h> 51 #include <sys/machtrap.h> 52 #include <sys/ontrap.h> 53 #include <sys/ivintr.h> 54 #include <sys/atomic.h> 55 #include <sys/panic.h> 56 #include <sys/dtrace.h> 57 #include <sys/simulate.h> 58 #include <sys/fault.h> 59 #include <sys/niagara2regs.h> 60 #include <sys/hsvc.h> 61 #include <sys/trapstat.h> 62 63 uint_t root_phys_addr_lo_mask = 0xffffffffU; 64 #if defined(NIAGARA2_IMPL) 65 char cpu_module_name[] = "SUNW,UltraSPARC-T2"; 66 #elif defined(VFALLS_IMPL) 67 char cpu_module_name[] = "SUNW,UltraSPARC-T2+"; 68 #endif 69 70 /* 71 * Hypervisor services information for the NIAGARA2 and Victoria Falls 72 * CPU module 73 */ 74 static boolean_t cpu_hsvc_available = B_TRUE; 75 static uint64_t cpu_sup_minor; /* Supported minor number */ 76 #if defined(NIAGARA2_IMPL) 77 static hsvc_info_t cpu_hsvc = { 78 HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR, 79 NIAGARA2_HSVC_MINOR, cpu_module_name 80 }; 81 #elif defined(VFALLS_IMPL) 82 static hsvc_info_t cpu_hsvc = { 83 HSVC_REV_1, NULL, HSVC_GROUP_VFALLS_CPU, VFALLS_HSVC_MAJOR, 84 VFALLS_HSVC_MINOR, cpu_module_name 85 }; 86 #endif 87 88 void 89 cpu_setup(void) 90 { 91 extern int mmu_exported_pagesize_mask; 92 extern int cpc_has_overflow_intr; 93 extern size_t contig_mem_prealloc_base; 94 int status; 95 96 /* 97 * Negotiate the API version for Niagara2 specific hypervisor 98 * services. 99 */ 100 status = hsvc_register(&cpu_hsvc, &cpu_sup_minor); 101 if (status != 0) { 102 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 103 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d", 104 cpu_hsvc.hsvc_modname, cpu_hsvc.hsvc_group, 105 cpu_hsvc.hsvc_major, cpu_hsvc.hsvc_minor, status); 106 cpu_hsvc_available = B_FALSE; 107 } 108 109 /* 110 * The setup common to all CPU modules is done in cpu_setup_common 111 * routine. 112 */ 113 cpu_setup_common(NULL); 114 115 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 116 117 if ((mmu_exported_pagesize_mask & 118 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 119 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 120 cmn_err(CE_PANIC, "machine description" 121 " does not have required sun4v page sizes" 122 " 8K, 64K and 4M: MD mask is 0x%x", 123 mmu_exported_pagesize_mask); 124 125 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT; 126 127 /* 128 * Niagara2 supports a 48-bit subset of the full 64-bit virtual 129 * address space. Virtual addresses between 0x0000800000000000 130 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 131 * and must never be mapped. In addition, software must not use 132 * pages within 4GB of the VA hole as instruction pages to 133 * avoid problems with prefetching into the VA hole. 134 */ 135 hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 136 hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32)); 137 138 /* 139 * Niagara2 has a performance counter overflow interrupt 140 */ 141 cpc_has_overflow_intr = 1; 142 143 /* 144 * Enable 4M pages for OOB. 145 */ 146 max_uheap_lpsize = MMU_PAGESIZE4M; 147 max_ustack_lpsize = MMU_PAGESIZE4M; 148 max_privmap_lpsize = MMU_PAGESIZE4M; 149 150 contig_mem_prealloc_base = NIAGARA2_PREALLOC_BASE; 151 } 152 153 /* 154 * Set the magic constants of the implementation. 155 */ 156 void 157 cpu_fiximp(struct cpu_node *cpunode) 158 { 159 /* 160 * The Cache node is optional in MD. Therefore in case "Cache" 161 * node does not exists in MD, set the default L2 cache associativity, 162 * size, linesize. 163 */ 164 if (cpunode->ecache_size == 0) 165 cpunode->ecache_size = L2CACHE_SIZE; 166 if (cpunode->ecache_linesize == 0) 167 cpunode->ecache_linesize = L2CACHE_LINESIZE; 168 if (cpunode->ecache_associativity == 0) 169 cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY; 170 } 171 172 void 173 cpu_map_exec_units(struct cpu *cp) 174 { 175 ASSERT(MUTEX_HELD(&cpu_lock)); 176 177 /* 178 * The cpu_ipipe and cpu_fpu fields are initialized based on 179 * the execution unit sharing information from the MD. They 180 * default to the CPU id in the absence of such information. 181 */ 182 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 183 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 184 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 185 186 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 187 if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 188 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 189 190 /* 191 * Niagara 2 defines the core to be at the FPU level 192 */ 193 cp->cpu_m.cpu_core = cp->cpu_m.cpu_fpu; 194 195 /* 196 * The cpu_chip field is initialized based on the information 197 * in the MD and assume that all cpus within a chip 198 * share the same L2 cache. If no such info is available, we 199 * set the cpu to belong to the defacto chip 0. 200 */ 201 cp->cpu_m.cpu_mpipe = cpunodes[cp->cpu_id].l2_cache_mapping; 202 if (cp->cpu_m.cpu_mpipe == NO_L2_CACHE_MAPPING_FOUND) 203 cp->cpu_m.cpu_mpipe = CPU_L2_CACHEID_INVALID; 204 205 cp->cpu_m.cpu_chip = cpunodes[cp->cpu_id].l2_cache_mapping; 206 if (cp->cpu_m.cpu_chip == NO_L2_CACHE_MAPPING_FOUND) 207 cp->cpu_m.cpu_chip = CPU_CHIPID_INVALID; 208 } 209 210 static int cpucnt; 211 212 void 213 cpu_init_private(struct cpu *cp) 214 { 215 extern void niagara_kstat_init(void); 216 217 ASSERT(MUTEX_HELD(&cpu_lock)); 218 219 cpu_map_exec_units(cp); 220 221 if ((cpucnt++ == 0) && (cpu_hsvc_available == B_TRUE)) 222 (void) niagara_kstat_init(); 223 } 224 225 /*ARGSUSED*/ 226 void 227 cpu_uninit_private(struct cpu *cp) 228 { 229 extern void niagara_kstat_fini(void); 230 231 ASSERT(MUTEX_HELD(&cpu_lock)); 232 if ((--cpucnt == 0) && (cpu_hsvc_available == B_TRUE)) 233 (void) niagara_kstat_fini(); 234 } 235 236 /* 237 * On Niagara2, any flush will cause all preceding stores to be 238 * synchronized wrt the i$, regardless of address or ASI. In fact, 239 * the address is ignored, so we always flush address 0. 240 */ 241 /*ARGSUSED*/ 242 void 243 dtrace_flush_sec(uintptr_t addr) 244 { 245 doflush(0); 246 } 247 248 /* 249 * Trapstat support for Niagara2 processor 250 * The Niagara2 provides HWTW support for TSB lookup and with HWTW 251 * enabled no TSB hit information will be available. Therefore setting 252 * the time spent in TLB miss handler for TSB hits to 0. 253 */ 254 int 255 cpu_trapstat_conf(int cmd) 256 { 257 int status = 0; 258 259 switch (cmd) { 260 case CPU_TSTATCONF_INIT: 261 case CPU_TSTATCONF_FINI: 262 case CPU_TSTATCONF_ENABLE: 263 case CPU_TSTATCONF_DISABLE: 264 break; 265 default: 266 status = EINVAL; 267 break; 268 } 269 return (status); 270 } 271 272 void 273 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 274 { 275 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 276 int i; 277 278 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 279 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0; 280 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0; 281 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0; 282 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0; 283 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 284 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 285 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 286 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 287 } 288 } 289 290 /* 291 * Page coloring support for hashed cache index mode 292 */ 293 294 /* 295 * Node id bits from machine description (MD). Node id distinguishes 296 * local versus remote memory. Because of MPO, page allocation does 297 * not cross node boundaries. Therefore, remove the node id bits from 298 * the color, since they are fixed. Either bit 30, or 31:30 in 299 * Victoria Falls processors. 300 * The number of node id bits is always 0 in Niagara2. 301 */ 302 typedef struct n2color { 303 uchar_t nnbits; /* number of node id bits */ 304 uchar_t nnmask; /* mask for node id bits */ 305 uchar_t lomask; /* mask for bits below node id */ 306 uchar_t lobits; /* number of bits below node id */ 307 } n2color_t; 308 309 n2color_t n2color[MMU_PAGE_SIZES]; 310 static uchar_t nhbits[] = {7, 7, 6, 5, 5, 5}; 311 312 /* 313 * Remove node id bits from color bits 32:28. 314 * This will reduce the number of colors. 315 * No change if number of node bits is zero. 316 */ 317 static inline uint_t 318 n2_hash2color(uint_t color, uchar_t szc) 319 { 320 n2color_t m = n2color[szc]; 321 322 if (m.nnbits > 0) { 323 color = ((color >> m.nnbits) & ~m.lomask) | (color & m.lomask); 324 ASSERT((color & ~(hw_page_array[szc].hp_colors - 1)) == 0); 325 } 326 327 return (color); 328 } 329 330 /* 331 * Restore node id bits into page color. 332 * This will increase the number of colors to match N2. 333 * No change if number of node bits is zero. 334 */ 335 static inline uint_t 336 n2_color2hash(uint_t color, uchar_t szc, uint_t node) 337 { 338 n2color_t m = n2color[szc]; 339 340 if (m.nnbits > 0) { 341 color = ((color & ~m.lomask) << m.nnbits) | (color & m.lomask); 342 color |= (node & m.nnmask) << m.lobits; 343 } 344 345 return (color); 346 } 347 348 /* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */ 349 350 /* 351 * iterator NULL means pfn is VA, do not adjust ra_to_pa 352 * iterator (-1) means pfn is RA, need to convert to PA 353 * iterator non-null means pfn is RA, use ra_to_pa 354 */ 355 uint_t 356 page_pfn_2_color_cpu(pfn_t pfn, uchar_t szc, void *cookie) 357 { 358 mem_node_iterator_t *it = cookie; 359 uint_t color; 360 361 ASSERT(szc <= TTE256M); 362 363 if (it == ((mem_node_iterator_t *)(-1))) { 364 pfn = plat_rapfn_to_papfn(pfn); 365 } else if (it != NULL) { 366 ASSERT(pfn >= it->mi_mblock_base && pfn <= it->mi_mblock_end); 367 pfn = pfn + it->mi_ra_to_pa; 368 } 369 pfn = PFN_BASE(pfn, szc); 370 color = ((pfn >> 15) ^ pfn) & 0x1f; 371 if (szc < TTE4M) { 372 /* 19:18 */ 373 color = (color << 2) | ((pfn >> 5) & 0x3); 374 if (szc > TTE64K) 375 color >>= 1; /* 19 */ 376 } 377 return (n2_hash2color(color, szc)); 378 } 379 380 static uint_t 381 page_papfn_2_color_cpu(pfn_t papfn, uchar_t szc) 382 { 383 uint_t color; 384 385 ASSERT(szc <= TTE256M); 386 387 papfn = PFN_BASE(papfn, szc); 388 color = ((papfn >> 15) ^ papfn) & 0x1f; 389 if (szc < TTE4M) { 390 /* 19:18 */ 391 color = (color << 2) | ((papfn >> 5) & 0x3); 392 if (szc > TTE64K) 393 color >>= 1; /* 19 */ 394 } 395 return (color); 396 } 397 398 #if TTE256M != 5 399 #error TTE256M is not 5 400 #endif 401 402 uint_t 403 page_get_nsz_color_mask_cpu(uchar_t szc, uint_t mask) 404 { 405 static uint_t ni2_color_masks[5] = {0x63, 0x1e, 0x3e, 0x1f, 0x1f}; 406 ASSERT(szc < TTE256M); 407 mask = n2_color2hash(mask, szc, 0); 408 mask &= ni2_color_masks[szc]; 409 if (szc == TTE64K || szc == TTE512K) 410 mask >>= 1; 411 return (n2_hash2color(mask, szc + 1)); 412 } 413 414 uint_t 415 page_get_nsz_color_cpu(uchar_t szc, uint_t color) 416 { 417 ASSERT(szc < TTE256M); 418 color = n2_color2hash(color, szc, 0); 419 if (szc == TTE64K || szc == TTE512K) 420 color >>= 1; 421 return (n2_hash2color(color, szc + 1)); 422 } 423 424 uint_t 425 page_get_color_shift_cpu(uchar_t szc, uchar_t nszc) 426 { 427 uint_t s; 428 ASSERT(nszc >= szc); 429 ASSERT(nszc <= TTE256M); 430 431 s = nhbits[szc] - n2color[szc].nnbits; 432 s -= nhbits[nszc] - n2color[nszc].nnbits; 433 434 return (s); 435 } 436 437 uint_t 438 page_convert_color_cpu(uint_t ncolor, uchar_t szc, uchar_t nszc) 439 { 440 uint_t color; 441 442 ASSERT(nszc > szc); 443 ASSERT(nszc <= TTE256M); 444 ncolor = n2_color2hash(ncolor, nszc, 0); 445 color = ncolor << (nhbits[szc] - nhbits[nszc]); 446 color = n2_hash2color(color, szc); 447 return (color); 448 } 449 450 #define PAPFN_2_MNODE(pfn) \ 451 (((pfn) & it->mi_mnode_pfn_mask) >> it->mi_mnode_pfn_shift) 452 453 /*ARGSUSED*/ 454 pfn_t 455 page_next_pfn_for_color_cpu(pfn_t pfn, uchar_t szc, uint_t color, 456 uint_t ceq_mask, uint_t color_mask, void *cookie) 457 { 458 mem_node_iterator_t *it = cookie; 459 pfn_t pstep = PNUM_SIZE(szc); 460 pfn_t npfn, pfn_ceq_mask, pfn_color; 461 pfn_t tmpmask, mask = (pfn_t)-1; 462 uint_t pfnmn; 463 464 ASSERT((color & ~ceq_mask) == 0); 465 ASSERT(pfn >= it->mi_mblock_base && pfn <= it->mi_mblock_end); 466 467 /* convert RA to PA for accurate color calculation */ 468 if (it->mi_init) { 469 /* first call after it, so cache these values */ 470 it->mi_hash_ceq_mask = 471 n2_color2hash(ceq_mask, szc, it->mi_mnode_mask); 472 it->mi_hash_color = 473 n2_color2hash(color, szc, it->mi_mnode); 474 it->mi_init = 0; 475 } else { 476 ASSERT(it->mi_hash_ceq_mask == 477 n2_color2hash(ceq_mask, szc, it->mi_mnode_mask)); 478 ASSERT(it->mi_hash_color == 479 n2_color2hash(color, szc, it->mi_mnode)); 480 } 481 ceq_mask = it->mi_hash_ceq_mask; 482 color = it->mi_hash_color; 483 pfn += it->mi_ra_to_pa; 484 485 /* restart here when we switch memblocks */ 486 next_mem_block: 487 if (szc <= TTE64K) { 488 pfnmn = PAPFN_2_MNODE(pfn); 489 } 490 if (((page_papfn_2_color_cpu(pfn, szc) ^ color) & ceq_mask) == 0 && 491 (szc > TTE64K || pfnmn == it->mi_mnode)) { 492 493 /* we start from the page with correct color */ 494 if (szc >= TTE512K) { 495 if (szc >= TTE4M) { 496 /* page color is PA[32:28] */ 497 pfn_ceq_mask = ceq_mask << 15; 498 } else { 499 /* page color is PA[32:28].PA[19:19] */ 500 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 501 ((ceq_mask >> 1) << 15); 502 } 503 npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 504 goto done; 505 } else { 506 /* 507 * We deal 64K or 8K page. Check if we could the 508 * satisfy the request without changing PA[32:28] 509 */ 510 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 511 pfn_ceq_mask |= it->mi_mnode_pfn_mask; 512 npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 513 514 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 515 goto done; 516 517 /* 518 * for next pfn we have to change bits PA[32:28] 519 * set PA[63:28] and PA[19:18] of the next pfn 520 */ 521 npfn = (pfn >> 15) << 15; 522 npfn |= (ceq_mask & color & 3) << 5; 523 pfn_ceq_mask = (szc == TTE8K) ? 0 : 524 (ceq_mask & 0x1c) << 13; 525 pfn_ceq_mask |= it->mi_mnode_pfn_mask; 526 npfn = ADD_MASKED(npfn, (1 << 15), pfn_ceq_mask, mask); 527 528 /* 529 * set bits PA[17:13] to match the color 530 */ 531 npfn |= ((npfn >> 15) ^ (color >> 2)) & (ceq_mask >> 2); 532 goto done; 533 } 534 } 535 536 /* 537 * we start from the page with incorrect color - rare case 538 */ 539 if (szc >= TTE512K) { 540 if (szc >= TTE4M) { 541 /* page color is in bits PA[32:28] */ 542 npfn = ((pfn >> 20) << 20) | (color << 15); 543 pfn_ceq_mask = (ceq_mask << 15) | 0x7fff; 544 } else { 545 /* try get the right color by changing bit PA[19:19] */ 546 npfn = pfn + pstep; 547 if (((page_papfn_2_color_cpu(npfn, szc) ^ color) & 548 ceq_mask) == 0) 549 goto done; 550 551 /* page color is PA[32:28].PA[19:19] */ 552 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 553 ((ceq_mask >> 1) << 15) | (0xff << 7); 554 pfn_color = ((color & 1) << 6) | ((color >> 1) << 15); 555 npfn = ((pfn >> 20) << 20) | pfn_color; 556 } 557 558 while (npfn <= pfn) { 559 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask); 560 } 561 goto done; 562 } 563 564 /* 565 * We deal 64K or 8K page of incorrect color. 566 * Try correcting color without changing PA[32:28] 567 */ 568 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 569 pfn_color = ((color & 3) << 5) | (color >> 2); 570 if (pfnmn == it->mi_mnode) { 571 npfn = (pfn & ~(pfn_t)0x7f); 572 npfn |= (((pfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 573 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 574 575 if (((page_papfn_2_color_cpu(npfn, szc) ^ color) & 576 ceq_mask) == 0) { 577 /* the color is fixed - find the next page */ 578 pfn_ceq_mask |= it->mi_mnode_pfn_mask; 579 while (npfn <= pfn) { 580 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, 581 mask); 582 } 583 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 584 goto done; 585 } 586 } 587 588 /* to fix the color need to touch PA[32:28] */ 589 npfn = (szc == TTE8K) ? ((pfn >> 15) << 15) : 590 (((pfn >> 18) << 18) | ((color & 0x1c) << 13)); 591 592 /* fix mnode if input pfn is in the wrong mnode. */ 593 if ((pfnmn = PAPFN_2_MNODE(npfn)) != it->mi_mnode) { 594 npfn += ((it->mi_mnode - pfnmn) & it->mi_mnode_mask) << 595 it->mi_mnode_pfn_shift; 596 } 597 598 tmpmask = (szc == TTE8K) ? 0 : (ceq_mask & 0x1c) << 13; 599 tmpmask |= it->mi_mnode_pfn_mask; 600 601 while (npfn <= pfn) { 602 npfn = ADD_MASKED(npfn, (1 << 15), tmpmask, mask); 603 } 604 605 /* set bits PA[19:13] to match the color */ 606 npfn |= (((npfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 607 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 608 609 done: 610 ASSERT(((page_papfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0); 611 ASSERT(PAPFN_2_MNODE(npfn) == it->mi_mnode); 612 613 /* PA to RA */ 614 npfn -= it->mi_ra_to_pa; 615 616 /* check for possible memblock switch */ 617 if (npfn > it->mi_mblock_end) { 618 pfn = plat_mem_node_iterator_init(npfn, it->mi_mnode, it, 0); 619 if (pfn == (pfn_t)-1) 620 return (pfn); 621 ASSERT(pfn >= it->mi_mblock_base && pfn <= it->mi_mblock_end); 622 pfn += it->mi_ra_to_pa; 623 goto next_mem_block; 624 } 625 626 return (npfn); 627 } 628 629 /* 630 * init page coloring 631 * VF encodes node_id for an L-group in either bit 30 or 31:30, 632 * which effectively reduces the number of colors available per mnode. 633 */ 634 void 635 page_coloring_init_cpu() 636 { 637 int i; 638 uchar_t id; 639 uchar_t lo; 640 uchar_t hi; 641 n2color_t m; 642 mem_node_iterator_t it; 643 static uchar_t idmask[] = {0, 0x7, 0x1f, 0x1f, 0x1f, 0x1f}; 644 645 (void) plat_mem_node_iterator_init(0, 0, &it, 1); 646 for (i = 0; i < mmu_page_sizes; i++) { 647 (void) memset(&m, 0, sizeof (m)); 648 id = it.mi_mnode_pfn_mask >> 15; /* node id mask */ 649 id &= idmask[i]; 650 lo = lowbit(id); 651 if (lo > 0) { 652 hi = highbit(id); 653 m.nnbits = hi - lo + 1; 654 m.nnmask = (1 << m.nnbits) - 1; 655 lo += nhbits[i] - 5; 656 m.lomask = (1 << (lo - 1)) - 1; 657 m.lobits = lo - 1; 658 } 659 hw_page_array[i].hp_colors = 1 << (nhbits[i] - m.nnbits); 660 n2color[i] = m; 661 } 662 } 663 664 /* 665 * group colorequiv colors on N2 by low order bits of the color first 666 */ 667 void 668 page_set_colorequiv_arr_cpu(void) 669 { 670 static uint_t nequiv_shades_log2[MMU_PAGE_SIZES] = {2, 5, 0, 0, 0, 0}; 671 672 nequiv_shades_log2[1] -= n2color[1].nnbits; 673 if (colorequiv > 1) { 674 int i; 675 uint_t sv_a = lowbit(colorequiv) - 1; 676 677 if (sv_a > 15) 678 sv_a = 15; 679 680 for (i = 0; i < MMU_PAGE_SIZES; i++) { 681 uint_t colors; 682 uint_t a = sv_a; 683 684 if ((colors = hw_page_array[i].hp_colors) <= 1) 685 continue; 686 while ((colors >> a) == 0) 687 a--; 688 if (a > (colorequivszc[i] & 0xf) + 689 (colorequivszc[i] >> 4)) { 690 if (a <= nequiv_shades_log2[i]) { 691 colorequivszc[i] = (uchar_t)a; 692 } else { 693 colorequivszc[i] = 694 ((a - nequiv_shades_log2[i]) << 4) | 695 nequiv_shades_log2[i]; 696 } 697 } 698 } 699 } 700 } 701