1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <sys/cpuvar.h> 39 #include <sys/async.h> 40 #include <sys/cmn_err.h> 41 #include <sys/debug.h> 42 #include <sys/dditypes.h> 43 #include <sys/sunddi.h> 44 #include <sys/cpu_module.h> 45 #include <sys/prom_debug.h> 46 #include <sys/vmsystm.h> 47 #include <sys/prom_plat.h> 48 #include <sys/sysmacros.h> 49 #include <sys/intreg.h> 50 #include <sys/machtrap.h> 51 #include <sys/ontrap.h> 52 #include <sys/ivintr.h> 53 #include <sys/atomic.h> 54 #include <sys/panic.h> 55 #include <sys/dtrace.h> 56 #include <sys/simulate.h> 57 #include <sys/fault.h> 58 #include <sys/niagararegs.h> 59 #include <sys/trapstat.h> 60 #include <sys/hsvc.h> 61 62 #define NI_MMU_PAGESIZE_MASK ((1 << TTE8K) | (1 << TTE64K) | (1 << TTE4M) \ 63 | (1 << TTE256M)) 64 65 uint_t root_phys_addr_lo_mask = 0xffffffffU; 66 static niagara_mmustat_t *cpu_tstat_va; /* VA of mmustat buffer */ 67 static uint64_t cpu_tstat_pa; /* PA of mmustat buffer */ 68 char cpu_module_name[] = "SUNW,UltraSPARC-T1"; 69 70 /* 71 * Hypervisor services information for the NIAGARA CPU module 72 */ 73 static boolean_t niagara_hsvc_available = B_TRUE; 74 static uint64_t niagara_sup_minor; /* Supported minor number */ 75 static hsvc_info_t niagara_hsvc = { 76 HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA_CPU, 1, 0, cpu_module_name 77 }; 78 79 void 80 cpu_setup(void) 81 { 82 extern int mmu_exported_pagesize_mask; 83 extern int cpc_has_overflow_intr; 84 int status; 85 char *ni_isa_set[] = { 86 "sparcv9+vis", 87 "sparcv9+vis2", 88 "sparcv8plus+vis", 89 "sparcv8plus+vis2", 90 NULL 91 }; 92 93 /* 94 * Negotiate the API version for Niagara specific hypervisor 95 * services. 96 */ 97 status = hsvc_register(&niagara_hsvc, &niagara_sup_minor); 98 if (status != 0) { 99 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 100 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 101 niagara_hsvc.hsvc_modname, niagara_hsvc.hsvc_group, 102 niagara_hsvc.hsvc_major, niagara_hsvc.hsvc_minor, status); 103 niagara_hsvc_available = B_FALSE; 104 } 105 106 /* 107 * The setup common to all CPU modules is done in cpu_setup_common 108 * routine. 109 */ 110 cpu_setup_common(ni_isa_set); 111 112 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 113 114 if (broken_md_flag) { 115 /* 116 * Turn on the missing bits supported by Niagara CPU in 117 * MMU pagesize mask returned by MD. 118 */ 119 mmu_exported_pagesize_mask |= NI_MMU_PAGESIZE_MASK; 120 } else { 121 if ((mmu_exported_pagesize_mask & 122 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 123 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 124 cmn_err(CE_PANIC, "machine description" 125 " does not have required sun4v page sizes" 126 " 8K, 64K and 4M: MD mask is 0x%x", 127 mmu_exported_pagesize_mask); 128 } 129 130 cpu_hwcap_flags |= AV_SPARC_ASI_BLK_INIT; 131 132 /* 133 * Niagara supports a 48-bit subset of the full 64-bit virtual 134 * address space. Virtual addresses between 0x0000800000000000 135 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 136 * and must never be mapped. In addition, software must not use 137 * pages within 4GB of the VA hole as instruction pages to 138 * avoid problems with prefetching into the VA hole. 139 */ 140 hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 141 hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32)); 142 143 /* 144 * Niagara has a performance counter overflow interrupt 145 */ 146 cpc_has_overflow_intr = 1; 147 148 shctx_on = 0; 149 } 150 151 #define MB(n) ((n) * 1024 * 1024) 152 /* 153 * Set the magic constants of the implementation. 154 */ 155 void 156 cpu_fiximp(struct cpu_node *cpunode) 157 { 158 /* 159 * The Cache node is optional in MD. Therefore in case "Cache" 160 * node does not exists in MD, set the default L2 cache associativity, 161 * size, linesize. 162 */ 163 if (cpunode->ecache_size == 0) 164 cpunode->ecache_size = MB(3); 165 if (cpunode->ecache_linesize == 0) 166 cpunode->ecache_linesize = 64; 167 if (cpunode->ecache_associativity == 0) 168 cpunode->ecache_associativity = 12; 169 } 170 171 void 172 cpu_map_exec_units(struct cpu *cp) 173 { 174 ASSERT(MUTEX_HELD(&cpu_lock)); 175 176 /* 177 * The cpu_ipipe and cpu_fpu fields are initialized based on 178 * the execution unit sharing information from the MD. They 179 * default to the CPU id in the absence of such information. 180 */ 181 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 182 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 183 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 184 185 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 186 if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 187 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 188 189 /* 190 * Niagara defines the the core to be at the ipipe level 191 */ 192 cp->cpu_m.cpu_core = cp->cpu_m.cpu_ipipe; 193 194 /* 195 * Niagara systems just have one chip. Therefore, the chip id 196 * mpipe id are always 0. 197 */ 198 cp->cpu_m.cpu_chip = 0; 199 cp->cpu_m.cpu_mpipe = 0; 200 } 201 202 static int niagara_cpucnt; 203 204 void 205 cpu_init_private(struct cpu *cp) 206 { 207 extern void niagara_kstat_init(void); 208 209 ASSERT(MUTEX_HELD(&cpu_lock)); 210 211 cpu_map_exec_units(cp); 212 213 if ((niagara_cpucnt++ == 0) && (niagara_hsvc_available == B_TRUE)) 214 niagara_kstat_init(); 215 } 216 217 /*ARGSUSED*/ 218 void 219 cpu_uninit_private(struct cpu *cp) 220 { 221 extern void niagara_kstat_fini(void); 222 223 ASSERT(MUTEX_HELD(&cpu_lock)); 224 225 if ((--niagara_cpucnt == 0) && (niagara_hsvc_available == B_TRUE)) 226 niagara_kstat_fini(); 227 } 228 229 /* 230 * On Niagara, any flush will cause all preceding stores to be 231 * synchronized wrt the i$, regardless of address or ASI. In fact, 232 * the address is ignored, so we always flush address 0. 233 */ 234 void 235 dtrace_flush_sec(uintptr_t addr) 236 { 237 doflush(0); 238 } 239 240 #define IS_FLOAT(i) (((i) & 0x1000000) != 0) 241 #define IS_IBIT_SET(x) (x & 0x2000) 242 #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 243 #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 244 (op == 3 && (op3 == IOP_V8_LDDFA || \ 245 op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 246 int 247 vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault) 248 { 249 char *badaddr; 250 int instr; 251 uint_t optype, op3, asi; 252 uint_t rd, ignor; 253 254 if (!USERMODE(rp->r_tstate)) 255 return (-1); 256 257 instr = fetch_user_instr((caddr_t)rp->r_pc); 258 259 rd = (instr >> 25) & 0x1f; 260 optype = (instr >> 30) & 0x3; 261 op3 = (instr >> 19) & 0x3f; 262 ignor = (instr >> 5) & 0xff; 263 if (IS_IBIT_SET(instr)) { 264 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 265 TSTATE_ASI_MASK); 266 } else { 267 asi = ignor; 268 } 269 270 if (!IS_VIS1(optype, op3) && 271 !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 272 return (-1); 273 } 274 switch (simulate_unimp(rp, &badaddr)) { 275 case SIMU_RETRY: 276 break; /* regs are already set up */ 277 /*NOTREACHED*/ 278 279 case SIMU_SUCCESS: 280 /* 281 * skip the successfully 282 * simulated instruction 283 */ 284 rp->r_pc = rp->r_npc; 285 rp->r_npc += 4; 286 break; 287 /*NOTREACHED*/ 288 289 case SIMU_FAULT: 290 siginfo->si_signo = SIGSEGV; 291 siginfo->si_code = SEGV_MAPERR; 292 siginfo->si_addr = badaddr; 293 *fault = FLTBOUNDS; 294 break; 295 296 case SIMU_DZERO: 297 siginfo->si_signo = SIGFPE; 298 siginfo->si_code = FPE_INTDIV; 299 siginfo->si_addr = (caddr_t)rp->r_pc; 300 *fault = FLTIZDIV; 301 break; 302 303 case SIMU_UNALIGN: 304 siginfo->si_signo = SIGBUS; 305 siginfo->si_code = BUS_ADRALN; 306 siginfo->si_addr = badaddr; 307 *fault = FLTACCESS; 308 break; 309 310 case SIMU_ILLEGAL: 311 default: 312 siginfo->si_signo = SIGILL; 313 op3 = (instr >> 19) & 0x3F; 314 if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) || 315 (op3 == IOP_V8_STDFA))) 316 siginfo->si_code = ILL_ILLADR; 317 else 318 siginfo->si_code = ILL_ILLOPC; 319 siginfo->si_addr = (caddr_t)rp->r_pc; 320 *fault = FLTILL; 321 break; 322 } 323 return (0); 324 } 325 326 /* 327 * Trapstat support for Niagara processor 328 */ 329 int 330 cpu_trapstat_conf(int cmd) 331 { 332 size_t len; 333 uint64_t mmustat_pa, hvret; 334 int status = 0; 335 336 if (niagara_hsvc_available == B_FALSE) 337 return (ENOTSUP); 338 339 switch (cmd) { 340 case CPU_TSTATCONF_INIT: 341 ASSERT(cpu_tstat_va == NULL); 342 len = (NCPU+1) * sizeof (niagara_mmustat_t); 343 cpu_tstat_va = contig_mem_alloc_align(len, 344 sizeof (niagara_mmustat_t)); 345 if (cpu_tstat_va == NULL) 346 status = EAGAIN; 347 else { 348 bzero(cpu_tstat_va, len); 349 cpu_tstat_pa = va_to_pa(cpu_tstat_va); 350 } 351 break; 352 353 case CPU_TSTATCONF_FINI: 354 if (cpu_tstat_va) { 355 len = (NCPU+1) * sizeof (niagara_mmustat_t); 356 contig_mem_free(cpu_tstat_va, len); 357 cpu_tstat_va = NULL; 358 cpu_tstat_pa = 0; 359 } 360 break; 361 362 case CPU_TSTATCONF_ENABLE: 363 hvret = hv_niagara_mmustat_conf((cpu_tstat_pa + 364 (CPU->cpu_id+1) * sizeof (niagara_mmustat_t)), 365 (uint64_t *)&mmustat_pa); 366 if (hvret != H_EOK) 367 status = EINVAL; 368 break; 369 370 case CPU_TSTATCONF_DISABLE: 371 hvret = hv_niagara_mmustat_conf(0, (uint64_t *)&mmustat_pa); 372 if (hvret != H_EOK) 373 status = EINVAL; 374 break; 375 376 default: 377 status = EINVAL; 378 break; 379 } 380 return (status); 381 } 382 383 void 384 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 385 { 386 niagara_mmustat_t *mmustatp; 387 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 388 int i, pgcnt; 389 390 if (cpu_tstat_va == NULL) 391 return; 392 393 mmustatp = &((niagara_mmustat_t *)cpu_tstat_va)[CPU->cpu_id+1]; 394 if (tstat_pgszs > NIAGARA_MMUSTAT_PGSZS) 395 tstat_pgszs = NIAGARA_MMUSTAT_PGSZS; 396 397 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 398 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 399 mmustatp->kitsb[i].tsbhit_count; 400 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 401 mmustatp->kitsb[i].tsbhit_time; 402 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 403 mmustatp->uitsb[i].tsbhit_count; 404 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 405 mmustatp->uitsb[i].tsbhit_time; 406 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 407 mmustatp->kdtsb[i].tsbhit_count; 408 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 409 mmustatp->kdtsb[i].tsbhit_time; 410 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 411 mmustatp->udtsb[i].tsbhit_count; 412 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 413 mmustatp->udtsb[i].tsbhit_time; 414 } 415 } 416