1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_US3_MODULE_H 27 #define _SYS_US3_MODULE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/async.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #ifdef _KERNEL 38 39 /* 40 * Macros to access the "cheetah cpu private" data structure. 41 */ 42 #define CPU_PRIVATE_PTR(cp, x) (&(((cheetah_private_t *)CPU_PRIVATE(cp))->x)) 43 #define CPU_PRIVATE_VAL(cp, x) (((cheetah_private_t *)CPU_PRIVATE(cp))->x) 44 45 #define CHP_WORD_TO_OFF(word, off) (((word) * 8) == off) 46 47 #if defined(JALAPENO) || defined(SERRANO) 48 /* JP J_REQ errors */ 49 #define C_AFSR_JREQ_ERRS (C_AFSR_RUE | C_AFSR_BP | C_AFSR_WBP | \ 50 C_AFSR_RCE | C_AFSR_TO | C_AFSR_BERR | C_AFSR_UMS) 51 /* JP AID errors */ 52 #define C_AFSR_AID_ERRS (C_AFSR_CPU | C_AFSR_FRU | C_AFSR_CPC | \ 53 C_AFSR_FRC) 54 55 #if defined(SERRANO) 56 /* SERRANO AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 57 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ 58 C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \ 59 C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \ 60 C_AFSR_FRU | C_AFSR_EDU | C_AFSR_ETI | C_AFSR_ETC) 61 62 #else /* SERRANO */ 63 /* JP AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 64 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ 65 C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \ 66 C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \ 67 C_AFSR_FRU | C_AFSR_EDU) 68 #endif /* SERRANO */ 69 70 #if defined(SERRANO) 71 /* 72 * SERRANO AFSR bits from {Instruction,Data}_access_error traps 73 * (Traps 0xa, 0x32) 74 */ 75 #define C_AFSR_ASYNC_ERRS (C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \ 76 C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP | \ 77 C_AFSR_ETU | C_AFSR_ETS) 78 #else /* SERRANO */ 79 /* JP AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 80 #define C_AFSR_ASYNC_ERRS (C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \ 81 C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP) 82 #endif /* SERRANO */ 83 84 #if defined(SERRANO) 85 /* SERRANO AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 86 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_ETI | \ 87 C_AFSR_ETC) 88 89 #else /* SERRANO */ 90 /* JP AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 91 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC) 92 #endif /* SERRANO */ 93 94 #if defined(SERRANO) 95 /* SERRANO AFSR bits from Fatal errors (processor asserts ERROR pin) */ 96 #define C_AFSR_FATAL_ERRS (C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \ 97 C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \ 98 C_AFSR_ISAP | C_AFSR_EFES | C_AFSR_ETS | C_AFSR_ETU) 99 100 #else /* SERRANO */ 101 /* JP AFSR bits from Fatal errors (processor asserts ERROR pin) */ 102 #define C_AFSR_FATAL_ERRS (C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \ 103 C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \ 104 C_AFSR_ISAP | C_AFSR_ETP) 105 #endif /* SERRANO */ 106 107 /* JP AFSR all valid error status bits */ 108 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 109 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 110 111 #if defined(SERRANO) 112 /* SERRANO AFSR all ME status bits */ 113 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \ 114 C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \ 115 C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETU | C_AFSR_OM | \ 116 C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \ 117 C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \ 118 C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS | \ 119 C_AFSR_ETC | C_AFSR_ETI) 120 121 #else /* SERRANO */ 122 /* JP AFSR all ME status bits */ 123 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \ 124 C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \ 125 C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETP | C_AFSR_OM | \ 126 C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \ 127 C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \ 128 C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS) 129 #endif /* SERRANO */ 130 131 /* JP AFSR bits due to a Memory error */ 132 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_FRC | C_AFSR_FRU |\ 133 C_AFSR_RCE | C_AFSR_RUE) 134 135 /* JP AFSR bits due to parity errors and have a valid BSYND */ 136 #define C_AFSR_MSYND_ERRS (C_AFSR_IVPE | C_AFSR_BP | C_AFSR_WBP) 137 138 /* JP AFSR bits with a valid ESYND field */ 139 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 140 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 141 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 142 C_AFSR_FRC | C_AFSR_FRU) 143 144 /* JP AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 145 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_RUE | C_AFSR_UCU | C_AFSR_EDU | \ 146 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVPE | C_AFSR_TO | \ 147 C_AFSR_BERR | C_AFSR_UMS | C_AFSR_OM | C_AFSR_WBP | \ 148 C_AFSR_FRU | C_AFSR_BP) 149 150 #elif defined(CHEETAH_PLUS) 151 152 /* Ch+ AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 153 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \ 154 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 155 C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE | \ 156 C_AFSR_THCE | C_AFSR_DBERR | C_AFSR_DTO | C_AFSR_IMU | \ 157 C_AFSR_IMC) 158 159 /* Ch+ AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 160 #define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \ 161 C_AFSR_TO | C_AFSR_BERR) 162 163 /* Ch+ AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 164 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_TSCE) 165 166 /* Ch+ AFSR bits from Fatal errors (processor asserts ERROR pin) */ 167 #define C_AFSR_FATAL_ERRS (C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \ 168 C_AFSR_TUE | C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_EMU) 169 170 /* Ch+ AFSR all valid error status bits */ 171 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 172 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 173 174 /* Ch+ AFSR all errors that set ME bit, in both AFSR and AFSR_EXT */ 175 #define C_AFSR_ALL_ME_ERRS (C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_DTO | \ 176 C_AFSR_DBERR | C_AFSR_TSCE | C_AFSR_TUE | C_AFSR_DUE | \ 177 C_AFSR_ISAP | C_AFSR_EMU | C_AFSR_IVU | C_AFSR_TO | \ 178 C_AFSR_BERR | C_AFSR_UCC | C_AFSR_UCU | C_AFSR_CPU | \ 179 C_AFSR_WDU | C_AFSR_EDU | C_AFSR_UE | \ 180 C_AFSR_L3_TUE_SH | C_AFSR_L3_TUE | C_AFSR_L3_EDU | \ 181 C_AFSR_L3_UCC | C_AFSR_L3_UCU | C_AFSR_L3_CPU | \ 182 C_AFSR_L3_WDU) 183 184 /* Ch+ AFSR bits due to an Ecache data error */ 185 #define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \ 186 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 187 C_AFSR_CPC) 188 189 /* Ch+ AFSR bits due to a Memory error */ 190 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC | \ 191 C_AFSR_DUE) 192 193 /* Ch+ AFSR bits due to an Mtag error and have a valid MSYND */ 194 #define C_AFSR_MSYND_ERRS (C_AFSR_EMU | C_AFSR_EMC | C_AFSR_IMU | \ 195 C_AFSR_IMC) 196 197 /* Ch+ AFSR bits with a valid ESYND field */ 198 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 199 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 200 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 201 C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE) 202 203 /* Ch+ AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 204 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \ 205 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \ 206 C_AFSR_BERR | C_AFSR_DUE | C_AFSR_TUE | C_AFSR_DTO | \ 207 C_AFSR_DBERR | C_AFSR_TUE_SH | C_AFSR_IMU) 208 209 #else /* CHEETAH_PLUS */ 210 211 /* AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 212 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \ 213 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 214 C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC) 215 216 /* AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 217 #define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \ 218 C_AFSR_TO | C_AFSR_BERR) 219 220 /* AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 221 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC) 222 223 /* AFSR bits from Fatal errors (processor asserts ERROR pin) */ 224 #define C_AFSR_FATAL_ERRS (C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \ 225 C_AFSR_EMU) 226 227 /* AFSR all valid error status bits */ 228 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 229 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 230 231 /* AFSR all ME status bits */ 232 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_IVU | \ 233 C_AFSR_EMU | C_AFSR_UCU | C_AFSR_EDU | C_AFSR_WDU | \ 234 C_AFSR_CPU | C_AFSR_UCC | C_AFSR_BERR | C_AFSR_TO) 235 236 /* AFSR bits due to an Ecache error */ 237 #define C_AFSR_EC_DATA_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | \ 238 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 239 C_AFSR_CPC) 240 241 /* AFSR bits due to a Memory error */ 242 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC) 243 244 /* AFSR bits due to an Mtag error and have a valid MSYND */ 245 #define C_AFSR_MSYND_ERRS (C_AFSR_EMU | C_AFSR_EMC) 246 247 /* AFSR bits with a valid ESYND field */ 248 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 249 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 250 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 251 C_AFSR_IVU | C_AFSR_IVC) 252 253 /* AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 254 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \ 255 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \ 256 C_AFSR_BERR) 257 258 #endif /* CHEETAH_PLUS */ 259 260 #if defined(JALAPENO) || defined(SERRANO) 261 /* AFSR all valid bits (except for ETW) */ 262 #define C_AFSR_MASK (C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_B_SYND | \ 263 C_AFSR_E_SYND | C_AFSR_AID | C_AFSR_JREQ) 264 #else /* JALAPENO || SERRANO */ 265 /* AFSR all valid bits */ 266 #define C_AFSR_MASK (C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_M_SYND | \ 267 C_AFSR_E_SYND) 268 #endif /* JALAPENO || SERRANO */ 269 270 /* 271 * Panther AFSR_EXT bits from Disrupting (Corrected) ECC error Trap 272 * (Trap 0x63) 273 */ 274 #define C_AFSR_EXT_CECC_ERRS (C_AFSR_L3_EDU | C_AFSR_L3_EDC | \ 275 C_AFSR_L3_WDU | C_AFSR_L3_WDC | C_AFSR_L3_CPU | \ 276 C_AFSR_L3_CPC | C_AFSR_L3_THCE) 277 278 /* 279 * Panther AFSR_EXT bits from {Instruction,Data}_access_error traps 280 * (Traps 0xa, 0x32) 281 */ 282 #define C_AFSR_EXT_ASYNC_ERRS (C_AFSR_L3_EDU) 283 284 /* Panther AFSR_EXT bits from Fast_ECC_error trap (Trap 0x70) */ 285 #define C_AFSR_EXT_FECC_ERRS (C_AFSR_L3_UCU | C_AFSR_L3_UCC) 286 287 /* Panther AFSR_EXT bits from Fatal errors (processor asserts ERROR pin) */ 288 #define C_AFSR_EXT_FATAL_ERRS (C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH | \ 289 C_AFSR_RED_ERR | C_AFSR_EFA_PAR_ERR) 290 291 /* Panther AFSR_EXT all valid error status bits */ 292 #define C_AFSR_EXT_ALL_ERRS (C_AFSR_EXT_FATAL_ERRS | \ 293 C_AFSR_EXT_FECC_ERRS | C_AFSR_EXT_CECC_ERRS | \ 294 C_AFSR_EXT_ASYNC_ERRS | C_AFSR_L3_MECC) 295 296 /* Panther AFSR_EXT bits due to L3 cache data errors */ 297 #define C_AFSR_EXT_L3_DATA_ERRS (C_AFSR_L3_WDU | C_AFSR_L3_WDC | \ 298 C_AFSR_L3_CPU | C_AFSR_L3_CPC | C_AFSR_L3_UCU | \ 299 C_AFSR_L3_UCC | C_AFSR_L3_EDU | C_AFSR_L3_EDC) 300 301 /* Panther AFSR_EXT bits with a valid ESYND field */ 302 #define C_AFSR_EXT_ESYND_ERRS (C_AFSR_L3_UCU | C_AFSR_L3_UCC | \ 303 C_AFSR_L3_EDU | C_AFSR_L3_EDC | C_AFSR_L3_WDU | \ 304 C_AFSR_L3_WDC | C_AFSR_L3_CPU | C_AFSR_L3_CPC) 305 306 /* PANTHER AFSR_EXT error bits for AFT Level 1 messages (uncorrected) */ 307 #define C_AFSR_EXT_LEVEL1 (C_AFSR_L3_UCU | C_AFSR_L3_EDU | \ 308 C_AFSR_L3_WDU | C_AFSR_L3_CPU | C_AFSR_L3_TUE | \ 309 C_AFSR_L3_TUE_SH) 310 311 /* 312 * AFSR / AFSR_EXT bits for which we need to panic the system. 313 */ 314 #define C_AFSR_PANIC(errs) (((errs) & (C_AFSR_FATAL_ERRS | \ 315 C_AFSR_EXT_FATAL_ERRS)) != 0) 316 317 /* 318 * For the Fast ECC TL1 handler, we are limited in how many registers 319 * we can use, so we need to store the AFSR_EXT bits within the AFSR 320 * register using some of the AFSR reserved bits. 321 */ 322 #define AFSR_EXT_IN_AFSR_MASK C_AFSR_EXT_ALL_ERRS 323 #define AFSR_EXT_IN_AFSR_SHIFT 20 324 325 /* 326 * Defines for the flag field in the CPU logout structure. See the 327 * definition of ch_cpu_logout_t for further description. 328 */ 329 #define CLO_FLAGS_TT_MASK 0xff000 330 #define CLO_FLAGS_TT_SHIFT 12 331 #define CLO_FLAGS_TL_MASK 0xf00 332 #define CLO_FLAGS_TL_SHIFT 8 333 #define CLO_NESTING_MAX 20 /* Arbitrary maximum value */ 334 335 #define C_M_SYND_SHIFT 16 336 #define GET_M_SYND(afsr) (((afsr) & C_AFSR_M_SYND) >> C_M_SYND_SHIFT) 337 #define GET_E_SYND(afsr) ((afsr) & C_AFSR_E_SYND) 338 339 /* 340 * Bits of Cheetah Asynchronous Fault Address Register 341 */ 342 #define C_AFAR_PA INT64_C(0x000007fffffffff0) /* PA<42:4> physical address */ 343 344 /* 345 * Defines for the different types of dcache_flush 346 * it is stored in dflush_type 347 */ 348 #define FLUSHALL_TYPE 0x0 /* blasts all cache lines */ 349 #define FLUSHMATCH_TYPE 0x1 /* flush entire cache but check each */ 350 /* each line for a match */ 351 #define FLUSHPAGE_TYPE 0x2 /* flush only one page and check */ 352 /* each line for a match */ 353 354 /* 355 * D-Cache Tag Data Register 356 * 357 * +----------+--------+----------+ 358 * | Reserved | DC_Tag | DC_Valid | 359 * +----------+--------+----------+ 360 * 63 31 30 1 0 361 * 362 */ 363 #define ICACHE_FLUSHSZ 0x20 /* one line in i$ */ 364 #define CHEETAH_DC_VBIT_SHIFT 1 365 #define CHEETAH_DC_VBIT_MASK 0x1 366 367 /* 368 * Define for max size of "reason" string in panic flows. Since this is on 369 * the stack, we want to keep it as small as is reasonable. 370 */ 371 #define MAX_REASON_STRING 40 372 373 /* 374 * These error types are specific to Cheetah and are used internally for the 375 * Cheetah fault structure flt_type field. 376 */ 377 #define CPU_TO 1 /* Timeout */ 378 #define CPU_BERR 2 /* Bus Error */ 379 #define CPU_CE 3 /* Correctable Memory Error */ 380 #define CPU_UE 4 /* Uncorrectable Memory Error */ 381 #define CPU_CE_ECACHE 5 /* Correctable Ecache Error */ 382 #define CPU_UE_ECACHE 6 /* Uncorrectable Ecache Error */ 383 #define CPU_EMC 7 /* Correctable Mtag Error */ 384 #define CPU_FATAL 8 /* Fatal Error */ 385 #define CPU_ORPH 9 /* Orphaned UCC/UCU error */ 386 #define CPU_IV 10 /* IVU or IVC */ 387 #define CPU_INV_AFSR 11 /* Invalid AFSR */ 388 #define CPU_UE_ECACHE_RETIRE 12 /* Uncorrectable Ecache, retire page */ 389 #define CPU_IC_PARITY 13 /* Icache parity error trap */ 390 #define CPU_DC_PARITY 14 /* Dcache parity error trap */ 391 #define CPU_DUE 15 /* Disrupting UE */ 392 #define CPU_FPUERR 16 /* FPU Error */ 393 /* 394 * These next six error types (17-22) are only used in Jalapeno code 395 */ 396 #define CPU_RCE 17 /* Correctable remote memory error */ 397 #define CPU_RUE 18 /* Uncorrectable remote memory error */ 398 #define CPU_FRC 19 /* Correctable foreign memory error */ 399 #define CPU_FRU 20 /* Uncorrectable foreign memory error */ 400 #define CPU_BPAR 21 /* Bus parity (BP or WBP) errorrs */ 401 #define CPU_UMS 22 /* Unsupported memory store */ 402 /* 403 * These next four error types (23-26) are only used in Panther code 404 */ 405 #define CPU_PC_PARITY 23 /* Pcache parity error */ 406 #define CPU_ITLB_PARITY 24 /* Panther ITLB parity error */ 407 #define CPU_DTLB_PARITY 25 /* Panther DTLB parity error */ 408 #define CPU_L3_ADDR_PE 26 /* Panther L3$ address parity error */ 409 410 /* 411 * Sets trap table entry ttentry by overwriting eight instructions from ttlabel 412 */ 413 #define CH_SET_TRAP(ttentry, ttlabel) \ 414 bcopy((const void *)&ttlabel, &ttentry, 32); \ 415 flush_instr_mem((caddr_t)&ttentry, 32); 416 417 /* 418 * Return values for implementation specific error logging in the routine 419 * cpu_impl_async_log_err() 420 */ 421 #define CH_ASYNC_LOG_DONE 0 /* finished logging the error */ 422 #define CH_ASYNC_LOG_CONTINUE 1 /* continue onto handle panicker */ 423 #define CH_ASYNC_LOG_UNKNOWN 2 /* unknown error type */ 424 #define CH_ASYNC_LOG_RECIRC 3 /* suppress logging of error */ 425 426 #ifndef _ASM 427 428 /* 429 * Define Cheetah family (UltraSPARC-III) specific asynchronous error structure 430 */ 431 typedef struct cheetah_async_flt { 432 struct async_flt cmn_asyncflt; /* common - see sun4u/sys/async.h */ 433 ushort_t flt_type; /* types of faults - cpu specific */ 434 uint64_t flt_bit; /* fault bit for this log msg */ 435 uint64_t afsr_ext; /* Panther has an AFSR_EXT register */ 436 uint64_t afsr_errs; /* Store all AFSR error bits together */ 437 uint64_t afar2; /* Serrano has an AFAR2 for FRC/FRU */ 438 ch_diag_data_t flt_diag_data; /* Diagnostic data */ 439 int flt_data_incomplete; /* Diagnostic data is incomplete */ 440 int flt_trapped_ce; /* CEEN fault caught by trap handler */ 441 #if defined(CPU_IMP_L1_CACHE_PARITY) 442 ch_l1_parity_log_t parity_data; /* L1$ Parity error logging info */ 443 #endif /* CPU_IMP_L1_CACHE_PARITY */ 444 pn_tlb_logout_t tlb_diag_data; /* TLB parity error Diagnostic data */ 445 uint32_t flt_fpdata[16]; /* Data from fpras failure */ 446 uint64_t flt_sdw_afar; /* Shadow AFAR */ 447 uint64_t flt_sdw_afsr; /* Shadow AFSR */ 448 uint64_t flt_sdw_afsr_ext; /* Shadow Extended AFSR */ 449 } ch_async_flt_t; 450 451 #define ECC_ALL_TRAPS (ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP | ECC_F_TRAP) 452 #define ECC_ORPH_TRAPS (ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP) 453 #define ECC_ASYNC_TRAPS (ECC_D_TRAP | ECC_I_TRAP) 454 #define ECC_MECC_TRAPS (ECC_D_TRAP | ECC_C_TRAP | ECC_F_TRAP) 455 456 /* 457 * Error type table struct. 458 */ 459 typedef struct ecc_type_to_info { 460 uint64_t ec_afsr_bit; /* AFSR bit of error */ 461 char *ec_reason; /* Short error description */ 462 uint_t ec_flags; /* Trap type error should be seen at */ 463 int ec_flt_type; /* Used by cpu_async_log_err */ 464 char *ec_desc; /* Long error description */ 465 uint64_t ec_err_payload; /* FM ereport payload information */ 466 char *ec_err_class; /* FM ereport class */ 467 } ecc_type_to_info_t; 468 469 typedef struct bus_config_eclk { 470 uint_t divisor; 471 uint64_t mask; 472 } bus_config_eclk_t; 473 474 #endif /* _ASM */ 475 476 #endif /* _KERNEL */ 477 478 #ifndef _ASM 479 480 #include <sys/cpuvar.h> 481 482 /* 483 * Since all the US3_* files share a bunch of routines between each other 484 * we will put all the "extern" definitions in this header file so that we 485 * don't have to repeat it all in every file. 486 */ 487 488 /* 489 * functions that are defined in the US3 cpu module: 490 * ------------------------------------------------- 491 */ 492 extern uint64_t get_safari_config(void); 493 extern void set_safari_config(uint64_t safari_config); 494 extern void shipit(int, int); 495 extern void cpu_aflt_log(int ce_code, int tagnum, ch_async_flt_t *aflt, 496 uint_t logflags, const char *endstr, const char *fmt, ...); 497 extern uint8_t flt_to_trap_type(struct async_flt *aflt); 498 extern char *tag_state_to_desc(uint64_t tagstate); 499 extern void cpu_log_err(struct async_flt *aflt); 500 extern void cpu_page_retire(ch_async_flt_t *ch_flt); 501 extern int clear_errors(ch_async_flt_t *ch_flt); 502 extern void cpu_init_ecache_scrub_dr(struct cpu *cp); 503 extern void get_cpu_error_state(ch_cpu_errors_t *); 504 extern void set_cpu_error_state(ch_cpu_errors_t *); 505 extern int cpu_flt_in_memory(ch_async_flt_t *ch_flt, uint64_t t_afsr_bit); 506 extern int cpu_queue_events(ch_async_flt_t *ch_flt, char *reason, 507 uint64_t t_afsr, ch_cpu_logout_t *clop); 508 extern void cpu_error_ecache_flush(ch_async_flt_t *); 509 extern void cpu_clearphys(struct async_flt *aflt); 510 extern void cpu_async_log_ic_parity_err(ch_async_flt_t *); 511 extern void cpu_async_log_dc_parity_err(ch_async_flt_t *); 512 extern uint64_t get_ecache_ctrl(void); 513 extern uint64_t get_jbus_config(void); 514 extern void set_jbus_config(uint64_t jbus_config); 515 extern uint64_t get_mcu_ctl_reg1(void); 516 extern void set_mcu_ctl_reg1(uint64_t mcu_ctl); 517 extern void cpu_init_trap(void); 518 extern int cpu_ecache_nway(void); 519 extern void cpu_delayed_logout(size_t, ch_cpu_logout_t *); 520 extern void cpu_payload_add_pcache(struct async_flt *, nvlist_t *); 521 extern void cpu_payload_add_tlb(struct async_flt *, nvlist_t *); 522 extern int cpu_scrub_cpu_setup(cpu_setup_t, int, void *); 523 #if defined(JALAPENO) || defined(SERRANO) 524 extern int afsr_to_jaid_status(uint64_t afsr, uint64_t afsr_bit); 525 #endif /* JALAPENO || SERRANO */ 526 /* 527 * Address of the level 15 interrupt handler preamble, used to log Fast ECC 528 * at TL>0 errors, which will be moved to the trap table address above. 529 */ 530 extern void ch_pil15_interrupt_instr(); 531 #ifdef CHEETAHPLUS_ERRATUM_25 532 extern int mondo_recover(uint16_t, int); 533 #endif /* CHEETAHPLUS_ERRATUM_25 */ 534 /* 535 * Adddresses of the Fast ECC Error trap handler preambles which will be 536 * moved to the appropriate trap table addresses. 537 */ 538 extern void fecc_err_instr(void); 539 extern void fecc_err_tl1_instr(void); 540 extern void fecc_err_tl1_cont_instr(void); 541 542 extern int afsr_to_overw_status(uint64_t afsr, uint64_t afsr_bit, 543 uint64_t *ow_bits); 544 #if defined(CHEETAH_PLUS) 545 extern int afsr_to_pn_esynd_status(uint64_t afsr, uint64_t afsr_bit); 546 #endif /* CHEETAH_PLUS */ 547 extern void flush_ecache(uint64_t physaddr, size_t ecachesize, size_t linesize); 548 extern void flush_dcache(void); 549 extern void flush_icache(void); 550 extern void flush_pcache(void); 551 extern void flush_ipb(void); 552 extern uint64_t get_dcu(void); 553 extern void set_dcu(uint64_t ncc); 554 extern void scrubphys(uint64_t paddr, int ecache_set_size); 555 extern void clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize); 556 extern void stick_adj(int64_t skew); 557 extern void stick_timestamp(int64_t *ts); 558 extern void icache_inval_all(void); 559 extern void dcache_inval_line(int index); 560 extern void ecache_flush_line(uint64_t flushaddr, int ec_size); 561 extern int ecache_get_lineinfo(uint32_t ecache_index, uint64_t *tag, 562 uint64_t *data); 563 #if defined(CPU_IMP_L1_CACHE_PARITY) 564 extern void get_dcache_dtag(uint32_t dcache_idx, uint64_t *data); 565 extern void get_icache_dtag(uint32_t icache_idx, uint64_t *data); 566 extern void get_pcache_dtag(uint32_t pcache_idx, uint64_t *data); 567 extern void correct_dcache_parity(size_t dcache_size, size_t dcache_linesize); 568 #endif /* CPU_IMP_L1_CACHE_PARITY */ 569 extern void cpu_check_block(caddr_t, uint_t); 570 extern uint32_t us3_gen_ecc(uint64_t data_low, uint64_t data_high); 571 extern int cpu_impl_async_log_err(void *, errorq_elem_t *); 572 extern void cpu_fast_ecc_error(struct regs *rp, ulong_t p_clo_flags); 573 extern void cpu_tl1_error(struct regs *rp, int panic); 574 extern void cpu_tl1_err_panic(struct regs *rp, ulong_t flags); 575 extern void cpu_disrupting_error(struct regs *rp, ulong_t p_clo_flags); 576 extern void cpu_deferred_error(struct regs *rp, ulong_t p_clo_flags); 577 #if defined(CPU_IMP_L1_CACHE_PARITY) 578 extern void cpu_parity_error(struct regs *rp, uint_t flags, caddr_t tpc); 579 #endif /* CPU_IMP_L1_CACHE_PARITY */ 580 extern void claimlines(uint64_t startpa, size_t len, int stride); 581 extern void copy_tsb_entry(uintptr_t src, uintptr_t dest); 582 extern void hwblkpagecopy(const void *src, void *dst); 583 #if defined(CHEETAH_PLUS) 584 extern void pn_cpu_log_diag_l2_info(ch_async_flt_t *ch_flt); 585 extern void set_afsr_ext(uint64_t afsr_ext); 586 #endif 587 extern void cpu_tlb_parity_error(struct regs *rp, ulong_t trap_va, 588 ulong_t tlb_info); 589 extern void log_flt_func(struct async_flt *aflt, char *unum); 590 extern uint64_t pn_get_tlb_index(uint64_t va, uint64_t pg_sz); 591 extern int popc64(uint64_t val); 592 593 /* 594 * variables and structures that are defined in the US3 cpu module: 595 * ---------------------------------------------------------------- 596 */ 597 extern bus_config_eclk_t bus_config_eclk[]; 598 extern ecc_type_to_info_t ecc_type_to_info[]; 599 extern uint64_t ch_err_tl1_paddrs[]; 600 extern uchar_t ch_err_tl1_pending[]; 601 #ifdef CHEETAHPLUS_ERRATUM_25 602 /* 603 * Tunable defined in us3_common.c 604 */ 605 extern int cheetah_sendmondo_recover; 606 #endif /* CHEETAHPLUS_ERRATUM_25 */ 607 /* 608 * The following allows for a one time calculation of the number of dcache 609 * lines vs. calculating the number every time through the scrub routine. 610 */ 611 int dcache_nlines; /* max number of D$ lines */ 612 613 extern uint64_t afar_overwrite[]; 614 extern uint64_t esynd_overwrite[]; 615 extern uint64_t msynd_overwrite[]; 616 617 #if defined(JALAPENO) || defined(SERRANO) 618 extern uint64_t jreq_overwrite[]; 619 #if defined(SERRANO) 620 extern uint64_t afar2_overwrite[]; 621 #endif /* SERRANO */ 622 #endif /* JALAPENO || SERRANO */ 623 624 /* 625 * variables and structures that are defined outside the US3 cpu module: 626 * --------------------------------------------------------------------- 627 */ 628 extern uint64_t xc_tick_limit; 629 extern uint64_t xc_tick_jump_limit; 630 extern struct kmem_cache *ch_private_cache; 631 632 #if defined(CPU_IMP_L1_CACHE_PARITY) 633 /* 634 * Addresses of the Dcache and Icache parity error trap table entries. 635 * If L1 cache parity protection is implemented, need to replace Dcache and 636 * Icache parity error handlers. 637 */ 638 extern void *tt0_dperr; 639 extern void *tt1_dperr; 640 extern void *tt1_swtrap1; 641 extern void *tt0_iperr; 642 extern void *tt1_iperr; 643 extern void *tt1_swtrap2; 644 /* 645 * Addresses of the Dcache and Icache parity error trap preambles, which will 646 * be moved to the appropriate trap table addresses. 647 */ 648 extern void dcache_parity_instr(); 649 extern void dcache_parity_tl1_instr(); 650 extern void dcache_parity_tl1_cont_instr(); 651 extern void icache_parity_instr(); 652 extern void icache_parity_tl1_instr(); 653 extern void icache_parity_tl1_cont_instr(); 654 #endif /* CPU_IMP_L1_CACHE_PARITY */ 655 656 /* 657 * Addresses of the Fast ECC error trap table entries. 658 */ 659 extern void *tt0_fecc; 660 extern void *tt1_fecc; 661 extern void *tt1_swtrap0; 662 /* 663 * Address of trap table level 15 interrupt handler in the trap table. 664 */ 665 extern void *tt_pil15; 666 /* 667 * D$ and I$ global parameters. 668 */ 669 extern int dcache_size; 670 extern int dcache_linesize; 671 extern int icache_size; 672 extern int icache_linesize; 673 674 /* 675 * Set of all offline cpus 676 */ 677 extern cpuset_t cpu_offline_set; 678 679 #endif /* _ASM */ 680 681 #ifdef __cplusplus 682 } 683 #endif 684 685 #endif /* _SYS_US3_MODULE_H */ 686