1*84612482Sminht /* 2*84612482Sminht * CDDL HEADER START 3*84612482Sminht * 4*84612482Sminht * The contents of this file are subject to the terms of the 5*84612482Sminht * Common Development and Distribution License, Version 1.0 only 6*84612482Sminht * (the "License"). You may not use this file except in compliance 7*84612482Sminht * with the License. 8*84612482Sminht * 9*84612482Sminht * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*84612482Sminht * or http://www.opensolaris.org/os/licensing. 11*84612482Sminht * See the License for the specific language governing permissions 12*84612482Sminht * and limitations under the License. 13*84612482Sminht * 14*84612482Sminht * When distributing Covered Code, include this CDDL HEADER in each 15*84612482Sminht * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*84612482Sminht * If applicable, add the following below this CDDL HEADER, with the 17*84612482Sminht * fields enclosed by brackets "[]" replaced with your own identifying 18*84612482Sminht * information: Portions Copyright [yyyy] [name of copyright owner] 19*84612482Sminht * 20*84612482Sminht * CDDL HEADER END 21*84612482Sminht */ 22*84612482Sminht /* 23*84612482Sminht * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*84612482Sminht * Use is subject to license terms. 25*84612482Sminht */ 26*84612482Sminht 27*84612482Sminht #ifndef _TODBQ4802_H 28*84612482Sminht #define _TODBQ4802_H 29*84612482Sminht 30*84612482Sminht #pragma ident "%Z%%M% %I% %E% SMI" 31*84612482Sminht 32*84612482Sminht #ifdef __cplusplus 33*84612482Sminht extern "C" { 34*84612482Sminht #endif 35*84612482Sminht 36*84612482Sminht extern char *v_rtc_addr_reg; 37*84612482Sminht 38*84612482Sminht #ifdef DEBUG 39*84612482Sminht #include <sys/promif.h> 40*84612482Sminht #define DPRINTF if (bq4802_debug_flags) prom_printf 41*84612482Sminht #else 42*84612482Sminht #define DPRINTF 43*84612482Sminht #endif /* DEBUG */ 44*84612482Sminht 45*84612482Sminht #define BQ4802_DATA_REG(x) (*(volatile uint8_t *)(v_rtc_addr_reg + x)) 46*84612482Sminht 47*84612482Sminht /* 48*84612482Sminht * Definitions for Real Time Clock driver (TI BQ4802 chip). 49*84612482Sminht */ 50*84612482Sminht #define RTC_SEC 0x0 /* Seconds */ 51*84612482Sminht #define RTC_ASEC 0x1 /* Seconds Alarm */ 52*84612482Sminht #define RTC_MIN 0x2 /* Minutes */ 53*84612482Sminht #define RTC_AMIN 0x3 /* Minutes Alarm */ 54*84612482Sminht #define RTC_HRS 0x4 /* Hours */ 55*84612482Sminht #define RTC_AHRS 0x5 /* Hours Alarm */ 56*84612482Sminht #define RTC_DOM 0x6 /* Day-of-Month */ 57*84612482Sminht #define RTC_ADOM 0x7 /* Day-of-Month Alarm */ 58*84612482Sminht #define RTC_DOW 0x8 /* Day-of-Week */ 59*84612482Sminht #define RTC_MON 0x9 /* Month */ 60*84612482Sminht #define RTC_YEAR 0xa /* Year */ 61*84612482Sminht #define RTC_CENTURY 0xf /* Century */ 62*84612482Sminht 63*84612482Sminht #define RTC_RATES 0xb /* Control Register B */ 64*84612482Sminht #define RTC_ENABLES 0xc /* Control Register C */ 65*84612482Sminht #define RTC_FLAGS 0xd /* Control Register D */ 66*84612482Sminht #define RTC_CNTRL 0xe /* Control Register E */ 67*84612482Sminht 68*84612482Sminht /* 69*84612482Sminht * Control register B definitions 70*84612482Sminht */ 71*84612482Sminht #define RTC_RS 0x0f /* Rate select for periodic interrupt */ 72*84612482Sminht #define RTC_WD 0x70 /* Watchdog time-out rate */ 73*84612482Sminht 74*84612482Sminht /* 75*84612482Sminht * Control register C definitions 76*84612482Sminht */ 77*84612482Sminht #define RTC_ABE 0x01 /* Alarm Int. Enable in Battery-backup Mode */ 78*84612482Sminht #define RTC_PWRIE 0x02 /* Power-fail Interrupt Enable */ 79*84612482Sminht #define RTC_PIE 0x04 /* Periodic Interrupt Enable */ 80*84612482Sminht #define RTC_AIE 0x08 /* Alarm Interrupt Enable */ 81*84612482Sminht 82*84612482Sminht /* 83*84612482Sminht * Control Register D definitions 84*84612482Sminht */ 85*84612482Sminht #define RTC_BVF 0x01 /* Battery-valid flag */ 86*84612482Sminht #define RTC_PWRF 0x02 /* Power-fail Interrupt flag */ 87*84612482Sminht #define RTC_PF 0x04 /* Periodic Interrupt flag */ 88*84612482Sminht #define RTC_AF 0x08 /* Alarm Interrupt flag */ 89*84612482Sminht 90*84612482Sminht /* 91*84612482Sminht * Control Register E definitions 92*84612482Sminht */ 93*84612482Sminht #define RTC_DSE 0x01 /* Daylight Savings Enable */ 94*84612482Sminht #define RTC_HM 0x02 /* Hour mode, 1 = 24 hour, 0 = 12 hour */ 95*84612482Sminht #define RTC_STOP_N 0x04 /* Oscillator Stop and Start */ 96*84612482Sminht #define RTC_UTI 0x08 /* Update Transfer Inhibit */ 97*84612482Sminht 98*84612482Sminht struct rtc_t { 99*84612482Sminht uint8_t rtc_sec; /* seconds */ 100*84612482Sminht uint8_t rtc_asec; /* alarm seconds */ 101*84612482Sminht uint8_t rtc_min; /* mins */ 102*84612482Sminht uint8_t rtc_amin; /* alarm mins */ 103*84612482Sminht uint8_t rtc_hrs; /* hours */ 104*84612482Sminht uint8_t rtc_ahrs; /* alarm hours */ 105*84612482Sminht uint8_t rtc_dom; /* day of the month */ 106*84612482Sminht uint8_t rtc_adom; /* alarm day of the month */ 107*84612482Sminht uint8_t rtc_dow; /* day of the week */ 108*84612482Sminht uint8_t rtc_mon; /* month */ 109*84612482Sminht uint8_t rtc_year; /* year */ 110*84612482Sminht uint8_t rtc_rates; /* rates */ 111*84612482Sminht uint8_t rtc_enables; /* enables */ 112*84612482Sminht uint8_t rtc_flags; /* flags */ 113*84612482Sminht uint8_t rtc_control; /* control */ 114*84612482Sminht uint8_t rtc_century; /* century */ 115*84612482Sminht }; 116*84612482Sminht 117*84612482Sminht #ifdef __cplusplus 118*84612482Sminht } 119*84612482Sminht #endif 120*84612482Sminht 121*84612482Sminht #endif /* _TODBQ4802_H */ 122