xref: /titanic_51/usr/src/uts/sun4u/sys/sbbcreg.h (revision 791a814c934fcd4deb13b26c1f116ff283272a0d)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_SBBCREG_H
27 #define	_SYS_SBBCREG_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * Register definitions for SBBC, a PCI device.
37  */
38 #define	SBBC_SC_MODE	0x00000020
39 
40 typedef struct pad12 {
41 	uint32_t pad[3];
42 }pad12_t;
43 
44 /*
45  * SBBC registers.
46  */
47 struct sbbc_regs_map {
48 	uint32_t devid;			/* 0x0.0000 All, device ID */
49 	pad12_t  pada;
50 	uint32_t devtemp;		/* 0x0.0010 All */
51 	pad12_t  padb;
52 	uint32_t incon_scratch;		/* 0x0.0020 All */
53 	pad12_t  padc;
54 	uint32_t incon_tstl1;		/* 0x0.0030 AR and SDC */
55 	pad12_t  padd;
56 	uint32_t incon_tsterr;		/* 0x0.0040 AR and SDC */
57 	pad12_t  pade;
58 	uint32_t device_conf;		/* 0x0.0050 All, device configuration */
59 	pad12_t  padf;
60 	uint32_t device_rstcntl;	/* 0x0.0060 SBBC,AR,dev reset control */
61 	pad12_t  padg;
62 	uint32_t device_rststat;	/* 0x0.0070 All, device reset status */
63 	pad12_t  padh;
64 	uint32_t device_errstat;	/* 0x0.0080 SBBC, device reset */
65 	pad12_t  padi;
66 	uint32_t device_errcntl;	/* 0x0.0090 SBBC,device error control */
67 	pad12_t  padj;
68 	uint32_t jtag_cntl;		/* 0x0.00a0 SBBC and SDC,JTAG control */
69 	pad12_t  padk;
70 	uint32_t jtag_cmd;		/* 0x0.00b0 SBBC and SDC,JTAG command */
71 	pad12_t  padl;
72 	uint32_t i2c_addrcmd;		/* 0x0.00c0 SBBC,I2C addr and command */
73 	pad12_t  padm;
74 	uint32_t i2c_data;		/* 0x0.00d0 SBBC, I2C data */
75 	pad12_t  padn;
76 	uint32_t pci_errstat;		/* 0x0.00e0 SBBC, PCI error status */
77 	pad12_t  pad2[45];
78 	uint32_t consbus_conf;		/* 0x0.0300 All */
79 	pad12_t  pado;
80 	uint32_t consbus_erraddr;	/* 0x0.0310 SBBC */
81 	pad12_t  padp;
82 	uint32_t consbus_errack;	/* 0x0.0320 SBBC */
83 	pad12_t  pad4[18];
84 	uint32_t pad5;
85 	uint32_t consbus_port0_err;	/* 0x0.0400 All */
86 	pad12_t  pad6[19];
87 	uint32_t pad7[2];
88 	uint32_t consbus_part_dom_err;	/* 0x0.04f0 SBBC and CBH */
89 	pad12_t  pad8[235];
90 	uint32_t pad8a[2];
91 	uint32_t sbbc_synch;		/* 0x0.1000 SBBC */
92 	pad12_t  padq[20];
93 	uint32_t padqa[3];
94 	uint32_t dev_access_tim0;	/* 0x0.1100 SBBC */
95 	pad12_t  padr;
96 	uint32_t dev_access_tim1;	/* 0x0.1110 SBBC */
97 	pad12_t  pads;
98 	uint32_t dev_access_tim2;	/* 0x0.1120 SBBC */
99 	pad12_t  padt;
100 	uint32_t dev_access_tim3;	/* 0x0.1130 SBBC */
101 	pad12_t  padu;
102 	uint32_t dev_access_tim4;	/* 0x0.1140 SBBC */
103 	pad12_t  padv;
104 	uint32_t dev_access_tim5;	/* 0x0.1150 SBBC */
105 	pad12_t  pad9[14];
106 	uint32_t pad9a[1];
107 	uint32_t spare_in_out;		/* 0x0.1200 SBBC */
108 	pad12_t  pad10[127];
109 	uint32_t pad10a[2];
110 	uint32_t monitor_cntl;		/* 0x0.1800 SBBC */
111 	pad12_t  pad11[170];
112 	uint32_t pad11a[1];
113 	uint32_t port_intr_gen0;	/* 0x0.2000 SBBC */
114 	pad12_t  padw;
115 	uint32_t port_intr_gen1;	/* 0x0.2010 SBBC */
116 	pad12_t  padx;
117 	uint32_t syscntlr_intr_gen;	/* 0x0.2020 SBBC */
118 	pad12_t  pad12[61];
119 	uint32_t sys_intr_status;	/* 0x0.2300 SBBC */
120 	pad12_t  pady;
121 	uint32_t sys_intr_enable;	/* 0x0.2310 SBBC */
122 	pad12_t  padz;
123 	uint32_t pci_intr_status;	/* 0x0.2320 SBBC */
124 	pad12_t  padaa;
125 	uint32_t pci_intr_enable;	/* 0x0.2330 SBBC */
126 	pad12_t  pad13[614];
127 	uint32_t pad13a[1];
128 	uint32_t pci_to_consbus_map;	/* 0x0.4000 SBBC */
129 	pad12_t  padab;
130 	uint32_t consbus_to_pci_map;	/* 0x0.4010 SBBC */
131 	uint32_t pad14[2247];
132 					/* 0x0.6330 SBBC */
133 };
134 
135 
136 /*
137  * SSC DEV presence registers
138  */
139 struct ssc_devpresence_regs_map {
140 	uint8_t devpres_reg0;
141 	uint8_t devpres_reg1;
142 	uint8_t devpres_reg2;
143 	uint8_t devpres_reg3;
144 	uint8_t devpres_reg4;
145 	uint8_t devpres_reg5;
146 	uint8_t devpres_reg6;
147 	uint8_t devpres_reg7;
148 	uint8_t devpres_reg8;
149 	uint8_t devpres_reg9;
150 	uint8_t devpres_rega;
151 	uint8_t devpres_regb;
152 };
153 
154 /*
155  * EChip
156  * 0088.0000 - 0089.FFFF
157  */
158 struct ssc_echip_regs {
159 	uint8_t offset[0x20000];
160 };
161 
162 /*
163  * Device Presence
164  * 008A.0000 - 008B.FFFF
165  */
166 struct ssc_devpresence_regs {
167 	uint8_t offset[0x20000];
168 };
169 
170 /*
171  * I2C Mux
172  * 008C.0000 - 008D.FFFF
173  */
174 struct ssc_i2cmux_regs {
175 	uint8_t offset[0x20000];
176 };
177 
178 /*
179  * Error Interrupts Status and Control
180  * 008E.0000 - 008F.FFFF
181  */
182 struct ssc_errintr_statcntl_regs {
183 	uint8_t offset[0x20000];
184 };
185 
186 /*
187  * Console Bus Window
188  * 0400.0000 - 07FF.FFFF
189  */
190 struct ssc_console_bus {
191 	uint8_t offset[0x4000000];
192 };
193 
194 /*
195  * SSC EILD registers
196  */
197 struct ssc_eild_reg_map {
198 	uint8_t darb_intr;
199 	uint8_t darb_intr_mask;
200 	uint8_t sbbc_cons_err;
201 	uint8_t sbbc_cons_err_mask;
202 	uint8_t pwr_supply;
203 };
204 
205 /*
206  * PCI SBBC slave mapping
207  */
208 struct pci_sbbc {
209 	uint8_t fprom[0x800000];	/* FPROM */
210 	struct sbbc_regs_map sbbc_internal_regs;	/* sbbc registers */
211 	uint8_t dontcare[0x79CD0];	/* reserved sbbc registers */
212 	struct ssc_echip_regs echip_regs;
213 	struct ssc_devpresence_regs devpres_regs;
214 	struct ssc_i2cmux_regs i2cmux_regs;
215 	struct ssc_errintr_statcntl_regs errintr_scntl_regs;
216 	uint8_t sram[0x100000];
217 	uint8_t reserved[0x3600000];
218 	struct ssc_console_bus consbus;
219 };
220 
221 
222 /*
223  * SBBC registers.
224  */
225 struct sbbc_common_devregs {
226 	uint32_t devid;			/* All, device ID */
227 	uint32_t devtemp;		/* All */
228 	uint32_t incon_scratch;		/* All */
229 	uint32_t incon_tstl1;		/* AR and SDC */
230 	uint32_t incon_tsterr;		/* AR and SDC */
231 	uint32_t device_conf;		/* All, device configuration */
232 	uint32_t device_rstcntl;	/* SBBC and AR, dev reset control */
233 	uint32_t device_rststat;	/* All, device reset status */
234 	uint32_t device_errstat;	/* SBBC, device reset */
235 	uint32_t device_errcntl;	/* SBBC, device error control */
236 	uint32_t jtag_cntl;		/* SBBC and SDC, JTAG control */
237 	uint32_t jtag_cmd;		/* SBBC and SDC, JTAG command */
238 	uint32_t i2c_addrcmd;		/* SBBC, I2C address and command */
239 	uint32_t i2c_data;		/* SBBC, I2C data */
240 	uint32_t pci_errstat;		/* SBBC, PCI error status */
241 	uint32_t domain_conf;		/* CBH */
242 	uint32_t safari_port0_conf;	/* AR and SDC */
243 	uint32_t safari_port1_conf;	/* AR and SDC */
244 	uint32_t safari_port2_conf;	/* AR and SDC */
245 	uint32_t safari_port3_conf;	/* AR and SDC */
246 	uint32_t safari_port4_conf;	/* AR and SDC */
247 	uint32_t safari_port5_conf;	/* AR and SDC */
248 	uint32_t safari_port6_conf;	/* AR and SDC */
249 	uint32_t safari_port7_conf;	/* AR and SDC */
250 	uint32_t safari_port8_conf;	/* AR and SDC */
251 	uint32_t safari_port9_conf;	/* AR and SDC */
252 	uint32_t safari_port0_err;	/* AR and SDC */
253 	uint32_t safari_port1_err;	/* AR and SDC */
254 	uint32_t safari_port2_err;	/* AR and SDC */
255 	uint32_t safari_port3_err;	/* AR and SDC */
256 	uint32_t safari_port4_err;	/* AR and SDC */
257 	uint32_t safari_port5_err;	/* AR and SDC */
258 	uint32_t safari_port6_err;	/* AR and SDC */
259 	uint32_t safari_port7_err;	/* AR and SDC */
260 	uint32_t safari_port8_err;	/* AR and SDC */
261 	uint32_t safari_port9_err;	/* AR and SDC */
262 	uint32_t consbus_conf;		/* All */
263 	uint32_t consbus_erraddr;	/* SBBC */
264 	uint32_t consbus_errack;	/* SBBC */
265 	uint32_t consbus_errinj0;	/* CBH */
266 	uint32_t consbus_errinj1;	/* CBH */
267 	uint32_t consbus_port0_err;	/* All */
268 	uint32_t consbus_port1_err;	/* SDC and CBH */
269 	uint32_t consbus_port2_err;	/* SDC and CBH */
270 	uint32_t consbus_port3_err;	/* SDC and CBH */
271 	uint32_t consbus_port4_err;	/* SDC and CBH */
272 	uint32_t consbus_port5_err;	/* CBH */
273 	uint32_t consbus_port6_err;	/* CBH */
274 	uint32_t consbus_port7_err;	/* CBH */
275 	uint32_t consbus_port8_err;	/* CBH */
276 	uint32_t consbus_port9_err;	/* CBH */
277 	uint32_t consbus_porta_err;	/* CBH */
278 	uint32_t consbus_portb_err;	/* CBH */
279 	uint32_t consbus_portc_err;	/* CBH */
280 	uint32_t consbus_portd_err;	/* CBH */
281 	uint32_t consbus_porte_err;	/* CBH */
282 	uint32_t consbus_part_dom_err;	/* SBBC and CBH */
283 	uint32_t sbbc_synch;		/* SBBC */
284 	uint32_t dev_access_tim0;	/* SBBC */
285 	uint32_t dev_access_tim1;	/* SBBC */
286 	uint32_t dev_access_tim2;	/* SBBC */
287 	uint32_t dev_access_tim3;	/* SBBC */
288 	uint32_t dev_access_tim4;	/* SBBC */
289 	uint32_t dev_access_tim5;	/* SBBC */
290 	uint32_t spare_in_out;		/* SBBC */
291 	uint32_t monitor_cntl;		/* SBBC */
292 	uint32_t port_intr_gen0;	/* SBBC */
293 	uint32_t port_intr_gen1;	/* SBBC */
294 	uint32_t syscntlr_intr_gen;	/* SBBC */
295 	uint32_t sys_intr_status;	/* SBBC */
296 	uint32_t sys_intr_enable;	/* SBBC */
297 	uint32_t pci_intr_status;	/* SBBC */
298 	uint32_t pci_intr_enable;	/* SBBC */
299 	uint32_t pci_to_consbus_map;	/* SBBC */
300 	uint32_t consbus_to_pci_map;	/* SBBC */
301 	uint32_t scm_consbus_addrmap;	/* CBH */
302 	uint32_t ar_slot0_trans_cnt;	/* AR */
303 	uint32_t ar_slot1_trans_cnt;	/* AR */
304 	uint32_t ar_slot2_trans_cnt;	/* AR */
305 	uint32_t ar_slot3_trans_cnt;	/* AR */
306 	uint32_t ar_slot4_trans_cnt;	/* AR */
307 	uint32_t ar_slot5_trans_cnt;	/* AR */
308 	uint32_t ar_slot6_trans_cnt;	/* AR */
309 	uint32_t ar_slot7_trans_cnt;	/* AR */
310 	uint32_t ar_slot8_trans_cnt;	/* AR */
311 	uint32_t ar_slot9_trans_cnt;	/* AR */
312 	uint32_t ar_trans_cnt_oflow;	/* AR */
313 	uint32_t ar_trans_cnt_uflow;	/* AR */
314 	uint32_t ar_l1l1_conf;		/* AR */
315 	uint32_t lock_step_err;		/* AR and SDC */
316 	uint32_t l2_check_err;		/* AR and SDC */
317 	uint32_t incon_tstl1_slave;	/* AR */
318 	uint32_t incon_tstl2_slave;	/* AR and SDC */
319 	uint32_t ecc_status;		/* SDC */
320 	uint32_t event_counter0;	/* SDC */
321 	uint32_t event_counter1;	/* SDC */
322 	uint32_t event_counter2;	/* SDC */
323 	uint32_t monitor_counter_cntl;	/* AR and SDC */
324 	uint32_t ar_transid_match;	/* AR */
325 };
326 
327 
328 #ifdef	__cplusplus
329 }
330 #endif
331 
332 #endif	/* _SYS_SBBCREG_H */
333