1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_CB_H 28 #define _SYS_PCI_CB_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 typedef uint16_t cb_nid_t; 37 enum cb_nintr_index { 38 CBNINTR_PBM = 0, /* all not shared */ 39 CBNINTR_PBM66 = 0, /* all not shared */ 40 CBNINTR_PBM33 = 0, /* all not shared */ 41 CBNINTR_UE = 1, /* all shared */ 42 CBNINTR_CE = 2, /* all shared */ 43 CBNINTR_POWER_FAIL = 3, /* psycho shared */ 44 CBNINTR_POWER_BUTTON = 3, /* sabre N/A */ 45 CBNINTR_PME_HB = 3, /* hummingbird N/A */ 46 CBNINTR_BUS_ERROR = 3, /* schizo shared */ 47 CBNINTR_THERMAL = 4, /* psycho shared */ 48 CBNINTR_PME = 4, /* schizo not shared */ 49 CBNINTR_CDMA = 4, /* schizo not shared */ 50 CBNINTR_PWR_MANAGE = 5, /* psycho shared */ 51 CBNINTR_MAX /* count coding */ 52 }; 53 54 /* 55 * control block soft state structure: 56 * 57 * Each pci node contains shares a control block structure with its peer 58 * node. The control block node contains csr and id registers for chip 59 * and acts as a "catch all" for other functionality that does not cleanly 60 * fall into other functional blocks. This block is also used to handle 61 * software workarounds for known hardware bugs in different chip revs. 62 */ 63 typedef struct cb cb_t; 64 struct cb { 65 pci_common_t *cb_pci_cmn_p; 66 cb_nid_t cb_node_id; 67 pci_ign_t cb_ign; /* 1st-attached-side interrupt grp# */ 68 69 kmutex_t cb_intr_lock; /* guards add/rem intr and intr dist */ 70 uint32_t cb_no_of_inos; /* # of actual inos, including PBM */ 71 uint32_t cb_inos[CBNINTR_MAX]; /* subset of pci_p->pci_inos array */ 72 73 uint64_t cb_base_pa; /* PA of schizo CSR bank, 2nd "reg" */ 74 uint64_t cb_icbase_pa; /* PA of tomatillo IChip register */ 75 /* bank, 4th "reg" entry */ 76 uint64_t cb_map_pa; /* 1st-attached-side map reg base PA */ 77 uint64_t cb_clr_pa; /* 1st-attached-side clr reg base PA */ 78 uint64_t cb_obsta_pa; /* 1st-attached-side sta reg base PA */ 79 80 uint64_t *cb_imr_save; 81 82 #ifdef _STARFIRE 83 caddr_t cb_ittrans_cookie; /* intr tgt translation */ 84 #endif 85 }; 86 87 #define CB_INO_TO_MONDO(cb_p, ino) ((cb_p)->cb_ign << PCI_INO_BITS | (ino)) 88 #define CB_MONDO_TO_XMONDO(cb_p, mondo) /* local mondo to global mondo */ \ 89 ((cb_p)->cb_node_id << (PCI_IGN_BITS + PCI_INO_BITS) | (mondo)) 90 91 extern void cb_create(pci_t *pci_p); 92 extern void cb_destroy(pci_t *pci_p); 93 extern void cb_suspend(cb_t *cb_p); 94 extern void cb_resume(cb_t *cb_p); 95 extern void cb_enable_nintr(pci_t *pci_p, enum cb_nintr_index idx); 96 extern void cb_disable_nintr(cb_t *cb_p, enum cb_nintr_index idx, int wait); 97 extern void cb_clear_nintr(cb_t *cb_p, enum cb_nintr_index idx); 98 extern void cb_intr_dist(void *arg); 99 100 #ifdef __cplusplus 101 } 102 #endif 103 104 #endif /* _SYS_PCI_CB_H */ 105