1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_OPL_OLYMPUS_REGS_H 27 #define _SYS_OPL_OLYMPUS_REGS_H 28 29 #include <sys/machasi.h> 30 #include <sys/cpu_impl.h> 31 32 /* 33 * This file is cpu dependent. 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #ifdef _ASM 41 /* 42 * assembler doesn't understand the 'ull' suffix for C constants so 43 * use the inttypes.h macros and undefine them here for assembly code 44 */ 45 #undef INT64_C 46 #define INT64_C(x) (x) 47 #undef UINT64_C 48 #define UINT64_C(x) (x) 49 #endif /* _ASM */ 50 51 /* 52 * Synchronous Fault Physical Address Register 53 */ 54 #define OPL_MMU_SFPAR 0x78 55 56 /* 57 * ASI_MCNTL: MEMORY CONTROL Register layout (ASI 0x45, VA 8) 58 * 59 * +-------------------------+---------+--------+--------+-----+---------+ 60 * | reserved [63:17] | NC_Cache|fw_fITLB|fw_fDTLB|00000|JPS1_TSBP| 61 * +-------------------------+---------+--------+--------+-----+---------+ 62 * 16 15 14 13-9 8 63 * +---------+---------+------+ 64 * |mpg_sITLB|mpg_sDTLB|000000| 65 * +---------+---------+------+ 66 * 7 6 5-0 67 */ 68 #define ASI_MCNTL 0x45 69 #define LSU_MCNTL 0x8 /* vaddr offset of ASI_MCNTL */ 70 #define MCNTL_FW_FDTLB INT64_C(0x0000000000004000) 71 #define MCNTL_FW_FITLB INT64_C(0x0000000000008000) 72 #define MCNTL_JPS1_TSBP INT64_C(0x0000000000000100) 73 #define MCNTL_MPG_SITLB INT64_C(0x0000000000000080) 74 #define MCNTL_MPG_SDTLB INT64_C(0x0000000000000040) 75 #define MCNTL_SPECULATIVE_SHIFT 41 /* bit 41 is speculative mode bit */ 76 77 /* 78 * ASI_UGESR: URGENT ERROR STATES layout (ASI 0x4C, VA 0x8) 79 * 80 * +--------+---+----+----+---+---+--+--+---+---+-+----+----+----+ 81 * |0[63:23]|CRE|TSBX|TSBP|PST|TST| F| R|SDC|WDT|0|DTLB|ITLB|CORE| 82 * +--------+---+----+----+---+---+--+--+---+---+-+----+----+----+ 83 * 22 21 20 19 18 17 16 15 14 10 9 8 84 * +-------+----+---+---+---+ 85 * |INSTEND|PRIV|DAE|IAE|UGE| 86 * +-------+----+---+---+---+ 87 * 5 4 3 2 1 0 88 * 89 */ 90 #define ASI_UGERSR 0x8 91 #define UGESR_IAUG_CRE INT64_C(0x0000000000400000) 92 #define UGESR_IAUG_TSBCTXT INT64_C(0x0000000000200000) 93 #define UGESR_IUG_TSBP INT64_C(0x0000000000100000) 94 #define UGESR_IUG_PSTATE INT64_C(0x0000000000080000) 95 #define UGESR_IUG_TSTATE INT64_C(0x0000000000040000) 96 #define UGESR_IUG_F INT64_C(0x0000000000020000) 97 #define UGESR_IUG_R INT64_C(0x0000000000010000) 98 #define UGESR_AUG_SDC INT64_C(0x0000000000008000) 99 #define UGESR_IUG_WDT INT64_C(0x0000000000004000) 100 #define UGESR_IUG_DTLB INT64_C(0x0000000000000400) 101 #define UGESR_IUG_ITLB INT64_C(0x0000000000000200) 102 #define UGESR_IUG_COREERR INT64_C(0x0000000000000100) 103 #define UGESR_PRIV INT64_C(0x0000000000000008) 104 #define UGESR_MULTI_DAE INT64_C(0x0000000000000004) 105 #define UGESR_MULTI_IAE INT64_C(0x0000000000000002) 106 #define UGESR_MULTI_UGE INT64_C(0x0000000000000001) 107 108 #define UGESR_CAN_RECOVER (UGESR_IUG_DTLB | \ 109 UGESR_IUG_ITLB | \ 110 UGESR_IUG_COREERR) 111 112 #define UGESR_MULTI (UGESR_MULTI_DAE | \ 113 UGESR_MULTI_IAE | \ 114 UGESR_MULTI_UGE) 115 116 #define UGESR_NOSYNC_PANIC (UGESR_IAUG_CRE | \ 117 UGESR_AUG_SDC | \ 118 UGESR_MULTI_DAE | \ 119 UGESR_MULTI_IAE | \ 120 UGESR_MULTI_UGE) 121 /* 122 * The value means 10000 Mz per 10ms. 123 */ 124 #define OPL_UGER_STICK_DIFF 10000 125 126 127 /* 128 * ASI_ECR: Control of Error Action layout (ASI 0x4C, VA 0x10) 129 * 130 * +-------------------------+------+--------+-----+-------+-----------+ 131 * | reserved [63:10] |RTE_UE|RTE_CEDG|0...0|WEAK_ED|UGE_HANDLER| 132 * +-------------------------+------+--------+-----+-------+-----------+ 133 * 9 8 7 - 2 1 0 134 * 135 */ 136 #define ASI_ECR ASI_AFSR 137 #define AFSR_ECR 0x10 138 #define ASI_ECR_RTE_UE INT64_C(0x0000000000000200) 139 #define ASI_ECR_RTE_CEDG INT64_C(0x0000000000000100) 140 #define ASI_ECR_WEAK_ED INT64_C(0x0000000000000002) 141 #define ASI_ECR_UGE_HANDLER INT64_C(0x0000000000000001) 142 143 144 /* 145 * ASI_L2_CTRL: Level-2 Cache Control Register (ASI 0x6A, VA 0x10) 146 * 147 * +---------------------+--------+-----+---------+----+--------+ 148 * | reserved[63:25] |UGE_TRAP|0...0|NUMINSWAY|0..0|U2_FLUSH| 149 * +---------------------+--------+-----+---------+----+--------+ 150 * 24 23 19 18 16 15 1 0 151 * 152 */ 153 #define ASI_L2_CTRL 0x6A /* L2$ Control Register */ 154 #define ASI_L2_CTRL_RW_ADDR 0x10 155 #define ASI_L2_CTRL_UGE_TRAP INT64_C(0x0000000001000000) 156 #define ASI_L2_CTRL_NUMINSWAY_MASK INT64_C(0x0000000000070000) 157 #define ASI_L2_CTRL_U2_FLUSH INT64_C(0x0000000000000001) 158 159 160 /* 161 * Synchronous Fault Status Register Layout (ASI 0x50/0x58, VA 0x18) 162 * 163 * IMMU and DMMU maintain their own SFSR Register 164 * 165 * +----+----+-----+----+--+-----+--+---+-+----+--+--+-----+--+-+ 166 * |TLB#|0..0|index|0..0|MK| EID |UE|UPA|0|mTLB|NC|NF| ASI |TM|0| 167 * +----+----+-----+----+--+-----+--+---+-+----+--+--+-----+--+-+ 168 * 63 62 61 58 48 46 45 32 31 30 28 27 25 24 23 16 15 14 169 * +----+-+---+--+-+--+--+ 170 * | FT |E| CT|PR|W|OW|FV| 171 * +----+-+---+--+-+--+--+ 172 * 13 7 6 5 4 3 2 1 0 173 * 174 */ 175 #define SFSR_MK_UE INT64_C(0x0000400000000000) 176 #define SFSR_EID_MOD INT64_C(0x0000300000000000) 177 #define SFSR_EID_SID INT64_C(0x00000FFF00000000) 178 #define SFSR_UE INT64_C(0x0000000080000000) 179 #define SFSR_BERR INT64_C(0x0000000040000000) 180 #define SFSR_TO INT64_C(0x0000000020000000) 181 #define SFSR_TLB_MUL INT64_C(0x0000000008000000) 182 #define SFSR_TLB_PRT INT64_C(0x0000000004000000) 183 184 #define SFSR_EID_MOD_SHIFT 44 185 #define SFSR_EID_SID_SHIFT 32 186 187 /* 188 * Error Mark ID: Module Type 189 */ 190 #define OPL_ERRID_MEM 0 191 #define OPL_ERRID_CHANNEL 1 192 #define OPL_ERRID_CPU 2 193 #define OPL_ERRID_PATH 3 194 195 196 #define SFSR_ERRS (SFSR_UE | SFSR_BERR | \ 197 SFSR_TO | SFSR_TLB_MUL | \ 198 SFSR_TLB_PRT) 199 200 #define SFSR_MEMORY (SFSR_UE | \ 201 SFSR_BERR | \ 202 SFSR_TO) 203 204 /* 205 * Miscellaneous ASI definitions 206 */ 207 #define ASI_IIU_INST_TRAP 0x60 /* Instruction breakpoint */ 208 #define ASI_ALL_FLUSH_L1I 0x67 /* Flush Level-1 Inst. cache */ 209 #define ASI_L2_TAG_READ 0x6B /* L2 Diagnostics Tag Read */ 210 #define ASI_L2_TAG_READ_REG 0x6C /* L2 Diagnostics Tag Read Register */ 211 #define ASI_EIDR 0x6E /* Urgent errors */ 212 #define ASI_CACHE_INV 0x74 /* Cache invalidation */ 213 #define ASI_ERR_INJCT 0x76 /* Error injection */ 214 /* 215 * Address of ASI scratch register. ASI 0x4F 216 */ 217 #define OPL_SCRATCHPAD_SAVE_AG1 0x00 /* used for saving global registers */ 218 #define OPL_SCRATCHPAD_SAVE_AG2 0x08 /* used for saving global registers */ 219 #define OPL_SCRATCHPAD_SAVE_AG3 0x10 /* used for saving global registers */ 220 #define OPL_SCRATCHPAD_ERRLOG 0x18 /* keeps EIDR, log's PA & err counter */ 221 #define OPL_SCRATCHPAD_UTSBREG4 0x20 222 #define OPL_SCRATCHPAD_UTSBREG5 0x28 223 #define OPL_SCRATCHPAD_UTSBREG6 0x30 224 #define OPL_SCRATCHPAD_UNUSED7 0x38 225 226 /* 227 * Error log scratchpad register format. 228 * 229 * +--------+-------------------+----------+ 230 * |ASI_EIDR| PA to logging buf | # of err | 231 * +--------+-------------------+----------+ 232 * 63 50 49 6 5 0 233 * 234 */ 235 236 #define ERRLOG_REG_LOGPA_MASK INT64_C(0x0003ffffffffffc0) /* PA to log */ 237 #define ERRLOG_REG_NUMERR_MASK INT64_C(0x000000000000003f) /* Counter */ 238 #define ERRLOG_REG_EIDR_MASK INT64_C(0x0000000000003fff) /* EIDR */ 239 240 #define ERRLOG_REG_EIDR_SHIFT 50 241 #define ERRLOG_REG_ERR_SHIFT 6 242 #define ERRLOG_REG_EIDR(reg) ((reg >> ERRLOG_REG_EIDR_SHIFT) & \ 243 ERRLOG_REG_EIDR_MASK) 244 #define ERRLOG_REG_LOGPA(reg) (reg & ERRLOG_REG_LOGPA_MASK) 245 #define ERRLOG_REG_NUMERR(reg) (reg & ERRLOG_REG_NUMERR_MASK) 246 247 #define ERRLOG_BUFSZ 0x2000 248 #define ERRLOG_SZ (1 << ERRLOG_REG_ERR_SHIFT) 249 #define ERRLOG_ALLOC_SZ (ERRLOG_BUFSZ * 512) 250 251 /* 252 * Olympus-C default cache parameters. 253 */ 254 #define OPL_DCACHE_SIZE 0x20000 255 #define OPL_DCACHE_LSIZE 0x40 256 #define OPL_ICACHE_SIZE 0x20000 257 #define OPL_ICACHE_LSIZE 0x40 258 #define OPL_ECACHE_SIZE 0x600000 259 #define OPL_ECACHE_LSIZE 0x100 260 #define OPL_ECACHE_NWAY 12 261 #define OPL_ECACHE_SETSIZE 0x80000 262 263 /* 264 * OPL platform has no vac consistent issue. So set it to 8KB. 265 */ 266 #define OPL_VAC_SIZE 0x2000 267 268 /* these are field offsets for opl_errlog structure */ 269 #define LOG_STICK_OFF 0x0 270 #define LOG_TL_OFF 0x8 271 #define LOG_ASI3_OFF 0x10 272 #define LOG_SFSR_OFF 0x18 273 #define LOG_SFAR_OFF 0x20 274 275 #define LOG_UGER_OFF 0x18 276 #define LOG_TSTATE_OFF 0x20 277 #define LOG_TPC_OFF 0x28 278 279 #ifndef _ASM 280 typedef struct opl_errlog { 281 uint64_t stick; 282 uint32_t tl; 283 uint32_t tt; 284 uint64_t asi3; 285 union { 286 struct { 287 uint64_t sfsr; 288 union { 289 uint64_t sfar; 290 uint64_t sfpar; 291 } sync_addr; 292 } sync; 293 struct { 294 uint64_t ugesr; 295 uint64_t tstate; 296 } ugesr; 297 } reg; 298 uint64_t tpc; 299 } opl_errlog_t; 300 #endif /* _ASM */ 301 302 #ifdef __cplusplus 303 } 304 #endif 305 306 #endif /* _SYS_OPL_OLYMPUS_REGS_H */ 307