1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MC_US3_H 28 #define _SYS_MC_US3_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined(_KERNEL) 37 38 #define NBANKS 4 39 #define NDGRPS 2 40 #define NDIMMS 4 41 #define MAX_DEVLEN 8 42 #define TRANSFER_SIZE 64 43 44 #ifndef _ASM 45 46 struct mc_soft_state { 47 dev_info_t *dip; /* dev info of myself */ 48 int portid; 49 int size; 50 void *memlayoutp; 51 volatile uchar_t *mc_base; /* Mapped base address of MC registers */ 52 }; 53 54 struct dimm_info { 55 char label[NDGRPS * NDIMMS][MAX_DEVLEN]; /* dimm label */ 56 char sym_flag; /* 1: symmetric 0: asymmetric */ 57 char data[1]; 58 }; 59 60 typedef char dimm_sid_t[DIMM_SERIAL_ID_LEN]; 61 62 struct pin_info { 63 uchar_t dimmtable[144]; 64 uchar_t pintable[576]; 65 }; 66 67 /* This struct is included at the following structs to set up list */ 68 typedef struct mc_dlist { 69 struct mc_dlist *next; 70 struct mc_dlist *prev; 71 int id; 72 } mc_dlist_t; 73 74 /* unique segment id */ 75 struct seg_info { 76 mc_dlist_t seg_node; 77 int nbanks; /* The number of banks at this segment */ 78 uint32_t ifactor; /* Max interleave factor at this segment */ 79 uint64_t base; 80 uint64_t size; /* memory size per segment */ 81 struct bank_info *hb_inseg; /* first bank at this segment */ 82 struct bank_info *tb_inseg; /* last bank at this segment */ 83 }; 84 85 /* id = mc_id * nbanks + bank_no */ 86 struct bank_info { 87 mc_dlist_t bank_node; 88 int local_id; /* unique local bank id per segment */ 89 int seg_id; /* unique segment id */ 90 int devgrp_id; /* unique device group id */ 91 ushort_t valid; /* valid flag per logic bank */ 92 ushort_t uk; /* Upper Mask field to mask match 4 PA[37:26] */ 93 uint_t um; /* Upper Match field to match PA[42:26] */ 94 uchar_t lk; /* Lower Mask field to mask match 4 PA[9:6] */ 95 uchar_t lm; /* Lower Match field to match PA[9:6] */ 96 uchar_t pos; /* front=0, back=1 */ 97 uint64_t size; /* memory size per logical bank */ 98 struct bank_info *n_inseg; /* next bank at the same segment */ 99 struct bank_info *p_inseg; /* previous bank at the same segment */ 100 struct dimm_info *dimminfop; 101 dimm_sid_t *dimmsidp[NDIMMS]; 102 }; 103 104 /* id = mc_id * ndevgrps + devgrp_no */ 105 struct dgrp_info { 106 mc_dlist_t dgrp_node; 107 int ndevices; /* The number of available devices on this dev group */ 108 uint64_t size; /* memory size per physical dimm group */ 109 int deviceids[NDIMMS]; /* 4 dimms per group on excalibur */ 110 }; 111 112 /* id = id of dgrp_info * ndevices + device_no */ 113 struct device_info { 114 mc_dlist_t dev_node; 115 char label[MAX_DEVLEN]; 116 uint64_t size; /* memory size per physical dimm */ 117 }; 118 119 /* id = portid */ 120 struct mctrl_info { 121 mc_dlist_t mctrl_node; 122 int ndevgrps; /* The number of dimm groups */ 123 int devgrpids[NDGRPS]; 124 }; 125 126 typedef struct dimm_sid_cache { 127 int mcid; /* mc portid */ 128 int seg_id; /* segment these DIMMs are in */ 129 int state; /* state of cache for this mc */ 130 dimm_sid_t *sids; /* ptr to array of serial ids */ 131 } dimm_sid_cache_t; 132 133 /* values for the state field of a dimm_sid_cache_t */ 134 #define MC_DIMM_SIDS_INVALID 0 135 #define MC_DIMM_SIDS_REQUESTED 1 136 #define MC_DIMM_SIDS_AVAILABLE 2 137 138 extern int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 139 extern int (*p2get_mem_info)(int, uint64_t, uint64_t *, uint64_t *, 140 uint64_t *, int *, int *, int *); 141 extern int (*p2get_mem_offset)(uint64_t, uint64_t *); 142 extern int (*p2get_mem_addr)(int, char *, uint64_t, uint64_t *); 143 extern int (*p2get_mem_sid)(int, int, char *, int, int *); 144 extern int (*p2init_sid_cache)(void); 145 extern void plat_add_mem_unum_label(char *, int, int, int); 146 extern dimm_sid_cache_t *plat_alloc_sid_cache(int *); 147 extern int plat_populate_sid_cache(dimm_sid_cache_t *, int); 148 149 uint64_t get_mcr(int); 150 151 #ifdef DEBUG 152 153 #include <sys/promif.h> 154 155 /* useful debugging level of DPRINTF */ 156 #define MC_ATTACH_DEBUG 0x00000001 157 #define MC_DETACH_DEBUG 0x00000002 158 #define MC_CMD_DEBUG 0x00000004 159 #define MC_REG_DEBUG 0x00000008 160 #define MC_GUNUM_DEBUG 0x00000010 161 #define MC_CNSTRC_DEBUG 0x00000020 162 #define MC_DESTRC_DEBUG 0x00000040 163 #define MC_LIST_DEBUG 0x00000080 164 165 static uint_t mc_debug = 0; 166 167 #define _PRINTF prom_printf 168 #define DPRINTF(flag, args) if (mc_debug & flag) _PRINTF args; 169 #else 170 #define DPRINTF(flag, args) 171 172 #endif /* DEBUG */ 173 174 #endif /* !_ASM */ 175 176 /* Memory Address Decoding Registers */ 177 #define ASI_MCU_CTRL 0x72 178 #define REGOFFSET 8 179 #define MADR0OFFSET 0x10 180 181 /* Mask and shift constants for Memory Address Decoding */ 182 #define MADR_UPA_MASK 0x7fffc000000LL /* 17 bits */ 183 #define MADR_LPA_MASK 0x000000003c0LL /* 4 bits */ 184 #define MADR_LK_MASK 0x0000003c000LL /* 4 bits */ 185 186 #define MADR_UPA_SHIFT 26 187 #define MADR_LPA_SHIFT 6 188 #define MADR_LK_SHIFT 14 189 190 #endif /* _KERNEL */ 191 192 #ifdef __cplusplus 193 } 194 #endif 195 196 #endif /* _SYS_MC_US3_H */ 197