1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MACHASI_H 28 #define _SYS_MACHASI_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Spitfire ancillary state registers, for asrset_t 38 */ 39 #define ASR_GSR (3) 40 41 /* 42 * alternate address space identifiers 43 * 44 * 0x00 - 0x7F are privileged 45 * 0x80 - 0xFF can be used by users 46 */ 47 48 49 /* 50 * UltraSPARC ASIs 51 */ 52 #define ASI_NQUAD_LD 0x24 /* 128-bit atomic load */ 53 #define ASI_NQUAD_LD_L 0x2c /* 128-bit atomic load little */ 54 55 #define ASI_QUAD_LDD_PHYS 0x34 /* 128-bit physical atomic load */ 56 #define ASI_QUAD_LDD_PHYS_L 0x3C /* 128-bit phys. atomic load little */ 57 58 #define ASI_INTR_DISPATCH_STATUS 0x48 /* interrupt vector dispatch status */ 59 #define ASI_INTR_RECEIVE_STATUS 0x49 /* interrupt vector receive status */ 60 61 #define ASI_BLK_AIUP 0x70 /* block as if user primary */ 62 #define ASI_BLK_AIUS 0x71 /* block as if user secondary */ 63 64 #define ASI_SDB_INTR_W 0x77 /* interrupt vector dispatch */ 65 #define ASI_SDB_INTR_R 0x7F /* incoming interrupt vector */ 66 #define ASI_INTR_DISPATCH ASI_SDB_INTR_W 67 #define ASI_INTR_RECEIVE ASI_SDB_INTR_R 68 69 #define ASI_BLK_AIUPL 0x78 /* block as if user primary little */ 70 #define ASI_BLK_AIUSL 0x79 /* block as if user secondary little */ 71 72 /* 73 * Spitfire asis 74 */ 75 #define ASI_LSU 0x45 /* load-store unit control */ 76 #define ASI_DC_INVAL 0x42 /* d$ invalidate */ 77 78 79 #define ASI_DC_DATA 0x46 /* d$ data */ 80 #define ASI_DC_TAG 0x47 /* d$ tag */ 81 82 #define ASI_UPA_CONFIG 0x4A /* upa configuration reg */ 83 84 #define ASI_ESTATE_ERR 0x4B /* estate error enable reg */ 85 86 #define ASI_AFSR 0x4C /* asynchronous fault status */ 87 #define ASI_AFAR 0x4D /* asynchronous fault address */ 88 89 #define ASI_IMMU 0x50 /* instruction mmu */ 90 #define ASI_IMMU_TSB_8K 0x51 /* immu tsb 8k ptr */ 91 #define ASI_IMMU_TSB_64K 0x52 /* immu tsb 64k ptr */ 92 #define ASI_DEVICE_SERIAL_ID 0x53 /* device serial id */ 93 #define ASI_ITLB_IN 0x54 /* immu tlb data in */ 94 #define ASI_ITLB_ACCESS 0x55 /* immu tlb data access */ 95 #define ASI_ITLB_TAGREAD 0x56 /* immu tlb tag read */ 96 #define ASI_ITLB_DEMAP 0x57 /* immu tlb demap */ 97 98 #define ASI_DMMU 0x58 /* data mmu */ 99 #define ASI_MMU_CTX ASI_DMMU 100 #define ASI_DMMU_TSB_8K 0x59 /* dmmu tsb 8k ptr */ 101 #define ASI_DMMU_TSB_64K 0x5A /* dmmu tsb 64k ptr */ 102 #define ASI_DMMU_TSB_DIRECT 0x5B /* dmmu tsb direct ptr */ 103 #define ASI_DTLB_IN 0x5C /* dmmu tlb data in */ 104 #define ASI_DTLB_ACCESS 0x5D /* dmmu tlb data access */ 105 #define ASI_DTLB_TAGREAD 0x5E /* dmmu tlb tag read */ 106 #define ASI_DTLB_DEMAP 0x5F /* dmmu tlb demap */ 107 108 #define ASI_IC_DATA 0x66 /* i$ data */ 109 #define ASI_IC_TAG 0x67 /* i$ tag */ 110 #define ASI_IC_DECODE 0x6E /* i$ pre-decode */ 111 #define ASI_IC_NEXT 0x6F /* i$ next field */ 112 113 #define ASI_EC_W 0x76 /* e$ access write */ 114 #define ASI_EC_R 0x7E /* e$ access read */ 115 #define ASI_EC_DIAG 0x4E /* e$ diagnostic reg */ 116 /* PRM calls this ASI_ECACHE_TAG */ 117 118 #ifdef __cplusplus 119 } 120 #endif 121 122 #endif /* _SYS_MACHASI_H */ 123