1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/debug.h> 29 #include <sys/types.h> 30 #include <sys/varargs.h> 31 #include <sys/errno.h> 32 #include <sys/cred.h> 33 #include <sys/dditypes.h> 34 #include <sys/devops.h> 35 #include <sys/modctl.h> 36 #include <sys/poll.h> 37 #include <sys/conf.h> 38 #include <sys/ddi.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/ndi_impldefs.h> 42 #include <sys/stat.h> 43 #include <sys/kmem.h> 44 #include <sys/vmem.h> 45 #include <sys/processor.h> 46 #include <sys/spitregs.h> 47 #include <sys/cpuvar.h> 48 #include <sys/cpupart.h> 49 #include <sys/mem_config.h> 50 #include <sys/ddi_impldefs.h> 51 #include <sys/systm.h> 52 #include <sys/machsystm.h> 53 #include <sys/autoconf.h> 54 #include <sys/cmn_err.h> 55 #include <sys/sysmacros.h> 56 #include <sys/x_call.h> 57 #include <sys/promif.h> 58 #include <sys/prom_plat.h> 59 #include <sys/membar.h> 60 #include <vm/seg_kmem.h> 61 #include <sys/mem_cage.h> 62 #include <sys/stack.h> 63 #include <sys/archsystm.h> 64 #include <vm/hat_sfmmu.h> 65 #include <sys/pte.h> 66 #include <sys/mmu.h> 67 #include <sys/cpu_module.h> 68 #include <sys/obpdefs.h> 69 #include <sys/note.h> 70 71 #include <sys/starfire.h> /* plat_max_... decls */ 72 #include <sys/cvc.h> 73 #include <sys/cpu_sgnblk_defs.h> 74 #include <sys/drmach.h> 75 #include <sys/dr_util.h> 76 #include <sys/pda.h> 77 78 #include <sys/sysevent.h> 79 #include <sys/sysevent/dr.h> 80 #include <sys/sysevent/eventdefs.h> 81 82 83 extern void bcopy32_il(uint64_t, uint64_t); 84 extern void flush_ecache_il( 85 uint64_t physaddr, int size, int linesz); 86 extern uint_t ldphysio_il(uint64_t physaddr); 87 extern void stphysio_il(uint64_t physaddr, uint_t value); 88 89 extern uint64_t mc_get_mem_alignment(void); 90 extern uint64_t mc_get_asr_addr(pnode_t); 91 extern uint64_t mc_get_idle_addr(pnode_t); 92 extern uint64_t mc_get_alignment_mask(pnode_t); 93 extern int mc_read_asr(pnode_t, uint_t *); 94 extern int mc_write_asr(pnode_t, uint_t); 95 extern uint64_t mc_asr_to_pa(uint_t); 96 extern uint_t mc_pa_to_asr(uint_t, uint64_t); 97 98 extern int pc_madr_add(int, int, int, int); 99 100 typedef struct { 101 struct drmach_node *node; 102 void *data; 103 } drmach_node_walk_args_t; 104 105 typedef struct drmach_node { 106 void *here; 107 108 pnode_t (*get_dnode)(struct drmach_node *node); 109 int (*walk)(struct drmach_node *node, void *data, 110 int (*cb)(drmach_node_walk_args_t *args)); 111 } drmach_node_t; 112 113 typedef struct { 114 int min_index; 115 int max_index; 116 int arr_sz; 117 drmachid_t *arr; 118 } drmach_array_t; 119 120 typedef struct { 121 void *isa; 122 123 sbd_error_t *(*release)(drmachid_t); 124 sbd_error_t *(*status)(drmachid_t, drmach_status_t *); 125 126 char name[MAXNAMELEN]; 127 } drmach_common_t; 128 129 typedef struct { 130 drmach_common_t cm; 131 int bnum; 132 int assigned; 133 int powered; 134 int connect_cpuid; 135 int cond; 136 drmach_node_t *tree; 137 drmach_array_t *devices; 138 } drmach_board_t; 139 140 typedef struct { 141 drmach_common_t cm; 142 drmach_board_t *bp; 143 int unum; 144 int busy; 145 int powered; 146 const char *type; 147 drmach_node_t *node; 148 } drmach_device_t; 149 150 typedef struct { 151 int flags; 152 drmach_device_t *dp; 153 sbd_error_t *err; 154 dev_info_t *dip; 155 } drmach_config_args_t; 156 157 typedef struct { 158 uint64_t idle_addr; 159 drmach_device_t *mem; 160 } drmach_mc_idle_script_t; 161 162 typedef struct { 163 uint64_t masr_addr; 164 uint_t masr; 165 uint_t _filler; 166 } drmach_rename_script_t; 167 168 typedef struct { 169 void (*run)(void *arg); 170 caddr_t data; 171 pda_handle_t *ph; 172 struct memlist *c_ml; 173 uint64_t s_copybasepa; 174 uint64_t t_copybasepa; 175 drmach_device_t *restless_mc; /* diagnostic output */ 176 } drmach_copy_rename_program_t; 177 178 typedef enum { 179 DO_IDLE, 180 DO_UNIDLE, 181 DO_PAUSE, 182 DO_UNPAUSE 183 } drmach_iopc_op_t; 184 185 typedef struct { 186 drmach_board_t *obj; 187 int ndevs; 188 void *a; 189 sbd_error_t *(*found)(void *a, const char *, int, drmachid_t); 190 sbd_error_t *err; 191 } drmach_board_cb_data_t; 192 193 static caddr_t drmach_shutdown_va; 194 195 static int drmach_initialized; 196 static drmach_array_t *drmach_boards; 197 198 static int drmach_cpu_delay = 100; 199 static int drmach_cpu_ntries = 50000; 200 201 volatile uchar_t *drmach_xt_mb; 202 203 /* 204 * Do not change the drmach_shutdown_mbox structure without 205 * considering the drmach_shutdown_asm assembly language code. 206 */ 207 struct drmach_shutdown_mbox { 208 uint64_t estack; 209 uint64_t flushaddr; 210 int size; 211 int linesize; 212 uint64_t physaddr; 213 }; 214 struct drmach_shutdown_mbox *drmach_shutdown_asm_mbox; 215 static sbd_error_t *drmach_device_new(drmach_node_t *, 216 drmach_board_t *, drmach_device_t **); 217 static sbd_error_t *drmach_cpu_new(drmach_device_t *); 218 static sbd_error_t *drmach_mem_new(drmach_device_t *); 219 static sbd_error_t *drmach_io_new(drmach_device_t *); 220 221 extern struct cpu *SIGBCPU; 222 223 #ifdef DEBUG 224 225 #define DRMACH_PR if (drmach_debug) printf 226 int drmach_debug = 0; /* set to non-zero to enable debug messages */ 227 #else 228 229 #define DRMACH_PR _NOTE(CONSTANTCONDITION) if (0) printf 230 #endif /* DEBUG */ 231 232 #define DRMACH_OBJ(id) ((drmach_common_t *)id) 233 234 #define DRMACH_IS_BOARD_ID(id) \ 235 ((id != 0) && \ 236 (DRMACH_OBJ(id)->isa == (void *)drmach_board_new)) 237 238 #define DRMACH_IS_CPU_ID(id) \ 239 ((id != 0) && \ 240 (DRMACH_OBJ(id)->isa == (void *)drmach_cpu_new)) 241 242 #define DRMACH_IS_MEM_ID(id) \ 243 ((id != 0) && \ 244 (DRMACH_OBJ(id)->isa == (void *)drmach_mem_new)) 245 246 #define DRMACH_IS_IO_ID(id) \ 247 ((id != 0) && \ 248 (DRMACH_OBJ(id)->isa == (void *)drmach_io_new)) 249 250 #define DRMACH_IS_DEVICE_ID(id) \ 251 ((id != 0) && \ 252 (DRMACH_OBJ(id)->isa == (void *)drmach_cpu_new || \ 253 DRMACH_OBJ(id)->isa == (void *)drmach_mem_new || \ 254 DRMACH_OBJ(id)->isa == (void *)drmach_io_new)) 255 256 #define DRMACH_IS_ID(id) \ 257 ((id != 0) && \ 258 (DRMACH_OBJ(id)->isa == (void *)drmach_board_new || \ 259 DRMACH_OBJ(id)->isa == (void *)drmach_cpu_new || \ 260 DRMACH_OBJ(id)->isa == (void *)drmach_mem_new || \ 261 DRMACH_OBJ(id)->isa == (void *)drmach_io_new)) 262 263 #define DRMACH_CPUID2BNUM(cpuid) \ 264 ((cpuid) / MAX_CPU_UNITS_PER_BOARD) 265 266 #define DRMACH_INTERNAL_ERROR() \ 267 drerr_new(1, ESTF_INTERNAL, drmach_ie_fmt, __LINE__) 268 static char *drmach_ie_fmt = "drmach.c %d"; 269 270 static struct { 271 const char *name; 272 const char *type; 273 sbd_error_t *(*new)(drmach_device_t *); 274 } name2type[] = { 275 { "SUNW,UltraSPARC", DRMACH_DEVTYPE_CPU, drmach_cpu_new }, 276 { "mem-unit", DRMACH_DEVTYPE_MEM, drmach_mem_new }, 277 { "pci", DRMACH_DEVTYPE_PCI, drmach_io_new }, 278 { "sbus", DRMACH_DEVTYPE_SBUS, drmach_io_new }, 279 }; 280 281 /* node types to cleanup when a board is unconfigured */ 282 #define MISC_COUNTER_TIMER_DEVNAME "counter-timer" 283 #define MISC_PERF_COUNTER_DEVNAME "perf-counter" 284 285 /* utility */ 286 #define MBYTE (1048576ull) 287 288 /* 289 * This is necessary because the CPU support needs 290 * to call cvc_assign_iocpu. 291 */ 292 #ifndef lint 293 char _depends_on[] = "drv/cvc"; 294 #endif /* lint */ 295 296 /* 297 * drmach autoconfiguration data structures and interfaces 298 */ 299 300 extern struct mod_ops mod_miscops; 301 302 static struct modlmisc modlmisc = { 303 &mod_miscops, 304 "Sun Enterprise 10000 DR %I%" 305 }; 306 307 static struct modlinkage modlinkage = { 308 MODREV_1, 309 (void *)&modlmisc, 310 NULL 311 }; 312 313 static kmutex_t drmach_i_lock; 314 315 int 316 _init(void) 317 { 318 int err; 319 320 /* check that we have the correct version of obp */ 321 if (prom_test("SUNW,UE10000,add-brd") != 0) { 322 323 cmn_err(CE_WARN, "!OBP/SSP upgrade is required to enable " 324 "DR Functionality"); 325 326 return (-1); 327 } 328 329 mutex_init(&drmach_i_lock, NULL, MUTEX_DRIVER, NULL); 330 331 drmach_xt_mb = (uchar_t *)vmem_alloc(static_alloc_arena, 332 NCPU * sizeof (uchar_t), VM_SLEEP); 333 drmach_shutdown_asm_mbox = (struct drmach_shutdown_mbox *) 334 vmem_alloc(static_alloc_arena, sizeof (struct drmach_shutdown_mbox), 335 VM_SLEEP); 336 337 if ((err = mod_install(&modlinkage)) != 0) { 338 mutex_destroy(&drmach_i_lock); 339 vmem_free(static_alloc_arena, (void *)drmach_xt_mb, 340 NCPU * sizeof (uchar_t)); 341 vmem_free(static_alloc_arena, (void *)drmach_shutdown_asm_mbox, 342 sizeof (struct drmach_shutdown_mbox)); 343 } 344 345 return (err); 346 } 347 348 int 349 _fini(void) 350 { 351 static int drmach_fini(void); 352 353 if (drmach_fini()) 354 return (DDI_FAILURE); 355 else 356 return (mod_remove(&modlinkage)); 357 } 358 359 int 360 _info(struct modinfo *modinfop) 361 { 362 return (mod_info(&modlinkage, modinfop)); 363 } 364 365 static pnode_t 366 drmach_node_obp_get_dnode(drmach_node_t *np) 367 { 368 return ((pnode_t)(uintptr_t)np->here); 369 } 370 371 static int 372 drmach_node_obp_walk(drmach_node_t *np, void *data, 373 int (*cb)(drmach_node_walk_args_t *args)) 374 { 375 pnode_t nodeid; 376 int rv; 377 drmach_node_walk_args_t args; 378 379 /* initialized args structure for callback */ 380 args.node = np; 381 args.data = data; 382 383 nodeid = prom_childnode(prom_rootnode()); 384 385 /* save our new position with in the tree */ 386 np->here = (void *)(uintptr_t)nodeid; 387 388 rv = 0; 389 while (nodeid != OBP_NONODE) { 390 rv = (*cb)(&args); 391 if (rv) 392 break; 393 394 nodeid = prom_nextnode(nodeid); 395 396 /* save our new position with in the tree */ 397 np->here = (void *)(uintptr_t)nodeid; 398 } 399 400 return (rv); 401 } 402 403 static drmach_node_t * 404 drmach_node_new(void) 405 { 406 drmach_node_t *np; 407 408 np = kmem_zalloc(sizeof (drmach_node_t), KM_SLEEP); 409 410 np->get_dnode = drmach_node_obp_get_dnode; 411 np->walk = drmach_node_obp_walk; 412 413 return (np); 414 } 415 416 static void 417 drmach_node_dispose(drmach_node_t *np) 418 { 419 kmem_free(np, sizeof (*np)); 420 } 421 422 static dev_info_t * 423 drmach_node_get_dip(drmach_node_t *np) 424 { 425 pnode_t nodeid; 426 427 nodeid = np->get_dnode(np); 428 if (nodeid == OBP_NONODE) 429 return (NULL); 430 else { 431 dev_info_t *dip; 432 433 /* The root node doesn't have to be held */ 434 dip = e_ddi_nodeid_to_dip(nodeid); 435 if (dip) { 436 /* 437 * Branch rooted at dip is already held, so release 438 * hold acquired in e_ddi_nodeid_to_dip() 439 */ 440 ddi_release_devi(dip); 441 ASSERT(e_ddi_branch_held(dip)); 442 } 443 444 return (dip); 445 } 446 /*NOTREACHED*/ 447 } 448 449 static pnode_t 450 drmach_node_get_dnode(drmach_node_t *np) 451 { 452 return (np->get_dnode(np)); 453 } 454 455 static int 456 drmach_node_walk(drmach_node_t *np, void *param, 457 int (*cb)(drmach_node_walk_args_t *args)) 458 { 459 return (np->walk(np, param, cb)); 460 } 461 462 static int 463 drmach_node_get_prop(drmach_node_t *np, char *name, void *buf) 464 { 465 pnode_t nodeid; 466 int rv; 467 468 nodeid = np->get_dnode(np); 469 if (nodeid == OBP_NONODE) 470 rv = -1; 471 else if (prom_getproplen(nodeid, (caddr_t)name) < 0) 472 rv = -1; 473 else { 474 (void) prom_getprop(nodeid, (caddr_t)name, (caddr_t)buf); 475 rv = 0; 476 } 477 478 return (rv); 479 } 480 481 static int 482 drmach_node_get_proplen(drmach_node_t *np, char *name, int *len) 483 { 484 pnode_t nodeid; 485 int rv; 486 487 nodeid = np->get_dnode(np); 488 if (nodeid == OBP_NONODE) 489 rv = -1; 490 else { 491 *len = prom_getproplen(nodeid, (caddr_t)name); 492 rv = (*len < 0 ? -1 : 0); 493 } 494 495 return (rv); 496 } 497 498 static drmachid_t 499 drmach_node_dup(drmach_node_t *np) 500 { 501 drmach_node_t *dup; 502 503 dup = drmach_node_new(); 504 dup->here = np->here; 505 506 return (dup); 507 } 508 509 /* 510 * drmach_array provides convenient array construction, access, 511 * bounds checking and array destruction logic. 512 */ 513 514 static drmach_array_t * 515 drmach_array_new(int min_index, int max_index) 516 { 517 drmach_array_t *arr; 518 519 arr = kmem_zalloc(sizeof (drmach_array_t), KM_SLEEP); 520 521 arr->arr_sz = (max_index - min_index + 1) * sizeof (void *); 522 if (arr->arr_sz > 0) { 523 arr->min_index = min_index; 524 arr->max_index = max_index; 525 526 arr->arr = kmem_zalloc(arr->arr_sz, KM_SLEEP); 527 return (arr); 528 } else { 529 kmem_free(arr, sizeof (*arr)); 530 return (0); 531 } 532 } 533 534 static int 535 drmach_array_set(drmach_array_t *arr, int idx, drmachid_t val) 536 { 537 if (idx < arr->min_index || idx > arr->max_index) 538 return (-1); 539 else { 540 arr->arr[idx - arr->min_index] = val; 541 return (0); 542 } 543 /*NOTREACHED*/ 544 } 545 546 static int 547 drmach_array_get(drmach_array_t *arr, int idx, drmachid_t *val) 548 { 549 if (idx < arr->min_index || idx > arr->max_index) 550 return (-1); 551 else { 552 *val = arr->arr[idx - arr->min_index]; 553 return (0); 554 } 555 /*NOTREACHED*/ 556 } 557 558 static int 559 drmach_array_first(drmach_array_t *arr, int *idx, drmachid_t *val) 560 { 561 int rv; 562 563 *idx = arr->min_index; 564 while ((rv = drmach_array_get(arr, *idx, val)) == 0 && *val == NULL) 565 *idx += 1; 566 567 return (rv); 568 } 569 570 static int 571 drmach_array_next(drmach_array_t *arr, int *idx, drmachid_t *val) 572 { 573 int rv; 574 575 *idx += 1; 576 while ((rv = drmach_array_get(arr, *idx, val)) == 0 && *val == NULL) 577 *idx += 1; 578 579 return (rv); 580 } 581 582 static void 583 drmach_array_dispose(drmach_array_t *arr, void (*disposer)(drmachid_t)) 584 { 585 drmachid_t val; 586 int idx; 587 int rv; 588 589 rv = drmach_array_first(arr, &idx, &val); 590 while (rv == 0) { 591 (*disposer)(val); 592 rv = drmach_array_next(arr, &idx, &val); 593 } 594 595 kmem_free(arr->arr, arr->arr_sz); 596 kmem_free(arr, sizeof (*arr)); 597 } 598 599 /*ARGSUSED*/ 600 static int 601 drmach_prom_select(pnode_t nodeid, void *arg, uint_t flags) 602 { 603 int rprop[64]; 604 pnode_t saved; 605 drmach_config_args_t *ap = (drmach_config_args_t *)arg; 606 drmach_device_t *dp = ap->dp; 607 sbd_error_t *err; 608 609 saved = drmach_node_get_dnode(dp->node); 610 611 if (nodeid != saved) 612 return (DDI_FAILURE); 613 614 if (saved == OBP_NONODE) { 615 err = DRMACH_INTERNAL_ERROR(); 616 DRERR_SET_C(&ap->err, &err); 617 return (DDI_FAILURE); 618 } 619 620 if (prom_getprop(nodeid, OBP_REG, (caddr_t)rprop) <= 0) { 621 return (DDI_FAILURE); 622 } 623 624 return (DDI_SUCCESS); 625 } 626 627 /*ARGSUSED*/ 628 static void 629 drmach_branch_callback(dev_info_t *rdip, void *arg, uint_t flags) 630 { 631 drmach_config_args_t *ap = (drmach_config_args_t *)arg; 632 633 ASSERT(ap->dip == NULL); 634 635 ap->dip = rdip; 636 } 637 638 sbd_error_t * 639 drmach_configure(drmachid_t id, int flags) 640 { 641 drmach_device_t *dp; 642 sbd_error_t *err; 643 drmach_config_args_t ca; 644 devi_branch_t b = {0}; 645 dev_info_t *fdip = NULL; 646 647 if (!DRMACH_IS_DEVICE_ID(id)) 648 return (drerr_new(0, ESTF_INAPPROP, NULL)); 649 dp = id; 650 651 ca.dp = dp; 652 ca.flags = flags; 653 ca.err = NULL; /* will be set if error detected */ 654 ca.dip = NULL; 655 656 b.arg = &ca; 657 b.type = DEVI_BRANCH_PROM; 658 b.create.prom_branch_select = drmach_prom_select; 659 b.devi_branch_callback = drmach_branch_callback; 660 661 if (e_ddi_branch_create(ddi_root_node(), &b, &fdip, 662 DEVI_BRANCH_CHILD | DEVI_BRANCH_CONFIGURE) != 0) { 663 char *path = kmem_alloc(MAXPATHLEN, KM_SLEEP); 664 665 /* 666 * If non-NULL, fdip is returned held and must be released. 667 */ 668 if (fdip != NULL) { 669 (void) ddi_pathname(fdip, path); 670 ddi_release_devi(fdip); 671 } else if (ca.dip != NULL) { 672 /* safe to call ddi_pathname as dip already held */ 673 (void) ddi_pathname(ca.dip, path); 674 } else { 675 (void) strcpy(path, "<none>"); 676 } 677 678 err = drerr_new(1, ESTF_DRVFAIL, path); 679 DRERR_SET_C(&ca.err, &err); 680 kmem_free(path, MAXPATHLEN); 681 } 682 683 return (ca.err); 684 } 685 686 static sbd_error_t * 687 drmach_device_new(drmach_node_t *node, 688 drmach_board_t *bp, drmach_device_t **dpp) 689 { 690 int i; 691 int rv; 692 drmach_device_t *dp; 693 sbd_error_t *err; 694 char name[OBP_MAXDRVNAME]; 695 696 rv = drmach_node_get_prop(node, OBP_NAME, name); 697 if (rv) { 698 /* every node is expected to have a name */ 699 err = drerr_new(1, ESTF_GETPROP, 700 "PROM Node 0x%x: property %s", 701 (uint_t)node->get_dnode(node), OBP_NAME); 702 703 return (err); 704 } 705 706 /* 707 * The node currently being examined is not listed in the name2type[] 708 * array. In this case, the node is no interest to drmach. Both 709 * dp and err are initialized here to yield nothing (no device or 710 * error structure) for this case. 711 */ 712 for (i = 0; i < sizeof (name2type) / sizeof (name2type[0]); i++) 713 if (strcmp(name2type[i].name, name) == 0) 714 break; 715 716 if (i < sizeof (name2type) / sizeof (name2type[0])) { 717 dp = kmem_zalloc(sizeof (drmach_device_t), KM_SLEEP); 718 719 dp->bp = bp; 720 dp->unum = -1; 721 dp->node = drmach_node_dup(node); 722 dp->type = name2type[i].type; 723 724 err = (name2type[i].new)(dp); 725 if (err) { 726 drmach_node_dispose(node); 727 kmem_free(dp, sizeof (*dp)); 728 dp = NULL; 729 } 730 731 *dpp = dp; 732 return (err); 733 } 734 735 /* 736 * The node currently being examined is not listed in the name2type[] 737 * array. In this case, the node is no interest to drmach. Both 738 * dp and err are initialized here to yield nothing (no device or 739 * error structure) for this case. 740 */ 741 *dpp = NULL; 742 return (NULL); 743 } 744 745 static void 746 drmach_device_dispose(drmachid_t id) 747 { 748 drmach_device_t *self = id; 749 750 if (self->node) 751 drmach_node_dispose(self->node); 752 753 kmem_free(self, sizeof (*self)); 754 } 755 756 static sbd_error_t * 757 drmach_device_get_prop(drmach_device_t *dp, char *name, void *buf) 758 { 759 sbd_error_t *err = NULL; 760 int rv; 761 762 rv = drmach_node_get_prop(dp->node, name, buf); 763 if (rv) { 764 err = drerr_new(1, ESTF_GETPROP, 765 "%s::%s: property %s", 766 dp->bp->cm.name, dp->cm.name, name); 767 } 768 769 return (err); 770 } 771 772 static sbd_error_t * 773 drmach_device_get_proplen(drmach_device_t *dp, char *name, int *len) 774 { 775 sbd_error_t *err = NULL; 776 int rv; 777 778 rv = drmach_node_get_proplen(dp->node, name, len); 779 if (rv) { 780 err = drerr_new(1, ESTF_GETPROPLEN, 781 "%s::%s: property %s", 782 dp->bp->cm.name, dp->cm.name, name); 783 } 784 785 return (err); 786 } 787 788 static drmach_board_t * 789 drmach_board_new(int bnum) 790 { 791 static sbd_error_t *drmach_board_release(drmachid_t); 792 static sbd_error_t *drmach_board_status(drmachid_t, drmach_status_t *); 793 794 drmach_board_t *bp; 795 796 bp = kmem_zalloc(sizeof (drmach_board_t), KM_SLEEP); 797 798 bp->cm.isa = (void *)drmach_board_new; 799 bp->cm.release = drmach_board_release; 800 bp->cm.status = drmach_board_status; 801 802 (void) drmach_board_name(bnum, bp->cm.name, sizeof (bp->cm.name)); 803 804 bp->bnum = bnum; 805 bp->devices = NULL; 806 bp->connect_cpuid = -1; 807 bp->tree = drmach_node_new(); 808 bp->assigned = !drmach_initialized; 809 bp->powered = !drmach_initialized; 810 811 drmach_array_set(drmach_boards, bnum, bp); 812 return (bp); 813 } 814 815 static void 816 drmach_board_dispose(drmachid_t id) 817 { 818 drmach_board_t *bp; 819 820 ASSERT(DRMACH_IS_BOARD_ID(id)); 821 bp = id; 822 823 if (bp->tree) 824 drmach_node_dispose(bp->tree); 825 826 if (bp->devices) 827 drmach_array_dispose(bp->devices, drmach_device_dispose); 828 829 kmem_free(bp, sizeof (*bp)); 830 } 831 832 static sbd_error_t * 833 drmach_board_status(drmachid_t id, drmach_status_t *stat) 834 { 835 sbd_error_t *err = NULL; 836 drmach_board_t *bp; 837 838 if (!DRMACH_IS_BOARD_ID(id)) 839 return (drerr_new(0, ESTF_INAPPROP, NULL)); 840 bp = id; 841 842 stat->assigned = bp->assigned; 843 stat->powered = bp->powered; 844 stat->busy = 0; /* assume not busy */ 845 stat->configured = 0; /* assume not configured */ 846 stat->empty = 0; 847 stat->cond = bp->cond = SBD_COND_OK; 848 strncpy(stat->type, "System Brd", sizeof (stat->type)); 849 stat->info[0] = '\0'; 850 851 if (bp->devices) { 852 int rv; 853 int d_idx; 854 drmachid_t d_id; 855 856 rv = drmach_array_first(bp->devices, &d_idx, &d_id); 857 while (rv == 0) { 858 drmach_status_t d_stat; 859 860 err = drmach_status(d_id, &d_stat); 861 if (err) 862 break; 863 864 stat->busy |= d_stat.busy; 865 stat->configured |= d_stat.configured; 866 867 rv = drmach_array_next(bp->devices, &d_idx, &d_id); 868 } 869 } 870 871 return (err); 872 } 873 874 /* a simple routine to reduce redundancy of this common logic */ 875 static pda_handle_t 876 drmach_pda_open(void) 877 { 878 pda_handle_t ph; 879 880 ph = pda_open(); 881 if (ph == NULL) { 882 /* catch in debug kernels */ 883 ASSERT(0); 884 cmn_err(CE_WARN, "pda_open failed"); 885 } 886 887 return (ph); 888 } 889 890 #ifdef DEBUG 891 int drmach_init_break = 0; 892 #endif 893 894 static int 895 hold_rele_branch(dev_info_t *rdip, void *arg) 896 { 897 int i; 898 int *holdp = (int *)arg; 899 char *name = ddi_node_name(rdip); 900 901 /* 902 * For Starfire, we must be children of the root devinfo node 903 */ 904 ASSERT(ddi_get_parent(rdip) == ddi_root_node()); 905 906 for (i = 0; i < sizeof (name2type) / sizeof (name2type[0]); i++) 907 if (strcmp(name2type[i].name, name) == 0) 908 break; 909 910 if (i == sizeof (name2type) / sizeof (name2type[0])) { 911 /* Not of interest to us */ 912 return (DDI_WALK_PRUNECHILD); 913 } 914 915 if (*holdp) { 916 ASSERT(!e_ddi_branch_held(rdip)); 917 e_ddi_branch_hold(rdip); 918 } else { 919 ASSERT(e_ddi_branch_held(rdip)); 920 e_ddi_branch_rele(rdip); 921 } 922 923 return (DDI_WALK_PRUNECHILD); 924 } 925 926 static int 927 drmach_init(void) 928 { 929 pnode_t nodeid; 930 dev_info_t *rdip; 931 int hold, circ; 932 933 #ifdef DEBUG 934 if (drmach_init_break) 935 debug_enter("drmach_init: drmach_init_break set\n"); 936 #endif 937 mutex_enter(&drmach_i_lock); 938 if (drmach_initialized) { 939 mutex_exit(&drmach_i_lock); 940 return (0); 941 } 942 943 drmach_boards = drmach_array_new(0, MAX_BOARDS - 1); 944 945 nodeid = prom_childnode(prom_rootnode()); 946 do { 947 int bnum; 948 drmachid_t id; 949 950 bnum = -1; 951 (void) prom_getprop(nodeid, OBP_BOARDNUM, (caddr_t)&bnum); 952 if (bnum == -1) 953 continue; 954 955 if (drmach_array_get(drmach_boards, bnum, &id) == -1) { 956 cmn_err(CE_WARN, "OBP node 0x%x has" 957 " invalid property value, %s=%d", 958 nodeid, OBP_BOARDNUM, bnum); 959 960 /* clean up */ 961 drmach_array_dispose( 962 drmach_boards, drmach_board_dispose); 963 964 mutex_exit(&drmach_i_lock); 965 return (-1); 966 } else if (id == NULL) 967 (void) drmach_board_new(bnum); 968 } while ((nodeid = prom_nextnode(nodeid)) != OBP_NONODE); 969 970 drmach_shutdown_va = vmem_alloc(heap_arena, PAGESIZE, VM_SLEEP); 971 972 /* 973 * Walk immediate children of devinfo root node and hold 974 * all devinfo branches of interest. 975 */ 976 hold = 1; 977 rdip = ddi_root_node(); 978 979 ndi_devi_enter(rdip, &circ); 980 ddi_walk_devs(ddi_get_child(rdip), hold_rele_branch, &hold); 981 ndi_devi_exit(rdip, circ); 982 983 drmach_initialized = 1; 984 985 mutex_exit(&drmach_i_lock); 986 987 return (0); 988 } 989 990 static int 991 drmach_fini(void) 992 { 993 dev_info_t *rdip; 994 int hold, circ; 995 996 if (drmach_initialized) { 997 int busy = 0; 998 int rv; 999 int idx; 1000 drmachid_t id; 1001 1002 ASSERT(drmach_boards != NULL); 1003 1004 rv = drmach_array_first(drmach_boards, &idx, &id); 1005 while (rv == 0) { 1006 sbd_error_t *err; 1007 drmach_status_t stat; 1008 1009 err = drmach_board_status(id, &stat); 1010 if (err) { 1011 /* catch in debug kernels */ 1012 ASSERT(0); 1013 sbd_err_clear(&err); 1014 busy = 1; 1015 } else 1016 busy |= stat.busy; 1017 1018 rv = drmach_array_next(drmach_boards, &idx, &id); 1019 } 1020 1021 if (busy) 1022 return (-1); 1023 1024 drmach_array_dispose(drmach_boards, drmach_board_dispose); 1025 drmach_boards = NULL; 1026 1027 vmem_free(heap_arena, drmach_shutdown_va, PAGESIZE); 1028 1029 /* 1030 * Walk immediate children of the root devinfo node 1031 * releasing holds acquired on branches in drmach_init() 1032 */ 1033 hold = 0; 1034 rdip = ddi_root_node(); 1035 1036 ndi_devi_enter(rdip, &circ); 1037 ddi_walk_devs(ddi_get_child(rdip), hold_rele_branch, &hold); 1038 ndi_devi_exit(rdip, circ); 1039 1040 mutex_destroy(&drmach_i_lock); 1041 1042 drmach_initialized = 0; 1043 } 1044 if (drmach_xt_mb != NULL) { 1045 vmem_free(static_alloc_arena, (void *)drmach_xt_mb, 1046 NCPU * sizeof (uchar_t)); 1047 } 1048 if (drmach_shutdown_asm_mbox != NULL) { 1049 vmem_free(static_alloc_arena, (void *)drmach_shutdown_asm_mbox, 1050 sizeof (struct drmach_shutdown_mbox)); 1051 } 1052 return (0); 1053 } 1054 1055 static sbd_error_t * 1056 drmach_get_mc_asr_addr(drmachid_t id, uint64_t *pa) 1057 { 1058 drmach_device_t *dp; 1059 pnode_t nodeid; 1060 uint64_t addr; 1061 1062 if (!DRMACH_IS_MEM_ID(id)) 1063 return (drerr_new(0, ESTF_INAPPROP, NULL)); 1064 dp = id; 1065 1066 nodeid = drmach_node_get_dnode(dp->node); 1067 if (nodeid == OBP_NONODE || nodeid == OBP_BADNODE) 1068 return (DRMACH_INTERNAL_ERROR()); 1069 1070 addr = mc_get_asr_addr(nodeid); 1071 if (addr == (uint64_t)-1) 1072 return (DRMACH_INTERNAL_ERROR()); 1073 1074 *pa = addr; 1075 return (NULL); 1076 } 1077 1078 static sbd_error_t * 1079 drmach_get_mc_idle_addr(drmachid_t id, uint64_t *pa) 1080 { 1081 drmach_device_t *dp; 1082 pnode_t nodeid; 1083 uint64_t addr; 1084 1085 if (!DRMACH_IS_MEM_ID(id)) 1086 return (drerr_new(0, ESTF_INAPPROP, NULL)); 1087 dp = id; 1088 1089 nodeid = drmach_node_get_dnode(dp->node); 1090 if (nodeid == OBP_NONODE || nodeid == OBP_BADNODE) 1091 return (DRMACH_INTERNAL_ERROR()); 1092 1093 addr = mc_get_idle_addr(nodeid); 1094 if (addr == (uint64_t)-1) 1095 return (DRMACH_INTERNAL_ERROR()); 1096 1097 *pa = addr; 1098 return (NULL); 1099 } 1100 1101 static sbd_error_t * 1102 drmach_read_mc_asr(drmachid_t id, uint_t *mcregp) 1103 { 1104 drmach_device_t *dp; 1105 pnode_t nodeid; 1106 sbd_error_t *err; 1107 1108 if (!DRMACH_IS_MEM_ID(id)) 1109 return (drerr_new(0, ESTF_INAPPROP, NULL)); 1110 dp = id; 1111 1112 nodeid = drmach_node_get_dnode(dp->node); 1113 if (nodeid == OBP_NONODE || nodeid == OBP_BADNODE) 1114 err = DRMACH_INTERNAL_ERROR(); 1115 else if (mc_read_asr(nodeid, mcregp) == -1) 1116 err = DRMACH_INTERNAL_ERROR(); 1117 else 1118 err = NULL; 1119 1120 return (err); 1121 } 1122 1123 static sbd_error_t * 1124 drmach_write_mc_asr(drmachid_t id, uint_t mcreg) 1125 { 1126 drmach_device_t *dp; 1127 pnode_t nodeid; 1128 sbd_error_t *err; 1129 1130 if (!DRMACH_IS_MEM_ID(id)) 1131 return (drerr_new(0, ESTF_INAPPROP, NULL)); 1132 dp = id; 1133 1134 nodeid = drmach_node_get_dnode(dp->node); 1135 if (nodeid == OBP_NONODE || nodeid == OBP_BADNODE) 1136 err = DRMACH_INTERNAL_ERROR(); 1137 else if (mc_write_asr(nodeid, mcreg) == -1) 1138 err = DRMACH_INTERNAL_ERROR(); 1139 else 1140 err = NULL; 1141 1142 return (err); 1143 } 1144 1145 static sbd_error_t * 1146 drmach_prep_rename_script(drmach_device_t *s_mem, drmach_device_t *t_mem, 1147 uint64_t t_slice_offset, caddr_t buf, int buflen) 1148 { 1149 int i, b, m; 1150 drmach_mc_idle_script_t *isp; 1151 drmach_rename_script_t *rsp; 1152 int s_bd, t_bd; 1153 uint_t s_masr, t_masr; 1154 uint64_t s_new_basepa, t_new_basepa; 1155 int b_idx, rv; 1156 sbd_error_t *err; 1157 drmachid_t b_id; 1158 drmach_board_t *brd; 1159 1160 #ifdef DEBUG 1161 /* 1162 * Starfire CPU/MEM/IO boards have only one MC per board. 1163 * This function has been coded with that fact in mind. 1164 */ 1165 ASSERT(MAX_MEM_UNITS_PER_BOARD == 1); 1166 1167 /* 1168 * calculate the maximum space that could be consumed, 1169 * then verify the available buffer space is adequate. 1170 */ 1171 m = sizeof (drmach_mc_idle_script_t *) * 2; /* two MCs */ 1172 b = sizeof (drmach_rename_script_t *) * 3 * MAX_CPU_UNITS_PER_BOARD; 1173 b += sizeof (drmach_rename_script_t *) * 3 * MAX_IO_UNITS_PER_BOARD; 1174 b *= MAX_BOARDS; 1175 b += sizeof (drmach_rename_script_t *) * 3; 1176 b += sizeof (drmach_rename_script_t *) * 1; 1177 ASSERT(m + b < buflen); 1178 #endif 1179 1180 /* 1181 * construct an array of MC idle register addresses of 1182 * both MCs. The array is zero terminated -- as expected 1183 * by drmach_copy_rename_prog__relocatable(). 1184 */ 1185 isp = (drmach_mc_idle_script_t *)buf; 1186 1187 /* source mc */ 1188 err = drmach_get_mc_idle_addr(s_mem, &isp->idle_addr); 1189 if (err) 1190 return (err); 1191 isp->mem = s_mem; 1192 isp += 1; 1193 1194 /* target mc */ 1195 err = drmach_get_mc_idle_addr(t_mem, &isp->idle_addr); 1196 if (err) 1197 return (err); 1198 isp->mem = t_mem; 1199 isp += 1; 1200 1201 /* terminator */ 1202 isp->idle_addr = 0; 1203 isp->mem = NULL; 1204 isp += 1; 1205 1206 /* fetch source mc asr register value */ 1207 err = drmach_read_mc_asr(s_mem, &s_masr); 1208 if (err) 1209 return (err); 1210 else if (s_masr & STARFIRE_MC_INTERLEAVE_MASK) { 1211 return (drerr_new(1, ESTF_INTERBOARD, "%s::%s", 1212 s_mem->bp->cm.name, s_mem->cm.name)); 1213 } 1214 1215 /* fetch target mc asr register value */ 1216 err = drmach_read_mc_asr(t_mem, &t_masr); 1217 if (err) 1218 return (err); 1219 else if (t_masr & STARFIRE_MC_INTERLEAVE_MASK) { 1220 return (drerr_new(1, ESTF_INTERBOARD, "%s::%s", 1221 t_mem->bp->cm.name, t_mem->cm.name)); 1222 } 1223 1224 /* get new source base pa from target's masr */ 1225 s_new_basepa = mc_asr_to_pa(t_masr); 1226 1227 /* 1228 * remove any existing slice offset to realign 1229 * memory with board's slice boundary 1230 */ 1231 s_new_basepa &= ~ (mc_get_mem_alignment() - 1); 1232 1233 /* get new target base pa from source's masr */ 1234 t_new_basepa = mc_asr_to_pa(s_masr); 1235 1236 /* remove any existing slice offset, then apply new offset */ 1237 t_new_basepa &= ~ (mc_get_mem_alignment() - 1); 1238 t_new_basepa += t_slice_offset; 1239 1240 /* encode new base pa into s_masr. turn off mem present bit */ 1241 s_masr = mc_pa_to_asr(s_masr, s_new_basepa); 1242 s_masr &= ~STARFIRE_MC_MEM_PRESENT_MASK; 1243 1244 /* encode new base pa into t_masr. turn on mem present bit */ 1245 t_masr = mc_pa_to_asr(t_masr, t_new_basepa); 1246 t_masr |= STARFIRE_MC_MEM_PRESENT_MASK; 1247 1248 /* 1249 * Step 0: Mark source memory as not present. 1250 */ 1251 m = 0; 1252 rsp = (drmach_rename_script_t *)isp; 1253 err = drmach_get_mc_asr_addr(s_mem, &rsp[m].masr_addr); 1254 if (err) 1255 return (err); 1256 rsp[m].masr = s_masr; 1257 m++; 1258 1259 /* 1260 * Step 1: Write source base address to target MC 1261 * with present bit off. 1262 */ 1263 err = drmach_get_mc_asr_addr(t_mem, &rsp[m].masr_addr); 1264 if (err) 1265 return (err); 1266 rsp[m].masr = t_masr & ~STARFIRE_MC_MEM_PRESENT_MASK; 1267 m++; 1268 1269 /* 1270 * Step 2: Now rewrite target reg with present bit on. 1271 */ 1272 rsp[m].masr_addr = rsp[m-1].masr_addr; 1273 rsp[m].masr = t_masr; 1274 m++; 1275 1276 s_bd = s_mem->bp->bnum; 1277 t_bd = t_mem->bp->bnum; 1278 1279 DRMACH_PR("preparing script for CPU and IO units:\n"); 1280 1281 rv = drmach_array_first(drmach_boards, &b_idx, &b_id); 1282 if (rv) { 1283 /* catch this in debug kernels */ 1284 ASSERT(0); 1285 return (DRMACH_INTERNAL_ERROR()); 1286 } 1287 1288 do { 1289 int d_idx; 1290 drmachid_t d_id; 1291 drmach_device_t *device; 1292 1293 ASSERT(DRMACH_IS_BOARD_ID(b_id)); 1294 brd = b_id; 1295 b = brd->bnum; 1296 1297 /* 1298 * Step 3: Update PC MADR tables for CPUs. 1299 */ 1300 rv = drmach_array_first(brd->devices, &d_idx, &d_id); 1301 if (rv) { 1302 /* must mean no devices on this board */ 1303 break; 1304 } 1305 1306 DRMACH_PR("\t%s\n", brd->cm.name); 1307 1308 do { 1309 ASSERT(DRMACH_IS_DEVICE_ID(d_id)); 1310 1311 if (!DRMACH_IS_CPU_ID(d_id)) 1312 continue; 1313 1314 device = d_id; 1315 i = device->unum; 1316 1317 DRMACH_PR("\t\t%s\n", device->cm.name); 1318 1319 /* 1320 * Disabled detaching mem node. 1321 */ 1322 rsp[m].masr_addr = STARFIRE_PC_MADR_ADDR(b, s_bd, i); 1323 rsp[m].masr = s_masr; 1324 m++; 1325 /* 1326 * Always write masr with present bit 1327 * off and then again with it on. 1328 */ 1329 rsp[m].masr_addr = STARFIRE_PC_MADR_ADDR(b, t_bd, i); 1330 rsp[m].masr = t_masr & ~STARFIRE_MC_MEM_PRESENT_MASK; 1331 m++; 1332 rsp[m].masr_addr = rsp[m-1].masr_addr; 1333 rsp[m].masr = t_masr; 1334 m++; 1335 1336 } while (drmach_array_next(brd->devices, &d_idx, &d_id) == 0); 1337 1338 /* 1339 * Step 4: Update PC MADR tables for IOs. 1340 */ 1341 rv = drmach_array_first(brd->devices, &d_idx, &d_id); 1342 /* this worked for previous loop, must work here too */ 1343 ASSERT(rv == 0); 1344 1345 do { 1346 ASSERT(DRMACH_IS_DEVICE_ID(d_id)); 1347 1348 if (!DRMACH_IS_IO_ID(d_id)) 1349 continue; 1350 1351 device = d_id; 1352 i = device->unum; 1353 1354 DRMACH_PR("\t\t%s\n", device->cm.name); 1355 1356 /* 1357 * Disabled detaching mem node. 1358 */ 1359 rsp[m].masr_addr = STARFIRE_PC_MADR_ADDR(b, s_bd, i+4); 1360 rsp[m].masr = s_masr; 1361 m++; 1362 /* 1363 * Always write masr with present bit 1364 * off and then again with it on. 1365 */ 1366 rsp[m].masr_addr = STARFIRE_PC_MADR_ADDR(b, t_bd, i+4); 1367 rsp[m].masr = t_masr & ~STARFIRE_MC_MEM_PRESENT_MASK; 1368 m++; 1369 rsp[m].masr_addr = rsp[m-1].masr_addr; 1370 rsp[m].masr = t_masr; 1371 m++; 1372 1373 } while (drmach_array_next(brd->devices, &d_idx, &d_id) == 0); 1374 } while (drmach_array_next(drmach_boards, &b_idx, &b_id) == 0); 1375 1376 /* 1377 * Zero masr_addr value indicates the END. 1378 */ 1379 rsp[m].masr_addr = 0ull; 1380 rsp[m].masr = 0; 1381 DRMACH_PR("number of steps in rename script = %d\n", m); 1382 m++; 1383 1384 /* paranoia */ 1385 ASSERT((caddr_t)&rsp[m] <= buf + buflen); 1386 1387 #ifdef DEBUG 1388 { 1389 int j; 1390 1391 DRMACH_PR("mc idle register address list:"); 1392 isp = (drmach_mc_idle_script_t *)buf; 1393 DRMACH_PR("source mc idle addr 0x%lx, mem id %p", 1394 isp[0].idle_addr, isp[0].mem); 1395 DRMACH_PR("target mc idle addr 0x%lx, mem id %p", 1396 isp[1].idle_addr, isp[1].mem); 1397 ASSERT(isp[2].idle_addr == 0); 1398 1399 DRMACH_PR("copy-rename script:"); 1400 for (j = 0; j < m; j++) { 1401 DRMACH_PR("0x%lx = 0x%08x", 1402 rsp[j].masr_addr, rsp[j].masr); 1403 } 1404 1405 DELAY(1000000); 1406 } 1407 #endif 1408 1409 /* return number of bytes consumed */ 1410 b = (caddr_t)&rsp[m] - buf; 1411 DRMACH_PR("total number of bytes consumed is %d\n", b); 1412 ASSERT(b <= buflen); 1413 1414 #ifdef lint 1415 buflen = buflen; 1416 #endif 1417 1418 return (NULL); 1419 } 1420 1421 /* 1422 * The routine performs the necessary memory COPY and MC adr SWITCH. 1423 * Both operations MUST be at the same "level" so that the stack is 1424 * maintained correctly between the copy and switch. The switch 1425 * portion implements a caching mechanism to guarantee the code text 1426 * is cached prior to execution. This is to guard against possible 1427 * memory access while the MC adr's are being modified. 1428 * 1429 * IMPORTANT: The _drmach_copy_rename_end() function must immediately 1430 * follow drmach_copy_rename_prog__relocatable() so that the correct 1431 * "length" of the drmach_copy_rename_prog__relocatable can be 1432 * calculated. This routine MUST be a LEAF function, i.e. it can 1433 * make NO function calls, primarily for two reasons: 1434 * 1435 * 1. We must keep the stack consistent across the "switch". 1436 * 2. Function calls are compiled to relative offsets, and 1437 * we execute this function we'll be executing it from 1438 * a copied version in a different area of memory, thus 1439 * the relative offsets will be bogus. 1440 * 1441 * Moreover, it must have the "__relocatable" suffix to inform DTrace 1442 * providers (and anything else, for that matter) that this 1443 * function's text is manually relocated elsewhere before it is 1444 * executed. That is, it cannot be safely instrumented with any 1445 * methodology that is PC-relative. 1446 */ 1447 static void 1448 drmach_copy_rename_prog__relocatable(drmach_copy_rename_program_t *prog) 1449 { 1450 extern void drmach_exec_script_il(drmach_rename_script_t *rsp); 1451 1452 drmach_mc_idle_script_t *isp; 1453 struct memlist *ml; 1454 int csize; 1455 int lnsize; 1456 uint64_t caddr; 1457 1458 isp = (drmach_mc_idle_script_t *)prog->data; 1459 1460 caddr = ecache_flushaddr; 1461 csize = (cpunodes[CPU->cpu_id].ecache_size << 1); 1462 lnsize = cpunodes[CPU->cpu_id].ecache_linesize; 1463 1464 /* 1465 * DO COPY. 1466 */ 1467 for (ml = prog->c_ml; ml; ml = ml->next) { 1468 uint64_t s_pa, t_pa; 1469 uint64_t nbytes; 1470 1471 s_pa = prog->s_copybasepa + ml->address; 1472 t_pa = prog->t_copybasepa + ml->address; 1473 nbytes = ml->size; 1474 1475 while (nbytes != 0ull) { 1476 /* 1477 * This copy does NOT use an ASI 1478 * that avoids the Ecache, therefore 1479 * the dst_pa addresses may remain 1480 * in our Ecache after the dst_pa 1481 * has been removed from the system. 1482 * A subsequent write-back to memory 1483 * will cause an ARB-stop because the 1484 * physical address no longer exists 1485 * in the system. Therefore we must 1486 * flush out local Ecache after we 1487 * finish the copy. 1488 */ 1489 1490 /* copy 32 bytes at src_pa to dst_pa */ 1491 bcopy32_il(s_pa, t_pa); 1492 1493 /* increment by 32 bytes */ 1494 s_pa += (4 * sizeof (uint64_t)); 1495 t_pa += (4 * sizeof (uint64_t)); 1496 1497 /* decrement by 32 bytes */ 1498 nbytes -= (4 * sizeof (uint64_t)); 1499 } 1500 } 1501 1502 /* 1503 * Since bcopy32_il() does NOT use an ASI to bypass 1504 * the Ecache, we need to flush our Ecache after 1505 * the copy is complete. 1506 */ 1507 flush_ecache_il(caddr, csize, lnsize); /* inline version */ 1508 1509 /* 1510 * Wait for MCs to go idle. 1511 */ 1512 do { 1513 register int t = 10; 1514 register uint_t v; 1515 1516 /* loop t cycles waiting for each mc to indicate it's idle */ 1517 do { 1518 v = ldphysio_il(isp->idle_addr) 1519 & STARFIRE_MC_IDLE_MASK; 1520 1521 } while (v != STARFIRE_MC_IDLE_MASK && t-- > 0); 1522 1523 /* bailout if timedout */ 1524 if (t <= 0) { 1525 prog->restless_mc = isp->mem; 1526 return; 1527 } 1528 1529 isp += 1; 1530 1531 /* stop if terminating zero has been reached */ 1532 } while (isp->idle_addr != 0); 1533 1534 /* advance passed terminating zero */ 1535 isp += 1; 1536 1537 /* 1538 * The following inline assembly routine caches 1539 * the rename script and then caches the code that 1540 * will do the rename. This is necessary 1541 * so that we don't have any memory references during 1542 * the reprogramming. We accomplish this by first 1543 * jumping through the code to guarantee it's cached 1544 * before we actually execute it. 1545 */ 1546 drmach_exec_script_il((drmach_rename_script_t *)isp); 1547 } 1548 1549 static void 1550 drmach_copy_rename_end(void) 1551 { 1552 /* 1553 * IMPORTANT: This function's location MUST be located immediately 1554 * following drmach_copy_rename_prog__relocatable to 1555 * accurately estimate its size. Note that this assumes 1556 * the compiler keeps these functions in the order in 1557 * which they appear :-o 1558 */ 1559 } 1560 1561 sbd_error_t * 1562 drmach_copy_rename_init(drmachid_t t_id, uint64_t t_slice_offset, 1563 drmachid_t s_id, struct memlist *c_ml, drmachid_t *pgm_id) 1564 { 1565 drmach_device_t *s_mem; 1566 drmach_device_t *t_mem; 1567 struct memlist *x_ml; 1568 uint64_t off_mask, s_copybasepa, t_copybasepa, t_basepa; 1569 int len; 1570 caddr_t bp, wp; 1571 pda_handle_t ph; 1572 sbd_error_t *err; 1573 drmach_copy_rename_program_t *prog; 1574 1575 if (!DRMACH_IS_MEM_ID(s_id)) 1576 return (drerr_new(0, ESTF_INAPPROP, NULL)); 1577 if (!DRMACH_IS_MEM_ID(t_id)) 1578 return (drerr_new(0, ESTF_INAPPROP, NULL)); 1579 s_mem = s_id; 1580 t_mem = t_id; 1581 1582 /* get starting physical address of target memory */ 1583 err = drmach_mem_get_base_physaddr(t_id, &t_basepa); 1584 if (err) 1585 return (err); 1586 1587 /* calculate slice offset mask from slice size */ 1588 off_mask = mc_get_mem_alignment() - 1; 1589 1590 /* calculate source and target base pa */ 1591 s_copybasepa = c_ml->address; 1592 t_copybasepa = t_basepa + ((c_ml->address & off_mask) - t_slice_offset); 1593 1594 /* paranoia */ 1595 ASSERT((c_ml->address & off_mask) >= t_slice_offset); 1596 1597 /* adjust copy memlist addresses to be relative to copy base pa */ 1598 x_ml = c_ml; 1599 while (x_ml != NULL) { 1600 x_ml->address -= s_copybasepa; 1601 x_ml = x_ml->next; 1602 } 1603 1604 #ifdef DEBUG 1605 { 1606 uint64_t s_basepa, s_size, t_size; 1607 1608 x_ml = c_ml; 1609 while (x_ml->next != NULL) 1610 x_ml = x_ml->next; 1611 1612 DRMACH_PR("source copy span: base pa 0x%lx, end pa 0x%lx\n", 1613 s_copybasepa, 1614 s_copybasepa + x_ml->address + x_ml->size); 1615 1616 DRMACH_PR("target copy span: base pa 0x%lx, end pa 0x%lx\n", 1617 t_copybasepa, 1618 t_copybasepa + x_ml->address + x_ml->size); 1619 1620 DRMACH_PR("copy memlist (relative to copy base pa):\n"); 1621 MEMLIST_DUMP(c_ml); 1622 1623 err = drmach_mem_get_base_physaddr(s_id, &s_basepa); 1624 ASSERT(err == NULL); 1625 1626 err = drmach_mem_get_size(s_id, &s_size); 1627 ASSERT(err == NULL); 1628 1629 err = drmach_mem_get_size(t_id, &t_size); 1630 ASSERT(err == NULL); 1631 1632 DRMACH_PR("current source base pa 0x%lx, size 0x%lx\n", 1633 s_basepa, s_size); 1634 DRMACH_PR("current target base pa 0x%lx, size 0x%lx\n", 1635 t_basepa, t_size); 1636 1637 ASSERT(s_copybasepa + x_ml->address + x_ml->size <= s_basepa + s_size); 1638 ASSERT(t_copybasepa + x_ml->address + x_ml->size <= t_basepa + t_size); 1639 } 1640 #endif 1641 1642 ph = drmach_pda_open(); 1643 if (ph == NULL) 1644 return (DRMACH_INTERNAL_ERROR()); 1645 1646 /* 1647 * bp will be page aligned, since we're calling 1648 * kmem_zalloc() with an exact multiple of PAGESIZE. 1649 */ 1650 wp = bp = kmem_zalloc(PAGESIZE, KM_SLEEP); 1651 1652 /* allocate space for copy rename struct */ 1653 len = sizeof (drmach_copy_rename_program_t); 1654 DRMACH_PR("prog = 0x%p, header len %d\n", wp, len); 1655 prog = (drmach_copy_rename_program_t *)wp; 1656 wp += (len + ecache_alignsize - 1) & ~ (ecache_alignsize - 1); 1657 1658 /* 1659 * Copy the code for the copy-rename routine into 1660 * a page aligned piece of memory. We do this to guarantee 1661 * that we're executing within the same page and thus reduce 1662 * the possibility of cache collisions between different 1663 * pages. 1664 */ 1665 len = (int)((ulong_t)drmach_copy_rename_end - 1666 (ulong_t)drmach_copy_rename_prog__relocatable); 1667 ASSERT(wp + len < bp + PAGESIZE); 1668 bcopy((caddr_t)drmach_copy_rename_prog__relocatable, wp, len); 1669 1670 DRMACH_PR("copy-rename function 0x%p, len %d\n", wp, len); 1671 prog->run = (void (*)())wp; 1672 wp += (len + ecache_alignsize - 1) & ~ (ecache_alignsize - 1); 1673 1674 /* 1675 * Prepare data page that will contain script of 1676 * operations to perform during copy-rename. 1677 * Allocate temporary buffer to hold script. 1678 */ 1679 err = drmach_prep_rename_script(s_mem, t_mem, t_slice_offset, 1680 wp, PAGESIZE - (wp - bp)); 1681 if (err) { 1682 (void) drmach_copy_rename_fini(prog); 1683 return (err); 1684 } 1685 1686 DRMACH_PR("copy-rename script 0x%p, len %d\n", wp, len); 1687 prog->data = wp; 1688 wp += (len + ecache_alignsize - 1) & ~ (ecache_alignsize - 1); 1689 1690 prog->ph = ph; 1691 prog->s_copybasepa = s_copybasepa; 1692 prog->t_copybasepa = t_copybasepa; 1693 prog->c_ml = c_ml; 1694 *pgm_id = prog; 1695 1696 return (NULL); 1697 } 1698 1699 sbd_error_t * 1700 drmach_copy_rename_fini(drmachid_t id) 1701 { 1702 drmach_copy_rename_program_t *prog = id; 1703 sbd_error_t *err = NULL; 1704 1705 if (prog->c_ml != NULL) 1706 memlist_delete(prog->c_ml); 1707 1708 if (prog->ph != NULL) 1709 pda_close(prog->ph); 1710 1711 if (prog->restless_mc != 0) { 1712 cmn_err(CE_WARN, "MC did not idle; OBP Node 0x%x", 1713 (uint_t)drmach_node_get_dnode(prog->restless_mc->node)); 1714 1715 err = DRMACH_INTERNAL_ERROR(); 1716 } 1717 1718 kmem_free(prog, PAGESIZE); 1719 1720 return (err); 1721 } 1722 1723 static sbd_error_t * 1724 drmach_io_new(drmach_device_t *dp) 1725 { 1726 static sbd_error_t *drmach_io_release(drmachid_t); 1727 static sbd_error_t *drmach_io_status(drmachid_t, drmach_status_t *); 1728 1729 sbd_error_t *err; 1730 int portid; 1731 1732 err = drmach_device_get_prop(dp, "upa-portid", &portid); 1733 if (err == NULL) { 1734 ASSERT(portid & 0x40); 1735 dp->unum = portid & 1; 1736 } 1737 1738 dp->cm.isa = (void *)drmach_io_new; 1739 dp->cm.release = drmach_io_release; 1740 dp->cm.status = drmach_io_status; 1741 1742 snprintf(dp->cm.name, sizeof (dp->cm.name), "%s%d", dp->type, dp->unum); 1743 1744 return (err); 1745 } 1746 1747 static void 1748 drmach_iopc_op(pda_handle_t ph, drmach_iopc_op_t op) 1749 { 1750 register int b; 1751 1752 for (b = 0; b < MAX_BOARDS; b++) { 1753 int p; 1754 ushort_t bda_ioc; 1755 board_desc_t *bdesc; 1756 1757 if (pda_board_present(ph, b) == 0) 1758 continue; 1759 1760 bdesc = (board_desc_t *)pda_get_board_info(ph, b); 1761 /* 1762 * Update PCs for IOCs. 1763 */ 1764 bda_ioc = bdesc->bda_ioc; 1765 for (p = 0; p < MAX_IOCS; p++) { 1766 u_longlong_t idle_addr; 1767 uchar_t value; 1768 1769 if (BDA_NBL(bda_ioc, p) != BDAN_GOOD) 1770 continue; 1771 1772 idle_addr = STARFIRE_BB_PC_ADDR(b, p, 1); 1773 1774 switch (op) { 1775 case DO_PAUSE: 1776 value = STARFIRE_BB_PC_PAUSE(p); 1777 break; 1778 1779 case DO_IDLE: 1780 value = STARFIRE_BB_PC_IDLE(p); 1781 break; 1782 1783 case DO_UNPAUSE: 1784 value = ldbphysio(idle_addr); 1785 value &= ~STARFIRE_BB_PC_PAUSE(p); 1786 break; 1787 1788 case DO_UNIDLE: 1789 value = ldbphysio(idle_addr); 1790 value &= ~STARFIRE_BB_PC_IDLE(p); 1791 break; 1792 1793 default: 1794 cmn_err(CE_PANIC, 1795 "drmach_iopc_op: unknown op (%d)", 1796 (int)op); 1797 /*NOTREACHED*/ 1798 } 1799 stbphysio(idle_addr, value); 1800 } 1801 } 1802 } 1803 1804 void 1805 drmach_copy_rename(drmachid_t id) 1806 { 1807 drmach_copy_rename_program_t *prog = id; 1808 uint64_t neer; 1809 1810 /* 1811 * UPA IDLE 1812 * Protocol = PAUSE -> IDLE -> UNPAUSE 1813 * In reality since we only "idle" the IOPCs it's sufficient 1814 * to just issue the IDLE operation since (in theory) all IOPCs 1815 * in the field are PC6. However, we'll be robust and do the 1816 * proper workaround protocol so that we never have to worry! 1817 */ 1818 drmach_iopc_op(prog->ph, DO_PAUSE); 1819 drmach_iopc_op(prog->ph, DO_IDLE); 1820 DELAY(100); 1821 drmach_iopc_op(prog->ph, DO_UNPAUSE); 1822 DELAY(100); 1823 1824 /* disable CE reporting */ 1825 neer = get_error_enable(); 1826 set_error_enable(neer & ~EER_CEEN); 1827 1828 /* run the copy/rename program */ 1829 prog->run(prog); 1830 1831 /* enable CE reporting */ 1832 set_error_enable(neer); 1833 1834 /* 1835 * UPA UNIDLE 1836 * Protocol = UNIDLE 1837 */ 1838 drmach_iopc_op(prog->ph, DO_UNIDLE); 1839 DELAY(100); 1840 } 1841 1842 /* 1843 * The counter-timer and perf-counter nodes are not being cleaned 1844 * up after a board that was present at start of day is detached. 1845 * If the board has become unconfigured with this operation, walk 1846 * the prom tree and find all counter-timer and perf-counter nodes 1847 * that have the same board number as the board that was just 1848 * unconfigured and remove them. 1849 */ 1850 static sbd_error_t * 1851 drmach_remove_counter_nodes(drmachid_t id) 1852 { 1853 int num; 1854 char name[OBP_MAXDRVNAME]; 1855 pnode_t child; 1856 dev_info_t *dip; 1857 sbd_error_t *err; 1858 drmach_status_t stat; 1859 drmach_board_t *bp; 1860 1861 if (!DRMACH_IS_BOARD_ID(id)) { 1862 return (drerr_new(0, ESTF_INAPPROP, NULL)); 1863 } 1864 1865 if ((err = drmach_board_status(id, &stat)) != NULL) { 1866 return (err); 1867 } 1868 1869 /* 1870 * Only clean up the counter-timer and perf-counter 1871 * nodes when the entire board is unconfigured. 1872 */ 1873 if (stat.configured) { 1874 return (NULL); 1875 } 1876 1877 bp = (drmach_board_t *)id; 1878 1879 err = NULL; 1880 1881 for (child = prom_childnode(prom_rootnode()); child != OBP_NONODE; 1882 child = prom_nextnode(child)) { 1883 1884 if (prom_getprop(child, OBP_BOARDNUM, (caddr_t)&num) == -1) { 1885 continue; 1886 } 1887 1888 if (bp->bnum != num) { 1889 continue; 1890 } 1891 1892 if (prom_getprop(child, OBP_NAME, (caddr_t)name) == -1) { 1893 continue; 1894 } 1895 1896 if (strncmp(name, MISC_COUNTER_TIMER_DEVNAME, OBP_MAXDRVNAME) && 1897 strncmp(name, MISC_PERF_COUNTER_DEVNAME, OBP_MAXDRVNAME)) { 1898 continue; 1899 } 1900 1901 /* Root node doesn't have to be held */ 1902 dip = e_ddi_nodeid_to_dip(child); 1903 1904 /* 1905 * If the node is only in the OBP tree, then 1906 * we don't have to remove it. 1907 */ 1908 if (dip) { 1909 dev_info_t *fdip = NULL; 1910 1911 DRMACH_PR("removing %s devinfo node\n", name); 1912 1913 e_ddi_branch_hold(dip); 1914 ddi_release_devi(dip); /* held in e_ddi_nodeid_to_dip */ 1915 1916 if (e_ddi_branch_destroy(dip, &fdip, 0)) { 1917 char *path = kmem_alloc(MAXPATHLEN, KM_SLEEP); 1918 1919 /* 1920 * If non-NULL, fdip is held and must be 1921 * released. 1922 */ 1923 if (fdip != NULL) { 1924 (void) ddi_pathname(fdip, path); 1925 ddi_release_devi(fdip); 1926 } else { 1927 (void) ddi_pathname(dip, path); 1928 } 1929 1930 err = drerr_new(1, ESTF_DRVFAIL, path); 1931 kmem_free(path, MAXPATHLEN); 1932 e_ddi_branch_rele(dip); 1933 break; 1934 } 1935 } 1936 } 1937 1938 return (err); 1939 } 1940 1941 /*ARGSUSED*/ 1942 sbd_error_t * 1943 drmach_pre_op(int cmd, drmachid_t id, drmach_opts_t *opts) 1944 { 1945 /* allow status and ncm operations to always succeed */ 1946 if ((cmd == SBD_CMD_STATUS) || (cmd == SBD_CMD_GETNCM)) { 1947 return (NULL); 1948 } 1949 1950 /* check all other commands for the required option string */ 1951 if ((opts->size > 0) && (opts->copts != NULL)) { 1952 1953 DRMACH_PR("platform options: %s\n", opts->copts); 1954 1955 if (strstr(opts->copts, "xfdr") != NULL) { 1956 return (NULL); 1957 } 1958 } 1959 1960 return (drerr_new(0, ESTF_SUPPORT, NULL)); 1961 } 1962 1963 /*ARGSUSED*/ 1964 sbd_error_t * 1965 drmach_post_op(int cmd, drmachid_t id, drmach_opts_t *opts) 1966 { 1967 sbd_error_t *err = NULL; 1968 1969 switch (cmd) { 1970 case SBD_CMD_UNCONFIGURE: 1971 1972 err = drmach_remove_counter_nodes(id); 1973 break; 1974 1975 case SBD_CMD_CONFIGURE: 1976 case SBD_CMD_DISCONNECT: 1977 case SBD_CMD_CONNECT: 1978 case SBD_CMD_GETNCM: 1979 case SBD_CMD_STATUS: 1980 break; 1981 1982 default: 1983 break; 1984 } 1985 1986 return (err); 1987 } 1988 1989 sbd_error_t * 1990 drmach_board_assign(int bnum, drmachid_t *id) 1991 { 1992 sbd_error_t *err; 1993 1994 if (!drmach_initialized && drmach_init() == -1) { 1995 err = DRMACH_INTERNAL_ERROR(); 1996 } else if (drmach_array_get(drmach_boards, bnum, id) == -1) { 1997 err = drerr_new(1, ESTF_BNUM, "%d", bnum); 1998 } else if (*id != NULL) { 1999 err = NULL; 2000 } else { 2001 drmach_board_t *bp; 2002 2003 *id = (drmachid_t)drmach_board_new(bnum); 2004 bp = *id; 2005 bp->assigned = 1; 2006 err = NULL; 2007 } 2008 2009 return (err); 2010 } 2011 2012 static int 2013 drmach_attach_board(void *arg) 2014 { 2015 drmach_board_t *obj = (drmach_board_t *)arg; 2016 cpuset_t cset; 2017 int retval; 2018 2019 /* 2020 * OBP disables traps during the board probe. 2021 * So, in order to prevent cross-call/cross-trap timeouts, 2022 * and thus panics, we effectively block anybody from 2023 * issuing xc's/xt's by doing a promsafe_xc_attention. 2024 * In the previous version of Starfire DR (2.6), a timeout 2025 * suspension mechanism was implemented in the send-mondo 2026 * assembly. That mechanism is unnecessary with the 2027 * existence of xc_attention/xc_dismissed. 2028 */ 2029 cset = cpu_ready_set; 2030 promsafe_xc_attention(cset); 2031 2032 retval = prom_starfire_add_brd(obj->connect_cpuid); 2033 2034 xc_dismissed(cset); 2035 2036 return (retval); 2037 } 2038 2039 sbd_error_t * 2040 drmach_board_connect(drmachid_t id, drmach_opts_t *opts) 2041 { 2042 drmach_board_t *obj = (drmach_board_t *)id; 2043 int retval; 2044 sbd_error_t *err; 2045 char *cptr, *copts; 2046 2047 if (!DRMACH_IS_BOARD_ID(id)) 2048 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2049 2050 if (opts->size > 0) 2051 copts = opts->copts; 2052 2053 if ((cptr = strstr(copts, "cpuid=")) != NULL) { 2054 int cpuid; 2055 2056 cptr += strlen("cpuid="); 2057 cpuid = stoi(&cptr); 2058 2059 if (DRMACH_CPUID2BNUM(cpuid) == obj->bnum) { 2060 obj->connect_cpuid = cpuid; 2061 obj->assigned = 1; 2062 } else 2063 return (drerr_new(1, ESTF_SETCPUVAL, "%d", cpuid)); 2064 } else { 2065 /* cpuid was not specified */ 2066 obj->connect_cpuid = -1; 2067 } 2068 2069 if (obj->connect_cpuid == -1) { 2070 err = drerr_new(1, ESTF_NOCPUID, obj->cm.name); 2071 return (err); 2072 } 2073 2074 cmn_err(CE_CONT, "DRMACH: PROM attach %s CPU %d\n", 2075 obj->cm.name, obj->connect_cpuid); 2076 2077 retval = prom_tree_update(drmach_attach_board, obj); 2078 2079 if (retval == 0) 2080 err = NULL; 2081 else { 2082 cmn_err(CE_WARN, "prom error: prom_starfire_add_brd(%d) " 2083 "returned %d", obj->connect_cpuid, retval); 2084 2085 err = drerr_new(1, ESTF_PROBE, obj->cm.name); 2086 } 2087 2088 obj->connect_cpuid = -1; 2089 2090 return (err); 2091 } 2092 2093 /*ARGSUSED*/ 2094 sbd_error_t * 2095 drmach_board_disconnect(drmachid_t id, drmach_opts_t *opts) 2096 { 2097 drmach_board_t *bp; 2098 int rv; 2099 int d_idx; /* device index */ 2100 drmachid_t d_id; /* device ID */ 2101 sbd_error_t *err; 2102 2103 if (!DRMACH_IS_BOARD_ID(id)) 2104 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2105 2106 bp = id; 2107 2108 /* 2109 * We need to make sure all of the board's device nodes 2110 * have been removed from the Solaris device tree before 2111 * continuing with the disconnect. Otherwise, we could 2112 * disconnect the board and remove the OBP device tree 2113 * nodes with Solaris device tree nodes remaining. 2114 * 2115 * On Starfire, Solaris device tree nodes are deleted 2116 * during unconfigure by drmach_unconfigure(). It's 2117 * necessary to do this here because drmach_unconfigure() 2118 * failures are not handled during unconfigure. 2119 */ 2120 if (bp->devices) { 2121 rv = drmach_array_first(bp->devices, &d_idx, &d_id); 2122 while (rv == 0) { 2123 err = drmach_unconfigure(d_id, DRMACH_DEVI_REMOVE); 2124 if (err) 2125 return (err); 2126 2127 rv = drmach_array_next(bp->devices, &d_idx, &d_id); 2128 } 2129 } 2130 2131 /* 2132 * Starfire board Solaris device tree counter nodes, 2133 * which are only present on start-of-day boards, are 2134 * removed in the dr_post_op() code flow after the 2135 * board is unconfigured. We call the counter node 2136 * removal function here because unconfigure errors 2137 * can cause the dr_post_op() function to be skipped 2138 * after an unconfigure operation even though all of 2139 * the board's devices have been transitioned to the 2140 * unconfigured state. 2141 */ 2142 err = drmach_remove_counter_nodes(id); 2143 if (err) 2144 return (err); 2145 2146 return (NULL); 2147 } 2148 2149 static int 2150 drmach_board_find_devices_cb(drmach_node_walk_args_t *args) 2151 { 2152 drmach_node_t *node = args->node; 2153 drmach_board_cb_data_t *data = args->data; 2154 drmach_board_t *obj = data->obj; 2155 2156 int rv; 2157 int bnum; 2158 drmach_device_t *device; 2159 2160 rv = drmach_node_get_prop(node, OBP_BOARDNUM, &bnum); 2161 if (rv) { 2162 /* 2163 * if the node does not have a board# property, then 2164 * by that information alone it is known that drmach 2165 * is not interested in it. 2166 */ 2167 return (0); 2168 } else if (bnum != obj->bnum) 2169 return (0); 2170 2171 /* 2172 * Create a device data structure from this node data. 2173 * The call may yield nothing if the node is not of interest 2174 * to drmach. 2175 */ 2176 data->err = drmach_device_new(node, obj, &device); 2177 if (data->err) 2178 return (-1); 2179 else if (device == NULL) { 2180 /* 2181 * drmach_device_new examined the node we passed in 2182 * and determined that it was one not of interest to 2183 * drmach. So, it is skipped. 2184 */ 2185 return (0); 2186 } 2187 2188 rv = drmach_array_set(obj->devices, data->ndevs++, device); 2189 if (rv) { 2190 drmach_device_dispose(device); 2191 data->err = DRMACH_INTERNAL_ERROR(); 2192 return (-1); 2193 } 2194 2195 data->err = (*data->found)(data->a, device->type, device->unum, device); 2196 return (data->err == NULL ? 0 : -1); 2197 } 2198 2199 sbd_error_t * 2200 drmach_board_find_devices(drmachid_t id, void *a, 2201 sbd_error_t *(*found)(void *a, const char *, int, drmachid_t)) 2202 { 2203 extern int plat_max_cpu_units_per_board(); 2204 extern int plat_max_mem_units_per_board(); 2205 extern int plat_max_io_units_per_board(); 2206 2207 drmach_board_t *obj = (drmach_board_t *)id; 2208 sbd_error_t *err; 2209 int max_devices; 2210 int rv; 2211 drmach_board_cb_data_t data; 2212 2213 max_devices = plat_max_cpu_units_per_board(); 2214 max_devices += plat_max_mem_units_per_board(); 2215 max_devices += plat_max_io_units_per_board(); 2216 2217 obj->devices = drmach_array_new(0, max_devices); 2218 2219 data.obj = obj; 2220 data.ndevs = 0; 2221 data.found = found; 2222 data.a = a; 2223 data.err = NULL; 2224 2225 rv = drmach_node_walk(obj->tree, &data, drmach_board_find_devices_cb); 2226 if (rv == 0) 2227 err = NULL; 2228 else { 2229 drmach_array_dispose(obj->devices, drmach_device_dispose); 2230 obj->devices = NULL; 2231 2232 if (data.err) 2233 err = data.err; 2234 else 2235 err = DRMACH_INTERNAL_ERROR(); 2236 } 2237 2238 return (err); 2239 } 2240 2241 int 2242 drmach_board_lookup(int bnum, drmachid_t *id) 2243 { 2244 int rv = 0; 2245 2246 if (!drmach_initialized && drmach_init() == -1) { 2247 *id = 0; 2248 rv = -1; 2249 } else if (drmach_array_get(drmach_boards, bnum, id)) { 2250 *id = 0; 2251 rv = -1; 2252 } 2253 return (rv); 2254 } 2255 2256 sbd_error_t * 2257 drmach_board_name(int bnum, char *buf, int buflen) 2258 { 2259 snprintf(buf, buflen, "SB%d", bnum); 2260 return (NULL); 2261 } 2262 2263 sbd_error_t * 2264 drmach_board_poweroff(drmachid_t id) 2265 { 2266 drmach_board_t *bp; 2267 sbd_error_t *err; 2268 drmach_status_t stat; 2269 2270 if (!DRMACH_IS_BOARD_ID(id)) 2271 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2272 bp = id; 2273 2274 err = drmach_board_status(id, &stat); 2275 if (err) 2276 return (err); 2277 else if (stat.configured || stat.busy) 2278 return (drerr_new(0, ESTF_CONFIGBUSY, bp->cm.name)); 2279 else { 2280 /* board power off is essentially a noop for Starfire */ 2281 bp->powered = 0; 2282 return (NULL); 2283 } 2284 /*NOTREACHED*/ 2285 } 2286 2287 sbd_error_t * 2288 drmach_board_poweron(drmachid_t id) 2289 { 2290 drmach_board_t *bp; 2291 2292 if (!DRMACH_IS_BOARD_ID(id)) 2293 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2294 bp = id; 2295 2296 /* board power on is essentially a noop for Starfire */ 2297 bp->powered = 1; 2298 2299 return (NULL); 2300 } 2301 2302 static sbd_error_t * 2303 drmach_board_release(drmachid_t id) 2304 { 2305 if (!DRMACH_IS_BOARD_ID(id)) 2306 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2307 return (NULL); 2308 } 2309 2310 /*ARGSUSED*/ 2311 sbd_error_t * 2312 drmach_board_test(drmachid_t id, drmach_opts_t *opts, int force) 2313 { 2314 return (NULL); 2315 } 2316 2317 sbd_error_t * 2318 drmach_board_unassign(drmachid_t id) 2319 { 2320 drmach_board_t *bp; 2321 sbd_error_t *err; 2322 drmach_status_t stat; 2323 2324 if (!DRMACH_IS_BOARD_ID(id)) 2325 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2326 bp = id; 2327 2328 err = drmach_board_status(id, &stat); 2329 if (err) 2330 return (err); 2331 else if (stat.configured || stat.busy) 2332 return (drerr_new(0, ESTF_CONFIGBUSY, bp->cm.name)); 2333 else if (drmach_array_set(drmach_boards, bp->bnum, 0) != 0) 2334 return (DRMACH_INTERNAL_ERROR()); 2335 else { 2336 drmach_board_dispose(bp); 2337 return (NULL); 2338 } 2339 /*NOTREACHED*/ 2340 } 2341 2342 static sbd_error_t * 2343 drmach_cpu_new(drmach_device_t *dp) 2344 { 2345 static sbd_error_t *drmach_cpu_release(drmachid_t); 2346 static sbd_error_t *drmach_cpu_status(drmachid_t, drmach_status_t *); 2347 2348 sbd_error_t *err; 2349 int portid; 2350 2351 err = drmach_device_get_prop(dp, "upa-portid", &portid); 2352 if (err == NULL) 2353 dp->unum = portid & 3; 2354 2355 dp->cm.isa = (void *)drmach_cpu_new; 2356 dp->cm.release = drmach_cpu_release; 2357 dp->cm.status = drmach_cpu_status; 2358 2359 snprintf(dp->cm.name, sizeof (dp->cm.name), "%s%d", dp->type, dp->unum); 2360 2361 return (err); 2362 } 2363 2364 /* 2365 * drmach_cpu_obp_detach() 2366 * This requires two steps, first, we must put the cpuid into the OBP 2367 * idle loop (Idle in Program) state. Then we call OBP to place the CPU 2368 * into the "Detached" state, which does any special processing to 2369 * actually detach the cpu, such as flushing ecache, and also ensures 2370 * that a subsequent breakpoint won't restart the cpu (if it was just in 2371 * Idle in Program state). 2372 */ 2373 static void 2374 drmach_cpu_obp_detach(int cpuid) 2375 { 2376 /* 2377 * Cpu may not be under OBP's control. Eg, if cpu exited to download 2378 * helper on a prior attach. 2379 */ 2380 if (CPU_SGN_EXISTS(cpuid) && 2381 !SGN_CPU_IS_OS(cpuid) && 2382 !SGN_CPU_IS_OBP(cpuid)) { 2383 cmn_err(CE_WARN, 2384 "unexpected signature (0x%x) for cpu %d", 2385 get_cpu_sgn(cpuid), cpuid); 2386 } 2387 2388 /* 2389 * Now we place the CPU into the "Detached" idle loop in OBP. 2390 * This is so that the CPU won't be restarted if we break into 2391 * OBP with a breakpoint or BREAK key from the console, and also 2392 * if we need to do any special processing, such as flushing the 2393 * cpu's ecache, disabling interrupts (by turning of the ET bit in 2394 * the PSR) and/or spinning in BBSRAM rather than global memory. 2395 */ 2396 DRMACH_PR("prom_starfire_rm_cpu(%d)\n", cpuid); 2397 prom_starfire_rm_cpu(cpuid); 2398 } 2399 2400 /* 2401 * drmach_cpu_obp_is_detached() returns TRUE if the cpu sigblock signature state 2402 * is SIGBST_DETACHED; otherwise it returns FALSE. This routine should only 2403 * be called after we have asked OBP to detach the CPU. It should NOT be 2404 * called as a check during any other flow. 2405 */ 2406 static int 2407 drmach_cpu_obp_is_detached(int cpuid) 2408 { 2409 if (!CPU_SGN_EXISTS(cpuid) || 2410 (SGN_CPU_IS_OS(cpuid) && SGN_CPU_STATE_IS_DETACHED(cpuid))) 2411 return (1); 2412 else 2413 return (0); 2414 } 2415 2416 static int 2417 drmach_cpu_start(struct cpu *cp) 2418 { 2419 int cpuid = cp->cpu_id; 2420 int ntries = drmach_cpu_ntries; 2421 extern void restart_other_cpu(int); 2422 2423 ASSERT(MUTEX_HELD(&cpu_lock)); 2424 ASSERT(cpunodes[cpuid].nodeid != (pnode_t)0); 2425 2426 cp->cpu_flags &= ~CPU_POWEROFF; 2427 2428 /* 2429 * NOTE: restart_other_cpu pauses cpus during the 2430 * slave cpu start. This helps to quiesce the 2431 * bus traffic a bit which makes the tick sync 2432 * routine in the prom more robust. 2433 */ 2434 DRMACH_PR("COLD START for cpu (%d)\n", cpuid); 2435 2436 prom_starfire_add_cpu(cpuid); 2437 2438 restart_other_cpu(cpuid); 2439 2440 /* 2441 * Wait for the cpu to reach its idle thread before 2442 * we zap him with a request to blow away the mappings 2443 * he (might) have for the drmach_shutdown_asm code 2444 * he may have executed on unconfigure. 2445 */ 2446 while ((cp->cpu_thread != cp->cpu_idle_thread) && (ntries > 0)) { 2447 DELAY(drmach_cpu_delay); 2448 ntries--; 2449 } 2450 2451 DRMACH_PR("waited %d out of %d loops for cpu %d\n", 2452 drmach_cpu_ntries - ntries, drmach_cpu_ntries, cpuid); 2453 2454 xt_one(cpuid, vtag_flushpage_tl1, 2455 (uint64_t)drmach_shutdown_va, (uint64_t)KCONTEXT); 2456 2457 return (0); 2458 } 2459 2460 /* 2461 * A detaching CPU is xcalled with an xtrap to drmach_cpu_stop_self() after 2462 * it has been offlined. The function of this routine is to get the cpu 2463 * spinning in a safe place. The requirement is that the system will not 2464 * reference anything on the detaching board (memory and i/o is detached 2465 * elsewhere) and that the CPU not reference anything on any other board 2466 * in the system. This isolation is required during and after the writes 2467 * to the domain masks to remove the board from the domain. 2468 * 2469 * To accomplish this isolation the following is done: 2470 * 1) Create a locked mapping to a location in BBSRAM where 2471 * the cpu will execute. 2472 * 2) Copy the target function (drmach_shutdown_asm) in which 2473 * the cpu will execute into BBSRAM. 2474 * 3) Jump into function with BBSRAM. 2475 * Function will: 2476 * 3.1) Flush its Ecache (displacement). 2477 * 3.2) Flush its Dcache with HW mechanism. 2478 * 3.3) Flush its Icache with HW mechanism. 2479 * 3.4) Flush all valid and _unlocked_ D-TLB entries. 2480 * 3.5) Flush all valid and _unlocked_ I-TLB entries. 2481 * 3.6) Clear xt_mb to signal completion. Note: cache line is 2482 * recovered by drmach_cpu_poweroff(). 2483 * 4) Jump into a tight loop. 2484 */ 2485 #define DRMACH_BBSRAM_OFFSET 0x1000 2486 2487 static void 2488 drmach_cpu_stop_self(void) 2489 { 2490 int cpuid = (int)CPU->cpu_id; 2491 tte_t tte; 2492 volatile uint_t *src, *dst; 2493 uint_t funclen; 2494 uint64_t bbsram_pa, bbsram_offset; 2495 uint_t bbsram_pfn; 2496 uint64_t bbsram_addr; 2497 void (*bbsram_func)(uint64_t); 2498 extern void drmach_shutdown_asm(uint64_t); 2499 extern void drmach_shutdown_asm_end(void); 2500 2501 funclen = (uint_t)drmach_shutdown_asm_end - (uint_t)drmach_shutdown_asm; 2502 ASSERT(funclen <= MMU_PAGESIZE); 2503 /* 2504 * We'll start from the 0th's base. 2505 */ 2506 bbsram_pa = STARFIRE_UPAID2UPS(cpuid) | STARFIRE_PSI_BASE; 2507 bbsram_offset = bbsram_pa | 0xfe0ULL; 2508 bbsram_pa += ldphysio(bbsram_offset) + DRMACH_BBSRAM_OFFSET; 2509 2510 bbsram_pfn = (uint_t)(bbsram_pa >> MMU_PAGESHIFT); 2511 2512 bbsram_addr = (uint64_t)drmach_shutdown_va; 2513 drmach_shutdown_asm_mbox->estack = bbsram_addr + (uint64_t)funclen; 2514 2515 tte.tte_inthi = TTE_VALID_INT | TTE_SZ_INT(TTE8K) | 2516 TTE_PFN_INTHI(bbsram_pfn); 2517 tte.tte_intlo = TTE_PFN_INTLO(bbsram_pfn) | 2518 TTE_HWWR_INT | TTE_PRIV_INT | TTE_LCK_INT; 2519 sfmmu_dtlb_ld(drmach_shutdown_va, KCONTEXT, &tte); /* load dtlb */ 2520 sfmmu_itlb_ld(drmach_shutdown_va, KCONTEXT, &tte); /* load itlb */ 2521 2522 for (src = (uint_t *)drmach_shutdown_asm, dst = (uint_t *)bbsram_addr; 2523 src < (uint_t *)drmach_shutdown_asm_end; src++, dst++) 2524 *dst = *src; 2525 2526 bbsram_func = (void (*)())bbsram_addr; 2527 drmach_shutdown_asm_mbox->flushaddr = ecache_flushaddr; 2528 drmach_shutdown_asm_mbox->size = (cpunodes[cpuid].ecache_size << 1); 2529 drmach_shutdown_asm_mbox->linesize = cpunodes[cpuid].ecache_linesize; 2530 drmach_shutdown_asm_mbox->physaddr 2531 = va_to_pa((void *)&drmach_xt_mb[cpuid]); 2532 2533 /* 2534 * Signal to drmach_cpu_poweroff() is via drmach_xt_mb cleared 2535 * by asm code 2536 */ 2537 2538 (*bbsram_func)(va_to_pa((void *)drmach_shutdown_asm_mbox)); 2539 } 2540 2541 static void 2542 drmach_cpu_shutdown_self(void) 2543 { 2544 cpu_t *cp = CPU; 2545 int cpuid = cp->cpu_id; 2546 extern void flush_windows(void); 2547 2548 flush_windows(); 2549 2550 (void) spl8(); 2551 2552 ASSERT(cp->cpu_intr_actv == 0); 2553 ASSERT(cp->cpu_thread == cp->cpu_idle_thread || 2554 cp->cpu_thread == cp->cpu_startup_thread); 2555 2556 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF; 2557 2558 drmach_cpu_stop_self(); 2559 2560 cmn_err(CE_PANIC, "CPU %d FAILED TO SHUTDOWN", cpuid); 2561 } 2562 2563 /* a helper routine to keep the math in one place */ 2564 static processorid_t 2565 drmach_cpu_calc_id(drmach_device_t *dp) 2566 { 2567 return (dp->bp->bnum * MAX_CPU_UNITS_PER_BOARD + dp->unum); 2568 } 2569 2570 /* 2571 * Move bootproc (SIGBCPU) to another cpu. If dst_cpu is NULL, a 2572 * destination cpu is chosen from the set of cpus not located on the 2573 * same board as the current bootproc cpu. 2574 */ 2575 static sbd_error_t * 2576 drmach_cpu_juggle_bootproc(drmach_device_t *dst_cpu) 2577 { 2578 processorid_t cpuid; 2579 struct cpu *cp; 2580 sbd_error_t *err; 2581 int rv; 2582 2583 ASSERT(MUTEX_HELD(&cpu_lock)); 2584 2585 /* dst_cpu is NULL when target cpu is unspecified. So, pick one. */ 2586 if (dst_cpu == NULL) { 2587 int avoid_board = DRMACH_CPUID2BNUM(SIGBCPU->cpu_id); 2588 int max_cpuid = MAX_BOARDS * MAX_CPU_UNITS_PER_BOARD; 2589 2590 for (cpuid = 0; cpuid < max_cpuid; cpuid++) 2591 if (DRMACH_CPUID2BNUM(cpuid) != avoid_board) { 2592 cp = cpu_get(cpuid); 2593 if (cp != NULL && cpu_is_online(cp)) 2594 break; 2595 } 2596 2597 if (cpuid == max_cpuid) { 2598 err = drerr_new(1, ESTF_JUGGLE, NULL); 2599 return (err); 2600 } 2601 2602 /* else, cp points to the selected target cpu */ 2603 } else { 2604 cpuid = drmach_cpu_calc_id(dst_cpu); 2605 2606 if ((cp = cpu_get(cpuid)) == NULL) { 2607 err = drerr_new(1, ESTF_NODEV, "%s::%s", 2608 dst_cpu->bp->cm.name, dst_cpu->cm.name); 2609 return (err); 2610 } 2611 2612 if (cpuid == SIGBCPU->cpu_id) { 2613 cmn_err(CE_WARN, 2614 "SIGBCPU(%d) same as new selection(%d)", 2615 SIGBCPU->cpu_id, cpuid); 2616 2617 /* technically not an error, but a no-op */ 2618 return (NULL); 2619 } 2620 } 2621 2622 cmn_err(CE_NOTE, "?relocating SIGBCPU from %d to %d", 2623 SIGBCPU->cpu_id, cpuid); 2624 2625 DRMACH_PR("moving SIGBCPU to CPU %d\n", cpuid); 2626 2627 /* 2628 * Tell OBP to initialize cvc-offset field of new CPU0 2629 * so that it's in sync with OBP and cvc_server 2630 */ 2631 prom_starfire_init_console(cpuid); 2632 2633 /* 2634 * Assign cvc to new cpu0's bbsram for I/O. This has to be 2635 * done BEFORE cpu0 is moved via obp, since this logic 2636 * will cause obp_helper to switch to a different bbsram for 2637 * cvc I/O. We don't want cvc writing to a buffer from which 2638 * nobody will pick up the data! 2639 */ 2640 cvc_assign_iocpu(cpuid); 2641 2642 rv = prom_starfire_move_cpu0(cpuid); 2643 2644 if (rv == 0) { 2645 SIGBCPU = cp; 2646 2647 DRMACH_PR("successfully juggled to CPU %d\n", cpuid); 2648 return (NULL); 2649 } else { 2650 DRMACH_PR("prom error: prom_starfire_move_cpu0(%d) " 2651 "returned %d\n", cpuid, rv); 2652 2653 /* 2654 * The move failed, hopefully obp_helper is still back 2655 * at the old bootproc. Move cvc back there. 2656 */ 2657 cvc_assign_iocpu(SIGBCPU->cpu_id); 2658 2659 2660 err = drerr_new(1, ESTF_MOVESIGB, "CPU %d", cpuid); 2661 return (err); 2662 } 2663 /*NOTREACHED*/ 2664 } 2665 2666 static sbd_error_t * 2667 drmach_cpu_release(drmachid_t id) 2668 { 2669 drmach_device_t *dp; 2670 processorid_t cpuid; 2671 struct cpu *cp; 2672 sbd_error_t *err; 2673 2674 if (!DRMACH_IS_CPU_ID(id)) 2675 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2676 dp = id; 2677 cpuid = drmach_cpu_calc_id(dp); 2678 2679 ASSERT(MUTEX_HELD(&cpu_lock)); 2680 2681 cp = cpu_get(cpuid); 2682 if (cp == NULL) 2683 err = DRMACH_INTERNAL_ERROR(); 2684 else if (SIGBCPU->cpu_id == cp->cpu_id) 2685 err = drmach_cpu_juggle_bootproc(NULL); 2686 else 2687 err = NULL; 2688 2689 return (err); 2690 } 2691 2692 static sbd_error_t * 2693 drmach_cpu_status(drmachid_t id, drmach_status_t *stat) 2694 { 2695 drmach_device_t *dp; 2696 2697 ASSERT(DRMACH_IS_CPU_ID(id)); 2698 dp = id; 2699 2700 stat->assigned = dp->bp->assigned; 2701 stat->powered = dp->bp->powered; 2702 mutex_enter(&cpu_lock); 2703 stat->configured = (cpu_get(drmach_cpu_calc_id(dp)) != NULL); 2704 mutex_exit(&cpu_lock); 2705 stat->busy = dp->busy; 2706 strncpy(stat->type, dp->type, sizeof (stat->type)); 2707 stat->info[0] = '\0'; 2708 2709 return (NULL); 2710 } 2711 2712 sbd_error_t * 2713 drmach_cpu_disconnect(drmachid_t id) 2714 { 2715 drmach_device_t *cpu; 2716 int cpuid; 2717 int ntries; 2718 int p; 2719 u_longlong_t pc_addr; 2720 uchar_t rvalue; 2721 2722 if (!DRMACH_IS_CPU_ID(id)) 2723 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2724 cpu = id; 2725 2726 cpuid = drmach_cpu_calc_id(cpu); 2727 if (SIGBCPU->cpu_id == cpuid) { 2728 /* this cpu is SIGBCPU, can't disconnect */ 2729 return (drerr_new(1, ESTF_HASSIGB, "%s::%s", 2730 cpu->bp->cm.name, cpu->cm.name)); 2731 } 2732 2733 /* 2734 * Make sure SIGBST_DETACHED is set before 2735 * mapping out the sig block. 2736 */ 2737 ntries = drmach_cpu_ntries; 2738 while (!drmach_cpu_obp_is_detached(cpuid) && ntries) { 2739 DELAY(drmach_cpu_delay); 2740 ntries--; 2741 } 2742 if (!drmach_cpu_obp_is_detached(cpuid)) { 2743 cmn_err(CE_WARN, "failed to mark cpu %d detached in sigblock", 2744 cpuid); 2745 } 2746 2747 /* map out signature block */ 2748 if (CPU_SGN_EXISTS(cpuid)) { 2749 CPU_SGN_MAPOUT(cpuid); 2750 } 2751 2752 /* 2753 * We now PC IDLE the processor to guarantee we 2754 * stop any transactions from coming from it. 2755 */ 2756 p = cpu->unum & 1; 2757 pc_addr = STARFIRE_BB_PC_ADDR(cpu->bp->bnum, cpu->unum, 0); 2758 2759 DRMACH_PR("PC idle cpu %d (addr = 0x%llx, port = %d, p = %d)", 2760 drmach_cpu_calc_id(cpu), pc_addr, cpu->unum, p); 2761 2762 rvalue = ldbphysio(pc_addr); 2763 rvalue |= STARFIRE_BB_PC_IDLE(p); 2764 stbphysio(pc_addr, rvalue); 2765 DELAY(50000); 2766 2767 return (NULL); 2768 } 2769 2770 sbd_error_t * 2771 drmach_cpu_get_id(drmachid_t id, processorid_t *cpuid) 2772 { 2773 drmach_device_t *cpu; 2774 2775 if (!DRMACH_IS_CPU_ID(id)) 2776 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2777 cpu = id; 2778 2779 *cpuid = drmach_cpu_calc_id(cpu); 2780 return (NULL); 2781 } 2782 2783 sbd_error_t * 2784 drmach_cpu_get_impl(drmachid_t id, int *ip) 2785 { 2786 drmach_device_t *cpu; 2787 int impl; 2788 2789 if (!DRMACH_IS_CPU_ID(id)) 2790 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2791 2792 cpu = id; 2793 2794 if (drmach_node_get_prop(cpu->node, "implementation#", &impl) == -1) { 2795 return (DRMACH_INTERNAL_ERROR()); 2796 } 2797 2798 *ip = impl; 2799 2800 return (NULL); 2801 } 2802 2803 void 2804 drmach_cpu_flush_ecache_sync(void) 2805 { 2806 ASSERT(curthread->t_bound_cpu == CPU); 2807 2808 /* 2809 * Now let's flush our ecache thereby removing all references 2810 * to the target (detaching) memory from all ecache's in 2811 * system. 2812 */ 2813 cpu_flush_ecache(); 2814 2815 /* 2816 * Delay 100 usec out of paranoia to insure everything 2817 * (hardware queues) has drained before we start reprogramming 2818 * the hardware. 2819 */ 2820 DELAY(100); 2821 } 2822 2823 sbd_error_t * 2824 drmach_get_dip(drmachid_t id, dev_info_t **dip) 2825 { 2826 drmach_device_t *dp; 2827 2828 if (!DRMACH_IS_DEVICE_ID(id)) 2829 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2830 dp = id; 2831 2832 *dip = drmach_node_get_dip(dp->node); 2833 return (NULL); 2834 } 2835 2836 sbd_error_t * 2837 drmach_io_is_attached(drmachid_t id, int *yes) 2838 { 2839 drmach_device_t *dp; 2840 dev_info_t *dip; 2841 int state; 2842 2843 if (!DRMACH_IS_IO_ID(id)) 2844 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2845 dp = id; 2846 2847 dip = drmach_node_get_dip(dp->node); 2848 if (dip == NULL) { 2849 *yes = 0; 2850 return (NULL); 2851 } 2852 2853 state = ddi_get_devstate(dip); 2854 *yes = (i_ddi_devi_attached(dip) || (state == DDI_DEVSTATE_UP)); 2855 2856 return (NULL); 2857 } 2858 2859 sbd_error_t * 2860 drmach_io_pre_release(drmachid_t id) 2861 { 2862 if (!DRMACH_IS_IO_ID(id)) 2863 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2864 return (NULL); 2865 } 2866 2867 static sbd_error_t * 2868 drmach_io_release(drmachid_t id) 2869 { 2870 if (!DRMACH_IS_IO_ID(id)) 2871 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2872 return (NULL); 2873 } 2874 2875 sbd_error_t * 2876 drmach_io_unrelease(drmachid_t id) 2877 { 2878 if (!DRMACH_IS_IO_ID(id)) 2879 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2880 return (NULL); 2881 } 2882 2883 /*ARGSUSED*/ 2884 sbd_error_t * 2885 drmach_io_post_release(drmachid_t id) 2886 { 2887 return (NULL); 2888 } 2889 2890 /*ARGSUSED*/ 2891 sbd_error_t * 2892 drmach_io_post_attach(drmachid_t id) 2893 { 2894 return (NULL); 2895 } 2896 2897 static sbd_error_t * 2898 drmach_io_status(drmachid_t id, drmach_status_t *stat) 2899 { 2900 drmach_device_t *dp; 2901 sbd_error_t *err; 2902 int configured; 2903 2904 ASSERT(DRMACH_IS_IO_ID(id)); 2905 dp = id; 2906 2907 err = drmach_io_is_attached(id, &configured); 2908 if (err) 2909 return (err); 2910 2911 stat->assigned = dp->bp->assigned; 2912 stat->powered = dp->bp->powered; 2913 stat->configured = (configured != 0); 2914 stat->busy = dp->busy; 2915 strncpy(stat->type, dp->type, sizeof (stat->type)); 2916 stat->info[0] = '\0'; 2917 2918 return (NULL); 2919 } 2920 2921 static sbd_error_t * 2922 drmach_mem_new(drmach_device_t *dp) 2923 { 2924 static sbd_error_t *drmach_mem_release(drmachid_t); 2925 static sbd_error_t *drmach_mem_status(drmachid_t, drmach_status_t *); 2926 2927 dp->unum = 0; 2928 dp->cm.isa = (void *)drmach_mem_new; 2929 dp->cm.release = drmach_mem_release; 2930 dp->cm.status = drmach_mem_status; 2931 2932 snprintf(dp->cm.name, sizeof (dp->cm.name), "%s", dp->type); 2933 2934 return (NULL); 2935 } 2936 2937 sbd_error_t * 2938 drmach_mem_add_span(drmachid_t id, uint64_t basepa, uint64_t size) 2939 { 2940 pfn_t basepfn = (pfn_t)(basepa >> PAGESHIFT); 2941 pgcnt_t npages = (pgcnt_t)(size >> PAGESHIFT); 2942 pda_handle_t ph; 2943 int rv; 2944 2945 ASSERT(size != 0); 2946 2947 if (!DRMACH_IS_MEM_ID(id)) 2948 return (drerr_new(0, ESTF_INAPPROP, NULL)); 2949 2950 kcage_range_lock(); 2951 rv = kcage_range_add(basepfn, npages, 1); 2952 kcage_range_unlock(); 2953 if (rv == ENOMEM) { 2954 cmn_err(CE_WARN, "%ld megabytes not available to kernel cage", 2955 (size == 0 ? 0 : size / MBYTE)); 2956 } else if (rv != 0) { 2957 /* catch this in debug kernels */ 2958 ASSERT(0); 2959 2960 cmn_err(CE_WARN, "unexpected kcage_range_add" 2961 " return value %d", rv); 2962 } 2963 2964 /* 2965 * Update the PDA (post2obp) structure with the 2966 * range of the newly added memory. 2967 */ 2968 ph = drmach_pda_open(); 2969 if (ph != NULL) { 2970 pda_mem_add_span(ph, basepa, size); 2971 pda_close(ph); 2972 } 2973 2974 return (NULL); 2975 } 2976 2977 sbd_error_t * 2978 drmach_mem_del_span(drmachid_t id, uint64_t basepa, uint64_t size) 2979 { 2980 drmach_device_t *mem = id; 2981 pfn_t basepfn = (pfn_t)(basepa >> PAGESHIFT); 2982 pgcnt_t npages = (pgcnt_t)(size >> PAGESHIFT); 2983 uint_t mcreg; 2984 sbd_error_t *err; 2985 pda_handle_t ph; 2986 int rv; 2987 2988 err = drmach_read_mc_asr(id, &mcreg); 2989 if (err) 2990 return (err); 2991 else if (mcreg & STARFIRE_MC_INTERLEAVE_MASK) { 2992 return (drerr_new(1, ESTF_INTERBOARD, "%s::%s", 2993 mem->bp->cm.name, mem->cm.name)); 2994 } 2995 2996 if (size > 0) { 2997 kcage_range_lock(); 2998 rv = kcage_range_delete_post_mem_del(basepfn, npages); 2999 kcage_range_unlock(); 3000 if (rv != 0) { 3001 cmn_err(CE_WARN, 3002 "unexpected kcage_range_delete_post_mem_del" 3003 " return value %d", rv); 3004 return (DRMACH_INTERNAL_ERROR()); 3005 } 3006 } 3007 3008 /* 3009 * Update the PDA (post2obp) structure with the 3010 * range of removed memory. 3011 */ 3012 ph = drmach_pda_open(); 3013 if (ph != NULL) { 3014 if (size > 0) 3015 pda_mem_del_span(ph, basepa, size); 3016 3017 /* update PDA to board's new mc register settings */ 3018 pda_mem_sync(ph, mem->bp->bnum, 0); 3019 3020 pda_close(ph); 3021 } 3022 3023 return (NULL); 3024 } 3025 3026 /* support routine for enable and disable */ 3027 static sbd_error_t * 3028 drmach_mem_update_interconnect(drmachid_t id, uint_t mcreg) 3029 { 3030 drmach_device_t *dp; 3031 pda_handle_t ph; 3032 int b; 3033 3034 if (!DRMACH_IS_MEM_ID(id)) 3035 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3036 dp = id; 3037 3038 ph = drmach_pda_open(); 3039 if (ph == NULL) 3040 return (DRMACH_INTERNAL_ERROR()); 3041 3042 for (b = 0; b < MAX_BOARDS; b++) { 3043 int p; 3044 int rv; 3045 ushort_t bda_proc, bda_ioc; 3046 board_desc_t *bdesc; 3047 3048 if (pda_board_present(ph, b) == 0) 3049 continue; 3050 3051 bdesc = (board_desc_t *)pda_get_board_info(ph, b); 3052 3053 /* 3054 * Update PCs for CPUs. 3055 */ 3056 3057 /* make sure definition in platmod is in sync with pda */ 3058 ASSERT(MAX_PROCMODS == MAX_CPU_UNITS_PER_BOARD); 3059 3060 bda_proc = bdesc->bda_proc; 3061 for (p = 0; p < MAX_PROCMODS; p++) { 3062 if (BDA_NBL(bda_proc, p) != BDAN_GOOD) 3063 continue; 3064 3065 rv = pc_madr_add(b, dp->bp->bnum, p, mcreg); 3066 if (rv) { 3067 pda_close(ph); 3068 return (DRMACH_INTERNAL_ERROR()); 3069 } 3070 } 3071 3072 /* 3073 * Update PCs for IOCs. 3074 */ 3075 3076 /* make sure definition in platmod is in sync with pda */ 3077 ASSERT(MAX_IOCS == MAX_IO_UNITS_PER_BOARD); 3078 3079 bda_ioc = bdesc->bda_ioc; 3080 for (p = 0; p < MAX_IOCS; p++) { 3081 if (BDA_NBL(bda_ioc, p) != BDAN_GOOD) 3082 continue; 3083 3084 rv = pc_madr_add(b, dp->bp->bnum, p + 4, mcreg); 3085 if (rv) { 3086 pda_close(ph); 3087 return (DRMACH_INTERNAL_ERROR()); 3088 } 3089 } 3090 } 3091 3092 pda_close(ph); 3093 return (NULL); 3094 } 3095 3096 sbd_error_t * 3097 drmach_mem_disable(drmachid_t id) 3098 { 3099 sbd_error_t *err; 3100 uint_t mcreg; 3101 3102 err = drmach_read_mc_asr(id, &mcreg); 3103 if (err == NULL) { 3104 ASSERT(mcreg & STARFIRE_MC_MEM_PRESENT_MASK); 3105 3106 /* Turn off presence bit. */ 3107 mcreg &= ~STARFIRE_MC_MEM_PRESENT_MASK; 3108 3109 err = drmach_mem_update_interconnect(id, mcreg); 3110 if (err == NULL) 3111 err = drmach_write_mc_asr(id, mcreg); 3112 } 3113 3114 return (err); 3115 } 3116 3117 sbd_error_t * 3118 drmach_mem_enable(drmachid_t id) 3119 { 3120 sbd_error_t *err; 3121 uint_t mcreg; 3122 3123 err = drmach_read_mc_asr(id, &mcreg); 3124 if (err == NULL) { 3125 mcreg |= STARFIRE_MC_MEM_PRESENT_MASK; 3126 3127 err = drmach_write_mc_asr(id, mcreg); 3128 if (err == NULL) 3129 err = drmach_mem_update_interconnect(id, mcreg); 3130 } 3131 3132 return (err); 3133 } 3134 3135 sbd_error_t * 3136 drmach_mem_get_alignment(drmachid_t id, uint64_t *mask) 3137 { 3138 drmach_device_t *mem; 3139 sbd_error_t *err; 3140 pnode_t nodeid; 3141 3142 if (!DRMACH_IS_MEM_ID(id)) 3143 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3144 mem = id; 3145 3146 nodeid = drmach_node_get_dnode(mem->node); 3147 if (nodeid == OBP_NONODE || nodeid == OBP_BADNODE) 3148 err = DRMACH_INTERNAL_ERROR(); 3149 else { 3150 uint64_t size; 3151 3152 size = mc_get_alignment_mask(nodeid); 3153 if (size == (uint64_t)-1) 3154 err = DRMACH_INTERNAL_ERROR(); 3155 else { 3156 *mask = size - 1; 3157 err = NULL; 3158 } 3159 } 3160 3161 return (err); 3162 } 3163 3164 sbd_error_t * 3165 drmach_mem_get_base_physaddr(drmachid_t id, uint64_t *pa) 3166 { 3167 sbd_error_t *err; 3168 uint_t mcreg; 3169 3170 err = drmach_read_mc_asr(id, &mcreg); 3171 if (err == NULL) 3172 *pa = mc_asr_to_pa(mcreg); 3173 3174 return (err); 3175 } 3176 3177 /* 3178 * Use of this routine after copy/rename will yield incorrect results, 3179 * because the OBP MEMAVAIL property will not correctly reflect the 3180 * programming of the MCs. 3181 */ 3182 sbd_error_t * 3183 drmach_mem_get_memlist(drmachid_t id, struct memlist **ml) 3184 { 3185 drmach_device_t *mem; 3186 int rv, i, rlen, rblks; 3187 sbd_error_t *err; 3188 struct memlist *mlist; 3189 struct sf_memunit_regspec *rlist; 3190 3191 if (!DRMACH_IS_MEM_ID(id)) 3192 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3193 mem = id; 3194 3195 err = drmach_device_get_proplen(mem, "dr-available", &rlen); 3196 if (err) 3197 return (err); 3198 3199 rlist = kmem_zalloc(rlen, KM_SLEEP); 3200 3201 err = drmach_device_get_prop(mem, "dr-available", rlist); 3202 if (err) { 3203 kmem_free(rlist, rlen); 3204 return (err); 3205 } 3206 3207 mlist = NULL; 3208 rblks = rlen / sizeof (struct sf_memunit_regspec); 3209 for (i = 0; i < rblks; i++) { 3210 uint64_t addr, size; 3211 3212 addr = (uint64_t)rlist[i].regspec_addr_hi << 32; 3213 addr |= (uint64_t)rlist[i].regspec_addr_lo; 3214 size = (uint64_t)rlist[i].regspec_size_hi << 32; 3215 size |= (uint64_t)rlist[i].regspec_size_lo; 3216 3217 mlist = memlist_add_span(mlist, addr, size); 3218 } 3219 3220 kmem_free(rlist, rlen); 3221 3222 /* 3223 * Make sure the incoming memlist doesn't already 3224 * intersect with what's present in the system (phys_install). 3225 */ 3226 memlist_read_lock(); 3227 rv = memlist_intersect(phys_install, mlist); 3228 memlist_read_unlock(); 3229 if (rv) { 3230 #ifdef DEBUG 3231 DRMACH_PR("OBP derived memlist intersects" 3232 " with phys_install\n"); 3233 memlist_dump(mlist); 3234 3235 DRMACH_PR("phys_install memlist:\n"); 3236 memlist_dump(phys_install); 3237 #endif 3238 3239 memlist_delete(mlist); 3240 return (DRMACH_INTERNAL_ERROR()); 3241 } 3242 3243 #ifdef DEBUG 3244 DRMACH_PR("OBP derived memlist:"); 3245 memlist_dump(mlist); 3246 #endif 3247 3248 *ml = mlist; 3249 return (NULL); 3250 } 3251 3252 sbd_error_t * 3253 drmach_mem_get_size(drmachid_t id, uint64_t *bytes) 3254 { 3255 drmach_device_t *mem; 3256 pda_handle_t ph; 3257 pgcnt_t npages; 3258 3259 if (!DRMACH_IS_MEM_ID(id)) 3260 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3261 mem = id; 3262 3263 ph = drmach_pda_open(); 3264 if (ph == NULL) 3265 return (DRMACH_INTERNAL_ERROR()); 3266 3267 npages = pda_get_mem_size(ph, mem->bp->bnum); 3268 *bytes = (uint64_t)npages << PAGESHIFT; 3269 3270 pda_close(ph); 3271 return (NULL); 3272 } 3273 3274 sbd_error_t * 3275 drmach_mem_get_slice_size(drmachid_t id, uint64_t *bytes) 3276 { 3277 if (!DRMACH_IS_MEM_ID(id)) 3278 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3279 3280 *bytes = mc_get_mem_alignment(); 3281 return (NULL); 3282 } 3283 3284 /* field debugging tool */ 3285 processorid_t drmach_mem_cpu_affinity_nail = 0; 3286 3287 processorid_t 3288 drmach_mem_cpu_affinity(drmachid_t id) 3289 { 3290 drmach_device_t *mp; 3291 drmach_board_t *bp; 3292 processorid_t cpuid; 3293 3294 if (!DRMACH_IS_MEM_ID(id)) 3295 return (CPU_CURRENT); 3296 3297 if (drmach_mem_cpu_affinity_nail) { 3298 cpuid = drmach_mem_cpu_affinity_nail; 3299 3300 if (cpuid < 0 || cpuid > NCPU) 3301 return (CPU_CURRENT); 3302 3303 mutex_enter(&cpu_lock); 3304 if (cpu[cpuid] == NULL || !CPU_ACTIVE(cpu[cpuid])) 3305 cpuid = CPU_CURRENT; 3306 mutex_exit(&cpu_lock); 3307 3308 return (cpuid); 3309 } 3310 3311 /* try to choose a proc on the target board */ 3312 mp = id; 3313 bp = mp->bp; 3314 if (bp->devices) { 3315 int rv; 3316 int d_idx; 3317 drmachid_t d_id; 3318 3319 rv = drmach_array_first(bp->devices, &d_idx, &d_id); 3320 while (rv == 0) { 3321 if (DRMACH_IS_CPU_ID(d_id)) { 3322 cpuid = drmach_cpu_calc_id(d_id); 3323 3324 mutex_enter(&cpu_lock); 3325 if (cpu[cpuid] && CPU_ACTIVE(cpu[cpuid])) { 3326 mutex_exit(&cpu_lock); 3327 DRMACH_PR("drmach_mem_cpu_affinity: " 3328 "selected cpuid=%d\n", cpuid); 3329 return (cpuid); 3330 } else { 3331 mutex_exit(&cpu_lock); 3332 } 3333 } 3334 3335 rv = drmach_array_next(bp->devices, &d_idx, &d_id); 3336 } 3337 } 3338 3339 /* otherwise, this proc, wherever it is */ 3340 DRMACH_PR("drmach_mem_cpu_affinity: using default CPU_CURRENT\n"); 3341 3342 return (CPU_CURRENT); 3343 } 3344 3345 static sbd_error_t * 3346 drmach_mem_release(drmachid_t id) 3347 { 3348 if (!DRMACH_IS_MEM_ID(id)) 3349 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3350 return (NULL); 3351 } 3352 3353 static sbd_error_t * 3354 drmach_mem_status(drmachid_t id, drmach_status_t *stat) 3355 { 3356 drmach_device_t *dp; 3357 sbd_error_t *err; 3358 uint64_t pa, slice_size; 3359 struct memlist *ml; 3360 3361 ASSERT(DRMACH_IS_MEM_ID(id)); 3362 dp = id; 3363 3364 /* get starting physical address of target memory */ 3365 err = drmach_mem_get_base_physaddr(id, &pa); 3366 if (err) 3367 return (err); 3368 3369 /* round down to slice boundary */ 3370 slice_size = mc_get_mem_alignment(); 3371 pa &= ~ (slice_size - 1); 3372 3373 /* stop at first span that is in slice */ 3374 memlist_read_lock(); 3375 for (ml = phys_install; ml; ml = ml->next) 3376 if (ml->address >= pa && ml->address < pa + slice_size) 3377 break; 3378 memlist_read_unlock(); 3379 3380 stat->assigned = dp->bp->assigned; 3381 stat->powered = dp->bp->powered; 3382 stat->configured = (ml != NULL); 3383 stat->busy = dp->busy; 3384 strncpy(stat->type, dp->type, sizeof (stat->type)); 3385 stat->info[0] = '\0'; 3386 3387 return (NULL); 3388 } 3389 3390 static int 3391 drmach_detach_board(void *arg) 3392 { 3393 cpuset_t cset; 3394 int retval; 3395 drmach_board_t *bp = (drmach_board_t *)arg; 3396 3397 cset = cpu_ready_set; 3398 promsafe_xc_attention(cset); 3399 3400 retval = prom_starfire_rm_brd(bp->bnum); 3401 3402 xc_dismissed(cset); 3403 3404 return (retval); 3405 } 3406 3407 sbd_error_t * 3408 drmach_board_deprobe(drmachid_t id) 3409 { 3410 drmach_board_t *bp; 3411 int retval; 3412 3413 if (!DRMACH_IS_BOARD_ID(id)) 3414 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3415 bp = id; 3416 3417 cmn_err(CE_CONT, "DR: PROM detach board %d\n", bp->bnum); 3418 3419 retval = prom_tree_update(drmach_detach_board, bp); 3420 3421 if (retval == 0) 3422 return (NULL); 3423 else { 3424 cmn_err(CE_WARN, "prom error: prom_starfire_rm_brd(%d) " 3425 "returned %d", bp->bnum, retval); 3426 return (drerr_new(1, ESTF_DEPROBE, "%s", bp->cm.name)); 3427 } 3428 } 3429 3430 /*ARGSUSED*/ 3431 static sbd_error_t * 3432 drmach_pt_juggle_bootproc(drmachid_t id, drmach_opts_t *opts) 3433 { 3434 drmach_device_t *cpu; 3435 sbd_error_t *err; 3436 3437 if (!DRMACH_IS_CPU_ID(id)) 3438 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3439 cpu = id; 3440 3441 mutex_enter(&cpu_lock); 3442 3443 err = drmach_cpu_juggle_bootproc(cpu); 3444 3445 mutex_exit(&cpu_lock); 3446 3447 return (err); 3448 } 3449 3450 /*ARGSUSED*/ 3451 static sbd_error_t * 3452 drmach_pt_dump_pdainfo(drmachid_t id, drmach_opts_t *opts) 3453 { 3454 drmach_board_t *bp; 3455 int board; 3456 int i; 3457 pda_handle_t ph; 3458 board_desc_t *bdesc; 3459 3460 if (!DRMACH_IS_BOARD_ID(id)) 3461 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3462 bp = id; 3463 board = bp->bnum; 3464 3465 ph = drmach_pda_open(); 3466 if (ph == NULL) 3467 return (DRMACH_INTERNAL_ERROR()); 3468 3469 if (pda_board_present(ph, board) == 0) { 3470 cmn_err(CE_CONT, "board %d is MISSING\n", board); 3471 pda_close(ph); 3472 return (DRMACH_INTERNAL_ERROR()); 3473 } 3474 3475 cmn_err(CE_CONT, "board %d is PRESENT\n", board); 3476 3477 bdesc = (board_desc_t *)pda_get_board_info(ph, board); 3478 if (bdesc == NULL) { 3479 cmn_err(CE_CONT, 3480 "no board descriptor found for board %d\n", 3481 board); 3482 pda_close(ph); 3483 return (DRMACH_INTERNAL_ERROR()); 3484 } 3485 3486 /* make sure definition in platmod is in sync with pda */ 3487 ASSERT(MAX_PROCMODS == MAX_CPU_UNITS_PER_BOARD); 3488 3489 for (i = 0; i < MAX_PROCMODS; i++) { 3490 if (BDA_NBL(bdesc->bda_proc, i) == BDAN_GOOD) 3491 cmn_err(CE_CONT, 3492 "proc %d.%d PRESENT\n", board, i); 3493 else 3494 cmn_err(CE_CONT, 3495 "proc %d.%d MISSING\n", board, i); 3496 } 3497 3498 for (i = 0; i < MAX_MGROUPS; i++) { 3499 if (BDA_NBL(bdesc->bda_mgroup, i) == BDAN_GOOD) 3500 cmn_err(CE_CONT, 3501 "mgroup %d.%d PRESENT\n", board, i); 3502 else 3503 cmn_err(CE_CONT, 3504 "mgroup %d.%d MISSING\n", board, i); 3505 } 3506 3507 /* make sure definition in platmod is in sync with pda */ 3508 ASSERT(MAX_IOCS == MAX_IO_UNITS_PER_BOARD); 3509 3510 for (i = 0; i < MAX_IOCS; i++) { 3511 int s; 3512 3513 if (BDA_NBL(bdesc->bda_ioc, i) == BDAN_GOOD) { 3514 cmn_err(CE_CONT, 3515 "ioc %d.%d PRESENT\n", board, i); 3516 for (s = 0; s < MAX_SLOTS_PER_IOC; s++) { 3517 if (BDA_NBL(bdesc->bda_ios[i], s) != BDAN_GOOD) 3518 continue; 3519 cmn_err(CE_CONT, 3520 "..scard %d.%d.%d PRESENT\n", 3521 board, i, s); 3522 } 3523 } else { 3524 cmn_err(CE_CONT, 3525 "ioc %d.%d MISSING\n", 3526 board, i); 3527 } 3528 } 3529 3530 cmn_err(CE_CONT, 3531 "board %d memsize = %d pages\n", 3532 board, pda_get_mem_size(ph, board)); 3533 3534 pda_close(ph); 3535 3536 return (NULL); 3537 } 3538 3539 /*ARGSUSED*/ 3540 sbd_error_t * 3541 drmach_pt_readmem(drmachid_t id, drmach_opts_t *opts) 3542 { 3543 struct memlist *ml; 3544 uint64_t src_pa; 3545 uint64_t dst_pa; 3546 uint64_t dst; 3547 3548 dst_pa = va_to_pa(&dst); 3549 3550 memlist_read_lock(); 3551 for (ml = phys_install; ml; ml = ml->next) { 3552 uint64_t nbytes; 3553 3554 src_pa = ml->address; 3555 nbytes = ml->size; 3556 3557 while (nbytes != 0ull) { 3558 3559 /* copy 32 bytes at arc_pa to dst_pa */ 3560 bcopy32_il(src_pa, dst_pa); 3561 3562 /* increment by 32 bytes */ 3563 src_pa += (4 * sizeof (uint64_t)); 3564 3565 /* decrement by 32 bytes */ 3566 nbytes -= (4 * sizeof (uint64_t)); 3567 } 3568 } 3569 memlist_read_unlock(); 3570 3571 return (NULL); 3572 } 3573 3574 static struct { 3575 const char *name; 3576 sbd_error_t *(*handler)(drmachid_t id, drmach_opts_t *opts); 3577 } drmach_pt_arr[] = { 3578 { "juggle", drmach_pt_juggle_bootproc }, 3579 { "pda", drmach_pt_dump_pdainfo }, 3580 { "readmem", drmach_pt_readmem }, 3581 3582 /* the following line must always be last */ 3583 { NULL, NULL } 3584 }; 3585 3586 /*ARGSUSED*/ 3587 sbd_error_t * 3588 drmach_passthru(drmachid_t id, drmach_opts_t *opts) 3589 { 3590 int i; 3591 sbd_error_t *err; 3592 3593 i = 0; 3594 while (drmach_pt_arr[i].name != NULL) { 3595 int len = strlen(drmach_pt_arr[i].name); 3596 3597 if (strncmp(drmach_pt_arr[i].name, opts->copts, len) == 0) 3598 break; 3599 3600 i += 1; 3601 } 3602 3603 if (drmach_pt_arr[i].name == NULL) 3604 err = drerr_new(0, ESTF_UNKPTCMD, opts->copts); 3605 else 3606 err = (*drmach_pt_arr[i].handler)(id, opts); 3607 3608 return (err); 3609 } 3610 3611 sbd_error_t * 3612 drmach_release(drmachid_t id) 3613 { 3614 drmach_common_t *cp; 3615 if (!DRMACH_IS_DEVICE_ID(id)) 3616 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3617 cp = id; 3618 3619 return (cp->release(id)); 3620 } 3621 3622 sbd_error_t * 3623 drmach_status(drmachid_t id, drmach_status_t *stat) 3624 { 3625 drmach_common_t *cp; 3626 3627 if (!DRMACH_IS_ID(id)) 3628 return (drerr_new(0, ESTF_NOTID, NULL)); 3629 cp = id; 3630 3631 return (cp->status(id, stat)); 3632 } 3633 3634 sbd_error_t * 3635 drmach_unconfigure(drmachid_t id, int flags) 3636 { 3637 drmach_device_t *dp; 3638 pnode_t nodeid; 3639 dev_info_t *dip, *fdip = NULL; 3640 3641 if (!DRMACH_IS_DEVICE_ID(id)) 3642 return (drerr_new(0, ESTF_INAPPROP, NULL)); 3643 3644 dp = id; 3645 3646 nodeid = drmach_node_get_dnode(dp->node); 3647 if (nodeid == OBP_NONODE) 3648 return (DRMACH_INTERNAL_ERROR()); 3649 3650 dip = e_ddi_nodeid_to_dip(nodeid); 3651 if (dip == NULL) 3652 return (NULL); 3653 3654 /* 3655 * Branch already held, so hold acquired in 3656 * e_ddi_nodeid_to_dip() can be released 3657 */ 3658 ddi_release_devi(dip); 3659 3660 if (flags & DEVI_BRANCH_DESTROY) 3661 flags |= DEVI_BRANCH_EVENT; 3662 3663 /* 3664 * Force flag is no longer necessary. See starcat/io/drmach.c 3665 * for details. 3666 */ 3667 ASSERT(e_ddi_branch_held(dip)); 3668 if (e_ddi_branch_unconfigure(dip, &fdip, flags)) { 3669 sbd_error_t *err; 3670 char *path = kmem_alloc(MAXPATHLEN, KM_SLEEP); 3671 3672 /* 3673 * If non-NULL, fdip is returned held and must be released. 3674 */ 3675 if (fdip != NULL) { 3676 (void) ddi_pathname(fdip, path); 3677 ndi_rele_devi(fdip); 3678 } else { 3679 (void) ddi_pathname(dip, path); 3680 } 3681 3682 err = drerr_new(1, ESTF_DRVFAIL, path); 3683 3684 kmem_free(path, MAXPATHLEN); 3685 3686 return (err); 3687 } 3688 3689 return (NULL); 3690 } 3691 3692 /* 3693 * drmach interfaces to legacy Starfire platmod logic 3694 * linkage via runtime symbol look up, called from plat_cpu_power* 3695 */ 3696 3697 /* 3698 * Start up a cpu. It is possible that we're attempting to restart 3699 * the cpu after an UNCONFIGURE in which case the cpu will be 3700 * spinning in its cache. So, all we have to do is wakeup him up. 3701 * Under normal circumstances the cpu will be coming from a previous 3702 * CONNECT and thus will be spinning in OBP. In both cases, the 3703 * startup sequence is the same. 3704 */ 3705 int 3706 drmach_cpu_poweron(struct cpu *cp) 3707 { 3708 DRMACH_PR("drmach_cpu_poweron: starting cpuid %d\n", cp->cpu_id); 3709 3710 ASSERT(MUTEX_HELD(&cpu_lock)); 3711 3712 if (drmach_cpu_start(cp) != 0) 3713 return (EBUSY); 3714 else 3715 return (0); 3716 } 3717 3718 int 3719 drmach_cpu_poweroff(struct cpu *cp) 3720 { 3721 int ntries, cnt; 3722 processorid_t cpuid = cp->cpu_id; 3723 void drmach_cpu_shutdown_self(void); 3724 3725 DRMACH_PR("drmach_cpu_poweroff: stopping cpuid %d\n", cp->cpu_id); 3726 3727 ASSERT(MUTEX_HELD(&cpu_lock)); 3728 3729 /* 3730 * Capture all CPUs (except for detaching proc) to prevent 3731 * crosscalls to the detaching proc until it has cleared its 3732 * bit in cpu_ready_set. 3733 * 3734 * The CPU's remain paused and the prom_mutex is known to be free. 3735 * This prevents the x-trap victim from blocking when doing prom 3736 * IEEE-1275 calls at a high PIL level. 3737 */ 3738 promsafe_pause_cpus(); 3739 3740 /* 3741 * Quiesce interrupts on the target CPU. We do this by setting 3742 * the CPU 'not ready'- (i.e. removing the CPU from cpu_ready_set) to 3743 * prevent it from receiving cross calls and cross traps. 3744 * This prevents the processor from receiving any new soft interrupts. 3745 */ 3746 mp_cpu_quiesce(cp); 3747 3748 /* setup xt_mb, will be cleared by drmach_shutdown_asm when ready */ 3749 drmach_xt_mb[cpuid] = 0x80; 3750 3751 xt_one_unchecked(cpuid, (xcfunc_t *)idle_stop_xcall, 3752 (uint64_t)drmach_cpu_shutdown_self, NULL); 3753 3754 ntries = drmach_cpu_ntries; 3755 cnt = 0; 3756 while (drmach_xt_mb[cpuid] && ntries) { 3757 DELAY(drmach_cpu_delay); 3758 ntries--; 3759 cnt++; 3760 } 3761 3762 drmach_xt_mb[cpuid] = 0; /* steal the cache line back */ 3763 3764 start_cpus(); 3765 3766 DRMACH_PR("waited %d out of %d tries for " 3767 "drmach_cpu_shutdown_self on cpu%d", 3768 drmach_cpu_ntries - ntries, drmach_cpu_ntries, cp->cpu_id); 3769 3770 drmach_cpu_obp_detach(cpuid); 3771 3772 CPU_SIGNATURE(OS_SIG, SIGST_DETACHED, SIGSUBST_NULL, cpuid); 3773 3774 return (0); 3775 } 3776 3777 /*ARGSUSED*/ 3778 int 3779 drmach_verify_sr(dev_info_t *dip, int sflag) 3780 { 3781 return (0); 3782 } 3783 3784 void 3785 drmach_suspend_last(void) 3786 { 3787 } 3788 3789 void 3790 drmach_resume_first(void) 3791 { 3792 } 3793 3794 /* 3795 * Log a DR sysevent. 3796 * Return value: 0 success, non-zero failure. 3797 */ 3798 int 3799 drmach_log_sysevent(int board, char *hint, int flag, int verbose) 3800 { 3801 sysevent_t *ev; 3802 sysevent_id_t eid; 3803 int rv, km_flag; 3804 sysevent_value_t evnt_val; 3805 sysevent_attr_list_t *evnt_attr_list = NULL; 3806 char attach_pnt[MAXNAMELEN]; 3807 3808 km_flag = (flag == SE_SLEEP) ? KM_SLEEP : KM_NOSLEEP; 3809 attach_pnt[0] = '\0'; 3810 if (drmach_board_name(board, attach_pnt, MAXNAMELEN)) { 3811 rv = -1; 3812 goto logexit; 3813 } 3814 if (verbose) 3815 DRMACH_PR("drmach_log_sysevent: %s %s, flag: %d, verbose: %d\n", 3816 attach_pnt, hint, flag, verbose); 3817 3818 if ((ev = sysevent_alloc(EC_DR, ESC_DR_AP_STATE_CHANGE, 3819 SUNW_KERN_PUB"dr", km_flag)) == NULL) { 3820 rv = -2; 3821 goto logexit; 3822 } 3823 evnt_val.value_type = SE_DATA_TYPE_STRING; 3824 evnt_val.value.sv_string = attach_pnt; 3825 if ((rv = sysevent_add_attr(&evnt_attr_list, DR_AP_ID, 3826 &evnt_val, km_flag)) != 0) 3827 goto logexit; 3828 3829 evnt_val.value_type = SE_DATA_TYPE_STRING; 3830 evnt_val.value.sv_string = hint; 3831 if ((rv = sysevent_add_attr(&evnt_attr_list, DR_HINT, 3832 &evnt_val, km_flag)) != 0) { 3833 sysevent_free_attr(evnt_attr_list); 3834 goto logexit; 3835 } 3836 3837 (void) sysevent_attach_attributes(ev, evnt_attr_list); 3838 3839 /* 3840 * Log the event but do not sleep waiting for its 3841 * delivery. This provides insulation from syseventd. 3842 */ 3843 rv = log_sysevent(ev, SE_NOSLEEP, &eid); 3844 3845 logexit: 3846 if (ev) 3847 sysevent_free(ev); 3848 if ((rv != 0) && verbose) 3849 cmn_err(CE_WARN, 3850 "drmach_log_sysevent failed (rv %d) for %s %s\n", 3851 rv, attach_pnt, hint); 3852 3853 return (rv); 3854 } 3855 3856 /*ARGSUSED*/ 3857 int 3858 drmach_allow_memrange_modify(drmachid_t id) 3859 { 3860 return (1); /* TRUE */ 3861 } 3862