xref: /titanic_51/usr/src/uts/sun4u/starcat/sys/iosramvar.h (revision 15d9d0b528387242011cdcc6190c9e598cfe3a07)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2000 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_IOSRAMVAR_H
28 #define	_SYS_IOSRAMVAR_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 
37 /*
38  * Data sizes used by the original author
39  */
40 #ifndef UINT32SZ
41 #define	UINT32SZ	sizeof (uint32_t)
42 #define	UINT64SZ	sizeof (uint64_t)
43 #endif
44 
45 /*
46  * Values used for tunnel switching
47  */
48 #define	OBP_TSWITCH_REQREPLY	0		/* request reply from SSC */
49 #define	OBP_TSWITCH_NOREPLY	1		/* don't wait for reply */
50 #define	IOSRAM_TSWITCH_RETRY	20		/* # of times to wait for */
51 						/*   current tunnel switch to */
52 						/*   end when starting a new */
53 						/*   one */
54 /*
55  * When performing back-to-back tunnel switches, we have to make sure that
56  * HWAD (the SC-side implementation) has time to find the new tunnel from
57  * one switch before we invalidate it for the next switch.  To ensure that,
58  * we make sure that the time between consecutive tunnel switches is at
59  * least twice the polling rate HWAD uses to detect the new tunnel.
60  */
61 #define	IOSRAM_TSWITCH_DELAY_US	100000
62 
63 /*
64  * Values used for hash table maintenance
65  */
66 #define	IOSRAM_HASHSZ	0x20		/* # hash entries */
67 #define	IOSRAM_HASH(key)	((((key) >> 24) ^ ((key) >> 16) ^\
68 				((key) >> 9) ^ (key)) & (IOSRAM_HASHSZ - 1))
69 
70 /*
71  * A pair of flags is associated with each IOSRAM chunk in the IOSRAM TOC.
72  * These flags are stored sequentially in the "SC Domain Communication Data"
73  * ('SDCD') IOSRAM chunk.  The data-valid/int-pending flags are one byte each
74  * and stored sequentially with data-valid flag being the first.  The following
75  * macros define the offset of the flags for each IOSRAM chunk based upon its
76  * location (index) in the IOSRAM TOC.
77  */
78 #define	IOSRAM_DATAVALID_FLAGOFF(index)		(2 * (index))
79 #define	IOSRAM_INTPENDING_FLAGOFF(index)	(2 * (index) + 1)
80 
81 /*
82  * IOSRAM node properties (per IOSRAM node)
83  */
84 #define	IOSRAM_REG_PROP		"reg"
85 #define	IOSRAM_TUNNELOK_PROP	"tunnel-capable"
86 
87 /*
88  * Other IOSRAM properties (on chosen node and parent hierarchy)
89  */
90 #define	IOSRAM_CHOSEN_PROP	"iosram"
91 #define	IOSRAM_PORTID_PROP	"portid"
92 
93 /*
94  * Interrupt priority (PIL) used for IOSRAM interrupts.  The value 5 was
95  * chosen somewhat arbitrarily based on the fact that it is higher than
96  * disks and lower than networks.
97  */
98 #define	IOSRAM_PIL	5
99 
100 /*
101  * IOSRAM header structure, located at the beginning of IOSRAM.
102  *
103  * NOTE - New fields may be appended to this structure, but no existing fields
104  *        may be altered in any way!!!
105  */
106 typedef struct {
107 	uint32_t	status;
108 	uint32_t	version;
109 	uint32_t	toc_offset;
110 	uint32_t	sms_mbox_version;
111 	uint32_t	os_mbox_version;
112 	uint32_t	obp_mbox_version;
113 	uint32_t	sms_change_mask;
114 	uint32_t	os_change_mask;
115 } iosram_hdr_t;
116 
117 /*
118  * Values for the status field
119  */
120 #define	IOSRAM_INVALID		0x494e5644	/* 'INVD' */
121 #define	IOSRAM_VALID		0x56414c44	/* 'VALD' */
122 #define	IOSRAM_INTRANSIT	0x494e5452	/* 'INTR' */
123 
124 /*
125  * Maximum IOSRAM Protocol version understood by this implementation
126  */
127 #define	IOSRAM_MAX_PROTOCOL_VERSION		1
128 
129 /*
130  * Bit definitions for *_change_mask fields
131  */
132 #define	IOSRAM_HDRFIELD_SMS_MBOX_VER	0x00000001
133 #define	IOSRAM_HDRFIELD_OS_MBOX_VER	0x00000002
134 #define	IOSRAM_HDRFIELD_TOC_INDEX	0x00000004
135 
136 /*
137  * Macros used to access fields in the header
138  */
139 #define	IOSRAM_GET_HDRFIELD32(softp, field)	\
140 	(ddi_get32((softp)->handle, &((iosram_hdr_t *)(softp)->iosramp)->field))
141 #define	IOSRAM_SET_HDRFIELD32(softp, field, val)	\
142 	(ddi_put32((softp)->handle, &((iosram_hdr_t *)(softp)->iosramp)->field,\
143 	(val)))
144 
145 /*
146  * IOSRAM contains various data chunks and the key, location and size of
147  * each IOSRAM chunk is communicated to the IOSRAM driver in the form of a
148  * Table of Contents.  This structre contains one entry for each IOSRAM
149  * chunk, as well as an initial index entry.  Each entry has the following
150  * structure.
151  *
152  * NOTE - Although the unused field may be renamed for some use in the future,
153  *        no other modification to this structure is allowed!!!
154  */
155 
156 typedef struct {
157 	uint32_t	key;		/* IOSRAM chunk key */
158 	uint32_t	off;		/* IOSRAM chunk starting offset */
159 	uint32_t	len;		/* IOSRAM chunk length */
160 	uint32_t	unused;		/* currently unused */
161 } iosram_toc_entry_t;
162 
163 /*
164  * Special values used in some TOC entries
165  */
166 #define	IOSRAM_FLAGS_KEY	0x53444344	/* 'SDCD' - flags chunk key */
167 #define	IOSRAM_INDEX_KEY	0x494e4458	/* 'INDX' - index entry key */
168 #define	IOSRAM_INDEX_OFF	0xFFFFFFFF	/* index entry offset */
169 
170 
171 /*
172  * IOSRAM flags structure.  An array of these - one for every IOSRAM chunk - is
173  * stored in the SDCD chunk.
174  */
175 typedef struct {
176 	uint8_t	data_valid;
177 	uint8_t	int_pending;
178 } iosram_flags_t;
179 
180 /*
181  * IOSRAM callback data structure
182  */
183 typedef struct {
184 	uchar_t		busy;		/* cback handler is active/busy */
185 	uchar_t		unregister;	/* delayed callback unregistration */
186 	void		(*handler)();	/* cback handler */
187 	void		*arg;		/* cback handler arg */
188 } iosram_cback_t;
189 
190 
191 /*
192  * IOSRAM per chunk state
193  */
194 typedef struct iosram_chunk {
195 	iosram_toc_entry_t toc_data;	/* Data from TOC entry */
196 	iosram_cback_t	cback;		/* callback info */
197 	uint8_t		*basep;		/* kvaddr for this IOSRAM chunk */
198 	iosram_flags_t	*flagsp;
199 	struct iosram_chunk *hash;	/* next entry in the hash list */
200 } iosram_chunk_t;
201 
202 
203 /*
204  * IOSRAM per instance state
205  */
206 
207 typedef struct iosramsoft {
208 	struct iosramsoft *prev;	/* ptr for linked list */
209 	struct iosramsoft *next;	/* ptr for linked list */
210 
211 	boolean_t	suspended;	/* TRUE if driver suspended */
212 	int		instance;	/* driver instance number */
213 	dev_info_t	*dip;		/* device information */
214 
215 	uchar_t		*iosramp;	/* IOSRAM mapped vaddr */
216 	int		iosramlen; 	/* IOSRAM length */
217 	int		nchunks;	/* # IOSRAM chunks */
218 	iosram_chunk_t	*chunks;	/* ptr to iosram_chunk array */
219 	iosram_chunk_t	*flags_chunk;	/* ptr to flags chunk */
220 	ddi_acc_handle_t handle;	/* IOSRAM map handle */
221 
222 	ddi_iblock_cookie_t real_iblk;	/* real intr iblock cookie */
223 	ddi_iblock_cookie_t soft_iblk;	/* soft intr iblock cookie */
224 	ddi_softintr_t	softintr_id;	/* soft interrupt ID */
225 	ushort_t	intr_busy;	/* softintr handler busy */
226 	ushort_t	intr_pending;	/* interrupt pending */
227 
228 	int		state;		/* IOSRAM state (see below) */
229 	int		portid;		/* Card port ID for tswitch */
230 	uint32_t	tswitch_ok;	/* # successful tunnel switch */
231 	uint32_t	tswitch_fail;	/* # failed tunnel switch */
232 
233 	ddi_acc_handle_t sbbc_handle;	/* SBBC regs map handle */
234 	iosram_sbbc_region_t *sbbc_region; /* region of SBBC registers */
235 	uint32_t	int_enable_sav;	/* save int enable reg. on suspend */
236 	kmutex_t	intr_mutex;	/* real interrupt handler mutex */
237 } iosramsoft_t;
238 
239 
240 /* IOSRAM state value */
241 #define	IOSRAM_STATE_INIT	0x0001	/* initialization */
242 #define	IOSRAM_STATE_SLAVE	0x0002	/* SLAVE IOSRAM */
243 #define	IOSRAM_STATE_MASTER	0x0004	/* MASTER IOSRAM */
244 #define	IOSRAM_STATE_MAPPED	0x0008	/* IOSRAM mapped */
245 
246 #define	IOSRAM_STATE_TSWITCH	0x0010	/* tunnel switch source/target */
247 #define	IOSRAM_STATE_DETACH	0x0020	/* IOSRAM instance being detached */
248 
249 
250 #if DEBUG
251 #define	IOSRAM_STATS	1		/* enable IOSRAM statistics */
252 #define	IOSRAM_LOG	1		/* enable IOSRAM logging */
253 #endif
254 
255 #if IOSRAM_STATS
256 
257 /*
258  * IOSRAM statistics
259  */
260 struct iosram_stat {
261 	uint32_t	read;		/* calls to iosram_read */
262 	uint32_t	write;		/* calls to iosram_{force_}write */
263 	uint32_t	getflag;	/* calls to iosram_getflag */
264 	uint32_t	setflag;	/* calls to iosram_getflag */
265 	uint32_t	tswitch;	/* # tunnel switch */
266 	uint32_t	callbacks;	/* # callbacks invoked */
267 	uint32_t	intr_recv;	/* # interrupts received */
268 	uint32_t	sintr_recv;	/* # softintr received */
269 	uint32_t	intr_send;	/* # interrupts sent */
270 	uint64_t	bread;		/* # bytes read */
271 	uint64_t	bwrite;		/* # bytes written */
272 };
273 
274 #define	IOSRAM_STAT(field)		iosram_stats.field++
275 #define	IOSRAM_STAT_ADD(field, amount)	iosram_stats.field += (uint64_t)amount
276 #define	IOSRAM_STAT_SET(field, count)	iosram_stats.field = (uint64_t)count
277 
278 #else /* !IOSRAM_STATS */
279 
280 #define	IOSRAM_STAT(field)
281 #define	IOSRAM_STAT_ADD(field, amount)
282 #define	IOSRAM_STAT_SET(field, count)
283 
284 #endif /* !IOSRAM_STATS */
285 
286 
287 #if IOSRAM_LOG
288 
289 /*
290  * IOSRAM log related structures and extern declarations
291  */
292 
293 #define	IOSRAM_MAXLOG	64
294 
295 typedef struct {
296 	uint32_t	seq;		/* logseg# */
297 	clock_t		tstamp;		/* time stamp */
298 	caddr_t		fmt;		/* format ptr */
299 	intptr_t 	arg1;		/* first arg */
300 	intptr_t 	arg2;		/* second arg */
301 	intptr_t 	arg3;		/* third arg */
302 	intptr_t 	arg4;		/* fourth arg */
303 } iosram_log_t;
304 
305 #define	IOSRAMLOG(level, fmt, a1, a2, a3, a4)			\
306 	if (iosram_log_level >= level) {			\
307 		iosram_log(fmt, (intptr_t)a1, (intptr_t)a2, 	\
308 			(intptr_t)a3, (intptr_t)a4);		\
309 	}
310 
311 extern int	iosram_log_level;
312 extern uint32_t	iosram_logseq;
313 extern iosram_log_t iosram_logbuf[IOSRAM_MAXLOG];
314 extern void iosram_log(caddr_t, intptr_t, intptr_t, intptr_t, intptr_t);
315 
316 #else	/* !IOSRAM_LOG */
317 
318 #define	IOSRAMLOG(level, fmt, a1, a2, a3, a4)
319 
320 #endif	/* !IOSRAM_LOG */
321 
322 
323 #ifdef	__cplusplus
324 }
325 #endif
326 
327 #endif	/* _SYS_IOSRAMVAR_H */
328