1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2000 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_IOSRAMREG_H 28 #define _SYS_IOSRAMREG_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 37 38 /* 39 * iosram_reg_t property (an array of following tuple/data) 40 * address format 41 * hi npt000ss bbbbbbbb dddddfff rrrrrrrr 42 * mid hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 43 * low llllllll llllllll llllllll llllllll 44 * 45 * size format 46 * hi hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 47 * low llllllll llllllll llllllll llllllll 48 * n=0 if relocatable 49 * p=1 if addressable region is prefetchable 50 * t=1 if address region is aliased 51 * ss=00 Config. space also n,p,t must be 0 52 * =01 I/O space p must be 0 53 * =10 32 bit address memory space 54 * =11 64 bit address memory space 55 * bbbbbbbb 8 bit bus number 56 * ddddd 5 bit device number 57 * fff 3 bit function number 58 * rrrrrrrr 8 bit register number 59 * hhhhhhhh 32 bit unsigned number 60 * llllllll 32 bit unsigned number 61 * 62 * address: 64 bits memory space 63 * hi 00000011 00000000 00000000 00000000 64 * 0x03000000 65 * mid 00000000 00000000 00000000 00000000 66 * 0x00000000 67 * low 00000000 00010000 00000000 00000000 68 * 0x00100000 69 * size 70 * hi 00000000 00000000 00000000 00000000 71 * low 00000000 00000011 11111111 11111111 72 */ 73 74 typedef struct { 75 uint32_t addr_hi; 76 uint32_t addr_lo; 77 uint32_t size; 78 } iosram_reg_t; 79 80 81 /* 82 * SBBC access structures. Each SBBC register is 32 bits aligned on a 16 83 * byte boundary. The iosram_sbbc_region structure should be mapped onto 84 * the SBBC register space starting at 0x1000 to achieve correct alignment 85 * between structure fields and SBBC registers. 86 */ 87 typedef struct iosram_sbbcr { 88 uint32_t reg; /* 32-bit register */ 89 uint32_t pad[3]; /* padding to fill out 16 bytes */ 90 } iosram_sbbcr_t; 91 92 typedef struct iosram_sbbc_region { 93 iosram_sbbcr_t synch[16]; /* 0x1000 - 10ff - semaphore region */ 94 iosram_sbbcr_t pad0[240]; /* 0x1100 - 1fff - padding */ 95 iosram_sbbcr_t p0_int_gen; /* 0x2000 - 200f - PCI port 0 */ 96 /* interrupt generation */ 97 iosram_sbbcr_t p1_int_gen; /* 0x2010 - 201f - PCI port 1 */ 98 /* interrupt generation */ 99 iosram_sbbcr_t pad1[48]; /* 0x2020 - 231f - padding */ 100 iosram_sbbcr_t int_status; /* 0x2320 - 232f - interrupt status */ 101 iosram_sbbcr_t int_enable; /* 0x2330 - 233f - interrupt enables */ 102 } iosram_sbbc_region_t; 103 104 #define IOSRAM_SBBC_MAP_OFFSET 0x1000 /* offset of SBBC regs to be mapped */ 105 #define IOSRAM_SBBC_MAP_INDEX 0x1 /* address space set # for SBBC regs */ 106 #define IOSRAM_SBBC_INT0 0x01 107 #define IOSRAM_SBBC_INT1 0x10 108 109 /* 110 * SBBC hardware semaphore access 111 */ 112 113 /* indices into sbbc_region->synch array */ 114 #define IOSRAM_SEMA_SMS_IDX 0x1 /* when accessed by SMS */ 115 #define IOSRAM_SEMA_DOM_IDX 0x8 /* when accessed by domain */ 116 #define IOSRAM_SEMA_OBP_IDX 0xf /* when accessed by OBP */ 117 118 /* mask for bits used to encode how semaphore was acquired (bits 1-4) */ 119 #define IOSRAM_SEMA_MASK 0x1e 120 121 /* read an write semaphore values using domain assigned register */ 122 #define IOSRAM_SEMA_RD(softp) ddi_get32((softp)->sbbc_handle, \ 123 &(softp->sbbc_region->synch[IOSRAM_SEMA_DOM_IDX].reg)); 124 #define IOSRAM_SEMA_WR(softp, v) ddi_put32((softp)->sbbc_handle, \ 125 &(softp->sbbc_region->synch[IOSRAM_SEMA_DOM_IDX].reg), v); 126 127 #define IOSRAM_SEMA_IS_HELD(v) ((v) & 0x1) 128 #define IOSRAM_SEMA_GET_IDX(v) (((v) & IOSRAM_SEMA_MASK) >> 1) 129 130 #ifdef __cplusplus 131 } 132 #endif 133 134 #endif /* _SYS_IOSRAMREG_H */ 135