1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4U_H 27 #define _SYS_PX_LIB4U_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Errors returned. 37 */ 38 #define H_EOK 0 /* Successful return */ 39 #define H_ENOINTR 1 /* Invalid interrupt id */ 40 #define H_EINVAL 2 /* Invalid argument */ 41 #define H_ENOACCESS 3 /* No access to resource */ 42 #define H_EIO 4 /* I/O error */ 43 #define H_ENOTSUPPORTED 5 /* Function not supported */ 44 #define H_ENOMAP 6 /* Mapping is not valid, */ 45 /* no translation exists */ 46 47 /* 48 * Register base definitions. 49 * 50 * The specific numeric values for CSR, XBUS, Configuration, 51 * Interrupt blocks and other register bases. 52 */ 53 typedef enum { 54 PX_REG_CSR = 0, 55 PX_REG_XBC, 56 PX_REG_CFG, 57 PX_REG_IC, 58 PX_REG_MAX 59 } px_reg_bank_t; 60 61 /* 62 * Registers/state/variables that need to be saved and restored during 63 * suspend/resume. 64 * 65 * SUN4U px specific data structure. 66 */ 67 68 /* Control block soft state structure */ 69 typedef struct px_cb_list { 70 px_t *pxp; 71 struct px_cb_list *next; 72 } px_cb_list_t; 73 74 typedef struct px_cb { 75 px_cb_list_t *pxl; /* linked list px */ 76 kmutex_t cb_mutex; /* lock for CB */ 77 sysino_t sysino; /* proxy sysino */ 78 cpuid_t cpuid; /* proxy cpuid */ 79 int attachcnt; /* number of attached px */ 80 uint_t (*px_cb_func)(caddr_t); /* CB intr dispatcher */ 81 } px_cb_t; 82 83 typedef struct pxu { 84 uint32_t chip_id; 85 uint8_t portid; 86 uint16_t tsb_cookie; 87 uint32_t tsb_size; 88 uint64_t *tsb_vaddr; 89 uint64_t tsb_paddr; /* Only used for Oberon */ 90 91 void *msiq_mapped_p; 92 px_cb_t *px_cb_p; 93 94 /* Soft state for suspend/resume */ 95 uint64_t *pec_config_state; 96 uint64_t *mmu_config_state; 97 uint64_t *ib_intr_map; 98 uint64_t *ib_config_state; 99 uint64_t *xcb_config_state; 100 uint64_t *msiq_config_state; 101 102 /* sun4u specific vars */ 103 caddr_t px_address[4]; 104 ddi_acc_handle_t px_ac[4]; 105 } pxu_t; 106 107 #define PX2CB(px_p) (((pxu_t *)px_p->px_plat_p)->px_cb_p) 108 109 /* 110 * Event Queue data structure. 111 */ 112 typedef struct eq_rec { 113 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */ 114 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */ 115 eq_rec_len : 10, /* DW 0 - 55:46 */ 116 eq_rec_addr0 : 14, /* DW 0 - 45:32 */ 117 eq_rec_rid : 16, /* DW 0 - 31:16 */ 118 eq_rec_data0 : 16; /* DW 0 - 15:00 */ 119 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */ 120 eq_rec_data1 : 16; /* DW 1 - 15:0 */ 121 uint64_t eq_rec_rsvd[6]; /* DW 2-7 */ 122 } eq_rec_t; 123 124 /* 125 * EQ record type 126 * 127 * Upper 4 bits of eq_rec_fmt_type is used 128 * to identify the EQ record type. 129 */ 130 #define EQ_REC_MSG 0x6 /* MSG - 0x3X */ 131 #define EQ_REC_MSI32 0xB /* MSI32 - 0x58 */ 132 #define EQ_REC_MSI64 0xF /* MSI64 - 0x78 */ 133 134 /* EQ State */ 135 #define EQ_IDLE_STATE 0x1 /* IDLE */ 136 #define EQ_ACTIVE_STATE 0x2 /* ACTIVE */ 137 #define EQ_ERROR_STATE 0x4 /* ERROR */ 138 139 #define MMU_INVALID_TTE 0ull 140 #define MMU_TTE_VALID(tte) (((tte) & MMU_TTE_V) == MMU_TTE_V) 141 #define MMU_OBERON_PADDR_MASK 0x7fffffffffff 142 #define MMU_FIRE_PADDR_MASK 0x7ffffffffff 143 144 /* 145 * control register decoding 146 */ 147 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 148 #define MMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 149 #define MMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 150 151 /* 152 * For Fire mmu bypass addresses, bit 43 specifies cacheability. 153 */ 154 #define MMU_FIRE_BYPASS_NONCACHE (1ull << 43) 155 156 /* 157 * For Oberon mmu bypass addresses, bit 47 specifies cacheability. 158 */ 159 #define MMU_OBERON_BYPASS_NONCACHE (1ull << 47) 160 161 /* 162 * The following macros define the address ranges supported for DVMA 163 * and mmu bypass transfers. For Oberon, bit 63 is used for ordering. 164 */ 165 #define MMU_FIRE_BYPASS_BASE 0xFFFC000000000000ull 166 #define MMU_FIRE_BYPASS_END 0xFFFC01FFFFFFFFFFull 167 168 #define MMU_OBERON_BYPASS_BASE 0x7FFC000000000000ull 169 #define MMU_OBERON_BYPASS_END 0x7FFC01FFFFFFFFFFull 170 171 #define MMU_TSB_PA_MASK 0x7FFFFFFFE000 172 173 /* 174 * The following macros are for loading and unloading io tte 175 * entries. 176 */ 177 #define MMU_TTE_SIZE 8 178 #define MMU_TTE_V (1ull << 63) 179 #define MMU_TTE_W (1ull << 1) 180 #define MMU_TTE_RO (1ull << 62) /* Oberon Relaxed Ordering */ 181 182 #define INO_BITS 6 /* INO#s are 6 bits long */ 183 #define IGN_BITS 5 /* IGN#s are 5 bits long */ 184 #define INO_MASK 0x3F /* INO#s mask */ 185 #define IGN_MASK 0x1F /* IGN#s mask */ 186 187 #define ID_TO_IGN(portid) ((uint16_t)((portid) & IGN_MASK)) 188 #define ID_TO_NODEID(portid) ((uint16_t)((portid) >> IGN_BITS)) 189 #define DEVINO_TO_SYSINO(portid, devino) \ 190 ((ID_TO_NODEID(portid) << (IGN_BITS + INO_BITS)) | \ 191 ((ID_TO_IGN(portid) << INO_BITS) | (devino & INO_MASK))) 192 #define SYSINO_TO_DEVINO(sysino) (sysino & INO_MASK) 193 194 /* Interrupt states */ 195 #define INTERRUPT_IDLE_STATE 0 196 #define INTERRUPT_RECEIVED_STATE 1 197 #define INTERRUPT_PENDING_STATE 3 198 199 /* 200 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer 201 * and TxLink Replay Timer Latency Table array sizes 202 * Num Link Width Packet Size 203 * 0 1 128 204 * 1 4 256 205 * 2 8 512 206 * 3 16 1024 207 * 4 - 2048 208 * 5 - 4096 209 */ 210 #define LINK_WIDTH_ARR_SIZE 4 211 #define LINK_MAX_PKT_ARR_SIZE 6 212 213 /* 214 * Defines for registers which have multi-bit fields. 215 */ 216 #define TLU_LINK_CONTROL_ASPM_DISABLED 0x0 217 #define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1 218 #define TLU_LINK_CONTROL_ASPM_L1_EN 0x2 219 #define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3 220 221 #define TLU_CONTROL_CONFIG_DEFAULT 0x1 222 #define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull 223 #define TLU_CONTROL_MPS_MASK 0x1C 224 #define TLU_CONTROL_MPS_SHIFT 2 225 226 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0 227 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1 228 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2 229 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3 230 231 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull 232 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull 233 234 #define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF 235 #define LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT 0x0 236 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF 0x157 237 238 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT 0xFFF 239 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT 0x0 240 241 #define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2 242 #define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5 243 #define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0 244 #define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120 245 #define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2 246 #define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c 247 248 /* LPU LTSSM states */ 249 #define LPU_LTSSM_L0 0x0 250 #define LPU_LTSSM_L1_IDLE 0x15 251 252 /* TLU Control register bits */ 253 #define TLU_REMAIN_DETECT_QUIET 8 254 255 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 256 #define PX_PA_BDF_SHIFT 12 257 #define PX_BDF_TO_CFGADDR(bdf, offset) (((bdf) << PX_PA_BDF_SHIFT) + (offset)) 258 259 /* 260 * The sequence of the chip_type appearance is significant. 261 * There are code depending on it: PX_CHIP_TYPE(pxu_p) < PX_CHIP_FIRE. 262 */ 263 typedef enum { 264 PX_CHIP_UNIDENTIFIED = 0, 265 PX_CHIP_FIRE = 1, 266 PX_CHIP_OBERON = 2 267 } px_chip_id_t; 268 269 /* 270 * [msb] [lsb] 271 * 0x00 <chip_type> <version#> <module-revision#> 272 */ 273 #define PX_CHIP_ID(t, v, m) (((t) << 16) | ((v) << 8) | (m)) 274 #define PX_CHIP_TYPE(pxu_p) (((pxu_p)->chip_id) >> 16) 275 #define PX_CHIP_REV(pxu_p) (((pxu_p)->chip_id) & 0xFF) 276 #define PX_CHIP_VER(pxu_p) ((((pxu_p)->chip_id) >> 8) & 0xFF) 277 278 /* 279 * Fire hardware specific version definitions. 280 */ 281 #define FIRE_VER_10 PX_CHIP_ID(PX_CHIP_FIRE, 0x01, 0x00) 282 #define FIRE_VER_20 PX_CHIP_ID(PX_CHIP_FIRE, 0x03, 0x00) 283 #define OBERON_VER_10 PX_CHIP_ID(PX_CHIP_OBERON, 0x00, 0x00) 284 #define FIRE_RANGE_PROP_MASK 0x7ff 285 #define OBERON_RANGE_PROP_MASK 0x7fff 286 287 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 288 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p); 289 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p); 290 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 291 292 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, 293 devino_t devino, sysino_t *sysino); 294 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 295 intr_valid_state_t *intr_valid_state); 296 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 297 intr_valid_state_t intr_valid_state); 298 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 299 intr_state_t *intr_state); 300 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 301 intr_state_t intr_state); 302 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, 303 sysino_t sysino, cpuid_t *cpuid); 304 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, 305 sysino_t sysino, cpuid_t cpuid); 306 307 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 308 pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index, 309 int flags); 310 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, 311 tsbid_t tsbid, pages_t pages); 312 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, 313 tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p); 314 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, 315 r_addr_t ra, io_attributes_t attr, io_addr_t *io_addr_p); 316 extern uint64_t hvio_get_bypass_base(pxu_t *pxu_p); 317 extern uint64_t hvio_get_bypass_end(pxu_t *pxu_p); 318 extern uint64_t px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank); 319 320 321 /* 322 * MSIQ Functions: 323 */ 324 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p); 325 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 326 pci_msiq_valid_state_t *msiq_valid_state); 327 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 328 pci_msiq_valid_state_t msiq_valid_state); 329 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 330 pci_msiq_state_t *msiq_state); 331 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 332 pci_msiq_state_t msiq_state); 333 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 334 msiqhead_t *msiq_head); 335 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 336 msiqhead_t msiq_head); 337 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 338 msiqtail_t *msiq_tail); 339 340 /* 341 * MSI Functions: 342 */ 343 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, 344 uint64_t addr64); 345 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 346 msiqid_t *msiq_id); 347 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 348 msiqid_t msiq_id); 349 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 350 pci_msi_valid_state_t *msi_valid_state); 351 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 352 pci_msi_valid_state_t msi_valid_state); 353 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 354 pci_msi_state_t *msi_state); 355 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 356 pci_msi_state_t msi_state); 357 358 /* 359 * MSG Functions: 360 */ 361 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 362 msiqid_t *msiq_id); 363 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 364 msiqid_t msiq_id); 365 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 366 pcie_msg_valid_state_t *msg_valid_state); 367 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 368 pcie_msg_valid_state_t msg_valid_state); 369 370 /* 371 * Suspend/Resume Functions: 372 */ 373 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 374 extern void hvio_resume(devhandle_t dev_hdl, 375 devino_t devino, pxu_t *pxu_p); 376 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 377 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 378 devino_t devino, pxu_t *pxu_p); 379 extern int px_send_pme_turnoff(caddr_t csr_base); 380 extern int px_link_wait4l1idle(caddr_t csr_base); 381 extern int px_link_retrain(caddr_t csr_base); 382 extern void px_enable_detect_quiet(caddr_t csr_base); 383 384 extern void px_lib_clr_errs(px_t *px_p); 385 386 /* 387 * Hotplug functions: 388 */ 389 extern int hvio_hotplug_init(dev_info_t *dip, void *arg); 390 extern int hvio_hotplug_uninit(dev_info_t *dip); 391 392 #ifdef __cplusplus 393 } 394 #endif 395 396 #endif /* _SYS_PX_LIB4U_H */ 397