1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4U_H 27 #define _SYS_PX_LIB4U_H 28 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * Errors returned. 36 */ 37 #define H_EOK 0 /* Successful return */ 38 #define H_ENOINTR 1 /* Invalid interrupt id */ 39 #define H_EINVAL 2 /* Invalid argument */ 40 #define H_ENOACCESS 3 /* No access to resource */ 41 #define H_EIO 4 /* I/O error */ 42 #define H_ENOTSUPPORTED 5 /* Function not supported */ 43 #define H_ENOMAP 6 /* Mapping is not valid, */ 44 /* no translation exists */ 45 46 /* 47 * Register base definitions. 48 * 49 * The specific numeric values for CSR, XBUS, Configuration, 50 * Interrupt blocks and other register bases. 51 */ 52 typedef enum { 53 PX_REG_CSR = 0, 54 PX_REG_XBC, 55 PX_REG_CFG, 56 PX_REG_IC, 57 PX_REG_MAX 58 } px_reg_bank_t; 59 60 /* 61 * Registers/state/variables that need to be saved and restored during 62 * suspend/resume. 63 * 64 * SUN4U px specific data structure. 65 */ 66 67 /* Control block soft state structure */ 68 typedef struct px_cb_list { 69 px_t *pxp; 70 struct px_cb_list *next; 71 } px_cb_list_t; 72 73 /* IO chip type */ 74 typedef enum { 75 PX_CHIP_UNIDENTIFIED = 0, 76 PX_CHIP_FIRE = 1, 77 PX_CHIP_OBERON = 2 78 } px_chip_type_t; 79 80 #define PX_CHIP_TYPE(pxu_p) ((pxu_p)->chip_type) 81 82 typedef struct px_cb { 83 px_cb_list_t *pxl; /* linked list px */ 84 kmutex_t cb_mutex; /* lock for CB */ 85 sysino_t sysino; /* proxy sysino */ 86 cpuid_t cpuid; /* proxy cpuid */ 87 int attachcnt; /* number of attached px */ 88 uint_t (*px_cb_func)(caddr_t); /* CB intr dispatcher */ 89 } px_cb_t; 90 91 typedef struct pxu { 92 px_chip_type_t chip_type; 93 uint8_t portid; 94 uint16_t tsb_cookie; 95 uint32_t tsb_size; 96 uint64_t *tsb_vaddr; 97 uint64_t tsb_paddr; /* Only used for Oberon */ 98 sysino_t hp_sysino; /* Oberon hotplug interrupt */ 99 100 void *msiq_mapped_p; 101 px_cb_t *px_cb_p; 102 103 /* Soft state for suspend/resume */ 104 uint64_t *pec_config_state; 105 uint64_t *mmu_config_state; 106 uint64_t *ib_intr_map; 107 uint64_t *ib_config_state; 108 uint64_t *xcb_config_state; 109 uint64_t *msiq_config_state; 110 uint_t cpr_flag; 111 112 /* sun4u specific vars */ 113 caddr_t px_address[4]; 114 ddi_acc_handle_t px_ac[4]; 115 116 /* PCItool */ 117 caddr_t pcitool_addr; 118 } pxu_t; 119 120 #define PX2CB(px_p) (((pxu_t *)px_p->px_plat_p)->px_cb_p) 121 122 /* cpr_flag */ 123 #define PX_NOT_CPR 0 124 #define PX_ENTERED_CPR 1 125 126 /* 127 * Event Queue data structure. 128 */ 129 typedef struct eq_rec { 130 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */ 131 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */ 132 eq_rec_len : 10, /* DW 0 - 55:46 */ 133 eq_rec_addr0 : 14, /* DW 0 - 45:32 */ 134 eq_rec_rid : 16, /* DW 0 - 31:16 */ 135 eq_rec_data0 : 16; /* DW 0 - 15:00 */ 136 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */ 137 eq_rec_data1 : 16; /* DW 1 - 15:0 */ 138 uint64_t eq_rec_rsvd[6]; /* DW 2-7 */ 139 } eq_rec_t; 140 141 /* 142 * EQ record type 143 * 144 * Upper 4 bits of eq_rec_fmt_type is used 145 * to identify the EQ record type. 146 */ 147 #define EQ_REC_MSG 0x6 /* MSG - 0x3X */ 148 #define EQ_REC_MSI32 0xB /* MSI32 - 0x58 */ 149 #define EQ_REC_MSI64 0xF /* MSI64 - 0x78 */ 150 151 /* EQ State */ 152 #define EQ_IDLE_STATE 0x1 /* IDLE */ 153 #define EQ_ACTIVE_STATE 0x2 /* ACTIVE */ 154 #define EQ_ERROR_STATE 0x4 /* ERROR */ 155 156 #define MMU_INVALID_TTE 0ull 157 #define MMU_TTE_VALID(tte) (((tte) & MMU_TTE_V) == MMU_TTE_V) 158 #define MMU_OBERON_PADDR_MASK 0x7fffffffffff 159 #define MMU_FIRE_PADDR_MASK 0x7ffffffffff 160 161 /* 162 * control register decoding 163 */ 164 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 165 #define MMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 166 #define MMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 167 168 /* 169 * For Fire mmu bypass addresses, bit 43 specifies cacheability. 170 */ 171 #define MMU_FIRE_BYPASS_NONCACHE (1ull << 43) 172 173 /* 174 * For Oberon mmu bypass addresses, bit 47 specifies cacheability. 175 */ 176 #define MMU_OBERON_BYPASS_NONCACHE (1ull << 47) 177 178 /* 179 * The following macros define the address ranges supported for DVMA 180 * and mmu bypass transfers. For Oberon, bit 63 is used for ordering. 181 */ 182 #define MMU_FIRE_BYPASS_BASE 0xFFFC000000000000ull 183 #define MMU_FIRE_BYPASS_END 0xFFFC03FFFFFFFFFFull 184 185 #define MMU_OBERON_BYPASS_BASE 0x7FFC000000000000ull 186 #define MMU_OBERON_BYPASS_END 0x7FFC7FFFFFFFFFFFull 187 188 #define MMU_OBERON_BYPASS_RO 0x8000000000000000ull 189 190 #define MMU_TSB_PA_MASK 0x7FFFFFFFE000 191 192 /* 193 * The following macros are for loading and unloading io tte 194 * entries. 195 */ 196 #define MMU_TTE_SIZE 8 197 #define MMU_TTE_V (1ull << 63) 198 #define MMU_TTE_W (1ull << 1) 199 #define MMU_TTE_RO (1ull << 62) /* Oberon Relaxed Ordering */ 200 201 #define INO_BITS 6 /* INO#s are 6 bits long */ 202 #define INO_MASK 0x3F /* INO#s mask */ 203 204 #define SYSINO_TO_DEVINO(sysino) (sysino & INO_MASK) 205 206 #define FIRE_IGN_MASK 0x1F /* IGN#s mask, 5 bits long for Fire */ 207 #define OBERON_IGN_MASK 0xFF /* IGN#s mask, 8 bits long for Oberon */ 208 209 #define ID_TO_IGN(chip, portid) ((portid) & ((chip) == PX_CHIP_OBERON ? \ 210 OBERON_IGN_MASK : FIRE_IGN_MASK)) 211 212 #define DEVINO_TO_SYSINO(portid, devino) \ 213 (((portid) << INO_BITS) | ((devino) & INO_MASK)) 214 215 /* Interrupt states */ 216 #define INTERRUPT_IDLE_STATE 0 217 #define INTERRUPT_RECEIVED_STATE 1 218 #define INTERRUPT_PENDING_STATE 3 219 220 /* 221 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer 222 * and TxLink Replay Timer Latency Table array sizes 223 * Num Link Width Packet Size 224 * 0 1 128 225 * 1 4 256 226 * 2 8 512 227 * 3 16 1024 228 * 4 - 2048 229 * 5 - 4096 230 */ 231 #define LINK_WIDTH_ARR_SIZE 4 232 #define LINK_MAX_PKT_ARR_SIZE 6 233 234 /* 235 * Defines for registers which have multi-bit fields. 236 */ 237 #define TLU_LINK_CONTROL_ASPM_DISABLED 0x0 238 #define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1 239 #define TLU_LINK_CONTROL_ASPM_L1_EN 0x2 240 #define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3 241 242 #define TLU_CONTROL_CONFIG_DEFAULT 0x1 243 #define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull 244 #define TLU_CONTROL_MPS_MASK 0x1C 245 #define TLU_CONTROL_MPS_SHIFT 2 246 247 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0 248 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1 249 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2 250 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3 251 252 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull 253 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull 254 255 #define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF 256 #define LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT 0x0 257 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF 0x157 258 259 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT 0xFFF 260 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT 0x0 261 262 #define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2 263 #define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5 264 #define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0 265 #define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120 266 #define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2 267 #define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c 268 269 /* LPU LTSSM states */ 270 #define LPU_LTSSM_L0 0x0 271 #define LPU_LTSSM_L1_IDLE 0x15 272 273 /* TLU Control register bits */ 274 #define TLU_REMAIN_DETECT_QUIET 8 275 276 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 277 #define PX_PA_BDF_SHIFT 12 278 #define PX_BDF_TO_CFGADDR(bdf, offset) (((bdf) << PX_PA_BDF_SHIFT) + (offset)) 279 280 /* 281 * Fire hardware specific version definitions. 282 * All Fire versions > 2.0 will be numerically greater than FIRE_MOD_REV_20 283 */ 284 #define FIRE_MOD_REV_20 0x03 285 286 /* 287 * Oberon specific definitions. 288 */ 289 #define OBERON_RANGE_PROP_MASK 0x7fff 290 291 /* 292 * HW specific paddr mask. 293 */ 294 extern uint64_t px_paddr_mask; 295 296 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 297 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p); 298 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p); 299 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 300 301 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, 302 devino_t devino, sysino_t *sysino); 303 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 304 intr_valid_state_t *intr_valid_state); 305 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 306 intr_valid_state_t intr_valid_state); 307 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 308 intr_state_t *intr_state); 309 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 310 intr_state_t intr_state); 311 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, pxu_t *pxu_p, 312 sysino_t sysino, cpuid_t *cpuid); 313 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, pxu_t *pxu_p, 314 sysino_t sysino, cpuid_t cpuid); 315 316 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 317 pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index, 318 int flags); 319 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, 320 tsbid_t tsbid, pages_t pages); 321 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, 322 tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p); 323 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, pxu_t *pxu_p, 324 r_addr_t ra, io_attributes_t attr, io_addr_t *io_addr_p); 325 extern uint64_t hvio_get_bypass_base(pxu_t *pxu_p); 326 extern uint64_t hvio_get_bypass_end(pxu_t *pxu_p); 327 extern uint64_t px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank); 328 329 330 /* 331 * MSIQ Functions: 332 */ 333 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p); 334 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 335 pci_msiq_valid_state_t *msiq_valid_state); 336 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 337 pci_msiq_valid_state_t msiq_valid_state); 338 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 339 pci_msiq_state_t *msiq_state); 340 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 341 pci_msiq_state_t msiq_state); 342 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 343 msiqhead_t *msiq_head); 344 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 345 msiqhead_t msiq_head); 346 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 347 msiqtail_t *msiq_tail); 348 349 /* 350 * MSI Functions: 351 */ 352 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, 353 uint64_t addr64); 354 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 355 msiqid_t *msiq_id); 356 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 357 msiqid_t msiq_id); 358 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 359 pci_msi_valid_state_t *msi_valid_state); 360 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 361 pci_msi_valid_state_t msi_valid_state); 362 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 363 pci_msi_state_t *msi_state); 364 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 365 pci_msi_state_t msi_state); 366 367 /* 368 * MSG Functions: 369 */ 370 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 371 msiqid_t *msiq_id); 372 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 373 msiqid_t msiq_id); 374 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 375 pcie_msg_valid_state_t *msg_valid_state); 376 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 377 pcie_msg_valid_state_t msg_valid_state); 378 379 /* 380 * Suspend/Resume Functions: 381 */ 382 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 383 extern void hvio_resume(devhandle_t dev_hdl, 384 devino_t devino, pxu_t *pxu_p); 385 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 386 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 387 devino_t devino, pxu_t *pxu_p); 388 extern int px_send_pme_turnoff(caddr_t csr_base); 389 extern int px_link_wait4l1idle(caddr_t csr_base); 390 extern int px_link_retrain(caddr_t csr_base); 391 extern void px_enable_detect_quiet(caddr_t csr_base); 392 393 extern void px_lib_clr_errs(px_t *px_p, dev_info_t *rdip, uint64_t addr); 394 395 /* 396 * Hotplug functions: 397 */ 398 extern int hvio_hotplug_init(dev_info_t *dip, void *arg); 399 extern int hvio_hotplug_uninit(dev_info_t *dip); 400 401 #ifdef __cplusplus 402 } 403 #endif 404 405 #endif /* _SYS_PX_LIB4U_H */ 406