1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/kmem.h> 30 #include <sys/conf.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/sunndi.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/fm/util.h> 36 #include <sys/modctl.h> 37 #include <sys/disp.h> 38 #include <sys/stat.h> 39 #include <sys/ddi_impldefs.h> 40 #include <sys/vmem.h> 41 #include <sys/iommutsb.h> 42 #include <sys/cpuvar.h> 43 #include <sys/ivintr.h> 44 #include <sys/byteorder.h> 45 #include <sys/hotplug/pci/pciehpc.h> 46 #include <sys/spl.h> 47 #include <px_obj.h> 48 #include <pcie_pwr.h> 49 #include "px_tools_var.h" 50 #include <px_regs.h> 51 #include <px_csr.h> 52 #include <sys/machsystm.h> 53 #include "px_lib4u.h" 54 #include "px_err.h" 55 #include "oberon_regs.h" 56 57 #pragma weak jbus_stst_order 58 59 extern void jbus_stst_order(); 60 61 ulong_t px_mmu_dvma_end = 0xfffffffful; 62 uint_t px_ranges_phi_mask = 0xfffffffful; 63 uint64_t *px_oberon_ubc_scratch_regs; 64 uint64_t px_paddr_mask; 65 66 static int px_goto_l23ready(px_t *px_p); 67 static int px_goto_l0(px_t *px_p); 68 static int px_pre_pwron_check(px_t *px_p); 69 static uint32_t px_identity_init(px_t *px_p); 70 static boolean_t px_cpr_callb(void *arg, int code); 71 static uint_t px_cb_intr(caddr_t arg); 72 73 /* 74 * px_lib_map_registers 75 * 76 * This function is called from the attach routine to map the registers 77 * accessed by this driver. 78 * 79 * used by: px_attach() 80 * 81 * return value: DDI_FAILURE on failure 82 */ 83 int 84 px_lib_map_regs(pxu_t *pxu_p, dev_info_t *dip) 85 { 86 ddi_device_acc_attr_t attr; 87 px_reg_bank_t reg_bank = PX_REG_CSR; 88 89 DBG(DBG_ATTACH, dip, "px_lib_map_regs: pxu_p:0x%p, dip 0x%p\n", 90 pxu_p, dip); 91 92 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 93 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 94 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 95 96 /* 97 * PCI CSR Base 98 */ 99 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], 100 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { 101 goto fail; 102 } 103 104 reg_bank++; 105 106 /* 107 * XBUS CSR Base 108 */ 109 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], 110 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { 111 goto fail; 112 } 113 114 pxu_p->px_address[reg_bank] -= FIRE_CONTROL_STATUS; 115 116 done: 117 for (; reg_bank >= PX_REG_CSR; reg_bank--) { 118 DBG(DBG_ATTACH, dip, "reg_bank 0x%x address 0x%p\n", 119 reg_bank, pxu_p->px_address[reg_bank]); 120 } 121 122 return (DDI_SUCCESS); 123 124 fail: 125 cmn_err(CE_WARN, "%s%d: unable to map reg entry %d\n", 126 ddi_driver_name(dip), ddi_get_instance(dip), reg_bank); 127 128 for (reg_bank--; reg_bank >= PX_REG_CSR; reg_bank--) { 129 pxu_p->px_address[reg_bank] = NULL; 130 ddi_regs_map_free(&pxu_p->px_ac[reg_bank]); 131 } 132 133 return (DDI_FAILURE); 134 } 135 136 /* 137 * px_lib_unmap_regs: 138 * 139 * This routine unmaps the registers mapped by map_px_registers. 140 * 141 * used by: px_detach(), and error conditions in px_attach() 142 * 143 * return value: none 144 */ 145 void 146 px_lib_unmap_regs(pxu_t *pxu_p) 147 { 148 int i; 149 150 for (i = 0; i < PX_REG_MAX; i++) { 151 if (pxu_p->px_ac[i]) 152 ddi_regs_map_free(&pxu_p->px_ac[i]); 153 } 154 } 155 156 int 157 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 158 { 159 160 caddr_t xbc_csr_base, csr_base; 161 px_dvma_range_prop_t px_dvma_range; 162 pxu_t *pxu_p; 163 uint8_t chip_mask; 164 px_t *px_p = DIP_TO_STATE(dip); 165 px_chip_type_t chip_type = px_identity_init(px_p); 166 167 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p", dip); 168 169 if (chip_type == PX_CHIP_UNIDENTIFIED) { 170 cmn_err(CE_WARN, "%s%d: Unrecognized Hardware Version\n", 171 NAMEINST(dip)); 172 return (DDI_FAILURE); 173 } 174 175 chip_mask = BITMASK(chip_type); 176 px_paddr_mask = (chip_type == PX_CHIP_FIRE) ? MMU_FIRE_PADDR_MASK : 177 MMU_OBERON_PADDR_MASK; 178 179 /* 180 * Allocate platform specific structure and link it to 181 * the px state structure. 182 */ 183 pxu_p = kmem_zalloc(sizeof (pxu_t), KM_SLEEP); 184 pxu_p->chip_type = chip_type; 185 pxu_p->portid = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 186 "portid", -1); 187 188 /* Map in the registers */ 189 if (px_lib_map_regs(pxu_p, dip) == DDI_FAILURE) { 190 kmem_free(pxu_p, sizeof (pxu_t)); 191 192 return (DDI_FAILURE); 193 } 194 195 xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 196 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 197 198 pxu_p->tsb_cookie = iommu_tsb_alloc(pxu_p->portid); 199 pxu_p->tsb_size = iommu_tsb_cookie_to_size(pxu_p->tsb_cookie); 200 pxu_p->tsb_vaddr = iommu_tsb_cookie_to_va(pxu_p->tsb_cookie); 201 202 pxu_p->tsb_paddr = va_to_pa(pxu_p->tsb_vaddr); 203 204 /* 205 * Create "virtual-dma" property to support child devices 206 * needing to know DVMA range. 207 */ 208 px_dvma_range.dvma_base = (uint32_t)px_mmu_dvma_end + 1 209 - ((pxu_p->tsb_size >> 3) << MMU_PAGE_SHIFT); 210 px_dvma_range.dvma_len = (uint32_t) 211 px_mmu_dvma_end - px_dvma_range.dvma_base + 1; 212 213 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 214 "virtual-dma", (int *)&px_dvma_range, 215 sizeof (px_dvma_range_prop_t) / sizeof (int)); 216 /* 217 * Initilize all fire hardware specific blocks. 218 */ 219 hvio_cb_init(xbc_csr_base, pxu_p); 220 hvio_ib_init(csr_base, pxu_p); 221 hvio_pec_init(csr_base, pxu_p); 222 hvio_mmu_init(csr_base, pxu_p); 223 224 px_p->px_plat_p = (void *)pxu_p; 225 226 /* 227 * Initialize all the interrupt handlers 228 */ 229 switch (PX_CHIP_TYPE(pxu_p)) { 230 case PX_CHIP_OBERON: 231 /* 232 * Oberon hotplug uses SPARE3 field in ILU Error Log Enable 233 * register to indicate the status of leaf reset, 234 * we need to preserve the value of this bit, and keep it in 235 * px_ilu_log_mask to reflect the state of the bit 236 */ 237 if (CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3)) 238 px_ilu_log_mask |= (1ull << 239 ILU_ERROR_LOG_ENABLE_SPARE3); 240 else 241 px_ilu_log_mask &= ~(1ull << 242 ILU_ERROR_LOG_ENABLE_SPARE3); 243 244 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 245 break; 246 247 case PX_CHIP_FIRE: 248 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 249 break; 250 251 default: 252 cmn_err(CE_WARN, "%s%d: PX primary bus Unknown\n", 253 ddi_driver_name(dip), ddi_get_instance(dip)); 254 return (DDI_FAILURE); 255 } 256 257 /* Initilize device handle */ 258 *dev_hdl = (devhandle_t)csr_base; 259 260 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 261 262 return (DDI_SUCCESS); 263 } 264 265 int 266 px_lib_dev_fini(dev_info_t *dip) 267 { 268 caddr_t csr_base; 269 uint8_t chip_mask; 270 px_t *px_p = DIP_TO_STATE(dip); 271 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 272 273 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 274 275 /* 276 * Deinitialize all the interrupt handlers 277 */ 278 switch (PX_CHIP_TYPE(pxu_p)) { 279 case PX_CHIP_OBERON: 280 case PX_CHIP_FIRE: 281 chip_mask = BITMASK(PX_CHIP_TYPE(pxu_p)); 282 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 283 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_DISABLE); 284 break; 285 286 default: 287 cmn_err(CE_WARN, "%s%d: PX primary bus Unknown\n", 288 ddi_driver_name(dip), ddi_get_instance(dip)); 289 return (DDI_FAILURE); 290 } 291 292 iommu_tsb_free(pxu_p->tsb_cookie); 293 294 px_lib_unmap_regs((pxu_t *)px_p->px_plat_p); 295 kmem_free(px_p->px_plat_p, sizeof (pxu_t)); 296 px_p->px_plat_p = NULL; 297 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "virtual-dma"); 298 299 return (DDI_SUCCESS); 300 } 301 302 /*ARGSUSED*/ 303 int 304 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 305 sysino_t *sysino) 306 { 307 px_t *px_p = DIP_TO_STATE(dip); 308 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 309 uint64_t ret; 310 311 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 312 "devino 0x%x\n", dip, devino); 313 314 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 315 pxu_p, devino, sysino)) != H_EOK) { 316 DBG(DBG_LIB_INT, dip, 317 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 318 return (DDI_FAILURE); 319 } 320 321 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 322 *sysino); 323 324 return (DDI_SUCCESS); 325 } 326 327 /*ARGSUSED*/ 328 int 329 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 330 intr_valid_state_t *intr_valid_state) 331 { 332 uint64_t ret; 333 334 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 335 dip, sysino); 336 337 if ((ret = hvio_intr_getvalid(DIP_TO_HANDLE(dip), 338 sysino, intr_valid_state)) != H_EOK) { 339 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 340 ret); 341 return (DDI_FAILURE); 342 } 343 344 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 345 *intr_valid_state); 346 347 return (DDI_SUCCESS); 348 } 349 350 /*ARGSUSED*/ 351 int 352 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 353 intr_valid_state_t intr_valid_state) 354 { 355 uint64_t ret; 356 357 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 358 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 359 360 if ((ret = hvio_intr_setvalid(DIP_TO_HANDLE(dip), 361 sysino, intr_valid_state)) != H_EOK) { 362 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 363 ret); 364 return (DDI_FAILURE); 365 } 366 367 return (DDI_SUCCESS); 368 } 369 370 /*ARGSUSED*/ 371 int 372 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 373 intr_state_t *intr_state) 374 { 375 uint64_t ret; 376 377 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 378 dip, sysino); 379 380 if ((ret = hvio_intr_getstate(DIP_TO_HANDLE(dip), 381 sysino, intr_state)) != H_EOK) { 382 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 383 ret); 384 return (DDI_FAILURE); 385 } 386 387 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 388 *intr_state); 389 390 return (DDI_SUCCESS); 391 } 392 393 /*ARGSUSED*/ 394 int 395 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 396 intr_state_t intr_state) 397 { 398 uint64_t ret; 399 400 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 401 "intr_state 0x%x\n", dip, sysino, intr_state); 402 403 if ((ret = hvio_intr_setstate(DIP_TO_HANDLE(dip), 404 sysino, intr_state)) != H_EOK) { 405 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 406 ret); 407 return (DDI_FAILURE); 408 } 409 410 return (DDI_SUCCESS); 411 } 412 413 /*ARGSUSED*/ 414 int 415 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 416 { 417 px_t *px_p = DIP_TO_STATE(dip); 418 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 419 uint64_t ret; 420 421 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 422 dip, sysino); 423 424 if ((ret = hvio_intr_gettarget(DIP_TO_HANDLE(dip), pxu_p, 425 sysino, cpuid)) != H_EOK) { 426 DBG(DBG_LIB_INT, dip, "hvio_intr_gettarget failed, ret 0x%lx\n", 427 ret); 428 return (DDI_FAILURE); 429 } 430 431 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 432 433 return (DDI_SUCCESS); 434 } 435 436 /*ARGSUSED*/ 437 int 438 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 439 { 440 px_t *px_p = DIP_TO_STATE(dip); 441 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 442 uint64_t ret; 443 444 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 445 "cpuid 0x%x\n", dip, sysino, cpuid); 446 447 if ((ret = hvio_intr_settarget(DIP_TO_HANDLE(dip), pxu_p, 448 sysino, cpuid)) != H_EOK) { 449 DBG(DBG_LIB_INT, dip, "hvio_intr_settarget failed, ret 0x%lx\n", 450 ret); 451 return (DDI_FAILURE); 452 } 453 454 return (DDI_SUCCESS); 455 } 456 457 /*ARGSUSED*/ 458 int 459 px_lib_intr_reset(dev_info_t *dip) 460 { 461 devino_t ino; 462 sysino_t sysino; 463 464 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 465 466 /* Reset all Interrupts */ 467 for (ino = 0; ino < INTERRUPT_MAPPING_ENTRIES; ino++) { 468 if (px_lib_intr_devino_to_sysino(dip, ino, 469 &sysino) != DDI_SUCCESS) 470 return (BF_FATAL); 471 472 if (px_lib_intr_setstate(dip, sysino, 473 INTR_IDLE_STATE) != DDI_SUCCESS) 474 return (BF_FATAL); 475 } 476 477 return (BF_NONE); 478 } 479 480 /*ARGSUSED*/ 481 int 482 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 483 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 484 { 485 px_t *px_p = DIP_TO_STATE(dip); 486 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 487 uint64_t ret; 488 489 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 490 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 491 dip, tsbid, pages, attr, addr, pfn_index, flags); 492 493 if ((ret = hvio_iommu_map(px_p->px_dev_hdl, pxu_p, tsbid, pages, 494 attr, addr, pfn_index, flags)) != H_EOK) { 495 DBG(DBG_LIB_DMA, dip, 496 "px_lib_iommu_map failed, ret 0x%lx\n", ret); 497 return (DDI_FAILURE); 498 } 499 500 return (DDI_SUCCESS); 501 } 502 503 /*ARGSUSED*/ 504 int 505 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 506 { 507 px_t *px_p = DIP_TO_STATE(dip); 508 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 509 uint64_t ret; 510 511 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 512 "pages 0x%x\n", dip, tsbid, pages); 513 514 if ((ret = hvio_iommu_demap(px_p->px_dev_hdl, pxu_p, tsbid, pages)) 515 != H_EOK) { 516 DBG(DBG_LIB_DMA, dip, 517 "px_lib_iommu_demap failed, ret 0x%lx\n", ret); 518 519 return (DDI_FAILURE); 520 } 521 522 return (DDI_SUCCESS); 523 } 524 525 /*ARGSUSED*/ 526 int 527 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 528 r_addr_t *r_addr_p) 529 { 530 px_t *px_p = DIP_TO_STATE(dip); 531 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 532 uint64_t ret; 533 534 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 535 dip, tsbid); 536 537 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), pxu_p, tsbid, 538 attr_p, r_addr_p)) != H_EOK) { 539 DBG(DBG_LIB_DMA, dip, 540 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 541 542 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 543 } 544 545 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 546 *attr_p, *r_addr_p); 547 548 return (DDI_SUCCESS); 549 } 550 551 552 /* 553 * Checks dma attributes against system bypass ranges 554 * The bypass range is determined by the hardware. Return them so the 555 * common code can do generic checking against them. 556 */ 557 /*ARGSUSED*/ 558 int 559 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 560 uint64_t *lo_p, uint64_t *hi_p) 561 { 562 px_t *px_p = DIP_TO_STATE(dip); 563 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 564 565 *lo_p = hvio_get_bypass_base(pxu_p); 566 *hi_p = hvio_get_bypass_end(pxu_p); 567 568 return (DDI_SUCCESS); 569 } 570 571 572 /*ARGSUSED*/ 573 int 574 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 575 io_addr_t *io_addr_p) 576 { 577 uint64_t ret; 578 px_t *px_p = DIP_TO_STATE(dip); 579 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 580 581 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 582 "attr 0x%x\n", dip, ra, attr); 583 584 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), pxu_p, ra, 585 attr, io_addr_p)) != H_EOK) { 586 DBG(DBG_LIB_DMA, dip, 587 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 588 return (DDI_FAILURE); 589 } 590 591 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 592 *io_addr_p); 593 594 return (DDI_SUCCESS); 595 } 596 597 /* 598 * bus dma sync entry point. 599 */ 600 /*ARGSUSED*/ 601 int 602 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 603 off_t off, size_t len, uint_t cache_flags) 604 { 605 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 606 px_t *px_p = DIP_TO_STATE(dip); 607 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 608 609 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 610 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 611 dip, rdip, handle, off, len, cache_flags); 612 613 /* 614 * No flush needed for Oberon 615 */ 616 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 617 return (DDI_SUCCESS); 618 619 /* 620 * jbus_stst_order is found only in certain cpu modules. 621 * Just return success if not present. 622 */ 623 if (&jbus_stst_order == NULL) 624 return (DDI_SUCCESS); 625 626 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 627 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 628 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 629 630 return (DDI_FAILURE); 631 } 632 633 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 634 return (DDI_SUCCESS); 635 636 /* 637 * No flush needed when sending data from memory to device. 638 * Nothing to do to "sync" memory to what device would already see. 639 */ 640 if (!(mp->dmai_rflags & DDI_DMA_READ) || 641 ((cache_flags & PX_DMA_SYNC_DDI_FLAGS) == DDI_DMA_SYNC_FORDEV)) 642 return (DDI_SUCCESS); 643 644 /* 645 * Perform necessary cpu workaround to ensure jbus ordering. 646 * CPU's internal "invalidate FIFOs" are flushed. 647 */ 648 649 #if !defined(lint) 650 kpreempt_disable(); 651 #endif 652 jbus_stst_order(); 653 #if !defined(lint) 654 kpreempt_enable(); 655 #endif 656 return (DDI_SUCCESS); 657 } 658 659 /* 660 * MSIQ Functions: 661 */ 662 /*ARGSUSED*/ 663 int 664 px_lib_msiq_init(dev_info_t *dip) 665 { 666 px_t *px_p = DIP_TO_STATE(dip); 667 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 668 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 669 px_dvma_addr_t pg_index; 670 size_t size; 671 int ret; 672 673 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 674 675 /* 676 * Map the EQ memory into the Fire MMU (has to be 512KB aligned) 677 * and then initialize the base address register. 678 * 679 * Allocate entries from Fire IOMMU so that the resulting address 680 * is properly aligned. Calculate the index of the first allocated 681 * entry. Note: The size of the mapping is assumed to be a multiple 682 * of the page size. 683 */ 684 size = msiq_state_p->msiq_cnt * 685 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 686 687 pxu_p->msiq_mapped_p = vmem_xalloc(px_p->px_mmu_p->mmu_dvma_map, 688 size, (512 * 1024), 0, 0, NULL, NULL, VM_NOSLEEP | VM_BESTFIT); 689 690 if (pxu_p->msiq_mapped_p == NULL) 691 return (DDI_FAILURE); 692 693 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 694 MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 695 696 if ((ret = px_lib_iommu_map(px_p->px_dip, PCI_TSBID(0, pg_index), 697 MMU_BTOP(size), PCI_MAP_ATTR_WRITE, msiq_state_p->msiq_buf_p, 698 0, MMU_MAP_BUF)) != DDI_SUCCESS) { 699 DBG(DBG_LIB_MSIQ, dip, 700 "hvio_msiq_init failed, ret 0x%lx\n", ret); 701 702 (void) px_lib_msiq_fini(dip); 703 return (DDI_FAILURE); 704 } 705 706 (void) hvio_msiq_init(DIP_TO_HANDLE(dip), pxu_p); 707 708 return (DDI_SUCCESS); 709 } 710 711 /*ARGSUSED*/ 712 int 713 px_lib_msiq_fini(dev_info_t *dip) 714 { 715 px_t *px_p = DIP_TO_STATE(dip); 716 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 717 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 718 px_dvma_addr_t pg_index; 719 size_t size; 720 721 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 722 723 /* 724 * Unmap and free the EQ memory that had been mapped 725 * into the Fire IOMMU. 726 */ 727 size = msiq_state_p->msiq_cnt * 728 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 729 730 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 731 MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 732 733 (void) px_lib_iommu_demap(px_p->px_dip, 734 PCI_TSBID(0, pg_index), MMU_BTOP(size)); 735 736 /* Free the entries from the Fire MMU */ 737 vmem_xfree(px_p->px_mmu_p->mmu_dvma_map, 738 (void *)pxu_p->msiq_mapped_p, size); 739 740 return (DDI_SUCCESS); 741 } 742 743 /*ARGSUSED*/ 744 int 745 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 746 uint_t *msiq_rec_cnt_p) 747 { 748 px_t *px_p = DIP_TO_STATE(dip); 749 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 750 size_t msiq_size; 751 752 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 753 dip, msiq_id); 754 755 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 756 ra_p = (r_addr_t *)((caddr_t)msiq_state_p->msiq_buf_p + 757 (msiq_id * msiq_size)); 758 759 *msiq_rec_cnt_p = msiq_state_p->msiq_rec_cnt; 760 761 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 762 ra_p, *msiq_rec_cnt_p); 763 764 return (DDI_SUCCESS); 765 } 766 767 /*ARGSUSED*/ 768 int 769 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 770 pci_msiq_valid_state_t *msiq_valid_state) 771 { 772 uint64_t ret; 773 774 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 775 dip, msiq_id); 776 777 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 778 msiq_id, msiq_valid_state)) != H_EOK) { 779 DBG(DBG_LIB_MSIQ, dip, 780 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 781 return (DDI_FAILURE); 782 } 783 784 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 785 *msiq_valid_state); 786 787 return (DDI_SUCCESS); 788 } 789 790 /*ARGSUSED*/ 791 int 792 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 793 pci_msiq_valid_state_t msiq_valid_state) 794 { 795 uint64_t ret; 796 797 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 798 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 799 800 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 801 msiq_id, msiq_valid_state)) != H_EOK) { 802 DBG(DBG_LIB_MSIQ, dip, 803 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 804 return (DDI_FAILURE); 805 } 806 807 return (DDI_SUCCESS); 808 } 809 810 /*ARGSUSED*/ 811 int 812 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 813 pci_msiq_state_t *msiq_state) 814 { 815 uint64_t ret; 816 817 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 818 dip, msiq_id); 819 820 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 821 msiq_id, msiq_state)) != H_EOK) { 822 DBG(DBG_LIB_MSIQ, dip, 823 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 824 return (DDI_FAILURE); 825 } 826 827 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 828 *msiq_state); 829 830 return (DDI_SUCCESS); 831 } 832 833 /*ARGSUSED*/ 834 int 835 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 836 pci_msiq_state_t msiq_state) 837 { 838 uint64_t ret; 839 840 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 841 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 842 843 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 844 msiq_id, msiq_state)) != H_EOK) { 845 DBG(DBG_LIB_MSIQ, dip, 846 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 847 return (DDI_FAILURE); 848 } 849 850 return (DDI_SUCCESS); 851 } 852 853 /*ARGSUSED*/ 854 int 855 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 856 msiqhead_t *msiq_head) 857 { 858 uint64_t ret; 859 860 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 861 dip, msiq_id); 862 863 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 864 msiq_id, msiq_head)) != H_EOK) { 865 DBG(DBG_LIB_MSIQ, dip, 866 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 867 return (DDI_FAILURE); 868 } 869 870 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: msiq_head 0x%x\n", 871 *msiq_head); 872 873 return (DDI_SUCCESS); 874 } 875 876 /*ARGSUSED*/ 877 int 878 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 879 msiqhead_t msiq_head) 880 { 881 uint64_t ret; 882 883 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 884 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 885 886 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 887 msiq_id, msiq_head)) != H_EOK) { 888 DBG(DBG_LIB_MSIQ, dip, 889 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 890 return (DDI_FAILURE); 891 } 892 893 return (DDI_SUCCESS); 894 } 895 896 /*ARGSUSED*/ 897 int 898 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 899 msiqtail_t *msiq_tail) 900 { 901 uint64_t ret; 902 903 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 904 dip, msiq_id); 905 906 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 907 msiq_id, msiq_tail)) != H_EOK) { 908 DBG(DBG_LIB_MSIQ, dip, 909 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 910 return (DDI_FAILURE); 911 } 912 913 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 914 *msiq_tail); 915 916 return (DDI_SUCCESS); 917 } 918 919 /*ARGSUSED*/ 920 void 921 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 922 msiq_rec_t *msiq_rec_p) 923 { 924 eq_rec_t *eq_rec_p = (eq_rec_t *)msiq_head_p; 925 926 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p eq_rec_p 0x%p\n", 927 dip, eq_rec_p); 928 929 if (!eq_rec_p->eq_rec_fmt_type) { 930 /* Set msiq_rec_type to zero */ 931 msiq_rec_p->msiq_rec_type = 0; 932 933 return; 934 } 935 936 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: EQ RECORD, " 937 "eq_rec_rid 0x%llx eq_rec_fmt_type 0x%llx " 938 "eq_rec_len 0x%llx eq_rec_addr0 0x%llx " 939 "eq_rec_addr1 0x%llx eq_rec_data0 0x%llx " 940 "eq_rec_data1 0x%llx\n", eq_rec_p->eq_rec_rid, 941 eq_rec_p->eq_rec_fmt_type, eq_rec_p->eq_rec_len, 942 eq_rec_p->eq_rec_addr0, eq_rec_p->eq_rec_addr1, 943 eq_rec_p->eq_rec_data0, eq_rec_p->eq_rec_data1); 944 945 /* 946 * Only upper 4 bits of eq_rec_fmt_type is used 947 * to identify the EQ record type. 948 */ 949 switch (eq_rec_p->eq_rec_fmt_type >> 3) { 950 case EQ_REC_MSI32: 951 msiq_rec_p->msiq_rec_type = MSI32_REC; 952 953 msiq_rec_p->msiq_rec_data.msi.msi_data = 954 eq_rec_p->eq_rec_data0; 955 break; 956 case EQ_REC_MSI64: 957 msiq_rec_p->msiq_rec_type = MSI64_REC; 958 959 msiq_rec_p->msiq_rec_data.msi.msi_data = 960 eq_rec_p->eq_rec_data0; 961 break; 962 case EQ_REC_MSG: 963 msiq_rec_p->msiq_rec_type = MSG_REC; 964 965 msiq_rec_p->msiq_rec_data.msg.msg_route = 966 eq_rec_p->eq_rec_fmt_type & 7; 967 msiq_rec_p->msiq_rec_data.msg.msg_targ = eq_rec_p->eq_rec_rid; 968 msiq_rec_p->msiq_rec_data.msg.msg_code = eq_rec_p->eq_rec_data0; 969 break; 970 default: 971 cmn_err(CE_WARN, "%s%d: px_lib_get_msiq_rec: " 972 "0x%x is an unknown EQ record type", 973 ddi_driver_name(dip), ddi_get_instance(dip), 974 (int)eq_rec_p->eq_rec_fmt_type); 975 break; 976 } 977 978 msiq_rec_p->msiq_rec_rid = eq_rec_p->eq_rec_rid; 979 msiq_rec_p->msiq_rec_msi_addr = ((eq_rec_p->eq_rec_addr1 << 16) | 980 (eq_rec_p->eq_rec_addr0 << 2)); 981 } 982 983 /*ARGSUSED*/ 984 void 985 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 986 { 987 eq_rec_t *eq_rec_p = (eq_rec_t *)msiq_head_p; 988 989 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p eq_rec_p 0x%p\n", 990 dip, eq_rec_p); 991 992 if (eq_rec_p->eq_rec_fmt_type) { 993 /* Zero out eq_rec_fmt_type field */ 994 eq_rec_p->eq_rec_fmt_type = 0; 995 } 996 } 997 998 /* 999 * MSI Functions: 1000 */ 1001 /*ARGSUSED*/ 1002 int 1003 px_lib_msi_init(dev_info_t *dip) 1004 { 1005 px_t *px_p = DIP_TO_STATE(dip); 1006 px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 1007 uint64_t ret; 1008 1009 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 1010 1011 if ((ret = hvio_msi_init(DIP_TO_HANDLE(dip), 1012 msi_state_p->msi_addr32, msi_state_p->msi_addr64)) != H_EOK) { 1013 DBG(DBG_LIB_MSIQ, dip, "px_lib_msi_init failed, ret 0x%lx\n", 1014 ret); 1015 return (DDI_FAILURE); 1016 } 1017 1018 return (DDI_SUCCESS); 1019 } 1020 1021 /*ARGSUSED*/ 1022 int 1023 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 1024 msiqid_t *msiq_id) 1025 { 1026 uint64_t ret; 1027 1028 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 1029 dip, msi_num); 1030 1031 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 1032 msi_num, msiq_id)) != H_EOK) { 1033 DBG(DBG_LIB_MSI, dip, 1034 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 1035 return (DDI_FAILURE); 1036 } 1037 1038 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 1039 *msiq_id); 1040 1041 return (DDI_SUCCESS); 1042 } 1043 1044 /*ARGSUSED*/ 1045 int 1046 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 1047 msiqid_t msiq_id, msi_type_t msitype) 1048 { 1049 uint64_t ret; 1050 1051 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 1052 "msq_id 0x%x\n", dip, msi_num, msiq_id); 1053 1054 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 1055 msi_num, msiq_id)) != H_EOK) { 1056 DBG(DBG_LIB_MSI, dip, 1057 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 1058 return (DDI_FAILURE); 1059 } 1060 1061 return (DDI_SUCCESS); 1062 } 1063 1064 /*ARGSUSED*/ 1065 int 1066 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 1067 pci_msi_valid_state_t *msi_valid_state) 1068 { 1069 uint64_t ret; 1070 1071 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 1072 dip, msi_num); 1073 1074 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 1075 msi_num, msi_valid_state)) != H_EOK) { 1076 DBG(DBG_LIB_MSI, dip, 1077 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 1078 return (DDI_FAILURE); 1079 } 1080 1081 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 1082 *msi_valid_state); 1083 1084 return (DDI_SUCCESS); 1085 } 1086 1087 /*ARGSUSED*/ 1088 int 1089 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 1090 pci_msi_valid_state_t msi_valid_state) 1091 { 1092 uint64_t ret; 1093 1094 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 1095 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 1096 1097 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 1098 msi_num, msi_valid_state)) != H_EOK) { 1099 DBG(DBG_LIB_MSI, dip, 1100 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 1101 return (DDI_FAILURE); 1102 } 1103 1104 return (DDI_SUCCESS); 1105 } 1106 1107 /*ARGSUSED*/ 1108 int 1109 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 1110 pci_msi_state_t *msi_state) 1111 { 1112 uint64_t ret; 1113 1114 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 1115 dip, msi_num); 1116 1117 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 1118 msi_num, msi_state)) != H_EOK) { 1119 DBG(DBG_LIB_MSI, dip, 1120 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 1121 return (DDI_FAILURE); 1122 } 1123 1124 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 1125 *msi_state); 1126 1127 return (DDI_SUCCESS); 1128 } 1129 1130 /*ARGSUSED*/ 1131 int 1132 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 1133 pci_msi_state_t msi_state) 1134 { 1135 uint64_t ret; 1136 1137 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 1138 "msi_state 0x%x\n", dip, msi_num, msi_state); 1139 1140 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 1141 msi_num, msi_state)) != H_EOK) { 1142 DBG(DBG_LIB_MSI, dip, 1143 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 1144 return (DDI_FAILURE); 1145 } 1146 1147 return (DDI_SUCCESS); 1148 } 1149 1150 /* 1151 * MSG Functions: 1152 */ 1153 /*ARGSUSED*/ 1154 int 1155 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1156 msiqid_t *msiq_id) 1157 { 1158 uint64_t ret; 1159 1160 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 1161 dip, msg_type); 1162 1163 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 1164 msg_type, msiq_id)) != H_EOK) { 1165 DBG(DBG_LIB_MSG, dip, 1166 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 1167 return (DDI_FAILURE); 1168 } 1169 1170 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1171 *msiq_id); 1172 1173 return (DDI_SUCCESS); 1174 } 1175 1176 /*ARGSUSED*/ 1177 int 1178 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1179 msiqid_t msiq_id) 1180 { 1181 uint64_t ret; 1182 1183 DBG(DBG_LIB_MSG, dip, "px_lib_msi_setstate: dip 0x%p msg_type 0x%x " 1184 "msiq_id 0x%x\n", dip, msg_type, msiq_id); 1185 1186 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1187 msg_type, msiq_id)) != H_EOK) { 1188 DBG(DBG_LIB_MSG, dip, 1189 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1190 return (DDI_FAILURE); 1191 } 1192 1193 return (DDI_SUCCESS); 1194 } 1195 1196 /*ARGSUSED*/ 1197 int 1198 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1199 pcie_msg_valid_state_t *msg_valid_state) 1200 { 1201 uint64_t ret; 1202 1203 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1204 dip, msg_type); 1205 1206 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1207 msg_valid_state)) != H_EOK) { 1208 DBG(DBG_LIB_MSG, dip, 1209 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1210 return (DDI_FAILURE); 1211 } 1212 1213 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1214 *msg_valid_state); 1215 1216 return (DDI_SUCCESS); 1217 } 1218 1219 /*ARGSUSED*/ 1220 int 1221 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1222 pcie_msg_valid_state_t msg_valid_state) 1223 { 1224 uint64_t ret; 1225 1226 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1227 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1228 1229 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1230 msg_valid_state)) != H_EOK) { 1231 DBG(DBG_LIB_MSG, dip, 1232 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1233 return (DDI_FAILURE); 1234 } 1235 1236 return (DDI_SUCCESS); 1237 } 1238 1239 /* 1240 * Suspend/Resume Functions: 1241 * Currently unsupported by hypervisor 1242 */ 1243 int 1244 px_lib_suspend(dev_info_t *dip) 1245 { 1246 px_t *px_p = DIP_TO_STATE(dip); 1247 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1248 px_cb_t *cb_p = PX2CB(px_p); 1249 devhandle_t dev_hdl, xbus_dev_hdl; 1250 uint64_t ret = H_EOK; 1251 1252 DBG(DBG_DETACH, dip, "px_lib_suspend: dip 0x%p\n", dip); 1253 1254 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; 1255 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; 1256 1257 if ((ret = hvio_suspend(dev_hdl, pxu_p)) != H_EOK) 1258 goto fail; 1259 1260 if (--cb_p->attachcnt == 0) { 1261 ret = hvio_cb_suspend(xbus_dev_hdl, pxu_p); 1262 if (ret != H_EOK) 1263 cb_p->attachcnt++; 1264 } 1265 pxu_p->cpr_flag = PX_ENTERED_CPR; 1266 1267 fail: 1268 return ((ret != H_EOK) ? DDI_FAILURE: DDI_SUCCESS); 1269 } 1270 1271 void 1272 px_lib_resume(dev_info_t *dip) 1273 { 1274 px_t *px_p = DIP_TO_STATE(dip); 1275 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1276 px_cb_t *cb_p = PX2CB(px_p); 1277 devhandle_t dev_hdl, xbus_dev_hdl; 1278 devino_t pec_ino = px_p->px_inos[PX_INTR_PEC]; 1279 devino_t xbc_ino = px_p->px_inos[PX_INTR_XBC]; 1280 1281 DBG(DBG_ATTACH, dip, "px_lib_resume: dip 0x%p\n", dip); 1282 1283 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; 1284 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; 1285 1286 if (++cb_p->attachcnt == 1) 1287 hvio_cb_resume(dev_hdl, xbus_dev_hdl, xbc_ino, pxu_p); 1288 1289 hvio_resume(dev_hdl, pec_ino, pxu_p); 1290 } 1291 1292 /* 1293 * Generate a unique Oberon UBC ID based on the Logicial System Board and 1294 * the IO Channel from the portid property field. 1295 */ 1296 static uint64_t 1297 oberon_get_ubc_id(dev_info_t *dip) 1298 { 1299 px_t *px_p = DIP_TO_STATE(dip); 1300 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1301 uint64_t ubc_id; 1302 1303 /* 1304 * Generate a unique 6 bit UBC ID using the 2 IO_Channel#[1:0] bits and 1305 * the 4 LSB_ID[3:0] bits from the Oberon's portid property. 1306 */ 1307 ubc_id = (((pxu_p->portid >> OBERON_PORT_ID_IOC) & 1308 OBERON_PORT_ID_IOC_MASK) | (((pxu_p->portid >> 1309 OBERON_PORT_ID_LSB) & OBERON_PORT_ID_LSB_MASK) 1310 << OBERON_UBC_ID_LSB)); 1311 1312 return (ubc_id); 1313 } 1314 1315 /* 1316 * Oberon does not have a UBC scratch register, so alloc an array of scratch 1317 * registers when needed and use a unique UBC ID as an index. This code 1318 * can be simplified if we use a pre-allocated array. They are currently 1319 * being dynamically allocated because it's only needed by the Oberon. 1320 */ 1321 static void 1322 oberon_set_cb(dev_info_t *dip, uint64_t val) 1323 { 1324 uint64_t ubc_id; 1325 1326 if (px_oberon_ubc_scratch_regs == NULL) 1327 px_oberon_ubc_scratch_regs = 1328 (uint64_t *)kmem_zalloc(sizeof (uint64_t)* 1329 OBERON_UBC_ID_MAX, KM_SLEEP); 1330 1331 ubc_id = oberon_get_ubc_id(dip); 1332 1333 px_oberon_ubc_scratch_regs[ubc_id] = val; 1334 1335 /* 1336 * Check if any scratch registers are still in use. If all scratch 1337 * registers are currently set to zero, then deallocate the scratch 1338 * register array. 1339 */ 1340 for (ubc_id = 0; ubc_id < OBERON_UBC_ID_MAX; ubc_id++) { 1341 if (px_oberon_ubc_scratch_regs[ubc_id] != NULL) 1342 return; 1343 } 1344 1345 /* 1346 * All scratch registers are set to zero so deallocate the scratch 1347 * register array and set the pointer to NULL. 1348 */ 1349 kmem_free(px_oberon_ubc_scratch_regs, 1350 (sizeof (uint64_t)*OBERON_UBC_ID_MAX)); 1351 1352 px_oberon_ubc_scratch_regs = NULL; 1353 } 1354 1355 /* 1356 * Oberon does not have a UBC scratch register, so use an allocated array of 1357 * scratch registers and use the unique UBC ID as an index into that array. 1358 */ 1359 static uint64_t 1360 oberon_get_cb(dev_info_t *dip) 1361 { 1362 uint64_t ubc_id; 1363 1364 if (px_oberon_ubc_scratch_regs == NULL) 1365 return (0); 1366 1367 ubc_id = oberon_get_ubc_id(dip); 1368 1369 return (px_oberon_ubc_scratch_regs[ubc_id]); 1370 } 1371 1372 /* 1373 * Misc Functions: 1374 * Currently unsupported by hypervisor 1375 */ 1376 static uint64_t 1377 px_get_cb(dev_info_t *dip) 1378 { 1379 px_t *px_p = DIP_TO_STATE(dip); 1380 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1381 1382 /* 1383 * Oberon does not currently have Scratchpad registers. 1384 */ 1385 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 1386 return (oberon_get_cb(dip)); 1387 1388 return (CSR_XR((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1)); 1389 } 1390 1391 static void 1392 px_set_cb(dev_info_t *dip, uint64_t val) 1393 { 1394 px_t *px_p = DIP_TO_STATE(dip); 1395 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1396 1397 /* 1398 * Oberon does not currently have Scratchpad registers. 1399 */ 1400 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1401 oberon_set_cb(dip, val); 1402 return; 1403 } 1404 1405 CSR_XS((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1, val); 1406 } 1407 1408 /*ARGSUSED*/ 1409 int 1410 px_lib_map_vconfig(dev_info_t *dip, 1411 ddi_map_req_t *mp, pci_config_offset_t off, 1412 pci_regspec_t *rp, caddr_t *addrp) 1413 { 1414 /* 1415 * No special config space access services in this layer. 1416 */ 1417 return (DDI_FAILURE); 1418 } 1419 1420 void 1421 px_lib_map_attr_check(ddi_map_req_t *mp) 1422 { 1423 ddi_acc_hdl_t *hp = mp->map_handlep; 1424 1425 /* fire does not accept byte masks from PIO store merge */ 1426 if (hp->ah_acc.devacc_attr_dataorder == DDI_STORECACHING_OK_ACC) 1427 hp->ah_acc.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1428 } 1429 1430 /* This function is called only by poke, caut put and pxtool poke. */ 1431 void 1432 px_lib_clr_errs(px_t *px_p, dev_info_t *rdip, uint64_t addr) 1433 { 1434 px_pec_t *pec_p = px_p->px_pec_p; 1435 dev_info_t *rpdip = px_p->px_dip; 1436 int rc_err, fab_err, i; 1437 int acctype = pec_p->pec_safeacc_type; 1438 ddi_fm_error_t derr; 1439 px_ranges_t *ranges_p; 1440 int range_len; 1441 uint32_t addr_high, addr_low; 1442 pcie_req_id_t bdf = 0; 1443 1444 /* Create the derr */ 1445 bzero(&derr, sizeof (ddi_fm_error_t)); 1446 derr.fme_version = DDI_FME_VERSION; 1447 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1448 derr.fme_flag = acctype; 1449 1450 if (acctype == DDI_FM_ERR_EXPECTED) { 1451 derr.fme_status = DDI_FM_NONFATAL; 1452 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, &derr); 1453 } 1454 1455 if (px_fm_enter(px_p) != DDI_SUCCESS) 1456 return; 1457 1458 /* send ereport/handle/clear fire registers */ 1459 rc_err = px_err_cmn_intr(px_p, &derr, PX_LIB_CALL, PX_FM_BLOCK_ALL); 1460 1461 /* Figure out if this is a cfg or mem32 access */ 1462 addr_high = (uint32_t)(addr >> 32); 1463 addr_low = (uint32_t)addr; 1464 range_len = px_p->px_ranges_length / sizeof (px_ranges_t); 1465 i = 0; 1466 for (ranges_p = px_p->px_ranges_p; i < range_len; i++, ranges_p++) { 1467 if (ranges_p->parent_high == addr_high) { 1468 switch (ranges_p->child_high & PCI_ADDR_MASK) { 1469 case PCI_ADDR_CONFIG: 1470 bdf = (pcie_req_id_t)(addr_low >> 12); 1471 addr_low = 0; 1472 break; 1473 case PCI_ADDR_MEM32: 1474 if (rdip) 1475 bdf = PCI_GET_BDF(rdip); 1476 else 1477 bdf = NULL; 1478 break; 1479 } 1480 break; 1481 } 1482 } 1483 1484 px_rp_en_q(px_p, bdf, addr_low, NULL); 1485 1486 /* 1487 * XXX - Current code scans the fabric for all px_tool accesses. 1488 * In future, do not scan fabric for px_tool access to IO Root Nexus 1489 */ 1490 fab_err = px_scan_fabric(px_p, rpdip, &derr); 1491 1492 px_err_panic(rc_err, PX_RC, fab_err, B_TRUE); 1493 px_fm_exit(px_p); 1494 px_err_panic(rc_err, PX_RC, fab_err, B_FALSE); 1495 } 1496 1497 #ifdef DEBUG 1498 int px_peekfault_cnt = 0; 1499 int px_pokefault_cnt = 0; 1500 #endif /* DEBUG */ 1501 1502 /*ARGSUSED*/ 1503 static int 1504 px_lib_do_poke(dev_info_t *dip, dev_info_t *rdip, 1505 peekpoke_ctlops_t *in_args) 1506 { 1507 px_t *px_p = DIP_TO_STATE(dip); 1508 px_pec_t *pec_p = px_p->px_pec_p; 1509 int err = DDI_SUCCESS; 1510 on_trap_data_t otd; 1511 1512 mutex_enter(&pec_p->pec_pokefault_mutex); 1513 pec_p->pec_ontrap_data = &otd; 1514 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1515 1516 /* Set up protected environment. */ 1517 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1518 uintptr_t tramp = otd.ot_trampoline; 1519 1520 otd.ot_trampoline = (uintptr_t)&poke_fault; 1521 err = do_poke(in_args->size, (void *)in_args->dev_addr, 1522 (void *)in_args->host_addr); 1523 otd.ot_trampoline = tramp; 1524 } else 1525 err = DDI_FAILURE; 1526 1527 px_lib_clr_errs(px_p, rdip, in_args->dev_addr); 1528 1529 if (otd.ot_trap & OT_DATA_ACCESS) 1530 err = DDI_FAILURE; 1531 1532 /* Take down protected environment. */ 1533 no_trap(); 1534 1535 pec_p->pec_ontrap_data = NULL; 1536 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1537 mutex_exit(&pec_p->pec_pokefault_mutex); 1538 1539 #ifdef DEBUG 1540 if (err == DDI_FAILURE) 1541 px_pokefault_cnt++; 1542 #endif 1543 return (err); 1544 } 1545 1546 /*ARGSUSED*/ 1547 static int 1548 px_lib_do_caut_put(dev_info_t *dip, dev_info_t *rdip, 1549 peekpoke_ctlops_t *cautacc_ctlops_arg) 1550 { 1551 size_t size = cautacc_ctlops_arg->size; 1552 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1553 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1554 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1555 size_t repcount = cautacc_ctlops_arg->repcount; 1556 uint_t flags = cautacc_ctlops_arg->flags; 1557 1558 px_t *px_p = DIP_TO_STATE(dip); 1559 px_pec_t *pec_p = px_p->px_pec_p; 1560 int err = DDI_SUCCESS; 1561 1562 /* 1563 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1564 * mutex. 1565 */ 1566 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1567 1568 pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1569 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1570 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1571 1572 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1573 for (; repcount; repcount--) { 1574 switch (size) { 1575 1576 case sizeof (uint8_t): 1577 i_ddi_put8(hp, (uint8_t *)dev_addr, 1578 *(uint8_t *)host_addr); 1579 break; 1580 1581 case sizeof (uint16_t): 1582 i_ddi_put16(hp, (uint16_t *)dev_addr, 1583 *(uint16_t *)host_addr); 1584 break; 1585 1586 case sizeof (uint32_t): 1587 i_ddi_put32(hp, (uint32_t *)dev_addr, 1588 *(uint32_t *)host_addr); 1589 break; 1590 1591 case sizeof (uint64_t): 1592 i_ddi_put64(hp, (uint64_t *)dev_addr, 1593 *(uint64_t *)host_addr); 1594 break; 1595 } 1596 1597 host_addr += size; 1598 1599 if (flags == DDI_DEV_AUTOINCR) 1600 dev_addr += size; 1601 1602 px_lib_clr_errs(px_p, rdip, dev_addr); 1603 1604 if (pec_p->pec_ontrap_data->ot_trap & OT_DATA_ACCESS) { 1605 err = DDI_FAILURE; 1606 #ifdef DEBUG 1607 px_pokefault_cnt++; 1608 #endif 1609 break; 1610 } 1611 } 1612 } 1613 1614 i_ddi_notrap((ddi_acc_handle_t)hp); 1615 pec_p->pec_ontrap_data = NULL; 1616 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1617 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1618 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1619 1620 return (err); 1621 } 1622 1623 1624 int 1625 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1626 peekpoke_ctlops_t *in_args) 1627 { 1628 return (in_args->handle ? px_lib_do_caut_put(dip, rdip, in_args) : 1629 px_lib_do_poke(dip, rdip, in_args)); 1630 } 1631 1632 1633 /*ARGSUSED*/ 1634 static int 1635 px_lib_do_peek(dev_info_t *dip, peekpoke_ctlops_t *in_args) 1636 { 1637 px_t *px_p = DIP_TO_STATE(dip); 1638 px_pec_t *pec_p = px_p->px_pec_p; 1639 int err = DDI_SUCCESS; 1640 on_trap_data_t otd; 1641 1642 mutex_enter(&pec_p->pec_pokefault_mutex); 1643 if (px_fm_enter(px_p) != DDI_SUCCESS) 1644 return (DDI_FAILURE); 1645 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1646 px_fm_exit(px_p); 1647 1648 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1649 uintptr_t tramp = otd.ot_trampoline; 1650 1651 otd.ot_trampoline = (uintptr_t)&peek_fault; 1652 err = do_peek(in_args->size, (void *)in_args->dev_addr, 1653 (void *)in_args->host_addr); 1654 otd.ot_trampoline = tramp; 1655 } else 1656 err = DDI_FAILURE; 1657 1658 no_trap(); 1659 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1660 mutex_exit(&pec_p->pec_pokefault_mutex); 1661 1662 #ifdef DEBUG 1663 if (err == DDI_FAILURE) 1664 px_peekfault_cnt++; 1665 #endif 1666 return (err); 1667 } 1668 1669 1670 static int 1671 px_lib_do_caut_get(dev_info_t *dip, peekpoke_ctlops_t *cautacc_ctlops_arg) 1672 { 1673 size_t size = cautacc_ctlops_arg->size; 1674 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1675 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1676 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1677 size_t repcount = cautacc_ctlops_arg->repcount; 1678 uint_t flags = cautacc_ctlops_arg->flags; 1679 1680 px_t *px_p = DIP_TO_STATE(dip); 1681 px_pec_t *pec_p = px_p->px_pec_p; 1682 int err = DDI_SUCCESS; 1683 1684 /* 1685 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1686 * mutex. 1687 */ 1688 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1689 1690 pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1691 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1692 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1693 1694 if (repcount == 1) { 1695 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1696 i_ddi_caut_get(size, (void *)dev_addr, 1697 (void *)host_addr); 1698 } else { 1699 int i; 1700 uint8_t *ff_addr = (uint8_t *)host_addr; 1701 for (i = 0; i < size; i++) 1702 *ff_addr++ = 0xff; 1703 1704 err = DDI_FAILURE; 1705 #ifdef DEBUG 1706 px_peekfault_cnt++; 1707 #endif 1708 } 1709 } else { 1710 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1711 for (; repcount; repcount--) { 1712 i_ddi_caut_get(size, (void *)dev_addr, 1713 (void *)host_addr); 1714 1715 host_addr += size; 1716 1717 if (flags == DDI_DEV_AUTOINCR) 1718 dev_addr += size; 1719 } 1720 } else { 1721 err = DDI_FAILURE; 1722 #ifdef DEBUG 1723 px_peekfault_cnt++; 1724 #endif 1725 } 1726 } 1727 1728 i_ddi_notrap((ddi_acc_handle_t)hp); 1729 pec_p->pec_ontrap_data = NULL; 1730 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1731 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1732 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1733 1734 return (err); 1735 } 1736 1737 /*ARGSUSED*/ 1738 int 1739 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1740 peekpoke_ctlops_t *in_args, void *result) 1741 { 1742 result = (void *)in_args->host_addr; 1743 return (in_args->handle ? px_lib_do_caut_get(dip, in_args) : 1744 px_lib_do_peek(dip, in_args)); 1745 } 1746 1747 /* 1748 * implements PPM interface 1749 */ 1750 int 1751 px_lib_pmctl(int cmd, px_t *px_p) 1752 { 1753 ASSERT((cmd & ~PPMREQ_MASK) == PPMREQ); 1754 switch (cmd) { 1755 case PPMREQ_PRE_PWR_OFF: 1756 /* 1757 * Currently there is no device power management for 1758 * the root complex (fire). When there is we need to make 1759 * sure that it is at full power before trying to send the 1760 * PME_Turn_Off message. 1761 */ 1762 DBG(DBG_PWR, px_p->px_dip, 1763 "ioctl: request to send PME_Turn_Off\n"); 1764 return (px_goto_l23ready(px_p)); 1765 1766 case PPMREQ_PRE_PWR_ON: 1767 DBG(DBG_PWR, px_p->px_dip, "ioctl: PRE_PWR_ON request\n"); 1768 return (px_pre_pwron_check(px_p)); 1769 1770 case PPMREQ_POST_PWR_ON: 1771 DBG(DBG_PWR, px_p->px_dip, "ioctl: POST_PWR_ON request\n"); 1772 return (px_goto_l0(px_p)); 1773 1774 default: 1775 return (DDI_FAILURE); 1776 } 1777 } 1778 1779 /* 1780 * sends PME_Turn_Off message to put the link in L2/L3 ready state. 1781 * called by px_ioctl. 1782 * returns DDI_SUCCESS or DDI_FAILURE 1783 * 1. Wait for link to be in L1 state (link status reg) 1784 * 2. write to PME_Turn_off reg to boradcast 1785 * 3. set timeout 1786 * 4. If timeout, return failure. 1787 * 5. If PM_TO_Ack, wait till link is in L2/L3 ready 1788 */ 1789 static int 1790 px_goto_l23ready(px_t *px_p) 1791 { 1792 pcie_pwr_t *pwr_p; 1793 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1794 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 1795 int ret = DDI_SUCCESS; 1796 clock_t end, timeleft; 1797 int mutex_held = 1; 1798 1799 /* If no PM info, return failure */ 1800 if (!PCIE_PMINFO(px_p->px_dip) || 1801 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1802 return (DDI_FAILURE); 1803 1804 mutex_enter(&pwr_p->pwr_lock); 1805 mutex_enter(&px_p->px_l23ready_lock); 1806 /* Clear the PME_To_ACK receieved flag */ 1807 px_p->px_pm_flags &= ~PX_PMETOACK_RECVD; 1808 /* 1809 * When P25 is the downstream device, after receiving 1810 * PME_To_ACK, fire will go to Detect state, which causes 1811 * the link down event. Inform FMA that this is expected. 1812 * In case of all other cards complaint with the pci express 1813 * spec, this will happen when the power is re-applied. FMA 1814 * code will clear this flag after one instance of LDN. Since 1815 * there will not be a LDN event for the spec compliant cards, 1816 * we need to clear the flag after receiving PME_To_ACK. 1817 */ 1818 px_p->px_pm_flags |= PX_LDN_EXPECTED; 1819 if (px_send_pme_turnoff(csr_base) != DDI_SUCCESS) { 1820 ret = DDI_FAILURE; 1821 goto l23ready_done; 1822 } 1823 px_p->px_pm_flags |= PX_PME_TURNOFF_PENDING; 1824 1825 end = ddi_get_lbolt() + drv_usectohz(px_pme_to_ack_timeout); 1826 while (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1827 timeleft = cv_timedwait(&px_p->px_l23ready_cv, 1828 &px_p->px_l23ready_lock, end); 1829 /* 1830 * if cv_timedwait returns -1, it is either 1831 * 1) timed out or 1832 * 2) there was a pre-mature wakeup but by the time 1833 * cv_timedwait is called again end < lbolt i.e. 1834 * end is in the past. 1835 * 3) By the time we make first cv_timedwait call, 1836 * end < lbolt is true. 1837 */ 1838 if (timeleft == -1) 1839 break; 1840 } 1841 if (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1842 /* 1843 * Either timedout or interrupt didn't get a 1844 * chance to grab the mutex and set the flag. 1845 * release the mutex and delay for sometime. 1846 * This will 1) give a chance for interrupt to 1847 * set the flag 2) creates a delay between two 1848 * consequetive requests. 1849 */ 1850 mutex_exit(&px_p->px_l23ready_lock); 1851 delay(drv_usectohz(50 * PX_MSEC_TO_USEC)); 1852 mutex_held = 0; 1853 if (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1854 ret = DDI_FAILURE; 1855 DBG(DBG_PWR, px_p->px_dip, " Timed out while waiting" 1856 " for PME_TO_ACK\n"); 1857 } 1858 } 1859 px_p->px_pm_flags &= 1860 ~(PX_PME_TURNOFF_PENDING | PX_PMETOACK_RECVD | PX_LDN_EXPECTED); 1861 1862 l23ready_done: 1863 if (mutex_held) 1864 mutex_exit(&px_p->px_l23ready_lock); 1865 /* 1866 * Wait till link is in L1 idle, if sending PME_Turn_Off 1867 * was succesful. 1868 */ 1869 if (ret == DDI_SUCCESS) { 1870 if (px_link_wait4l1idle(csr_base) != DDI_SUCCESS) { 1871 DBG(DBG_PWR, px_p->px_dip, " Link is not at L1" 1872 " even though we received PME_To_ACK.\n"); 1873 /* 1874 * Workaround for hardware bug with P25. 1875 * Due to a hardware bug with P25, link state 1876 * will be Detect state rather than L1 after 1877 * link is transitioned to L23Ready state. Since 1878 * we don't know whether link is L23ready state 1879 * without Fire's state being L1_idle, we delay 1880 * here just to make sure that we wait till link 1881 * is transitioned to L23Ready state. 1882 */ 1883 delay(drv_usectohz(100 * PX_MSEC_TO_USEC)); 1884 } 1885 pwr_p->pwr_link_lvl = PM_LEVEL_L3; 1886 1887 } 1888 mutex_exit(&pwr_p->pwr_lock); 1889 return (ret); 1890 } 1891 1892 /* 1893 * Message interrupt handler intended to be shared for both 1894 * PME and PME_TO_ACK msg handling, currently only handles 1895 * PME_To_ACK message. 1896 */ 1897 uint_t 1898 px_pmeq_intr(caddr_t arg) 1899 { 1900 px_t *px_p = (px_t *)arg; 1901 1902 DBG(DBG_PWR, px_p->px_dip, " PME_To_ACK received \n"); 1903 mutex_enter(&px_p->px_l23ready_lock); 1904 cv_broadcast(&px_p->px_l23ready_cv); 1905 if (px_p->px_pm_flags & PX_PME_TURNOFF_PENDING) { 1906 px_p->px_pm_flags |= PX_PMETOACK_RECVD; 1907 } else { 1908 /* 1909 * This maybe the second ack received. If so then, 1910 * we should be receiving it during wait4L1 stage. 1911 */ 1912 px_p->px_pmetoack_ignored++; 1913 } 1914 mutex_exit(&px_p->px_l23ready_lock); 1915 return (DDI_INTR_CLAIMED); 1916 } 1917 1918 static int 1919 px_pre_pwron_check(px_t *px_p) 1920 { 1921 pcie_pwr_t *pwr_p; 1922 1923 /* If no PM info, return failure */ 1924 if (!PCIE_PMINFO(px_p->px_dip) || 1925 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1926 return (DDI_FAILURE); 1927 1928 /* 1929 * For the spec compliant downstream cards link down 1930 * is expected when the device is powered on. 1931 */ 1932 px_p->px_pm_flags |= PX_LDN_EXPECTED; 1933 return (pwr_p->pwr_link_lvl == PM_LEVEL_L3 ? DDI_SUCCESS : DDI_FAILURE); 1934 } 1935 1936 static int 1937 px_goto_l0(px_t *px_p) 1938 { 1939 pcie_pwr_t *pwr_p; 1940 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1941 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 1942 int ret = DDI_SUCCESS; 1943 uint64_t time_spent = 0; 1944 1945 /* If no PM info, return failure */ 1946 if (!PCIE_PMINFO(px_p->px_dip) || 1947 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1948 return (DDI_FAILURE); 1949 1950 mutex_enter(&pwr_p->pwr_lock); 1951 /* 1952 * The following link retrain activity will cause LDN and LUP event. 1953 * Receiving LDN prior to receiving LUP is expected, not an error in 1954 * this case. Receiving LUP indicates link is fully up to support 1955 * powering up down stream device, and of course any further LDN and 1956 * LUP outside this context will be error. 1957 */ 1958 px_p->px_lup_pending = 1; 1959 if (px_link_retrain(csr_base) != DDI_SUCCESS) { 1960 ret = DDI_FAILURE; 1961 goto l0_done; 1962 } 1963 1964 /* LUP event takes the order of 15ms amount of time to occur */ 1965 for (; px_p->px_lup_pending && (time_spent < px_lup_poll_to); 1966 time_spent += px_lup_poll_interval) 1967 drv_usecwait(px_lup_poll_interval); 1968 if (px_p->px_lup_pending) 1969 ret = DDI_FAILURE; 1970 l0_done: 1971 px_enable_detect_quiet(csr_base); 1972 if (ret == DDI_SUCCESS) 1973 pwr_p->pwr_link_lvl = PM_LEVEL_L0; 1974 mutex_exit(&pwr_p->pwr_lock); 1975 return (ret); 1976 } 1977 1978 /* 1979 * Extract the drivers binding name to identify which chip we're binding to. 1980 * Whenever a new bus bridge is created, the driver alias entry should be 1981 * added here to identify the device if needed. If a device isn't added, 1982 * the identity defaults to PX_CHIP_UNIDENTIFIED. 1983 */ 1984 static uint32_t 1985 px_identity_init(px_t *px_p) 1986 { 1987 dev_info_t *dip = px_p->px_dip; 1988 char *name = ddi_binding_name(dip); 1989 uint32_t revision = 0; 1990 1991 revision = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1992 "module-revision#", 0); 1993 1994 /* Check for Fire driver binding name */ 1995 if (strcmp(name, "pciex108e,80f0") == 0) { 1996 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 1997 "(FIRE), module-revision %d\n", NAMEINST(dip), 1998 revision); 1999 2000 return ((revision >= FIRE_MOD_REV_20) ? 2001 PX_CHIP_FIRE : PX_CHIP_UNIDENTIFIED); 2002 } 2003 2004 /* Check for Oberon driver binding name */ 2005 if (strcmp(name, "pciex108e,80f8") == 0) { 2006 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 2007 "(OBERON), module-revision %d\n", NAMEINST(dip), 2008 revision); 2009 2010 return (PX_CHIP_OBERON); 2011 } 2012 2013 DBG(DBG_ATTACH, dip, "%s%d: Unknown PCI Express Host bridge %s %x\n", 2014 ddi_driver_name(dip), ddi_get_instance(dip), name, revision); 2015 2016 return (PX_CHIP_UNIDENTIFIED); 2017 } 2018 2019 int 2020 px_err_add_intr(px_fault_t *px_fault_p) 2021 { 2022 dev_info_t *dip = px_fault_p->px_fh_dip; 2023 px_t *px_p = DIP_TO_STATE(dip); 2024 2025 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 2026 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, 2027 NULL, NULL) == 0); 2028 2029 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 2030 2031 return (DDI_SUCCESS); 2032 } 2033 2034 void 2035 px_err_rem_intr(px_fault_t *px_fault_p) 2036 { 2037 dev_info_t *dip = px_fault_p->px_fh_dip; 2038 px_t *px_p = DIP_TO_STATE(dip); 2039 2040 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 2041 IB_INTR_WAIT); 2042 2043 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 2044 } 2045 2046 /* 2047 * px_cb_intr_redist() - sun4u only, CB interrupt redistribution 2048 */ 2049 void 2050 px_cb_intr_redist(void *arg) 2051 { 2052 px_cb_t *cb_p = (px_cb_t *)arg; 2053 px_cb_list_t *pxl; 2054 px_t *pxp = NULL; 2055 px_fault_t *f_p = NULL; 2056 uint32_t new_cpuid; 2057 intr_valid_state_t enabled = 0; 2058 2059 mutex_enter(&cb_p->cb_mutex); 2060 2061 pxl = cb_p->pxl; 2062 if (!pxl) 2063 goto cb_done; 2064 2065 pxp = pxl->pxp; 2066 f_p = &pxp->px_cb_fault; 2067 for (; pxl && (f_p->px_fh_sysino != cb_p->sysino); ) { 2068 pxl = pxl->next; 2069 pxp = pxl->pxp; 2070 f_p = &pxp->px_cb_fault; 2071 } 2072 if (pxl == NULL) 2073 goto cb_done; 2074 2075 new_cpuid = intr_dist_cpuid(); 2076 if (new_cpuid == cb_p->cpuid) 2077 goto cb_done; 2078 2079 if ((px_lib_intr_getvalid(pxp->px_dip, f_p->px_fh_sysino, &enabled) 2080 != DDI_SUCCESS) || !enabled) { 2081 DBG(DBG_IB, pxp->px_dip, "px_cb_intr_redist: CB not enabled, " 2082 "sysino(0x%x)\n", f_p->px_fh_sysino); 2083 goto cb_done; 2084 } 2085 2086 PX_INTR_DISABLE(pxp->px_dip, f_p->px_fh_sysino); 2087 2088 cb_p->cpuid = new_cpuid; 2089 cb_p->sysino = f_p->px_fh_sysino; 2090 PX_INTR_ENABLE(pxp->px_dip, cb_p->sysino, cb_p->cpuid); 2091 2092 cb_done: 2093 mutex_exit(&cb_p->cb_mutex); 2094 } 2095 2096 /* 2097 * px_cb_add_intr() - Called from attach(9E) to create CB if not yet 2098 * created, to add CB interrupt vector always, but enable only once. 2099 */ 2100 int 2101 px_cb_add_intr(px_fault_t *fault_p) 2102 { 2103 px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip); 2104 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2105 px_cb_t *cb_p = (px_cb_t *)px_get_cb(fault_p->px_fh_dip); 2106 px_cb_list_t *pxl, *pxl_new; 2107 boolean_t is_proxy = B_FALSE; 2108 2109 /* create cb */ 2110 if (cb_p == NULL) { 2111 cb_p = kmem_zalloc(sizeof (px_cb_t), KM_SLEEP); 2112 2113 mutex_init(&cb_p->cb_mutex, NULL, MUTEX_DRIVER, 2114 (void *) ipltospl(FM_ERR_PIL)); 2115 2116 cb_p->px_cb_func = px_cb_intr; 2117 pxu_p->px_cb_p = cb_p; 2118 px_set_cb(fault_p->px_fh_dip, (uint64_t)cb_p); 2119 2120 /* px_lib_dev_init allows only FIRE and OBERON */ 2121 px_err_reg_enable( 2122 (pxu_p->chip_type == PX_CHIP_FIRE) ? 2123 PX_ERR_JBC : PX_ERR_UBC, 2124 pxu_p->px_address[PX_REG_XBC]); 2125 } else 2126 pxu_p->px_cb_p = cb_p; 2127 2128 /* register cb interrupt */ 2129 VERIFY(add_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL, 2130 (intrfunc)cb_p->px_cb_func, (caddr_t)cb_p, NULL, NULL) == 0); 2131 2132 2133 /* update cb list */ 2134 mutex_enter(&cb_p->cb_mutex); 2135 if (cb_p->pxl == NULL) { 2136 is_proxy = B_TRUE; 2137 pxl = kmem_zalloc(sizeof (px_cb_list_t), KM_SLEEP); 2138 pxl->pxp = px_p; 2139 cb_p->pxl = pxl; 2140 cb_p->sysino = fault_p->px_fh_sysino; 2141 cb_p->cpuid = intr_dist_cpuid(); 2142 } else { 2143 /* 2144 * Find the last pxl or 2145 * stop short at encountering a redundent entry, or 2146 * both. 2147 */ 2148 pxl = cb_p->pxl; 2149 for (; !(pxl->pxp == px_p) && pxl->next; pxl = pxl->next) {}; 2150 ASSERT(pxl->pxp != px_p); 2151 2152 /* add to linked list */ 2153 pxl_new = kmem_zalloc(sizeof (px_cb_list_t), KM_SLEEP); 2154 pxl_new->pxp = px_p; 2155 pxl->next = pxl_new; 2156 } 2157 cb_p->attachcnt++; 2158 mutex_exit(&cb_p->cb_mutex); 2159 2160 if (is_proxy) { 2161 /* add to interrupt redistribution list */ 2162 intr_dist_add(px_cb_intr_redist, cb_p); 2163 2164 /* enable cb hw interrupt */ 2165 px_ib_intr_enable(px_p, cb_p->cpuid, fault_p->px_intr_ino); 2166 } 2167 2168 return (DDI_SUCCESS); 2169 } 2170 2171 /* 2172 * px_cb_rem_intr() - Called from detach(9E) to remove its CB 2173 * interrupt vector, to shift proxy to the next available px, 2174 * or disable CB interrupt when itself is the last. 2175 */ 2176 void 2177 px_cb_rem_intr(px_fault_t *fault_p) 2178 { 2179 px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip), *pxp; 2180 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2181 px_cb_t *cb_p = PX2CB(px_p); 2182 px_cb_list_t *pxl, *prev; 2183 px_fault_t *f_p; 2184 2185 ASSERT(cb_p->pxl); 2186 2187 /* find and remove this px, and update cb list */ 2188 mutex_enter(&cb_p->cb_mutex); 2189 2190 pxl = cb_p->pxl; 2191 if (pxl->pxp == px_p) { 2192 cb_p->pxl = pxl->next; 2193 } else { 2194 prev = pxl; 2195 pxl = pxl->next; 2196 for (; pxl && (pxl->pxp != px_p); prev = pxl, pxl = pxl->next) { 2197 }; 2198 if (!pxl) { 2199 cmn_err(CE_WARN, "px_cb_rem_intr: can't find px_p 0x%p " 2200 "in registered CB list.", (void *)px_p); 2201 mutex_exit(&cb_p->cb_mutex); 2202 return; 2203 } 2204 prev->next = pxl->next; 2205 } 2206 pxu_p->px_cb_p = NULL; 2207 cb_p->attachcnt--; 2208 kmem_free(pxl, sizeof (px_cb_list_t)); 2209 mutex_exit(&cb_p->cb_mutex); 2210 2211 /* disable cb hw interrupt */ 2212 if (fault_p->px_fh_sysino == cb_p->sysino) 2213 px_ib_intr_disable(px_p->px_ib_p, fault_p->px_intr_ino, 2214 IB_INTR_WAIT); 2215 2216 /* if last px, remove from interrupt redistribution list */ 2217 if (cb_p->pxl == NULL) 2218 intr_dist_rem(px_cb_intr_redist, cb_p); 2219 2220 /* de-register interrupt */ 2221 VERIFY(rem_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 2222 2223 /* if not last px, assign next px to manage cb */ 2224 mutex_enter(&cb_p->cb_mutex); 2225 if (cb_p->pxl) { 2226 if (fault_p->px_fh_sysino == cb_p->sysino) { 2227 pxp = cb_p->pxl->pxp; 2228 f_p = &pxp->px_cb_fault; 2229 cb_p->sysino = f_p->px_fh_sysino; 2230 2231 PX_INTR_ENABLE(pxp->px_dip, cb_p->sysino, cb_p->cpuid); 2232 (void) px_lib_intr_setstate(pxp->px_dip, cb_p->sysino, 2233 INTR_IDLE_STATE); 2234 } 2235 mutex_exit(&cb_p->cb_mutex); 2236 return; 2237 } 2238 2239 /* clean up after the last px */ 2240 mutex_exit(&cb_p->cb_mutex); 2241 2242 /* px_lib_dev_init allows only FIRE and OBERON */ 2243 px_err_reg_disable( 2244 (pxu_p->chip_type == PX_CHIP_FIRE) ? PX_ERR_JBC : PX_ERR_UBC, 2245 pxu_p->px_address[PX_REG_XBC]); 2246 2247 mutex_destroy(&cb_p->cb_mutex); 2248 px_set_cb(fault_p->px_fh_dip, 0ull); 2249 kmem_free(cb_p, sizeof (px_cb_t)); 2250 } 2251 2252 /* 2253 * px_cb_intr() - sun4u only, CB interrupt dispatcher 2254 */ 2255 uint_t 2256 px_cb_intr(caddr_t arg) 2257 { 2258 px_cb_t *cb_p = (px_cb_t *)arg; 2259 px_t *pxp; 2260 px_fault_t *f_p; 2261 int ret; 2262 2263 mutex_enter(&cb_p->cb_mutex); 2264 2265 if (!cb_p->pxl) { 2266 mutex_exit(&cb_p->cb_mutex); 2267 return (DDI_INTR_UNCLAIMED); 2268 } 2269 2270 pxp = cb_p->pxl->pxp; 2271 f_p = &pxp->px_cb_fault; 2272 2273 ret = f_p->px_err_func((caddr_t)f_p); 2274 2275 mutex_exit(&cb_p->cb_mutex); 2276 return (ret); 2277 } 2278 2279 #ifdef FMA 2280 void 2281 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 2282 { 2283 /* populate the rc_status by reading the registers - TBD */ 2284 } 2285 #endif /* FMA */ 2286 2287 /* 2288 * Unprotected raw reads/writes of fabric device's config space. 2289 * Only used for temporary PCI-E Fabric Error Handling. 2290 */ 2291 uint32_t 2292 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) 2293 { 2294 px_ranges_t *rp = px_p->px_ranges_p; 2295 uint64_t range_prop, base_addr; 2296 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 2297 uint32_t val; 2298 2299 /* Get Fire's Physical Base Address */ 2300 range_prop = px_get_range_prop(px_p, rp, bank); 2301 2302 /* Get config space first. */ 2303 base_addr = range_prop + PX_BDF_TO_CFGADDR(bdf, offset); 2304 2305 val = ldphysio(base_addr); 2306 2307 return (LE_32(val)); 2308 } 2309 2310 void 2311 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 2312 uint32_t val) { 2313 px_ranges_t *rp = px_p->px_ranges_p; 2314 uint64_t range_prop, base_addr; 2315 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 2316 2317 /* Get Fire's Physical Base Address */ 2318 range_prop = px_get_range_prop(px_p, rp, bank); 2319 2320 /* Get config space first. */ 2321 base_addr = range_prop + PX_BDF_TO_CFGADDR(bdf, offset); 2322 2323 stphysio(base_addr, LE_32(val)); 2324 } 2325 2326 /* 2327 * cpr callback 2328 * 2329 * disable fabric error msg interrupt prior to suspending 2330 * all device drivers; re-enable fabric error msg interrupt 2331 * after all devices are resumed. 2332 */ 2333 static boolean_t 2334 px_cpr_callb(void *arg, int code) 2335 { 2336 px_t *px_p = (px_t *)arg; 2337 px_ib_t *ib_p = px_p->px_ib_p; 2338 px_pec_t *pec_p = px_p->px_pec_p; 2339 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2340 caddr_t csr_base; 2341 devino_t ce_ino, nf_ino, f_ino; 2342 px_ino_t *ce_ino_p, *nf_ino_p, *f_ino_p; 2343 uint64_t imu_log_enable, imu_intr_enable; 2344 uint64_t imu_log_mask, imu_intr_mask; 2345 2346 ce_ino = px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id); 2347 nf_ino = px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id); 2348 f_ino = px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id); 2349 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2350 2351 imu_log_enable = CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE); 2352 imu_intr_enable = CSR_XR(csr_base, IMU_INTERRUPT_ENABLE); 2353 2354 imu_log_mask = BITMASK(IMU_ERROR_LOG_ENABLE_FATAL_MES_NOT_EN_LOG_EN) | 2355 BITMASK(IMU_ERROR_LOG_ENABLE_NONFATAL_MES_NOT_EN_LOG_EN) | 2356 BITMASK(IMU_ERROR_LOG_ENABLE_COR_MES_NOT_EN_LOG_EN); 2357 2358 imu_intr_mask = 2359 BITMASK(IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_S_INT_EN) | 2360 BITMASK(IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_S_INT_EN) | 2361 BITMASK(IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_S_INT_EN) | 2362 BITMASK(IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_P_INT_EN) | 2363 BITMASK(IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_P_INT_EN) | 2364 BITMASK(IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_P_INT_EN); 2365 2366 switch (code) { 2367 case CB_CODE_CPR_CHKPT: 2368 /* disable imu rbne on corr/nonfatal/fatal errors */ 2369 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, 2370 imu_log_enable & (~imu_log_mask)); 2371 2372 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, 2373 imu_intr_enable & (~imu_intr_mask)); 2374 2375 /* disable CORR intr mapping */ 2376 px_ib_intr_disable(ib_p, ce_ino, IB_INTR_NOWAIT); 2377 2378 /* disable NON FATAL intr mapping */ 2379 px_ib_intr_disable(ib_p, nf_ino, IB_INTR_NOWAIT); 2380 2381 /* disable FATAL intr mapping */ 2382 px_ib_intr_disable(ib_p, f_ino, IB_INTR_NOWAIT); 2383 2384 break; 2385 2386 case CB_CODE_CPR_RESUME: 2387 pxu_p->cpr_flag = PX_NOT_CPR; 2388 mutex_enter(&ib_p->ib_ino_lst_mutex); 2389 2390 ce_ino_p = px_ib_locate_ino(ib_p, ce_ino); 2391 nf_ino_p = px_ib_locate_ino(ib_p, nf_ino); 2392 f_ino_p = px_ib_locate_ino(ib_p, f_ino); 2393 2394 /* enable CORR intr mapping */ 2395 if (ce_ino_p) 2396 px_ib_intr_enable(px_p, ce_ino_p->ino_cpuid, ce_ino); 2397 else 2398 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2399 "reenable PCIe Correctable msg intr.\n"); 2400 2401 /* enable NON FATAL intr mapping */ 2402 if (nf_ino_p) 2403 px_ib_intr_enable(px_p, nf_ino_p->ino_cpuid, nf_ino); 2404 else 2405 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2406 "reenable PCIe Non Fatal msg intr.\n"); 2407 2408 /* enable FATAL intr mapping */ 2409 if (f_ino_p) 2410 px_ib_intr_enable(px_p, f_ino_p->ino_cpuid, f_ino); 2411 else 2412 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2413 "reenable PCIe Fatal msg intr.\n"); 2414 2415 mutex_exit(&ib_p->ib_ino_lst_mutex); 2416 2417 /* enable corr/nonfatal/fatal not enable error */ 2418 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, (imu_log_enable | 2419 (imu_log_mask & px_imu_log_mask))); 2420 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, (imu_intr_enable | 2421 (imu_intr_mask & px_imu_intr_mask))); 2422 2423 break; 2424 } 2425 2426 return (B_TRUE); 2427 } 2428 2429 uint64_t 2430 px_get_rng_parent_hi_mask(px_t *px_p) 2431 { 2432 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2433 uint64_t mask; 2434 2435 switch (PX_CHIP_TYPE(pxu_p)) { 2436 case PX_CHIP_OBERON: 2437 mask = OBERON_RANGE_PROP_MASK; 2438 break; 2439 case PX_CHIP_FIRE: 2440 mask = PX_RANGE_PROP_MASK; 2441 break; 2442 default: 2443 mask = PX_RANGE_PROP_MASK; 2444 } 2445 2446 return (mask); 2447 } 2448 2449 /* 2450 * fetch chip's range propery's value 2451 */ 2452 uint64_t 2453 px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank) 2454 { 2455 uint64_t mask, range_prop; 2456 2457 mask = px_get_rng_parent_hi_mask(px_p); 2458 range_prop = (((uint64_t)(rp[bank].parent_high & mask)) << 32) | 2459 rp[bank].parent_low; 2460 2461 return (range_prop); 2462 } 2463 2464 /* 2465 * add cpr callback 2466 */ 2467 void 2468 px_cpr_add_callb(px_t *px_p) 2469 { 2470 px_p->px_cprcb_id = callb_add(px_cpr_callb, (void *)px_p, 2471 CB_CL_CPR_POST_USER, "px_cpr"); 2472 } 2473 2474 /* 2475 * remove cpr callback 2476 */ 2477 void 2478 px_cpr_rem_callb(px_t *px_p) 2479 { 2480 (void) callb_delete(px_p->px_cprcb_id); 2481 } 2482 2483 /*ARGSUSED*/ 2484 static uint_t 2485 px_hp_intr(caddr_t arg1, caddr_t arg2) 2486 { 2487 px_t *px_p = (px_t *)arg1; 2488 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2489 int rval; 2490 2491 rval = pciehpc_intr(px_p->px_dip); 2492 2493 #ifdef DEBUG 2494 if (rval == DDI_INTR_UNCLAIMED) 2495 cmn_err(CE_WARN, "%s%d: UNCLAIMED intr\n", 2496 ddi_driver_name(px_p->px_dip), 2497 ddi_get_instance(px_p->px_dip)); 2498 #endif 2499 2500 /* Set the interrupt state to idle */ 2501 if (px_lib_intr_setstate(px_p->px_dip, 2502 pxu_p->hp_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) 2503 return (DDI_INTR_UNCLAIMED); 2504 2505 return (rval); 2506 } 2507 2508 int 2509 px_lib_hotplug_init(dev_info_t *dip, void *arg) 2510 { 2511 px_t *px_p = DIP_TO_STATE(dip); 2512 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2513 uint64_t ret; 2514 2515 if ((ret = hvio_hotplug_init(dip, arg)) == DDI_SUCCESS) { 2516 if (px_lib_intr_devino_to_sysino(px_p->px_dip, 2517 px_p->px_inos[PX_INTR_HOTPLUG], &pxu_p->hp_sysino) != 2518 DDI_SUCCESS) { 2519 #ifdef DEBUG 2520 cmn_err(CE_WARN, "%s%d: devino_to_sysino fails\n", 2521 ddi_driver_name(px_p->px_dip), 2522 ddi_get_instance(px_p->px_dip)); 2523 #endif 2524 return (DDI_FAILURE); 2525 } 2526 2527 VERIFY(add_ivintr(pxu_p->hp_sysino, PX_PCIEHP_PIL, 2528 (intrfunc)px_hp_intr, (caddr_t)px_p, NULL, NULL) == 0); 2529 2530 px_ib_intr_enable(px_p, intr_dist_cpuid(), 2531 px_p->px_inos[PX_INTR_HOTPLUG]); 2532 } 2533 2534 return (ret); 2535 } 2536 2537 void 2538 px_lib_hotplug_uninit(dev_info_t *dip) 2539 { 2540 if (hvio_hotplug_uninit(dip) == DDI_SUCCESS) { 2541 px_t *px_p = DIP_TO_STATE(dip); 2542 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2543 2544 px_ib_intr_disable(px_p->px_ib_p, 2545 px_p->px_inos[PX_INTR_HOTPLUG], IB_INTR_WAIT); 2546 2547 VERIFY(rem_ivintr(pxu_p->hp_sysino, PX_PCIEHP_PIL) == 0); 2548 } 2549 } 2550 2551 /* 2552 * px_hp_intr_redist() - sun4u only, HP interrupt redistribution 2553 */ 2554 void 2555 px_hp_intr_redist(px_t *px_p) 2556 { 2557 if (px_p && (px_p->px_dev_caps & PX_HOTPLUG_CAPABLE)) { 2558 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 2559 px_p->px_inos[PX_INTR_HOTPLUG], B_FALSE); 2560 } 2561 } 2562 2563 boolean_t 2564 px_lib_is_in_drain_state(px_t *px_p) 2565 { 2566 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2567 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2568 uint64_t drain_status; 2569 2570 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 2571 drain_status = CSR_BR(csr_base, DRAIN_CONTROL_STATUS, DRAIN); 2572 } else { 2573 drain_status = CSR_BR(csr_base, TLU_STATUS, DRAIN); 2574 } 2575 2576 return (drain_status); 2577 } 2578 2579 pcie_req_id_t 2580 px_lib_get_bdf(px_t *px_p) 2581 { 2582 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2583 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2584 pcie_req_id_t bdf; 2585 2586 bdf = CSR_BR(csr_base, DMC_PCI_EXPRESS_CONFIGURATION, REQ_ID); 2587 2588 return (bdf); 2589 } 2590