1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Psycho+ specifics implementation: 30 * interrupt mapping register 31 * PBM configuration 32 * ECC and PBM error handling 33 * Iommu mapping handling 34 * Streaming Cache flushing 35 */ 36 37 #include <sys/types.h> 38 #include <sys/kmem.h> 39 #include <sys/sysmacros.h> 40 #include <sys/async.h> 41 #include <sys/ivintr.h> 42 #include <sys/systm.h> 43 #include <sys/intreg.h> /* UPAID_TO_IGN() */ 44 #include <sys/intr.h> 45 #include <sys/sunddi.h> 46 #include <sys/sunndi.h> 47 #include <sys/machsystm.h> 48 #include <sys/fm/util.h> 49 #include <sys/ddi_impldefs.h> 50 #include <sys/iommutsb.h> 51 #include <sys/spl.h> 52 #include <sys/fm/util.h> 53 #include <sys/fm/protocol.h> 54 #include <sys/fm/io/pci.h> 55 #include <sys/fm/io/sun4upci.h> 56 #include <sys/pci/pci_obj.h> 57 #include <sys/pci/pcipsy.h> 58 59 #ifdef _STARFIRE 60 #include <sys/starfire.h> 61 #endif /* _STARFIRE */ 62 63 static uint32_t pci_identity_init(pci_t *pci_p); 64 static int pci_intr_setup(pci_t *pci_p); 65 static void pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p); 66 67 static pci_ksinfo_t *pci_name_kstat; 68 69 /*LINTLIBRARY*/ 70 /* called by pci_attach() DDI_ATTACH to initialize pci objects */ 71 int 72 pci_obj_setup(pci_t *pci_p) 73 { 74 pci_common_t *cmn_p; 75 int ret; 76 77 mutex_enter(&pci_global_mutex); 78 cmn_p = get_pci_common_soft_state(pci_p->pci_id); 79 if (cmn_p == NULL) { 80 uint_t id = pci_p->pci_id; 81 if (alloc_pci_common_soft_state(id) != DDI_SUCCESS) { 82 mutex_exit(&pci_global_mutex); 83 return (DDI_FAILURE); 84 } 85 cmn_p = get_pci_common_soft_state(id); 86 cmn_p->pci_common_id = id; 87 } 88 89 ASSERT((pci_p->pci_side == 0) || (pci_p->pci_side == 1)); 90 if (cmn_p->pci_p[pci_p->pci_side]) { 91 /* second side attach */ 92 pci_p->pci_side = PCI_OTHER_SIDE(pci_p->pci_side); 93 ASSERT(cmn_p->pci_p[pci_p->pci_side] == NULL); 94 } 95 96 cmn_p->pci_p[pci_p->pci_side] = pci_p; 97 pci_p->pci_common_p = cmn_p; 98 99 if (cmn_p->pci_common_refcnt == 0) { 100 /* Perform allocation first to avoid delicate unwinding. */ 101 if (pci_alloc_tsb(pci_p) != DDI_SUCCESS) { 102 cmn_p->pci_p[pci_p->pci_side] = NULL; 103 pci_p->pci_common_p = NULL; 104 free_pci_common_soft_state(cmn_p->pci_common_id); 105 mutex_exit(&pci_global_mutex); 106 return (DDI_FAILURE); 107 } 108 cmn_p->pci_common_tsb_cookie = pci_p->pci_tsb_cookie; 109 cmn_p->pci_chip_id = pci_identity_init(pci_p); 110 111 ib_create(pci_p); 112 cmn_p->pci_common_ib_p = pci_p->pci_ib_p; 113 114 cb_create(pci_p); 115 cmn_p->pci_common_cb_p = pci_p->pci_cb_p; 116 117 iommu_create(pci_p); 118 cmn_p->pci_common_iommu_p = pci_p->pci_iommu_p; 119 120 ecc_create(pci_p); 121 cmn_p->pci_common_ecc_p = pci_p->pci_ecc_p; 122 } else { 123 ASSERT(cmn_p->pci_common_refcnt == 1); 124 125 pci_p->pci_tsb_cookie = cmn_p->pci_common_tsb_cookie; 126 pci_p->pci_ib_p = cmn_p->pci_common_ib_p; 127 pci_p->pci_cb_p = cmn_p->pci_common_cb_p; 128 pci_p->pci_iommu_p = cmn_p->pci_common_iommu_p; 129 pci_p->pci_ecc_p = cmn_p->pci_common_ecc_p; 130 } 131 132 pbm_create(pci_p); 133 sc_create(pci_p); 134 135 pci_fm_create(pci_p); 136 137 if ((ret = pci_intr_setup(pci_p)) != DDI_SUCCESS) 138 goto done; 139 if (CHIP_TYPE(pci_p) == PCI_CHIP_PSYCHO) 140 pci_kstat_create(pci_p); 141 142 cmn_p->pci_common_attachcnt++; 143 cmn_p->pci_common_refcnt++; 144 done: 145 mutex_exit(&pci_global_mutex); 146 if (ret != DDI_SUCCESS) 147 cmn_err(CE_NOTE, "Interrupt register failure, returning 0x%x\n", 148 ret); 149 return (ret); 150 } 151 152 /* called by pci_detach() DDI_DETACH to destroy pci objects */ 153 void 154 pci_obj_destroy(pci_t *pci_p) 155 { 156 pci_common_t *cmn_p; 157 158 mutex_enter(&pci_global_mutex); 159 160 cmn_p = pci_p->pci_common_p; 161 cmn_p->pci_common_refcnt--; 162 cmn_p->pci_common_attachcnt--; 163 164 pci_kstat_destroy(pci_p); 165 166 sc_destroy(pci_p); 167 pbm_destroy(pci_p); 168 pci_fm_destroy(pci_p); 169 170 if (cmn_p->pci_common_refcnt != 0) { 171 cmn_p->pci_p[pci_p->pci_side] = NULL; 172 mutex_exit(&pci_global_mutex); 173 return; 174 } 175 176 ecc_destroy(pci_p); 177 iommu_destroy(pci_p); 178 cb_destroy(pci_p); 179 ib_destroy(pci_p); 180 181 free_pci_common_soft_state(cmn_p->pci_common_id); 182 pci_intr_teardown(pci_p); 183 mutex_exit(&pci_global_mutex); 184 } 185 186 /* called by pci_attach() DDI_RESUME to (re)initialize pci objects */ 187 void 188 pci_obj_resume(pci_t *pci_p) 189 { 190 pci_common_t *cmn_p = pci_p->pci_common_p; 191 192 mutex_enter(&pci_global_mutex); 193 194 if (cmn_p->pci_common_attachcnt == 0) { 195 ib_configure(pci_p->pci_ib_p); 196 iommu_configure(pci_p->pci_iommu_p); 197 ecc_configure(pci_p); 198 ib_resume(pci_p->pci_ib_p); 199 } 200 201 pbm_configure(pci_p->pci_pbm_p); 202 sc_configure(pci_p->pci_sc_p); 203 204 if (cmn_p->pci_common_attachcnt == 0) 205 cb_resume(pci_p->pci_cb_p); 206 207 pbm_resume(pci_p->pci_pbm_p); 208 209 cmn_p->pci_common_attachcnt++; 210 mutex_exit(&pci_global_mutex); 211 } 212 213 /* called by pci_detach() DDI_SUSPEND to suspend pci objects */ 214 void 215 pci_obj_suspend(pci_t *pci_p) 216 { 217 mutex_enter(&pci_global_mutex); 218 219 pbm_suspend(pci_p->pci_pbm_p); 220 if (!--pci_p->pci_common_p->pci_common_attachcnt) { 221 ib_suspend(pci_p->pci_ib_p); 222 cb_suspend(pci_p->pci_cb_p); 223 } 224 225 mutex_exit(&pci_global_mutex); 226 } 227 228 static uint32_t javelin_prom_fix[] = {0xfff800, 0, 0, 0x3f}; 229 static int 230 pci_intr_setup(pci_t *pci_p) 231 { 232 extern char *platform; 233 dev_info_t *dip = pci_p->pci_dip; 234 pbm_t *pbm_p = pci_p->pci_pbm_p; 235 cb_t *cb_p = pci_p->pci_cb_p; 236 int i, no_of_intrs; 237 238 /* 239 * This is a hack to fix a broken imap entry in the javelin PROM. 240 * see bugid 4226603 241 */ 242 if (strcmp((const char *)&platform, "SUNW,Ultra-250") == 0) 243 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 244 "interrupt-map-mask", (caddr_t)javelin_prom_fix, 245 sizeof (javelin_prom_fix)); 246 247 /* 248 * Get the interrupts property. 249 */ 250 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 251 "interrupts", (caddr_t)&pci_p->pci_inos, 252 &pci_p->pci_inos_len) != DDI_SUCCESS) 253 cmn_err(CE_PANIC, "%s%d: no interrupts property\n", 254 ddi_driver_name(dip), ddi_get_instance(dip)); 255 256 /* 257 * figure out number of interrupts in the "interrupts" property 258 * and convert them all into ino. 259 */ 260 i = ddi_getprop(DDI_DEV_T_ANY, dip, 0, "#interrupt-cells", 1); 261 i = CELLS_1275_TO_BYTES(i); 262 no_of_intrs = pci_p->pci_inos_len / i; 263 for (i = 0; i < no_of_intrs; i++) 264 pci_p->pci_inos[i] = IB_MONDO_TO_INO(pci_p->pci_inos[i]); 265 266 if (pci_p->pci_common_p->pci_common_refcnt == 0) { 267 cb_p->cb_no_of_inos = no_of_intrs; 268 if (i = cb_register_intr(pci_p)) 269 goto teardown; 270 if (i = ecc_register_intr(pci_p)) 271 goto teardown; 272 273 intr_dist_add(cb_intr_dist, cb_p); 274 cb_enable_intr(pci_p); 275 ecc_enable_intr(pci_p); 276 } 277 278 if (i = pbm_register_intr(pbm_p)) { 279 if (pci_p->pci_common_p->pci_common_refcnt == 0) 280 intr_dist_rem(cb_intr_dist, cb_p); 281 goto teardown; 282 } 283 intr_dist_add(pbm_intr_dist, pbm_p); 284 ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_PBM]); 285 286 if (pci_p->pci_common_p->pci_common_refcnt == 0) 287 intr_dist_add_weighted(ib_intr_dist_all, pci_p->pci_ib_p); 288 return (DDI_SUCCESS); 289 teardown: 290 pci_intr_teardown(pci_p); 291 return (i); 292 } 293 294 /* 295 * pci_fix_ranges - fixes the config space entry of the "ranges" 296 * property on psycho+ platforms 297 */ 298 void 299 pci_fix_ranges(pci_ranges_t *rng_p, int rng_entries) 300 { 301 int i; 302 for (i = 0; i < rng_entries; i++, rng_p++) 303 if ((rng_p->child_high & PCI_REG_ADDR_M) == PCI_ADDR_CONFIG) 304 rng_p->parent_low |= rng_p->child_high; 305 } 306 307 /* 308 * map_pci_registers 309 * 310 * This function is called from the attach routine to map the registers 311 * accessed by this driver. 312 * 313 * used by: pci_attach() 314 * 315 * return value: DDI_FAILURE on failure 316 */ 317 int 318 map_pci_registers(pci_t *pci_p, dev_info_t *dip) 319 { 320 ddi_device_acc_attr_t attr; 321 322 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 323 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 324 325 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 326 if (ddi_regs_map_setup(dip, 0, &pci_p->pci_address[0], 0, 0, 327 &attr, &pci_p->pci_ac[0]) != DDI_SUCCESS) { 328 cmn_err(CE_WARN, "%s%d: unable to map reg entry 0\n", 329 ddi_driver_name(dip), ddi_get_instance(dip)); 330 return (DDI_FAILURE); 331 } 332 /* 333 * if we don't have streaming buffer, then we don't have 334 * pci_address[2]. 335 */ 336 if (pci_stream_buf_exists && 337 ddi_regs_map_setup(dip, 2, &pci_p->pci_address[2], 0, 0, 338 &attr, &pci_p->pci_ac[2]) != DDI_SUCCESS) { 339 cmn_err(CE_WARN, "%s%d: unable to map reg entry 2\n", 340 ddi_driver_name(dip), ddi_get_instance(dip)); 341 ddi_regs_map_free(&pci_p->pci_ac[0]); 342 return (DDI_FAILURE); 343 } 344 345 /* 346 * The second register set contains the bridge's configuration 347 * header. This header is at the very beginning of the bridge's 348 * configuration space. This space has litte-endian byte order. 349 */ 350 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 351 if (ddi_regs_map_setup(dip, 1, &pci_p->pci_address[1], 0, 352 PCI_CONF_HDR_SIZE, &attr, &pci_p->pci_ac[1]) != DDI_SUCCESS) { 353 354 cmn_err(CE_WARN, "%s%d: unable to map reg entry 1\n", 355 ddi_driver_name(dip), ddi_get_instance(dip)); 356 ddi_regs_map_free(&pci_p->pci_ac[0]); 357 if (pci_stream_buf_exists) 358 ddi_regs_map_free(&pci_p->pci_ac[2]); 359 return (DDI_FAILURE); 360 } 361 DEBUG3(DBG_ATTACH, dip, "address (%p,%p,%p)\n", 362 pci_p->pci_address[0], pci_p->pci_address[1], 363 pci_p->pci_address[2]); 364 365 return (DDI_SUCCESS); 366 } 367 368 /* 369 * unmap_pci_registers: 370 * 371 * This routine unmap the registers mapped by map_pci_registers. 372 * 373 * used by: pci_detach() 374 * 375 * return value: none 376 */ 377 void 378 unmap_pci_registers(pci_t *pci_p) 379 { 380 ddi_regs_map_free(&pci_p->pci_ac[0]); 381 ddi_regs_map_free(&pci_p->pci_ac[1]); 382 if (pci_stream_buf_exists) 383 ddi_regs_map_free(&pci_p->pci_ac[2]); 384 } 385 386 /* 387 * These convenience wrappers relies on map_pci_registers() to setup 388 * pci_address[0-2] correctly at first. 389 */ 390 /* The psycho+ reg base is at 1fe.0000.0000 */ 391 static uintptr_t 392 get_reg_base(pci_t *pci_p) 393 { 394 return ((uintptr_t)pci_p->pci_address[pci_stream_buf_exists ? 2 : 0]); 395 } 396 397 /* The psycho+ config reg base is always the 2nd reg entry */ 398 static uintptr_t 399 get_config_reg_base(pci_t *pci_p) 400 { 401 return ((uintptr_t)(pci_p->pci_address[1])); 402 } 403 404 uint64_t 405 ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id) 406 { 407 return ((mondo) | (cpu_id << COMMON_INTR_MAP_REG_TID_SHIFT) | 408 COMMON_INTR_MAP_REG_VALID); 409 410 } 411 412 uint32_t 413 ib_map_reg_get_cpu(volatile uint64_t reg) 414 { 415 return ((reg & COMMON_INTR_MAP_REG_TID) >> 416 COMMON_INTR_MAP_REG_TID_SHIFT); 417 } 418 419 uint64_t * 420 ib_intr_map_reg_addr(ib_t *ib_p, ib_ino_t ino) 421 { 422 uint64_t *addr; 423 424 if (ino & 0x20) 425 addr = (uint64_t *)(ib_p->ib_obio_intr_map_regs + 426 (((uint_t)ino & 0x1f) << 3)); 427 else 428 addr = (uint64_t *)(ib_p->ib_slot_intr_map_regs + 429 (((uint_t)ino & 0x3c) << 1)); 430 return (addr); 431 } 432 433 uint64_t * 434 ib_clear_intr_reg_addr(ib_t *ib_p, ib_ino_t ino) 435 { 436 uint64_t *addr; 437 438 if (ino & 0x20) 439 addr = (uint64_t *)(ib_p->ib_obio_clear_intr_regs + 440 (((uint_t)ino & 0x1f) << 3)); 441 else 442 addr = (uint64_t *)(ib_p->ib_slot_clear_intr_regs + 443 (((uint_t)ino & 0x1f) << 3)); 444 return (addr); 445 } 446 447 /* 448 * psycho have one mapping register per slot 449 */ 450 void 451 ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 452 { 453 if (!IB_IS_OBIO_INO(ino)) { 454 ASSERT(ino_p->ino_slot_no < 8); 455 ib_p->ib_map_reg_counters[ino_p->ino_slot_no]++; 456 } 457 } 458 459 /* 460 * return true if the ino shares mapping register with other interrupts 461 * of the same slot, or is still shared by other On-board devices. 462 */ 463 int 464 ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 465 { 466 ASSERT(IB_IS_OBIO_INO(ino) || ino_p->ino_slot_no < 8); 467 468 if (IB_IS_OBIO_INO(ino)) 469 return (ino_p->ino_ih_size); 470 else 471 return (--ib_p->ib_map_reg_counters[ino_p->ino_slot_no]); 472 } 473 474 /*ARGSUSED*/ 475 void 476 pci_pbm_intr_dist(pbm_t *pbm_p) 477 { 478 } 479 480 uintptr_t 481 pci_ib_setup(ib_t *ib_p) 482 { 483 pci_t *pci_p = ib_p->ib_pci_p; 484 uintptr_t a = get_reg_base(pci_p); 485 486 ib_p->ib_ign = PCI_ID_TO_IGN(pci_p->pci_id); 487 ib_p->ib_max_ino = PSYCHO_MAX_INO; 488 ib_p->ib_slot_intr_map_regs = a + PSYCHO_IB_SLOT_INTR_MAP_REG_OFFSET; 489 ib_p->ib_obio_intr_map_regs = a + PSYCHO_IB_OBIO_INTR_MAP_REG_OFFSET; 490 ib_p->ib_obio_clear_intr_regs = 491 a + PSYCHO_IB_OBIO_CLEAR_INTR_REG_OFFSET; 492 return (a); 493 } 494 495 uint32_t 496 pci_xlate_intr(dev_info_t *dip, dev_info_t *rdip, ib_t *ib_p, uint32_t intr) 497 { 498 int32_t len; 499 dev_info_t *cdip; 500 pci_regspec_t *pci_rp; 501 uint32_t bus, dev, phys_hi; 502 503 if ((intr > PCI_INTD) || (intr < PCI_INTA)) 504 goto done; 505 if (ddi_prop_exists(DDI_DEV_T_ANY, rdip, NULL, "interrupt-map")) 506 goto done; 507 /* 508 * Hack for pre 1275 imap machines e.g. quark & tazmo 509 * We need to turn any PCI interrupts into ino interrupts. machines 510 * supporting imap will have this done in the map. 511 */ 512 cdip = get_my_childs_dip(dip, rdip); 513 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, "reg", 514 (caddr_t)&pci_rp, &len) != DDI_SUCCESS) 515 return (0); 516 phys_hi = pci_rp->pci_phys_hi; 517 kmem_free(pci_rp, len); 518 519 bus = PCI_REG_BUS_G(phys_hi); 520 dev = PCI_REG_DEV_G(phys_hi); 521 522 /* 523 * The ino for a given device id is derived as 0BSSNN where 524 * 525 * B = 0 for bus A, 1 for bus B 526 * SS = dev - 1 for bus A, dev - 2 for bus B 527 * NN = 00 for INTA#, 01 for INTB#, 10 for INTC#, 11 for INTD# 528 * 529 * if pci bus number > 0x80, then devices are located on the A side(66) 530 */ 531 DEBUG3(DBG_IB, dip, "pci_xlate_intr: bus=%x, dev=%x, intr=%x\n", 532 bus, dev, intr); 533 intr--; 534 intr |= (bus & 0x80) ? ((dev - 1) << 2) : (0x10 | ((dev - 2) << 2)); 535 536 DEBUG1(DBG_IB, dip, "pci_xlate_intr: done ino=%x\n", intr); 537 done: 538 return (IB_INO_TO_MONDO(ib_p, intr)); 539 } 540 541 /* 542 * Return the cpuid to to be used for an ino. Psycho has special slot-cpu 543 * constraints on cpu assignment: 544 * 545 * On multi-function pci cards, functions have separate devinfo nodes and 546 * interrupts. Some pci support hardware, such as the psycho/pcipsy chip, 547 * control interrupt-to-cpu binding on a per pci-slot basis instead of per 548 * function. For hardware like this, if an interrupt for one function has 549 * already been directed to a particular cpu, we can't choose a different 550 * cpu for another function implemented in the same pci-slot - if we did 551 * we would be redirecting the first function too (which causes problems 552 * for consistent interrupt distribution). 553 * 554 * This function determines if there is already an established slot-oriented 555 * interrupt-to-cpu binding established, if there is then it returns that 556 * cpu. Otherwise a new cpu is selected by intr_dist_cpuid(). 557 * 558 * The devinfo node we are trying to associate a cpu with is 559 * ino_p->ino_ih_head->ih_dip. 560 */ 561 uint32_t 562 pci_intr_dist_cpuid(ib_t *ib_p, ib_ino_info_t *ino_p) 563 { 564 dev_info_t *rdip = ino_p->ino_ih_head->ih_dip; 565 dev_info_t *prdip = ddi_get_parent(rdip); 566 ib_ino_info_t *sino_p; 567 dev_info_t *sdip; 568 dev_info_t *psdip; 569 char *buf1 = NULL, *buf2 = NULL; 570 char *s1, *s2, *s3; 571 int l2; 572 int cpu_id; 573 574 /* must be psycho driver parent (not ebus) */ 575 if (strcmp(ddi_driver_name(prdip), "pcipsy") != 0) 576 goto newcpu; 577 578 /* 579 * From PCI 1275 binding: 2.2.1.3 Unit Address representation: 580 * Since the "unit-number" is the address that appears in on Open 581 * Firmware 'device path', it follows that only the DD and DD,FF 582 * forms of the text representation can appear in a 'device path'. 583 * 584 * The rdip unit address is of the form "DD[,FF]". Define two 585 * unit address strings that represent same-slot use: "DD" and "DD,". 586 * The first compare uses strcmp, the second uses strncmp. 587 */ 588 s1 = ddi_get_name_addr(rdip); 589 if (s1 == NULL) 590 goto newcpu; 591 592 buf1 = kmem_alloc(MAXNAMELEN, KM_SLEEP); /* strcmp */ 593 buf2 = kmem_alloc(MAXNAMELEN, KM_SLEEP); /* strncmp */ 594 s1 = strcpy(buf1, s1); 595 s2 = strcpy(buf2, s1); 596 597 s1 = strrchr(s1, ','); 598 if (s1) { 599 *s1 = '\0'; /* have "DD,FF" */ 600 s1 = buf1; /* search via strcmp "DD" */ 601 602 s2 = strrchr(s2, ','); 603 *(s2 + 1) = '\0'; 604 s2 = buf2; 605 l2 = strlen(s2); /* search via strncmp "DD," */ 606 } else { 607 (void) strcat(s2, ","); /* have "DD" */ 608 l2 = strlen(s2); /* search via strncmp "DD," */ 609 } 610 611 /* 612 * Search the established ino list for devinfo nodes bound 613 * to an ino that matches one of the slot use strings. 614 */ 615 ASSERT(MUTEX_HELD(&ib_p->ib_ino_lst_mutex)); 616 for (sino_p = ib_p->ib_ino_lst; sino_p; sino_p = sino_p->ino_next) { 617 /* skip self and non-established */ 618 if ((sino_p == ino_p) || (sino_p->ino_established == 0)) 619 continue; 620 621 /* skip non-siblings */ 622 sdip = sino_p->ino_ih_head->ih_dip; 623 psdip = ddi_get_parent(sdip); 624 if (psdip != prdip) 625 continue; 626 627 /* must be psycho driver parent (not ebus) */ 628 if (strcmp(ddi_driver_name(psdip), "pcipsy") != 0) 629 continue; 630 631 s3 = ddi_get_name_addr(sdip); 632 if ((s1 && (strcmp(s1, s3) == 0)) || 633 (strncmp(s2, s3, l2) == 0)) { 634 extern int intr_dist_debug; 635 636 if (intr_dist_debug) 637 cmn_err(CE_CONT, "intr_dist: " 638 "pcipsy`pci_intr_dist_cpuid " 639 "%s#%d %s: cpu %d established " 640 "by %s#%d %s\n", ddi_driver_name(rdip), 641 ddi_get_instance(rdip), 642 ddi_deviname(rdip, buf1), sino_p->ino_cpuid, 643 ddi_driver_name(sdip), 644 ddi_get_instance(sdip), 645 ddi_deviname(sdip, buf2)); 646 break; 647 } 648 } 649 650 /* If a slot use match is found then use established cpu */ 651 if (sino_p) { 652 cpu_id = sino_p->ino_cpuid; /* target established cpu */ 653 goto out; 654 } 655 656 newcpu: cpu_id = intr_dist_cpuid(); /* target new cpu */ 657 658 out: if (buf1) 659 kmem_free(buf1, MAXNAMELEN); 660 if (buf2) 661 kmem_free(buf2, MAXNAMELEN); 662 return (cpu_id); 663 } 664 665 666 /*ARGSUSED*/ 667 uint_t 668 cb_thermal_intr(caddr_t a) 669 { 670 cmn_err(CE_WARN, "pci: Thermal warning detected!\n"); 671 if (pci_thermal_intr_fatal) { 672 do_shutdown(); 673 674 /* 675 * In case do_shutdown() fails to halt the system. 676 */ 677 (void) timeout((void(*)(void *))power_down, NULL, 678 thermal_powerdown_delay * hz); 679 } 680 return (DDI_INTR_CLAIMED); 681 } 682 683 void 684 pci_cb_teardown(pci_t *pci_p) 685 { 686 cb_t *cb_p = pci_p->pci_cb_p; 687 uint32_t mondo; 688 689 if (pci_p->pci_thermal_interrupt != -1) { 690 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 691 pci_p->pci_inos[CBNINTR_THERMAL]); 692 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 693 694 cb_disable_nintr(cb_p, CBNINTR_THERMAL, IB_INTR_WAIT); 695 rem_ivintr(mondo, NULL); 696 } 697 #ifdef _STARFIRE 698 pc_ittrans_uninit(cb_p->cb_ittrans_cookie); 699 #endif /* _STARFIRE */ 700 } 701 702 int 703 cb_register_intr(pci_t *pci_p) 704 { 705 uint32_t mondo; 706 707 if (pci_p->pci_thermal_interrupt == -1) 708 return (DDI_SUCCESS); 709 710 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 711 pci_p->pci_inos[CBNINTR_THERMAL]); 712 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 713 714 VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_THERMAL], 715 cb_thermal_intr, (caddr_t)pci_p->pci_cb_p, NULL) == 0); 716 717 return (PCI_ATTACH_RETCODE(PCI_CB_OBJ, PCI_OBJ_INTR_ADD, DDI_SUCCESS)); 718 } 719 720 void 721 cb_enable_intr(pci_t *pci_p) 722 { 723 if (pci_p->pci_thermal_interrupt != -1) 724 cb_enable_nintr(pci_p, CBNINTR_THERMAL); 725 } 726 727 uint64_t 728 cb_ino_to_map_pa(cb_t *cb_p, ib_ino_t ino) 729 { 730 return (cb_p->cb_map_pa + ((ino & 0x1f) << 3)); 731 } 732 733 uint64_t 734 cb_ino_to_clr_pa(cb_t *cb_p, ib_ino_t ino) 735 { 736 return (cb_p->cb_clr_pa + ((ino & 0x1f) << 3)); 737 } 738 739 /* 740 * allow removal of exported/shared thermal interrupt 741 */ 742 int 743 cb_remove_xintr(pci_t *pci_p, dev_info_t *dip, dev_info_t *rdip, 744 ib_ino_t ino, ib_mondo_t mondo) 745 { 746 if (ino != pci_p->pci_inos[CBNINTR_THERMAL]) 747 return (DDI_FAILURE); 748 749 cb_disable_nintr(pci_p->pci_cb_p, CBNINTR_THERMAL, IB_INTR_WAIT); 750 rem_ivintr(mondo, NULL); 751 752 DEBUG1(DBG_R_INTX, dip, "remove xintr %x\n", ino); 753 return (DDI_SUCCESS); 754 } 755 756 int 757 pci_ecc_add_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 758 { 759 uint32_t mondo; 760 761 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 762 pci_p->pci_inos[inum]); 763 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 764 765 VERIFY(add_ivintr(mondo, pci_pil[inum], ecc_intr, 766 (caddr_t)eii_p, NULL) == 0); 767 768 return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, DDI_SUCCESS)); 769 } 770 771 void 772 pci_ecc_rem_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 773 { 774 uint32_t mondo; 775 776 mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 777 pci_p->pci_inos[inum]); 778 mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 779 780 rem_ivintr(mondo, NULL); 781 } 782 783 static int pbm_has_pass_1_cheerio(pci_t *pci_p); 784 785 void 786 pbm_configure(pbm_t *pbm_p) 787 { 788 pci_t *pci_p = pbm_p->pbm_pci_p; 789 cb_t *cb_p = pci_p->pci_cb_p; 790 dev_info_t *dip = pci_p->pci_dip; 791 int instance = ddi_get_instance(dip); 792 uint32_t mask = 1 << instance; 793 uint64_t l; 794 uint16_t s = 0; 795 796 /* 797 * Workarounds for hardware bugs: 798 * 799 * bus parking 800 * 801 * Pass 2 psycho parts have a bug that requires bus 802 * parking to be disabled. 803 * 804 * Pass 1 cheerio parts have a bug which prevents them 805 * from working on a PBM with bus parking enabled. 806 * 807 * rerun disable 808 * 809 * Pass 1 and 2 psycho's require that the rerun's be 810 * enabled. 811 * 812 * retry limit 813 * 814 * For pass 1 and pass 2 psycho parts we disable the 815 * retry limit. This is because the limit of 16 seems 816 * too restrictive for devices that are children of pci 817 * to pci bridges. For pass 3 this limit will be 64. 818 * 819 * DMA write/PIO read sync 820 * 821 * For pass 2 psycho, the disable this feature. 822 */ 823 l = lddphysio(cb_p->cb_base_pa + PSYCHO_CB_CONTROL_STATUS_REG_OFFSET); 824 l &= PSYCHO_CB_CONTROL_STATUS_VER; 825 l >>= PSYCHO_CB_CONTROL_STATUS_VER_SHIFT; 826 827 DEBUG2(DBG_ATTACH, dip, "cb_create: ver=%d, mask=%x\n", l, mask); 828 pci_rerun_disable = (uint32_t)-1; 829 830 switch (l) { 831 case 0: 832 DEBUG0(DBG_ATTACH, dip, "cb_create: psycho pass 1\n"); 833 if (!pci_disable_pass1_workarounds) { 834 if (pbm_has_pass_1_cheerio(pci_p)) 835 pci_bus_parking_enable &= ~mask; 836 pci_rerun_disable &= ~mask; 837 pci_retry_disable |= mask; 838 } 839 break; 840 case 1: 841 if (!pci_disable_pass2_workarounds) { 842 pci_bus_parking_enable &= ~mask; 843 pci_rerun_disable &= ~mask; 844 pci_retry_disable |= mask; 845 pci_dwsync_disable |= mask; 846 } 847 break; 848 case 2: 849 if (!pci_disable_pass3_workarounds) { 850 pci_dwsync_disable |= mask; 851 if (pbm_has_pass_1_cheerio(pci_p)) 852 pci_bus_parking_enable &= ~mask; 853 } 854 break; 855 case 3: 856 if (!pci_disable_plus_workarounds) { 857 pci_dwsync_disable |= mask; 858 if (pbm_has_pass_1_cheerio(pci_p)) 859 pci_bus_parking_enable &= ~mask; 860 } 861 break; 862 default: 863 if (!pci_disable_default_workarounds) { 864 pci_dwsync_disable |= mask; 865 if (pbm_has_pass_1_cheerio(pci_p)) 866 pci_bus_parking_enable &= ~mask; 867 } 868 break; 869 } 870 871 /* 872 * Clear any PBM errors. 873 */ 874 l = (PSYCHO_PCI_AFSR_E_MASK << PSYCHO_PCI_AFSR_PE_SHIFT) | 875 (PSYCHO_PCI_AFSR_E_MASK << PSYCHO_PCI_AFSR_SE_SHIFT); 876 *pbm_p->pbm_async_flt_status_reg = l; 877 878 /* 879 * Clear error bits in configuration status register. 880 */ 881 s = PCI_STAT_PERROR | PCI_STAT_S_PERROR | 882 PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB | 883 PCI_STAT_S_TARG_AB | PCI_STAT_S_PERROR; 884 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s); 885 pbm_p->pbm_config_header->ch_status_reg = s; 886 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg==%x\n", 887 pbm_p->pbm_config_header->ch_status_reg); 888 889 l = *pbm_p->pbm_ctrl_reg; /* save control register state */ 890 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg==%llx\n", l); 891 892 /* 893 * See if any SERR# signals are asserted. We'll clear them later. 894 */ 895 if (l & COMMON_PCI_CTRL_SERR) 896 cmn_err(CE_WARN, "%s%d: SERR asserted on pci bus\n", 897 ddi_driver_name(dip), instance); 898 899 /* 900 * Determine if PCI bus is running at 33 or 66 mhz. 901 */ 902 if (l & COMMON_PCI_CTRL_SPEED) 903 pbm_p->pbm_speed = PBM_SPEED_66MHZ; 904 else 905 pbm_p->pbm_speed = PBM_SPEED_33MHZ; 906 DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n", 907 pbm_p->pbm_speed == PBM_SPEED_66MHZ ? 66 : 33); 908 909 /* 910 * Enable error interrupts. 911 */ 912 if (pci_error_intr_enable & mask) 913 l |= PSYCHO_PCI_CTRL_ERR_INT_EN; 914 else 915 l &= ~PSYCHO_PCI_CTRL_ERR_INT_EN; 916 917 /* 918 * Disable pci streaming byte errors and error interrupts. 919 */ 920 pci_sbh_error_intr_enable &= ~mask; 921 l &= ~PSYCHO_PCI_CTRL_SBH_INT_EN; 922 923 /* 924 * Enable/disable bus parking. 925 */ 926 if ((pci_bus_parking_enable & mask) && 927 !ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 928 "no-bus-parking")) 929 l |= PSYCHO_PCI_CTRL_ARB_PARK; 930 else 931 l &= ~PSYCHO_PCI_CTRL_ARB_PARK; 932 933 /* 934 * Enable arbitration. 935 */ 936 if (pci_p->pci_side == B) 937 l = (l & ~PSYCHO_PCI_CTRL_ARB_EN_MASK) | pci_b_arb_enable; 938 else 939 l = (l & ~PSYCHO_PCI_CTRL_ARB_EN_MASK) | pci_a_arb_enable; 940 941 /* 942 * Make sure SERR is clear 943 */ 944 l |= COMMON_PCI_CTRL_SERR; 945 946 /* 947 * Make sure power management interrupt is disabled. 948 */ 949 l &= ~PSYCHO_PCI_CTRL_WAKEUP_EN; 950 951 #ifdef _STARFIRE 952 /* 953 * Hack to determine whether we do Starfire special handling 954 * For starfire, we simply program a constant odd-value 955 * (0x1D) in the MID field. 956 * 957 * Zero out the MID field before ORing. We leave the LSB of 958 * the MID field intact since we cannot have a zero (even) 959 * MID value. 960 */ 961 l &= 0xFF0FFFFFFFFFFFFFULL; 962 l |= 0x1DULL << 51; 963 964 /* 965 * Program in the Interrupt Group Number. Here we have to 966 * convert the starfire 7bit upaid into a 5bit value. 967 */ 968 l |= (uint64_t)STARFIRE_UPAID2HWIGN(pbm_p->pbm_pci_p->pci_id) 969 << COMMON_CB_CONTROL_STATUS_IGN_SHIFT; 970 #endif /* _STARFIRE */ 971 972 /* 973 * Now finally write the control register with the appropriate value. 974 */ 975 DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 976 *pbm_p->pbm_ctrl_reg = l; 977 978 /* 979 * Allow the diag register to be set based upon variable that 980 * can be configured via /etc/system. 981 */ 982 l = *pbm_p->pbm_diag_reg; 983 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg==%llx\n", l); 984 if (pci_retry_disable & mask) 985 l |= COMMON_PCI_DIAG_DIS_RETRY; 986 if (pci_retry_enable & mask) 987 l &= ~COMMON_PCI_DIAG_DIS_RETRY; 988 if (pci_intsync_disable & mask) 989 l |= COMMON_PCI_DIAG_DIS_INTSYNC; 990 else 991 l &= ~COMMON_PCI_DIAG_DIS_INTSYNC; 992 if (pci_dwsync_disable & mask) 993 l |= PSYCHO_PCI_DIAG_DIS_DWSYNC; 994 else 995 l &= ~PSYCHO_PCI_DIAG_DIS_DWSYNC; 996 DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 997 *pbm_p->pbm_diag_reg = l; 998 999 /* 1000 * Enable SERR# and parity reporting via command register. 1001 */ 1002 s = pci_perr_enable & mask ? PCI_COMM_PARITY_DETECT : 0; 1003 s |= pci_serr_enable & mask ? PCI_COMM_SERR_ENABLE : 0; 1004 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s); 1005 pbm_p->pbm_config_header->ch_command_reg = s; 1006 DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg==%x\n", 1007 pbm_p->pbm_config_header->ch_command_reg); 1008 1009 /* 1010 * The current versions of the obp are suppose to set the latency 1011 * timer register but do not. Bug 1234181 is open against this 1012 * problem. Until this bug is fixed we check to see if the obp 1013 * has attempted to set the latency timer register by checking 1014 * for the existence of a "latency-timer" property. 1015 */ 1016 if (pci_set_latency_timer_register) { 1017 DEBUG1(DBG_ATTACH, dip, 1018 "pbm_configure: set psycho latency timer to %x\n", 1019 pci_latency_timer); 1020 pbm_p->pbm_config_header->ch_latency_timer_reg = 1021 pci_latency_timer; 1022 } 1023 1024 (void) ndi_prop_update_int(DDI_DEV_T_ANY, dip, "latency-timer", 1025 (int)pbm_p->pbm_config_header->ch_latency_timer_reg); 1026 } 1027 1028 uint_t 1029 pbm_disable_pci_errors(pbm_t *pbm_p) 1030 { 1031 pci_t *pci_p = pbm_p->pbm_pci_p; 1032 ib_t *ib_p = pci_p->pci_ib_p; 1033 1034 /* 1035 * Disable error and streaming byte hole interrupts via the 1036 * PBM control register. 1037 */ 1038 *pbm_p->pbm_ctrl_reg &= 1039 ~(PSYCHO_PCI_CTRL_ERR_INT_EN | PSYCHO_PCI_CTRL_SBH_INT_EN); 1040 1041 /* 1042 * Disable error interrupts via the interrupt mapping register. 1043 */ 1044 ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_NOWAIT); 1045 return (BF_NONE); 1046 } 1047 1048 /*ARGSUSED*/ 1049 uint64_t 1050 pci_sc_configure(pci_t *pci_p) 1051 { 1052 return (0); 1053 } 1054 1055 /*ARGSUSED*/ 1056 void 1057 pci_pbm_dma_sync(pbm_t *pbm_p, ib_ino_t ino) 1058 { 1059 uint64_t pa = pbm_p->pbm_sync_reg_pa; 1060 if (pa) 1061 (void) lddphysio(pa); /* Load from Sync Register */ 1062 } 1063 1064 /*ARGSUSED*/ 1065 dvma_context_t 1066 pci_iommu_get_dvma_context(iommu_t *iommu_p, dvma_addr_t dvma_pg_index) 1067 { 1068 ASSERT(0); 1069 return (0); 1070 } 1071 1072 /*ARGSUSED*/ 1073 void 1074 pci_iommu_free_dvma_context(iommu_t *iommu_p, dvma_context_t ctx) 1075 { 1076 ASSERT(0); 1077 } 1078 1079 void 1080 pci_iommu_config(iommu_t *iommu_p, uint64_t iommu_ctl, uint64_t cfgpa) 1081 { 1082 volatile uint64_t *pbm_csr_p = (volatile uint64_t *) 1083 get_pbm_reg_base(iommu_p->iommu_pci_p); 1084 volatile uint64_t pbm_ctl = *pbm_csr_p; 1085 1086 volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg; 1087 volatile uint64_t tsb_bar_val = iommu_p->iommu_tsb_paddr; 1088 volatile uint64_t *tsb_bar_p = iommu_p->iommu_tsb_base_addr_reg; 1089 1090 DEBUG2(DBG_ATTACH, iommu_p->iommu_pci_p->pci_dip, 1091 "\npci_iommu_config: pbm_csr_p=%016llx pbm_ctl=%016llx", 1092 pbm_csr_p, pbm_ctl); 1093 DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 1094 "\n\tiommu_ctl_p=%016llx iommu_ctl=%016llx", 1095 iommu_ctl_p, iommu_ctl); 1096 DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 1097 "\n\tcfgpa=%016llx tsb_bar_val=%016llx", cfgpa, tsb_bar_val); 1098 1099 if (!cfgpa) 1100 goto reprog; 1101 1102 /* disable PBM arbiters - turn off bits 0-7 */ 1103 *pbm_csr_p = (pbm_ctl >> 8) << 8; 1104 1105 /* make sure we own the bus by reading any child device config space */ 1106 (void) ldphysio(cfgpa); /* also flushes the prev write */ 1107 reprog: 1108 *tsb_bar_p = tsb_bar_val; 1109 *iommu_ctl_p = iommu_ctl; 1110 1111 *pbm_csr_p = pbm_ctl; /* re-enable bus arbitration */ 1112 pbm_ctl = *pbm_csr_p; /* flush all prev writes */ 1113 } 1114 1115 int 1116 pci_sc_ctx_inv(dev_info_t *dip, sc_t *sc_p, ddi_dma_impl_t *mp) 1117 { 1118 ASSERT(0); 1119 return (DDI_FAILURE); 1120 } 1121 1122 void 1123 pci_cb_setup(pci_t *pci_p) 1124 { 1125 uint64_t csr, csr_pa, pa; 1126 cb_t *cb_p = pci_p->pci_cb_p; 1127 1128 /* cb_p->cb_node_id = 0; */ 1129 cb_p->cb_ign = PCI_ID_TO_IGN(pci_p->pci_id); 1130 pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[0]); 1131 cb_p->cb_base_pa = pa = pa >> (32 - MMU_PAGESHIFT) << 32; 1132 cb_p->cb_map_pa = pa + PSYCHO_IB_OBIO_INTR_MAP_REG_OFFSET; 1133 cb_p->cb_clr_pa = pa + PSYCHO_IB_OBIO_CLEAR_INTR_REG_OFFSET; 1134 cb_p->cb_obsta_pa = pa + COMMON_IB_OBIO_INTR_STATE_DIAG_REG; 1135 1136 csr_pa = pa + PSYCHO_CB_CONTROL_STATUS_REG_OFFSET; 1137 csr = lddphysio(csr_pa); 1138 1139 /* 1140 * Clear any pending address parity errors. 1141 */ 1142 if (csr & COMMON_CB_CONTROL_STATUS_APERR) { 1143 csr |= COMMON_CB_CONTROL_STATUS_APERR; 1144 cmn_err(CE_WARN, "clearing UPA address parity error\n"); 1145 } 1146 csr |= COMMON_CB_CONTROL_STATUS_APCKEN; 1147 csr &= ~COMMON_CB_CONTROL_STATUS_IAP; 1148 stdphysio(csr_pa, csr); 1149 1150 #ifdef _STARFIRE 1151 /* Setup Starfire interrupt target translation */ 1152 pc_ittrans_init(pci_p->pci_id, &cb_p->cb_ittrans_cookie); 1153 #endif /* _STARFIRE */ 1154 1155 } 1156 1157 void 1158 pci_ecc_setup(ecc_t *ecc_p) 1159 { 1160 ecc_p->ecc_ue.ecc_errpndg_mask = 0; 1161 ecc_p->ecc_ue.ecc_offset_mask = PSYCHO_ECC_UE_AFSR_DW_OFFSET; 1162 ecc_p->ecc_ue.ecc_offset_shift = PSYCHO_ECC_UE_AFSR_DW_OFFSET_SHIFT; 1163 ecc_p->ecc_ue.ecc_size_log2 = 3; 1164 1165 ecc_p->ecc_ce.ecc_errpndg_mask = 0; 1166 ecc_p->ecc_ce.ecc_offset_mask = PSYCHO_ECC_CE_AFSR_DW_OFFSET; 1167 ecc_p->ecc_ce.ecc_offset_shift = PSYCHO_ECC_CE_AFSR_DW_OFFSET_SHIFT; 1168 ecc_p->ecc_ce.ecc_size_log2 = 3; 1169 } 1170 1171 /* 1172 * overwrite dvma end address (only on virtual-dma systems) 1173 * initialize tsb size 1174 * reset context bits 1175 * return: IOMMU CSR bank base address (VA) 1176 */ 1177 uintptr_t 1178 pci_iommu_setup(iommu_t *iommu_p) 1179 { 1180 pci_dvma_range_prop_t *dvma_prop; 1181 int dvma_prop_len; 1182 1183 pci_t *pci_p = iommu_p->iommu_pci_p; 1184 dev_info_t *dip = pci_p->pci_dip; 1185 uint_t tsb_size = iommu_tsb_cookie_to_size(pci_p->pci_tsb_cookie); 1186 uint_t tsb_size_prop; 1187 1188 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1189 "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) != 1190 DDI_PROP_SUCCESS) 1191 goto tsb_done; 1192 1193 if (dvma_prop_len != sizeof (pci_dvma_range_prop_t)) { 1194 cmn_err(CE_WARN, "%s%d: invalid virtual-dma property", 1195 ddi_driver_name(dip), ddi_get_instance(dip)); 1196 goto tsb_end; 1197 } 1198 iommu_p->iommu_dvma_end = dvma_prop->dvma_base + 1199 (dvma_prop->dvma_len - 1); 1200 tsb_size_prop = IOMMU_BTOP(dvma_prop->dvma_len) * sizeof (uint64_t); 1201 tsb_size = MIN(tsb_size_prop, tsb_size); 1202 tsb_end: 1203 kmem_free(dvma_prop, dvma_prop_len); 1204 tsb_done: 1205 iommu_p->iommu_tsb_size = iommu_tsb_size_encode(tsb_size); 1206 1207 if (CHIP_TYPE(pci_p) != PCI_CHIP_HUMMINGBIRD) 1208 pci_preserve_iommu_tsb = 0; 1209 1210 /* 1211 * Psycho has no context support. 1212 */ 1213 iommu_p->iommu_ctx_bitmap = NULL; 1214 iommu_p->iommu_flush_ctx_reg = NULL; 1215 pci_use_contexts = 0; 1216 pci_sc_use_contexts = 0; 1217 1218 /* 1219 * Determine the virtual address of the register block 1220 * containing the iommu control registers. 1221 */ 1222 return (get_reg_base(pci_p)); 1223 } 1224 1225 /*ARGSUSED*/ 1226 void 1227 pci_iommu_teardown(iommu_t *iommu_p) 1228 { 1229 } 1230 1231 /* The psycho+ PBM reg base is at 1fe.0000.2000 */ 1232 uintptr_t 1233 get_pbm_reg_base(pci_t *pci_p) 1234 { 1235 return ((uintptr_t)(pci_p->pci_address[0] + 1236 (pci_stream_buf_exists ? 0 : PSYCHO_PCI_PBM_REG_BASE))); 1237 } 1238 1239 void 1240 pci_post_uninit_child(pci_t *pci_p) 1241 { 1242 } 1243 1244 void 1245 pci_pbm_setup(pbm_t *pbm_p) 1246 { 1247 pci_t *pci_p = pbm_p->pbm_pci_p; 1248 1249 /* 1250 * Get the base virtual address for the PBM control block. 1251 */ 1252 uintptr_t a = get_pbm_reg_base(pci_p); 1253 1254 /* 1255 * Get the virtual address of the PCI configuration header. 1256 * This should be mapped little-endian. 1257 */ 1258 pbm_p->pbm_config_header = 1259 (config_header_t *)get_config_reg_base(pci_p); 1260 1261 /* 1262 * Get the virtual addresses for control, error and diag 1263 * registers. 1264 */ 1265 pbm_p->pbm_ctrl_reg = (uint64_t *)(a + PSYCHO_PCI_CTRL_REG_OFFSET); 1266 pbm_p->pbm_diag_reg = (uint64_t *)(a + PSYCHO_PCI_DIAG_REG_OFFSET); 1267 pbm_p->pbm_async_flt_status_reg = 1268 (uint64_t *)(a + PSYCHO_PCI_ASYNC_FLT_STATUS_REG_OFFSET); 1269 pbm_p->pbm_async_flt_addr_reg = 1270 (uint64_t *)(a + PSYCHO_PCI_ASYNC_FLT_ADDR_REG_OFFSET); 1271 1272 if (CHIP_TYPE(pci_p) >= PCI_CHIP_SABRE) 1273 pbm_p->pbm_sync_reg_pa = 1274 pci_p->pci_cb_p->cb_base_pa + DMA_WRITE_SYNC_REG; 1275 } 1276 1277 /*ARGSUSED*/ 1278 void 1279 pci_pbm_teardown(pbm_t *pbm_p) 1280 { 1281 } 1282 1283 void 1284 pci_sc_setup(sc_t *sc_p) 1285 { 1286 pci_t *pci_p = sc_p->sc_pci_p; 1287 1288 /* 1289 * Determine the virtual addresses of the streaming cache 1290 * control/status and flush registers. 1291 */ 1292 uintptr_t a = get_pbm_reg_base(pci_p); 1293 sc_p->sc_ctrl_reg = (uint64_t *)(a + PSYCHO_SC_CTRL_REG_OFFSET); 1294 sc_p->sc_invl_reg = (uint64_t *)(a + PSYCHO_SC_INVL_REG_OFFSET); 1295 sc_p->sc_sync_reg = (uint64_t *)(a + PSYCHO_SC_SYNC_REG_OFFSET); 1296 1297 /* 1298 * Determine the virtual addresses of the streaming cache 1299 * diagnostic access registers. 1300 */ 1301 a = get_reg_base(pci_p); 1302 if (pci_p->pci_bus_range.lo != 0) { 1303 sc_p->sc_data_diag_acc = (uint64_t *) 1304 (a + PSYCHO_SC_A_DATA_DIAG_OFFSET); 1305 sc_p->sc_tag_diag_acc = (uint64_t *) 1306 (a + PSYCHO_SC_A_TAG_DIAG_OFFSET); 1307 sc_p->sc_ltag_diag_acc = (uint64_t *) 1308 (a + PSYCHO_SC_A_LTAG_DIAG_OFFSET); 1309 } else { 1310 sc_p->sc_data_diag_acc = (uint64_t *) 1311 (a + PSYCHO_SC_B_DATA_DIAG_OFFSET); 1312 sc_p->sc_tag_diag_acc = (uint64_t *) 1313 (a + PSYCHO_SC_B_TAG_DIAG_OFFSET); 1314 sc_p->sc_ltag_diag_acc = (uint64_t *) 1315 (a + PSYCHO_SC_B_LTAG_DIAG_OFFSET); 1316 } 1317 } 1318 1319 int 1320 pci_get_numproxy(dev_info_t *dip) 1321 { 1322 return (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1323 "#upa-interrupt-proxies", 1)); 1324 } 1325 1326 int 1327 pci_get_portid(dev_info_t *dip) 1328 { 1329 return (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1330 "upa-portid", -1)); 1331 } 1332 1333 /* 1334 * pbm_has_pass_1_cheerio 1335 * 1336 * 1337 * Given a PBM soft state pointer, this routine scans it child nodes 1338 * to see if one is a pass 1 cheerio. 1339 * 1340 * return value: 1 if pass 1 cheerio is found, 0 otherwise 1341 */ 1342 static int 1343 pbm_has_pass_1_cheerio(pci_t *pci_p) 1344 { 1345 dev_info_t *cdip; 1346 int found = 0; 1347 char *s; 1348 int rev; 1349 1350 cdip = ddi_get_child(pci_p->pci_dip); 1351 while (cdip != NULL && found == 0) { 1352 s = ddi_get_name(cdip); 1353 if (strcmp(s, "ebus") == 0 || strcmp(s, "pci108e,1000") == 0) { 1354 rev = 1355 ddi_getprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 1356 "revision-id", 0); 1357 if (rev == 0) 1358 found = 1; 1359 } 1360 cdip = ddi_get_next_sibling(cdip); 1361 } 1362 return (found); 1363 } 1364 1365 /* 1366 * Psycho Performance Events. 1367 */ 1368 pci_kev_mask_t 1369 psycho_pci_events[] = { 1370 {"dvma_stream_rd_a", 0x0}, {"dvma_stream_wr_a", 0x1}, 1371 {"dvma_const_rd_a", 0x2}, {"dvma_const_wr_a", 0x3}, 1372 {"dvma_stream_buf_mis_a", 0x4}, {"dvma_cycles_a", 0x5}, 1373 {"dvma_wd_xfr_a", 0x6}, {"pio_cycles_a", 0x7}, 1374 {"dvma_stream_rd_b", 0x8}, {"dvma_stream_wr_b", 0x9}, 1375 {"dvma_const_rd_b", 0xa}, {"dvma_const_wr_b", 0xb}, 1376 {"dvma_stream_buf_mis_b", 0xc}, {"dvma_cycles_b", 0xd}, 1377 {"dvma_wd_xfr_b", 0xe}, {"pio_cycles_b", 0xf}, 1378 {"dvma_tlb_misses", 0x10}, {"interrupts", 0x11}, 1379 {"upa_inter_nack", 0x12}, {"pio_reads", 0x13}, 1380 {"pio_writes", 0x14}, {"merge_buffer", 0x15}, 1381 {"dma_tbwalk_a", 0x16}, {"dma_stc_a", 0x17}, 1382 {"dma_tbwalk_b", 0x18}, {"dma_stc_b", 0x19}, 1383 {"clear_pic", 0x1f} 1384 }; 1385 1386 /* 1387 * Create the picN kstat's. 1388 */ 1389 void 1390 pci_kstat_init() 1391 { 1392 pci_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 1393 KM_NOSLEEP); 1394 1395 if (pci_name_kstat == NULL) { 1396 cmn_err(CE_WARN, "pcipsy : no space for kstat\n"); 1397 } else { 1398 pci_name_kstat->pic_no_evs = 1399 sizeof (psycho_pci_events) / sizeof (pci_kev_mask_t); 1400 pci_name_kstat->pic_shift[0] = PSYCHO_SHIFT_PIC0; 1401 pci_name_kstat->pic_shift[1] = PSYCHO_SHIFT_PIC1; 1402 pci_create_name_kstat("pcip", 1403 pci_name_kstat, psycho_pci_events); 1404 } 1405 } 1406 1407 /* 1408 * Called from _fini() 1409 */ 1410 void 1411 pci_kstat_fini() 1412 { 1413 if (pci_name_kstat != NULL) { 1414 pci_delete_name_kstat(pci_name_kstat); 1415 kmem_free(pci_name_kstat, sizeof (pci_ksinfo_t)); 1416 pci_name_kstat = NULL; 1417 } 1418 } 1419 1420 /* ARGSUSED */ 1421 void 1422 pci_add_pci_kstat(pci_t *pci_p) 1423 { 1424 } 1425 1426 /* ARGSUSED */ 1427 void 1428 pci_rem_pci_kstat(pci_t *pci_p) 1429 { 1430 } 1431 1432 /* 1433 * Create the performance 'counters' kstat. 1434 */ 1435 void 1436 pci_add_upstream_kstat(pci_t *pci_p) 1437 { 1438 pci_common_t *cmn_p = pci_p->pci_common_p; 1439 pci_cntr_pa_t *cntr_pa_p = &cmn_p->pci_cmn_uks_pa; 1440 uint64_t regbase = va_to_pa((void *)get_reg_base(pci_p)); 1441 1442 cntr_pa_p->pcr_pa = regbase + PSYCHO_PERF_PCR_OFFSET; 1443 cntr_pa_p->pic_pa = regbase + PSYCHO_PERF_PIC_OFFSET; 1444 cmn_p->pci_common_uksp = pci_create_cntr_kstat(pci_p, "pcip", 1445 NUM_OF_PICS, pci_cntr_kstat_pa_update, cntr_pa_p); 1446 } 1447 1448 /* 1449 * Extract the drivers binding name to identify which chip 1450 * we're binding to. Whenever a new bus bridge is created, the driver alias 1451 * entry should be added here to identify the device if needed. If a device 1452 * isn't added, the identity defaults to PCI_CHIP_UNIDENTIFIED. 1453 */ 1454 static uint32_t 1455 pci_identity_init(pci_t *pci_p) 1456 { 1457 dev_info_t *dip = pci_p->pci_dip; 1458 char *name = ddi_binding_name(dip); 1459 1460 if (strcmp(name, "pci108e,8000") == 0) 1461 return (CHIP_ID(PCI_CHIP_PSYCHO, 0x00, 0x00)); 1462 if (strcmp(name, "pci108e,a000") == 0) 1463 return (CHIP_ID(PCI_CHIP_SABRE, 0x00, 0x00)); 1464 if (strcmp(name, "pci108e,a001") == 0) 1465 return (CHIP_ID(PCI_CHIP_HUMMINGBIRD, 0x00, 0x00)); 1466 cmn_err(CE_CONT, "?%s%d:using default chip identity\n", 1467 ddi_driver_name(dip), ddi_get_instance(dip)); 1468 return (CHIP_ID(PCI_CHIP_PSYCHO, 0x00, 0x00)); 1469 } 1470 1471 /*ARGSUSED*/ 1472 void 1473 pci_post_init_child(pci_t *pci_p, dev_info_t *child) 1474 { 1475 } 1476 1477 /*ARGSUSED*/ 1478 int 1479 pci_pbm_add_intr(pci_t *pci_p) 1480 { 1481 return (DDI_SUCCESS); 1482 } 1483 1484 /*ARGSUSED*/ 1485 void 1486 pci_pbm_rem_intr(pci_t *pci_p) 1487 { 1488 } 1489 1490 /*ARGSUSED*/ 1491 void 1492 pci_pbm_suspend(pci_t *pci_p) 1493 { 1494 } 1495 1496 /*ARGSUSED*/ 1497 void 1498 pci_pbm_resume(pci_t *pci_p) 1499 { 1500 } 1501 1502 /* 1503 * pcipsy error handling 101: 1504 * 1505 * The various functions below are responsible for error handling. Given 1506 * a particular error, they must gather the appropriate state, report all 1507 * errors with correct payload, and attempt recovery where ever possible. 1508 * 1509 * Recovery in the context of this driver is being able notify a leaf device 1510 * of the failed transaction. This leaf device may either be the master or 1511 * target for this transaction and may have already received an error 1512 * notification via a PCI interrupt. Notification is done via DMA and access 1513 * handles. If we capture an address for the transaction then we can map it 1514 * to a handle(if the leaf device is fma-compliant) and fault the handle as 1515 * well as call the device driver registered callback. 1516 * 1517 * The hardware can either interrupt or trap upon detection of an error, in 1518 * some rare cases it also causes a fatal reset. 1519 * 1520 * pbm_error_intr() and ecc_intr() are responsible for PCI Block Module 1521 * errors(generic PCI + bridge specific) and ECC errors, respectively. They 1522 * are common between pcisch and pcipsy and therefore exist in pci_pbm.c and 1523 * pci_ecc.c. To support error handling certain chip specific handlers 1524 * must exist and they are defined below. 1525 * 1526 * cpu_deferred_error() and cpu_async_error(), handle the traps that may 1527 * have originated from IO space. They call into the registered IO callbacks 1528 * to report and handle errors that may have caused the trap. 1529 * 1530 * pci_pbm_err_handler() is called by pbm_error_intr() or pci_err_callback() 1531 * (generic fma callback for pcipsy/pcisch, pci_fm.c). pci_err_callback() is 1532 * called when the CPU has trapped because of a possible IO error(TO/BERR/UE). 1533 * It will call pci_pbm_err_handler() to report and handle all PCI/PBM/IOMMU 1534 * related errors which are detected by the chip. 1535 * 1536 * pci_pbm_err_handler() calls a generic interface pbm_afsr_report()(pci_pbm.c) 1537 * to report the pbm specific errors and attempt to map the failed address 1538 * (if captured) to a device instance. pbm_afsr_report() calls a chip specific 1539 * interface to interpret the afsr bits pci_pbm_classify()(pcisch.c/pcipsy.c). 1540 * 1541 * ecc_err_handler()(pci_ecc.c) also calls a chip specific interface to 1542 * interpret the afsr, pci_ecc_classify(). ecc_err_handler() also calls 1543 * pci_pbm_err_handler() and ndi_fm_handler_dispatch() to log any related 1544 * errors. 1545 * 1546 * To make sure that the trap code and the interrupt code are not going 1547 * to step on each others toes we have a per chip pci_fm_mutex. This also 1548 * makes it necessary for us to be cautious while we are at a high PIL, so 1549 * that we do not cause a subsequent trap that causes us to hang. 1550 * 1551 * The attempt to commonize code was meant to keep in line with the current 1552 * pci driver implementation and it was not meant to confuse. If you are 1553 * confused then don't worry, I was too. 1554 */ 1555 1556 /* 1557 * For Psycho, a UE is always fatal, except if it is a translation error on a 1558 * Darwin platform. We ignore these because they do not cause data corruption. 1559 */ 1560 int 1561 ecc_ue_is_fatal(struct async_flt *ecc) 1562 { 1563 return (((uint_t)(ecc->flt_stat >> SABRE_UE_AFSR_PDTE_SHIFT) & 1564 SABRE_UE_AFSR_E_PDTE) == 0); 1565 } 1566 1567 /* 1568 * pci_ecc_classify, called by ecc_handler to classify ecc errors 1569 * and determine if we should panic or not. 1570 * 1571 * Note that it is possible yet extremely rare for more than one 1572 * primary error bit to be set. We classify the ecc error based 1573 * on the first set bit that is found. 1574 */ 1575 void 1576 pci_ecc_classify(uint64_t err, ecc_errstate_t *ecc_err_p) 1577 { 1578 struct async_flt *ecc = &ecc_err_p->ecc_aflt; 1579 pci_common_t *cmn_p = ecc_err_p->ecc_ii_p.ecc_p->ecc_pci_cmn_p; 1580 1581 ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1582 1583 ecc_err_p->ecc_bridge_type = PCI_BRIDGE_TYPE(cmn_p); 1584 /* 1585 * Get the parent bus id that caused the error. 1586 */ 1587 ecc_err_p->ecc_dev_id = (ecc_err_p->ecc_afsr & PSYCHO_ECC_UE_AFSR_ID) 1588 >> PSYCHO_ECC_UE_AFSR_ID_SHIFT; 1589 /* 1590 * Determine the doubleword offset of the error. 1591 */ 1592 ecc_err_p->ecc_dw_offset = (ecc_err_p->ecc_afsr & 1593 PSYCHO_ECC_UE_AFSR_DW_OFFSET) 1594 >> PSYCHO_ECC_UE_AFSR_DW_OFFSET_SHIFT; 1595 /* 1596 * Determine the primary error type. 1597 */ 1598 if (err & COMMON_ECC_UE_AFSR_E_PIO) { 1599 if (ecc_err_p->ecc_ii_p.ecc_type == CBNINTR_UE) { 1600 if (ecc_err_p->ecc_pri) { 1601 ecc->flt_erpt_class = PCI_ECC_PIO_UE; 1602 } else { 1603 ecc->flt_erpt_class = PCI_ECC_SEC_PIO_UE; 1604 } 1605 ecc->flt_panic = ecc_ue_is_fatal(&ecc_err_p->ecc_aflt); 1606 } else { 1607 ecc->flt_erpt_class = ecc_err_p->ecc_pri ? 1608 PCI_ECC_PIO_CE : PCI_ECC_SEC_PIO_CE; 1609 return; 1610 } 1611 } else if (err & COMMON_ECC_UE_AFSR_E_DRD) { 1612 if (ecc_err_p->ecc_ii_p.ecc_type == CBNINTR_UE) { 1613 if (ecc_err_p->ecc_pri) { 1614 ecc->flt_erpt_class = PCI_ECC_DRD_UE; 1615 } else { 1616 ecc->flt_erpt_class = PCI_ECC_SEC_DRD_UE; 1617 } 1618 ecc->flt_panic = ecc_ue_is_fatal(&ecc_err_p->ecc_aflt); 1619 } else { 1620 ecc->flt_erpt_class = ecc_err_p->ecc_pri ? 1621 PCI_ECC_DRD_CE : PCI_ECC_SEC_DRD_CE; 1622 return; 1623 } 1624 } else if (err & COMMON_ECC_UE_AFSR_E_DWR) { 1625 if (ecc_err_p->ecc_ii_p.ecc_type == CBNINTR_UE) { 1626 if (ecc_err_p->ecc_pri) { 1627 ecc->flt_erpt_class = PCI_ECC_DWR_UE; 1628 } else { 1629 ecc->flt_erpt_class = PCI_ECC_SEC_DWR_UE; 1630 } 1631 ecc->flt_panic = ecc_ue_is_fatal(&ecc_err_p->ecc_aflt); 1632 } else { 1633 ecc->flt_erpt_class = ecc_err_p->ecc_pri ? 1634 PCI_ECC_DWR_CE : PCI_ECC_SEC_DWR_CE; 1635 return; 1636 } 1637 } 1638 } 1639 1640 ushort_t 1641 pci_ecc_get_synd(uint64_t afsr) 1642 { 1643 return ((ushort_t)((afsr & PSYCHO_ECC_CE_AFSR_SYND) 1644 >> PSYCHO_ECC_CE_AFSR_SYND_SHIFT)); 1645 } 1646 1647 /* 1648 * pci_pbm_classify, called by pbm_afsr_report to classify piow afsr. 1649 */ 1650 int 1651 pci_pbm_classify(pbm_errstate_t *pbm_err_p) 1652 { 1653 uint32_t e; 1654 int nerr = 0; 1655 char **tmp_class; 1656 1657 if (pbm_err_p->pbm_pri) { 1658 tmp_class = &pbm_err_p->pbm_pci.pci_err_class; 1659 e = PBM_AFSR_TO_PRIERR(pbm_err_p->pbm_afsr); 1660 pbm_err_p->pbm_log = FM_LOG_PCI; 1661 } else { 1662 tmp_class = &pbm_err_p->pbm_err_class; 1663 e = PBM_AFSR_TO_SECERR(pbm_err_p->pbm_afsr); 1664 pbm_err_p->pbm_log = FM_LOG_PBM; 1665 } 1666 1667 if (e & PSYCHO_PCI_AFSR_E_MA) { 1668 *tmp_class = pbm_err_p->pbm_pri ? PCI_MA : PCI_SEC_MA; 1669 nerr++; 1670 } 1671 if (e & PSYCHO_PCI_AFSR_E_TA) { 1672 *tmp_class = pbm_err_p->pbm_pri ? PCI_REC_TA : PCI_SEC_REC_TA; 1673 nerr++; 1674 } 1675 if (e & PSYCHO_PCI_AFSR_E_RTRY) { 1676 pbm_err_p->pbm_err_class = pbm_err_p->pbm_pri ? 1677 PCI_PBM_RETRY : PCI_SEC_PBM_RETRY; 1678 pbm_err_p->pbm_log = FM_LOG_PBM; 1679 nerr++; 1680 } 1681 if (e & PSYCHO_PCI_AFSR_E_PERR) { 1682 *tmp_class = pbm_err_p->pbm_pri ? PCI_MDPE : PCI_SEC_MDPE; 1683 nerr++; 1684 } 1685 return (nerr); 1686 } 1687 1688 /* 1689 * Function used to clear PBM/PCI/IOMMU error state after error handling 1690 * is complete. Only clearing error bits which have been logged. Called by 1691 * pci_pbm_err_handler and pci_bus_exit. 1692 */ 1693 static void 1694 pci_clear_error(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 1695 { 1696 pbm_t *pbm_p = pci_p->pci_pbm_p; 1697 1698 ASSERT(MUTEX_HELD(&pbm_p->pbm_pci_p->pci_common_p->pci_fm_mutex)); 1699 1700 *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat; 1701 *pbm_p->pbm_async_flt_status_reg = pbm_err_p->pbm_afsr; 1702 pbm_p->pbm_config_header->ch_status_reg = 1703 pbm_err_p->pbm_pci.pci_cfg_stat; 1704 } 1705 1706 /*ARGSUSED*/ 1707 int 1708 pci_pbm_err_handler(dev_info_t *dip, ddi_fm_error_t *derr, 1709 const void *impl_data, int caller) 1710 { 1711 int fatal = 0; 1712 int nonfatal = 0; 1713 int unknown = 0; 1714 uint32_t prierr, secerr; 1715 pbm_errstate_t pbm_err; 1716 char buf[FM_MAX_CLASS]; 1717 pci_t *pci_p = (pci_t *)impl_data; 1718 pbm_t *pbm_p = pci_p->pci_pbm_p; 1719 int ret = 0; 1720 uint64_t pbm_ctl_stat; 1721 uint16_t pci_cfg_stat; 1722 1723 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1724 pci_pbm_errstate_get(pci_p, &pbm_err); 1725 1726 derr->fme_ena = derr->fme_ena ? derr->fme_ena : 1727 fm_ena_generate(0, FM_ENA_FMT1); 1728 1729 prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr); 1730 secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr); 1731 1732 if (derr->fme_flag == DDI_FM_ERR_EXPECTED) { 1733 if (caller == PCI_TRAP_CALL) { 1734 /* 1735 * For ddi_caut_get treat all events as 1736 * nonfatal. The trampoline will set 1737 * err_ena = 0, err_status = NONFATAL. We only 1738 * really call this function so that pci_clear_error() 1739 * and ndi_fm_handler_dispatch() will get called. 1740 */ 1741 derr->fme_status = DDI_FM_NONFATAL; 1742 nonfatal++; 1743 goto done; 1744 } else { 1745 /* 1746 * For ddi_caut_put treat all events as nonfatal. Here 1747 * we have the handle and can call ndi_fm_acc_err_set(). 1748 */ 1749 derr->fme_status = DDI_FM_NONFATAL; 1750 ndi_fm_acc_err_set(pbm_p->pbm_excl_handle, derr); 1751 nonfatal++; 1752 goto done; 1753 } 1754 } else if (derr->fme_flag == DDI_FM_ERR_PEEK) { 1755 /* 1756 * For ddi_peek treat all events as nonfatal. We only 1757 * really call this function so that pci_clear_error() 1758 * and ndi_fm_handler_dispatch() will get called. 1759 */ 1760 nonfatal++; 1761 goto done; 1762 } else if (derr->fme_flag == DDI_FM_ERR_POKE) { 1763 /* 1764 * For ddi_poke we can treat as nonfatal if the 1765 * following conditions are met : 1766 * 1. Make sure only primary error is MA/TA 1767 * 2. Make sure no secondary error 1768 * 3. check pci config header stat reg to see MA/TA is 1769 * logged. We cannot verify only MA/TA is recorded 1770 * since it gets much more complicated when a 1771 * PCI-to-PCI bridge is present. 1772 */ 1773 if ((prierr == PSYCHO_PCI_AFSR_E_MA) && !secerr && 1774 (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_MAST_AB)) { 1775 nonfatal++; 1776 goto done; 1777 } 1778 if ((prierr == PSYCHO_PCI_AFSR_E_TA) && !secerr && 1779 (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_TARG_AB)) { 1780 nonfatal++; 1781 goto done; 1782 } 1783 } 1784 1785 if (prierr || secerr) { 1786 ret = pbm_afsr_report(dip, derr->fme_ena, &pbm_err); 1787 if (ret == DDI_FM_FATAL) 1788 fatal++; 1789 else 1790 nonfatal++; 1791 } 1792 1793 ret = pci_cfg_report(dip, derr, &pbm_err.pbm_pci, caller, prierr); 1794 if (ret == DDI_FM_FATAL) 1795 fatal++; 1796 else if (ret == DDI_FM_NONFATAL) 1797 nonfatal++; 1798 1799 pbm_ctl_stat = pbm_err.pbm_ctl_stat; 1800 pci_cfg_stat = pbm_err.pbm_pci.pci_cfg_stat; 1801 1802 /* 1803 * PBM Received System Error - During any transaction, or 1804 * at any point on the bus, some device may detect a critical 1805 * error and signal a system error to the system. 1806 */ 1807 if (pbm_ctl_stat & COMMON_PCI_CTRL_SERR) { 1808 /* 1809 * may be expected (master abort from pci-pci bridge during 1810 * poke will generate SERR) 1811 */ 1812 if (derr->fme_flag != DDI_FM_ERR_POKE) { 1813 pbm_err.pbm_pci.pci_err_class = PCI_REC_SERR; 1814 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 1815 PCI_ERROR_SUBCLASS, pbm_err.pbm_pci.pci_err_class); 1816 ddi_fm_ereport_post(dip, buf, derr->fme_ena, 1817 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1818 PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pci_cfg_stat, 1819 PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, 1820 pbm_err.pbm_pci.pci_cfg_comm, PCI_PA, 1821 DATA_TYPE_UINT64, (uint64_t)0, NULL); 1822 } 1823 unknown++; 1824 } 1825 1826 /* Streaming Byte Hole Error */ 1827 if (pbm_ctl_stat & COMMON_PCI_CTRL_SBH_ERR) { 1828 if (pci_panic_on_sbh_errors) 1829 fatal++; 1830 else 1831 nonfatal++; 1832 pbm_err.pbm_err_class = PCI_PSY_SBH; 1833 pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 1834 } 1835 done: 1836 ret = ndi_fm_handler_dispatch(dip, NULL, derr); 1837 if (ret == DDI_FM_FATAL) { 1838 fatal++; 1839 } else if (ret == DDI_FM_NONFATAL) { 1840 nonfatal++; 1841 } else if (ret == DDI_FM_UNKNOWN) { 1842 unknown++; 1843 } 1844 1845 /* 1846 * rserr not claimed as nonfatal by a child is treated as fatal 1847 */ 1848 if (unknown && !nonfatal && !fatal) 1849 fatal++; 1850 1851 /* Cleanup and reset error bits */ 1852 pci_clear_error(pci_p, &pbm_err); 1853 1854 return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 1855 (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); 1856 } 1857 1858 int 1859 pci_check_error(pci_t *pci_p) 1860 { 1861 pbm_t *pbm_p = pci_p->pci_pbm_p; 1862 uint16_t pci_cfg_stat; 1863 uint64_t pbm_ctl_stat, pbm_afsr; 1864 1865 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1866 1867 pci_cfg_stat = pbm_p->pbm_config_header->ch_status_reg; 1868 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 1869 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 1870 1871 if ((pci_cfg_stat & (PCI_STAT_S_PERROR | PCI_STAT_S_TARG_AB | 1872 PCI_STAT_R_TARG_AB | PCI_STAT_R_MAST_AB | 1873 PCI_STAT_S_SYSERR | PCI_STAT_PERROR)) || 1874 (pbm_ctl_stat & (COMMON_PCI_CTRL_SBH_ERR | 1875 COMMON_PCI_CTRL_SERR)) || 1876 (PBM_AFSR_TO_PRIERR(pbm_afsr))) 1877 return (1); 1878 1879 return (0); 1880 1881 } 1882 1883 /* 1884 * Function used to gather PBM/PCI error state for the 1885 * pci_pbm_err_handler. This function must be called while pci_fm_mutex 1886 * is held. 1887 */ 1888 static void 1889 pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 1890 { 1891 pbm_t *pbm_p = pci_p->pci_pbm_p; 1892 1893 ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1894 bzero(pbm_err_p, sizeof (pbm_errstate_t)); 1895 1896 /* 1897 * Capture all pbm error state for later logging 1898 */ 1899 pbm_err_p->pbm_bridge_type = PCI_BRIDGE_TYPE(pci_p->pci_common_p); 1900 pbm_err_p->pbm_pci.pci_cfg_stat = 1901 pbm_p->pbm_config_header->ch_status_reg; 1902 pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 1903 pbm_err_p->pbm_pci.pci_cfg_comm = 1904 pbm_p->pbm_config_header->ch_command_reg; 1905 pbm_err_p->pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 1906 pbm_err_p->pbm_afar = *pbm_p->pbm_async_flt_addr_reg; 1907 pbm_err_p->pbm_pci.pci_pa = *pbm_p->pbm_async_flt_addr_reg; 1908 } 1909 1910 void 1911 pbm_clear_error(pbm_t *pbm_p) 1912 { 1913 uint64_t pbm_afsr, pbm_ctl_stat; 1914 1915 /* 1916 * for poke() support - called from POKE_FLUSH. Spin waiting 1917 * for MA, TA or SERR to be cleared by a pbm_error_intr(). 1918 * We have to wait for SERR too in case the device is beyond 1919 * a pci-pci bridge. 1920 */ 1921 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 1922 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 1923 while (((pbm_afsr >> PSYCHO_PCI_AFSR_PE_SHIFT) & 1924 (PSYCHO_PCI_AFSR_E_MA | PSYCHO_PCI_AFSR_E_TA)) || 1925 (pbm_ctl_stat & COMMON_PCI_CTRL_SERR)) { 1926 pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 1927 pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 1928 } 1929 } 1930 1931 /*ARGSUSED*/ 1932 void 1933 pci_format_addr(dev_info_t *dip, uint64_t *afar, uint64_t afsr) 1934 { 1935 /* 1936 * For Psycho the full address is stored in hardware. So 1937 * there is no need to format it. 1938 */ 1939 } 1940 1941 /*ARGSUSED*/ 1942 int 1943 pci_bus_quiesce(pci_t *pci_p, dev_info_t *dip, void *result) 1944 { 1945 return (DDI_FAILURE); 1946 } 1947 1948 /*ARGSUSED*/ 1949 int 1950 pci_bus_unquiesce(pci_t *pci_p, dev_info_t *dip, void *result) 1951 { 1952 return (DDI_FAILURE); 1953 } 1954 1955 void 1956 pci_vmem_free(iommu_t *iommu_p, ddi_dma_impl_t *mp, void *dvma_addr, 1957 size_t npages) 1958 { 1959 pci_vmem_do_free(iommu_p, dvma_addr, npages, 1960 (mp->dmai_flags & DMAI_FLAGS_VMEMCACHE)); 1961 } 1962 1963 1964 /* 1965 * NOTE: This call is only used by legacy systems (eg. E250 and E450) that 1966 * require unregistering the pci driver's thermal intrerrupt handler before 1967 * they can register their own. 1968 */ 1969 void 1970 pci_thermal_rem_intr(dev_info_t *rdip, uint_t inum) 1971 { 1972 pci_t *pci_p; 1973 dev_info_t *pdip; 1974 uint32_t dev_mondo, pci_mondo; 1975 int instance; 1976 1977 for (pdip = ddi_get_parent(rdip); pdip; pdip = ddi_get_parent(pdip)) { 1978 if (strcmp(ddi_driver_name(pdip), "pcipsy") == 0) 1979 break; 1980 } 1981 1982 if (!pdip) { 1983 cmn_err(CE_WARN, "pci_thermal_rem_intr() no pcipsy parent\n"); 1984 return; 1985 } 1986 1987 instance = ddi_get_instance(pdip); 1988 pci_p = get_pci_soft_state(instance); 1989 1990 /* Calculate the requesting device's mondo */ 1991 dev_mondo = pci_xlate_intr(pci_p->pci_dip, rdip, pci_p->pci_ib_p, 1992 IB_MONDO_TO_INO(i_ddi_get_inum(rdip, inum))); 1993 1994 /* get pci's thermal mondo */ 1995 pci_mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 1996 pci_p->pci_inos[CBNINTR_THERMAL]); 1997 pci_mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, pci_mondo); 1998 1999 if (pci_mondo == dev_mondo) { 2000 DEBUG2(DBG_ATTACH, rdip, "pci_thermal_rem_intr unregistered " 2001 "for dip=%s%d:", ddi_driver_name(rdip), 2002 ddi_get_instance(rdip)); 2003 rem_ivintr(pci_mondo, NULL); 2004 } 2005 } 2006