1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI nexus driver tunables 30 */ 31 32 #include <sys/types.h> 33 #include <sys/cmn_err.h> 34 #include <sys/time.h> 35 #include <sys/thread.h> 36 #include <sys/ksynch.h> 37 #include <sys/pci.h> 38 #include <sys/pci/pci_space.h> 39 40 41 /*LINTLIBRARY*/ 42 43 /* 44 * Used to disallow bypass requests for tomatillos ver <= 2.3 45 * 0 allow bypass, 1 disallow it. errata #75 46 */ 47 uint_t tomatillo_disallow_bypass = 0; 48 49 /* 50 * The three variables below enable a workround for 51 * tomatillo's micro TLB bug. errata #82 52 */ 53 uint_t tm_mtlb_maxpgs = 20; 54 uint_t tm_mtlb_gc = 0; /* for garbage collection */ 55 uint_t tm_mtlb_gc_manual = 0; /* for manual tuning */ 56 57 /* 58 * By initializing pci_interrupt_priorities_property to 1, the priority 59 * level of the interrupt handler for a PCI device can be defined via an 60 * "interrupt-priorities" property. This property is an array of integer 61 * values that have a one to one mapping the the "interrupts" property. 62 * For example, if a device's "interrupts" property was (1, 2) and its 63 * "interrupt-priorities" value was (5, 12), the handler for the first 64 * interrupt would run at cpu priority 5 and the second at priority 12. 65 * This would override the drivers standard mechanism for assigning 66 * priorities to interrupt handlers. 67 */ 68 uint_t pci_interrupt_priorities_property = 1; 69 70 /* 71 * By initializing pci_config_space_size_zero to 1, the driver will 72 * tolerate mapping requests for configuration space "reg" entries whose 73 * size is not zero. 74 */ 75 uint_t pci_config_space_size_zero = 1; 76 77 int pci_dvma_sync_before_unmap = 0; 78 int pci_sync_lock = 0; 79 80 int tomatillo_store_store_wrka = 0; 81 uint32_t pci_spurintr_duration = 60000000; /* One minute */ 82 uint64_t pci_spurintr_msgs = PCI_SPURINTR_MSG_DEFAULT; 83 84 /* 85 * The variable controls the default setting of the command register 86 * for pci devices. See init_child() for details. 87 * 88 * This flags also controls the setting of bits in the bridge control 89 * register pci to pci bridges. See init_child() for details. 90 */ 91 ushort_t pci_command_default = PCI_COMM_SERR_ENABLE | 92 PCI_COMM_WAIT_CYC_ENAB | 93 PCI_COMM_PARITY_DETECT | 94 PCI_COMM_ME | 95 PCI_COMM_MAE | 96 PCI_COMM_IO; 97 /* 98 * The following variable enables a workaround for the following obp bug: 99 * 100 * 1234181 - obp should set latency timer registers in pci 101 * configuration header 102 * 103 * Until this bug gets fixed in the obp, the following workaround should 104 * be enabled. 105 */ 106 uint_t pci_set_latency_timer_register = 1; 107 108 /* 109 * The following variable enables a workaround for an obp bug to be 110 * submitted. A bug requesting a workaround fof this problem has 111 * been filed: 112 * 113 * 1235094 - need workarounds on positron nexus drivers to set cache 114 * line size registers 115 * 116 * Until this bug gets fixed in the obp, the following workaround should 117 * be enabled. 118 */ 119 uint_t pci_set_cache_line_size_register = 1; 120 121 /* 122 * The following driver parameters are defined as variables to allow 123 * patching for debugging and tuning. Flags that can be set on a per 124 * PBM basis are bit fields where the PBM device instance number maps 125 * to the bit position. 126 */ 127 #ifdef DEBUG 128 uint64_t pci_debug_flags = 0; 129 uint_t pci_warn_pp0 = 0; 130 #endif 131 uint_t pci_disable_pass1_workarounds = 0; 132 uint_t pci_disable_pass2_workarounds = 0; 133 uint_t pci_disable_pass3_workarounds = 0; 134 uint_t pci_disable_plus_workarounds = 0; 135 uint_t pci_disable_default_workarounds = 0; 136 uint_t ecc_error_intr_enable = 1; 137 uint_t pci_sbh_error_intr_enable = (uint_t)-1; 138 uint_t pci_mmu_error_intr_enable = (uint_t)-1; 139 uint_t pci_stream_buf_enable = (uint_t)-1; 140 uint_t pci_stream_buf_exists = 1; 141 uint_t pci_rerun_disable = 0; 142 143 uint_t pci_enable_retry_arb = (uint_t)-1; 144 145 uint_t pci_bus_parking_enable = (uint_t)-1; 146 uint_t pci_error_intr_enable = (uint_t)-1; 147 uint_t pci_retry_disable = 0; 148 uint_t pci_retry_enable = 0; 149 uint_t pci_dwsync_disable = 0; 150 uint_t pci_intsync_disable = 0; 151 uint_t pci_b_arb_enable = 0xf; 152 uint_t pci_a_arb_enable = 0xf; 153 uint_t pci_ecc_afsr_retries = 100; /* XXX - what's a good value? */ 154 155 uint_t pci_intr_retry_intv = 5; /* for interrupt retry reg */ 156 uint8_t pci_latency_timer = 0x40; /* for pci latency timer reg */ 157 uint_t pci_panic_on_sbh_errors = 0; 158 uint_t pci_panic_on_fatal_errors = 1; /* should be 1 at beta */ 159 uint_t pci_thermal_intr_fatal = 1; /* thermal interrupts fatal */ 160 uint_t pci_buserr_interrupt = 1; /* safari buserr interrupt */ 161 uint_t pci_set_dto_value = 0; /* overwrite the prom settings? */ 162 uint_t pci_dto_value = 1; /* schizo consistent buf timeout PTO */ 163 uint_t pci_lock_sbuf = 0; 164 165 uint_t pci_use_contexts = 1; 166 uint_t pci_sc_use_contexts = 1; 167 uint_t pci_context_minpages = 2; 168 uint_t pci_ctx_flush_warn = CE_IGNORE; 169 uint_t pci_ctx_unsuccess_count = 0; /* unsuccessful ctx flush count */ 170 uint_t pci_ctx_no_active_flush = 0; /* cannot handle active ctx flush */ 171 uint_t pci_ctx_no_compat = 0; /* maintain compatibility */ 172 173 uint64_t pci_perr_enable = -1ull; 174 uint64_t pci_serr_enable = -1ull; 175 uint64_t pci_perr_fatal = -1ull; 176 uint64_t pci_serr_fatal = -1ull; 177 hrtime_t pci_intrpend_timeout = 5ll * NANOSEC; /* 5 seconds in nanoseconds */ 178 hrtime_t pci_sync_buf_timeout = 1ll * NANOSEC; /* 1 second in nanoseconds */ 179 hrtime_t pci_cdma_intr_timeout = 1ll * NANOSEC; /* consistent sync trigger */ 180 uint32_t pci_cdma_intr_count = 15; /* num of pci_cdma_intr_timeout cycles */ 181 182 uint32_t pci_dto_fault_warn = CE_WARN; /* set to CE_IGNORE for no messages */ 183 uint64_t pci_dto_intr_enable = 0; 184 uint64_t pci_dto_count = 0; 185 uint64_t pci_errtrig_pa = 0x0; 186 187 /* 188 * The following flag controls behavior of the ino handler routine 189 * when multiple interrupts are attached to a single ino. Typically 190 * this case would occur for the ino's assigned to the PCI bus slots 191 * with multi-function devices or bus bridges. 192 * 193 * Setting the flag to zero causes the ino handler routine to return 194 * after finding the first interrupt handler to claim the interrupt. 195 * 196 * Setting the flag to non-zero causes the ino handler routine to 197 * return after making one complete pass through the interrupt 198 * handlers. 199 */ 200 uint_t pci_check_all_handlers = 1; 201 202 /* 203 * The following value is the number of consecutive unclaimed interrupts that 204 * will be tolerated for a particular ino_p before the interrupt is deemed to 205 * be jabbering and is blocked. 206 */ 207 uint_t pci_unclaimed_intr_max = 20; 208 209 ulong_t pci_iommu_dvma_end = 0xfffffffful; 210 uint_t pci_lock_tlb = 0; 211 uint64_t pci_dvma_debug_on = 0; 212 uint64_t pci_dvma_debug_off = 0; 213 uint32_t pci_dvma_debug_rec = 512; 214 215 /* 216 * dvma address space allocation cache variables 217 */ 218 uint_t pci_dvma_page_cache_entries = 0x200; /* # of chunks (1 << bits) */ 219 uint_t pci_dvma_page_cache_clustsz = 0x8; /* # of pages per chunk */ 220 #ifdef PCI_DMA_PROF 221 uint_t pci_dvmaft_npages = 0; /* FT fail due npages */ 222 uint_t pci_dvmaft_limit = 0; /* FT fail due limits */ 223 uint_t pci_dvmaft_free = 0; /* FT free */ 224 uint_t pci_dvmaft_success = 0; /* FT success */ 225 uint_t pci_dvmaft_exhaust = 0; /* FT vmem fallback */ 226 uint_t pci_dvma_vmem_alloc = 0; /* vmem alloc */ 227 uint_t pci_dvma_vmem_xalloc = 0; /* vmem xalloc */ 228 uint_t pci_dvma_vmem_xfree = 0; /* vmem xfree */ 229 uint_t pci_dvma_vmem_free = 0; /* vmem free */ 230 #endif 231 uint_t pci_disable_fdvma = 0; 232 233 uint_t pci_iommu_ctx_lock_failure = 0; 234 235 /* 236 * This flag preserves prom iommu settings by copying prom TSB entries 237 * to corresponding kernel TSB entry locations. It should be removed 238 * after the interface properties from obp have become default. 239 */ 240 uint_t pci_preserve_iommu_tsb = 1; 241 242 /* 243 * memory callback list id callback list for kmem_alloc failure clients 244 */ 245 uintptr_t pci_kmem_clid = 0; 246 247 /* 248 * Perform a consistent-mode sync/flush during interrupt. 249 */ 250 uint_t pci_intr_dma_sync = 0; 251 252 /* 253 * This flag is used to enable max prefetch streaming cache mode 254 * feature of XMITS. 255 */ 256 uint_t pci_xmits_sc_max_prf = 0; 257 258 /* 259 * This flag is used to enable pcix error reporting in XMITS. 260 */ 261 uint64_t xmits_error_intr_enable = -1ull; 262 263 /* 264 * Enable parity error recovery for xmits 265 */ 266 uint_t xmits_perr_recov_int_enable = 0; 267 268 /* 269 * This flag controls whether or not DVMA remap support is 270 * enabled (currently, Schizo/XMITS only). 271 */ 272 int pci_dvma_remap_enabled = 0; 273 274 /* 275 * Serialize PCI relocations, since they are time critical. 276 */ 277 kthread_t *pci_reloc_thread = NULL; 278 kmutex_t pci_reloc_mutex; 279 kcondvar_t pci_reloc_cv; 280 int pci_reloc_presuspend = 0; 281 int pci_reloc_suspend = 0; 282 id_t pci_dvma_cbid; 283 id_t pci_fast_dvma_cbid; 284 int pci_dma_panic_on_leak = 0; 285 286 /* 287 * Set Outstanding Maximum Split Transactions. Legal settings are: 288 * 0 = 1 Outstanding Transacation, 1 = 2, 2 = 3, 3 = 4, 4 = 8, 5 = 12, 289 * 6 = 16, 7 = 32. 290 */ 291 uint_t xmits_max_transactions = 0; 292 293 /* 294 * Set Max Memory Read Byte Count. Legal settings are: 295 * 0 = 512 Max Memory Read Bytes, 1 = 1024, 2 = 2048, 3 = 4096. 296 */ 297 uint_t xmits_max_read_bytes = 0; 298 299 /* 300 * Bits 15:0 increase the maximum PIO retries allowed by XMITS. 301 */ 302 uint_t xmits_upper_retry_counter = 0x3E8; 303 304 /* 305 * default values for xmits pcix diag BUG_FIX_CNTL bits 47:32 306 * depending on mode: pcix or pci. 307 */ 308 uint_t xmits_pcix_diag_bugcntl_pcix = 0xA0; 309 uint_t xmits_pcix_diag_bugcntl_pci = 0xFF; 310