1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * Sun4u PCI to PCI bus bridge nexus driver 29 */ 30 31 #include <sys/conf.h> 32 #include <sys/kmem.h> 33 #include <sys/debug.h> 34 #include <sys/modctl.h> 35 #include <sys/autoconf.h> 36 #include <sys/ddi_impldefs.h> 37 #include <sys/ddi_subrdefs.h> 38 #include <sys/pcie.h> 39 #include <sys/pcie_impl.h> 40 #include <sys/pci_cap.h> 41 #include <sys/pci/pci_nexus.h> 42 #include <sys/pci/pci_regs.h> 43 #include <sys/ddi.h> 44 #include <sys/sunndi.h> 45 #include <sys/sunddi.h> 46 #include <sys/fm/protocol.h> 47 #include <sys/ddifm.h> 48 #include <sys/pci/pci_pwr.h> 49 #include <sys/pci/pci_debug.h> 50 #include <sys/hotplug/pci/pcihp.h> 51 #include <sys/open.h> 52 #include <sys/stat.h> 53 #include <sys/file.h> 54 55 #define NUM_LOGICAL_SLOTS 32 56 57 #define PPB_RANGE_LEN 2 58 59 #define PPB_32BIT_IO 1 60 #define PPB_32bit_MEM 1 61 62 #define PPB_MEMGRAIN 0x100000 63 #define PPB_IOGRAIN 0x1000 64 65 #define PPB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8)) 66 #define PPB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo)) 67 #define PPB_32bit_MEMADDR(addr) (PPB_LADDR(0, ((uint16_t)(addr) & 0xFFF0))) 68 69 typedef struct slot_table { 70 uchar_t bus_id[128]; 71 uchar_t slot_name[32]; 72 uint8_t device_no; 73 uint8_t phys_slot_num; 74 } slot_table_t; 75 76 /* 77 * The variable controls the default setting of the command register 78 * for pci devices. See ppb_initchild() for details. 79 */ 80 static ushort_t ppb_command_default = PCI_COMM_SERR_ENABLE | 81 PCI_COMM_WAIT_CYC_ENAB | 82 PCI_COMM_PARITY_DETECT | 83 PCI_COMM_ME | 84 PCI_COMM_MAE | 85 PCI_COMM_IO; 86 87 static int ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, 88 off_t, off_t, caddr_t *); 89 static int ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, 90 void *, void *); 91 static int ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, 92 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 93 94 /* 95 * fm_init busop to initialize our children 96 */ 97 static int ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 98 ddi_iblock_cookie_t *ibc); 99 static void ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle); 100 static void ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle); 101 static int ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, 102 void *arg, void *result); 103 104 struct bus_ops ppb_bus_ops = { 105 BUSO_REV, 106 ppb_bus_map, 107 0, 108 0, 109 0, 110 i_ddi_map_fault, 111 ddi_dma_map, 112 ddi_dma_allochdl, 113 ddi_dma_freehdl, 114 ddi_dma_bindhdl, 115 ddi_dma_unbindhdl, 116 ddi_dma_flush, 117 ddi_dma_win, 118 ddi_dma_mctl, 119 ppb_ctlops, 120 ddi_bus_prop_op, 121 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 122 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 123 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 124 ndi_post_event, /* (*bus_post_event)(); */ 125 0, /* (*bus_intr_ctl)(); */ 126 0, /* (*bus_config)(); */ 127 0, /* (*bus_unconfig)(); */ 128 ppb_fm_init_child, /* (*bus_fm_init)(); */ 129 NULL, /* (*bus_fm_fini)(); */ 130 ppb_bus_enter, /* (*bus_enter)() */ 131 ppb_bus_exit, /* (*bus_exit)() */ 132 ppb_bus_power, /* (*bus_power)() */ 133 ppb_intr_ops /* (*bus_intr_op)(); */ 134 }; 135 136 static int ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp); 137 static int ppb_close(dev_t dev, int flags, int otyp, cred_t *credp); 138 static int ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, 139 cred_t *credp, int *rvalp); 140 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 141 int flags, char *name, caddr_t valuep, int *lengthp); 142 143 static struct cb_ops ppb_cb_ops = { 144 ppb_open, /* open */ 145 ppb_close, /* close */ 146 nulldev, /* strategy */ 147 nulldev, /* print */ 148 nulldev, /* dump */ 149 nulldev, /* read */ 150 nulldev, /* write */ 151 ppb_ioctl, /* ioctl */ 152 nodev, /* devmap */ 153 nodev, /* mmap */ 154 nodev, /* segmap */ 155 nochpoll, /* poll */ 156 ppb_prop_op, /* cb_prop_op */ 157 NULL, /* streamtab */ 158 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 159 CB_REV, /* rev */ 160 nodev, /* int (*cb_aread)() */ 161 nodev /* int (*cb_awrite)() */ 162 }; 163 164 static int ppb_probe(dev_info_t *); 165 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 166 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 167 static int ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 168 void *arg, void **result); 169 static int ppb_pwr(dev_info_t *dip, int component, int level); 170 171 struct dev_ops ppb_ops = { 172 DEVO_REV, /* devo_rev */ 173 0, /* refcnt */ 174 ppb_info, /* info */ 175 nulldev, /* identify */ 176 ppb_probe, /* probe */ 177 ppb_attach, /* attach */ 178 ppb_detach, /* detach */ 179 nulldev, /* reset */ 180 &ppb_cb_ops, /* driver operations */ 181 &ppb_bus_ops, /* bus operations */ 182 ppb_pwr, /* power */ 183 ddi_quiesce_not_needed, /* quiesce */ 184 }; 185 186 /* 187 * Module linkage information for the kernel. 188 */ 189 190 static struct modldrv modldrv = { 191 &mod_driverops, /* Type of module */ 192 "Standard PCI to PCI bridge nexus driver", 193 &ppb_ops, /* driver ops */ 194 }; 195 196 static struct modlinkage modlinkage = { 197 MODREV_1, 198 (void *)&modldrv, 199 NULL 200 }; 201 202 /* 203 * soft state pointer and structure template: 204 */ 205 static void *ppb_state; 206 207 struct ppb_cfg_state { 208 dev_info_t *dip; 209 ushort_t command; 210 uchar_t cache_line_size; 211 uchar_t latency_timer; 212 uchar_t header_type; 213 uchar_t sec_latency_timer; 214 ushort_t bridge_control; 215 }; 216 217 typedef struct { 218 219 dev_info_t *dip; 220 221 /* 222 * configuration register state for the bus: 223 */ 224 uchar_t ppb_cache_line_size; 225 uchar_t ppb_latency_timer; 226 227 /* 228 * PM support 229 */ 230 ddi_acc_handle_t ppb_conf_hdl; 231 uint16_t ppb_pm_cap_ptr; 232 pci_pwr_t *ppb_pwr_p; 233 234 /* 235 * HP support 236 */ 237 boolean_t hotplug_capable; 238 239 kmutex_t ppb_mutex; 240 uint_t ppb_soft_state; 241 #define PPB_SOFT_STATE_CLOSED 0x00 242 #define PPB_SOFT_STATE_OPEN 0x01 243 #define PPB_SOFT_STATE_OPEN_EXCL 0x02 244 int fm_cap; 245 ddi_iblock_cookie_t fm_ibc; 246 247 uint16_t parent_bus; 248 } ppb_devstate_t; 249 250 /* 251 * The following variable enables a workaround for the following obp bug: 252 * 253 * 1234181 - obp should set latency timer registers in pci 254 * configuration header 255 * 256 * Until this bug gets fixed in the obp, the following workaround should 257 * be enabled. 258 */ 259 static uint_t ppb_set_latency_timer_register = 1; 260 261 /* 262 * The following variable enables a workaround for an obp bug to be 263 * submitted. A bug requesting a workaround fof this problem has 264 * been filed: 265 * 266 * 1235094 - need workarounds on positron nexus drivers to set cache 267 * line size registers 268 * 269 * Until this bug gets fixed in the obp, the following workaround should 270 * be enabled. 271 */ 272 static uint_t ppb_set_cache_line_size_register = 1; 273 274 /* 275 * forward function declarations: 276 */ 277 278 /* 279 * FMA error callback 280 * Register error handling callback with our parent. We will just call 281 * our children's error callbacks and return their status. 282 */ 283 static int ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, 284 const void *impl_data); 285 286 /* 287 * init/fini routines to alloc/dealloc fm structures and 288 * register/unregister our callback. 289 */ 290 static void ppb_fm_init(ppb_devstate_t *ppb_p); 291 static void ppb_fm_fini(ppb_devstate_t *ppb_p); 292 293 static void ppb_removechild(dev_info_t *); 294 static int ppb_initchild(dev_info_t *child); 295 static void ppb_uninitchild(dev_info_t *child); 296 static dev_info_t *get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 297 static void ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *dip); 298 static void ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip); 299 static void ppb_init_hotplug(ppb_devstate_t *ppb); 300 static void ppb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t); 301 uint64_t pci_debug_flags = 0; 302 303 int 304 _init(void) 305 { 306 int e; 307 if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t), 308 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 309 ddi_soft_state_fini(&ppb_state); 310 return (e); 311 } 312 313 int 314 _fini(void) 315 { 316 int e; 317 318 if ((e = mod_remove(&modlinkage)) == 0) 319 ddi_soft_state_fini(&ppb_state); 320 return (e); 321 } 322 323 int 324 _info(struct modinfo *modinfop) 325 { 326 return (mod_info(&modlinkage, modinfop)); 327 } 328 329 /*ARGSUSED*/ 330 static int 331 ppb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 332 { 333 ppb_devstate_t *ppb_p; /* per ppb state pointer */ 334 minor_t minor = getminor((dev_t)arg); 335 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 336 337 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 338 instance); 339 340 switch (infocmd) { 341 default: 342 return (DDI_FAILURE); 343 344 case DDI_INFO_DEVT2INSTANCE: 345 *result = (void *)(uintptr_t)instance; 346 return (DDI_SUCCESS); 347 348 case DDI_INFO_DEVT2DEVINFO: 349 if (ppb_p == NULL) 350 return (DDI_FAILURE); 351 *result = (void *)ppb_p->dip; 352 return (DDI_SUCCESS); 353 } 354 } 355 356 /*ARGSUSED*/ 357 static int 358 ppb_probe(register dev_info_t *devi) 359 { 360 return (DDI_PROBE_SUCCESS); 361 } 362 363 /*ARGSUSED*/ 364 static int 365 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 366 { 367 int instance; 368 ppb_devstate_t *ppb; 369 ddi_acc_handle_t config_handle; 370 371 switch (cmd) { 372 case DDI_ATTACH: 373 374 /* 375 * Make sure the "device_type" property exists. 376 */ 377 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 378 "device_type", "pci"); 379 380 /* 381 * Allocate and get soft state structure. 382 */ 383 instance = ddi_get_instance(devi); 384 if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS) 385 return (DDI_FAILURE); 386 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, instance); 387 ppb->dip = devi; 388 mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL); 389 ppb->ppb_soft_state = PPB_SOFT_STATE_CLOSED; 390 if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) { 391 mutex_destroy(&ppb->ppb_mutex); 392 ddi_soft_state_free(ppb_state, instance); 393 return (DDI_FAILURE); 394 } 395 ppb_pwr_setup(ppb, devi); 396 397 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 398 mutex_enter(&ppb->ppb_pwr_p->pwr_mutex); 399 400 /* 401 * Before reading config registers, make sure power is 402 * on, and remains on. 403 */ 404 ppb->ppb_pwr_p->pwr_fp++; 405 406 pci_pwr_change(ppb->ppb_pwr_p, 407 ppb->ppb_pwr_p->current_lvl, 408 pci_pwr_new_lvl(ppb->ppb_pwr_p)); 409 } 410 411 ppb->ppb_cache_line_size = 412 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 413 ppb->ppb_latency_timer = 414 pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 415 416 /* 417 * Check whether the "ranges" property is present. 418 * Otherwise create the ranges property by reading 419 * the configuration registers 420 */ 421 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS, 422 "ranges") == 0) { 423 ppb_create_ranges_prop(devi, config_handle); 424 } 425 426 pci_config_teardown(&config_handle); 427 428 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 429 ppb->ppb_pwr_p->pwr_fp--; 430 431 pci_pwr_change(ppb->ppb_pwr_p, 432 ppb->ppb_pwr_p->current_lvl, 433 pci_pwr_new_lvl(ppb->ppb_pwr_p)); 434 435 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 436 } 437 438 /* 439 * Initialize hotplug support on this bus. At minimum 440 * (for non hotplug bus) this would create ":devctl" minor 441 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls 442 * to this bus. This all takes place if this nexus has hot-plug 443 * slots and successfully initializes Hot Plug Framework. 444 */ 445 ppb->hotplug_capable = B_FALSE; 446 ppb_init_hotplug(ppb); 447 if (ppb->hotplug_capable == B_FALSE) { 448 /* 449 * create minor node for devctl interfaces 450 */ 451 if (ddi_create_minor_node(devi, "devctl", S_IFCHR, 452 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 453 DDI_NT_NEXUS, 0) != DDI_SUCCESS) { 454 if (ppb->ppb_pwr_p != NULL) { 455 ppb_pwr_teardown(ppb, devi); 456 } 457 mutex_destroy(&ppb->ppb_mutex); 458 ddi_soft_state_free(ppb_state, instance); 459 return (DDI_FAILURE); 460 } 461 } 462 463 DEBUG1(DBG_ATTACH, devi, 464 "ppb_attach(): this nexus %s hotplug slots\n", 465 ppb->hotplug_capable == B_TRUE ? "has":"has no"); 466 467 ppb_fm_init(ppb); 468 ddi_report_dev(devi); 469 470 return (DDI_SUCCESS); 471 472 case DDI_RESUME: 473 /* 474 * Get the soft state structure for the bridge. 475 */ 476 ppb = (ppb_devstate_t *) 477 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 478 479 pci_pwr_resume(devi, ppb->ppb_pwr_p); 480 481 return (DDI_SUCCESS); 482 } 483 return (DDI_FAILURE); 484 } 485 486 /*ARGSUSED*/ 487 static int 488 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 489 { 490 ppb_devstate_t *ppb; 491 492 switch (cmd) { 493 case DDI_DETACH: 494 /* 495 * And finally free the per-pci soft state after 496 * uninitializing hotplug support for this bus. 497 */ 498 ppb = (ppb_devstate_t *) 499 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 500 501 ppb_fm_fini(ppb); 502 503 if (ppb->hotplug_capable == B_TRUE) 504 if (pcihp_uninit(devi) == DDI_FAILURE) 505 return (DDI_FAILURE); 506 else 507 ddi_remove_minor_node(devi, "devctl"); 508 509 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 510 511 if (ppb->ppb_pwr_p != NULL) { 512 ppb_pwr_teardown(ppb, devi); 513 } 514 mutex_destroy(&ppb->ppb_mutex); 515 ddi_soft_state_free(ppb_state, ddi_get_instance(devi)); 516 517 return (DDI_SUCCESS); 518 519 case DDI_SUSPEND: 520 ppb = (ppb_devstate_t *) 521 ddi_get_soft_state(ppb_state, ddi_get_instance(devi)); 522 523 pci_pwr_suspend(devi, ppb->ppb_pwr_p); 524 525 return (DDI_SUCCESS); 526 } 527 return (DDI_FAILURE); 528 } 529 530 /*ARGSUSED*/ 531 static int 532 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 533 off_t offset, off_t len, caddr_t *vaddrp) 534 { 535 register dev_info_t *pdip; 536 537 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 538 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map) 539 (pdip, rdip, mp, offset, len, vaddrp)); 540 } 541 542 /*ARGSUSED*/ 543 static int 544 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip, 545 ddi_ctl_enum_t ctlop, void *arg, void *result) 546 { 547 pci_regspec_t *drv_regp; 548 int reglen; 549 int rn; 550 struct attachspec *as; 551 struct detachspec *ds; 552 int totreg; 553 ppb_devstate_t *ppb_p; 554 555 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 556 ddi_get_instance(dip)); 557 558 switch (ctlop) { 559 case DDI_CTLOPS_REPORTDEV: 560 if (rdip == (dev_info_t *)0) 561 return (DDI_FAILURE); 562 cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n", 563 ddi_node_name(rdip), ddi_get_name_addr(rdip), 564 ddi_driver_name(rdip), 565 ddi_get_instance(rdip)); 566 return (DDI_SUCCESS); 567 568 case DDI_CTLOPS_INITCHILD: 569 return (ppb_initchild((dev_info_t *)arg)); 570 571 case DDI_CTLOPS_UNINITCHILD: 572 ppb_uninitchild((dev_info_t *)arg); 573 return (DDI_SUCCESS); 574 575 case DDI_CTLOPS_ATTACH: 576 if (!pcie_is_child(dip, rdip)) 577 return (DDI_SUCCESS); 578 579 as = (struct attachspec *)arg; 580 if ((ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) && 581 (as->when == DDI_POST) && (as->result == DDI_SUCCESS)) 582 pf_init(rdip, ppb_p->fm_ibc, as->cmd); 583 584 return (DDI_SUCCESS); 585 586 case DDI_CTLOPS_DETACH: 587 if (!pcie_is_child(dip, rdip)) 588 return (DDI_SUCCESS); 589 590 ds = (struct detachspec *)arg; 591 if ((ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) && 592 (ds->when == DDI_PRE)) 593 pf_fini(rdip, ds->cmd); 594 595 return (DDI_SUCCESS); 596 597 case DDI_CTLOPS_SIDDEV: 598 return (DDI_SUCCESS); 599 600 case DDI_CTLOPS_REGSIZE: 601 case DDI_CTLOPS_NREGS: 602 if (rdip == (dev_info_t *)0) 603 return (DDI_FAILURE); 604 break; 605 default: 606 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 607 } 608 609 *(int *)result = 0; 610 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 611 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", 612 (caddr_t)&drv_regp, ®len) != DDI_SUCCESS) 613 return (DDI_FAILURE); 614 615 totreg = reglen / sizeof (pci_regspec_t); 616 if (ctlop == DDI_CTLOPS_NREGS) 617 *(int *)result = totreg; 618 else if (ctlop == DDI_CTLOPS_REGSIZE) { 619 rn = *(int *)arg; 620 if (rn >= totreg) { 621 kmem_free(drv_regp, reglen); 622 return (DDI_FAILURE); 623 } 624 *(off_t *)result = drv_regp[rn].pci_size_low | 625 ((uint64_t)drv_regp[rn].pci_size_hi << 32); 626 } 627 628 kmem_free(drv_regp, reglen); 629 return (DDI_SUCCESS); 630 } 631 632 633 static dev_info_t * 634 get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 635 { 636 dev_info_t *cdip = rdip; 637 638 for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 639 ; 640 641 return (cdip); 642 } 643 644 645 static int 646 ppb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 647 ddi_intr_handle_impl_t *hdlp, void *result) 648 { 649 dev_info_t *cdip = rdip; 650 pci_regspec_t *pci_rp; 651 int reglen, len; 652 uint32_t d, intr; 653 654 if ((intr_op == DDI_INTROP_SUPPORTED_TYPES) || 655 (hdlp->ih_type != DDI_INTR_TYPE_FIXED)) 656 goto done; 657 658 /* 659 * If the interrupt-map property is defined at this 660 * node, it will have performed the interrupt 661 * translation as part of the property, so no 662 * rotation needs to be done. 663 */ 664 if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 665 "interrupt-map", &len) == DDI_PROP_SUCCESS) 666 goto done; 667 668 cdip = get_my_childs_dip(dip, rdip); 669 670 /* 671 * Use the devices reg property to determine its 672 * PCI bus number and device number. 673 */ 674 if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 675 "reg", (caddr_t)&pci_rp, ®len) != DDI_SUCCESS) 676 return (DDI_FAILURE); 677 678 intr = hdlp->ih_vector; 679 680 /* Spin the interrupt */ 681 d = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 682 683 if ((intr >= PCI_INTA) && (intr <= PCI_INTD)) 684 hdlp->ih_vector = ((intr - 1 + (d % 4)) % 4 + 1); 685 else 686 cmn_err(CE_WARN, "%s%d: %s: PCI intr=%x out of range", 687 ddi_driver_name(rdip), ddi_get_instance(rdip), 688 ddi_driver_name(dip), intr); 689 690 kmem_free(pci_rp, reglen); 691 692 done: 693 /* Pass up the request to our parent. */ 694 return (i_ddi_intr_ops(dip, rdip, intr_op, hdlp, result)); 695 } 696 697 static int 698 ppb_bus_power(dev_info_t *dip, void *impl_arg, pm_bus_power_op_t op, 699 void *arg, void *result) 700 { 701 ppb_devstate_t *ppb; 702 703 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 704 ddi_get_instance(dip)); 705 706 return (pci_pwr_ops(ppb->ppb_pwr_p, dip, impl_arg, op, arg, result)); 707 } 708 709 710 /* 711 * name_child 712 * 713 * This function is called from init_child to name a node. It is 714 * also passed as a callback for node merging functions. 715 * 716 * return value: DDI_SUCCESS, DDI_FAILURE 717 */ 718 static int 719 ppb_name_child(dev_info_t *child, char *name, int namelen) 720 { 721 pci_regspec_t *pci_rp; 722 uint_t slot, func; 723 char **unit_addr; 724 uint_t n; 725 726 /* 727 * Pseudo nodes indicate a prototype node with per-instance 728 * properties to be merged into the real h/w device node. 729 * The interpretation of the unit-address is DD[,F] 730 * where DD is the device id and F is the function. 731 */ 732 if (ndi_dev_is_persistent_node(child) == 0) { 733 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 734 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 735 DDI_PROP_SUCCESS) { 736 cmn_err(CE_WARN, "cannot name node from %s.conf", 737 ddi_driver_name(child)); 738 return (DDI_FAILURE); 739 } 740 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 741 cmn_err(CE_WARN, "unit-address property in %s.conf" 742 " not well-formed", ddi_driver_name(child)); 743 ddi_prop_free(unit_addr); 744 return (DDI_FAILURE); 745 } 746 (void) snprintf(name, namelen, "%s", *unit_addr); 747 ddi_prop_free(unit_addr); 748 return (DDI_SUCCESS); 749 } 750 751 /* 752 * Get the address portion of the node name based on 753 * the function and device number. 754 */ 755 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 756 "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 757 return (DDI_FAILURE); 758 } 759 760 slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 761 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 762 763 if (func != 0) 764 (void) snprintf(name, namelen, "%x,%x", slot, func); 765 else 766 (void) snprintf(name, namelen, "%x", slot); 767 768 ddi_prop_free(pci_rp); 769 return (DDI_SUCCESS); 770 } 771 772 static int 773 ppb_initchild(dev_info_t *child) 774 { 775 char name[MAXNAMELEN]; 776 ddi_acc_handle_t config_handle; 777 ushort_t command_preserve, command; 778 uint_t n; 779 ushort_t bcr; 780 uchar_t header_type; 781 uchar_t min_gnt, latency_timer; 782 ppb_devstate_t *ppb; 783 784 /* 785 * Name the child 786 */ 787 if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) 788 return (DDI_FAILURE); 789 790 ddi_set_name_addr(child, name); 791 ddi_set_parent_data(child, NULL); 792 793 /* 794 * Pseudo nodes indicate a prototype node with per-instance 795 * properties to be merged into the real h/w device node. 796 * The interpretation of the unit-address is DD[,F] 797 * where DD is the device id and F is the function. 798 */ 799 if (ndi_dev_is_persistent_node(child) == 0) { 800 extern int pci_allow_pseudo_children; 801 802 /* 803 * Try to merge the properties from this prototype 804 * node into real h/w nodes. 805 */ 806 if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) { 807 /* 808 * Merged ok - return failure to remove the node. 809 */ 810 ppb_removechild(child); 811 return (DDI_FAILURE); 812 } 813 814 /* workaround for ddivs to run under PCI */ 815 if (pci_allow_pseudo_children) 816 return (DDI_SUCCESS); 817 818 /* 819 * The child was not merged into a h/w node, 820 * but there's not much we can do with it other 821 * than return failure to cause the node to be removed. 822 */ 823 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 824 ddi_driver_name(child), ddi_get_name_addr(child), 825 ddi_driver_name(child)); 826 ppb_removechild(child); 827 return (DDI_NOT_WELL_FORMED); 828 } 829 830 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 831 ddi_get_instance(ddi_get_parent(child))); 832 833 ddi_set_parent_data(child, NULL); 834 835 /* 836 * If hardware is PM capable, set up the power info structure. 837 * This also ensures the the bus will not be off (0MHz) otherwise 838 * system panics during a bus access. 839 */ 840 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 841 /* 842 * Create a pwr_info struct for child. Bus will be 843 * at full speed after creating info. 844 */ 845 pci_pwr_create_info(ppb->ppb_pwr_p, child); 846 #ifdef DEBUG 847 ASSERT(ppb->ppb_pwr_p->current_lvl == PM_LEVEL_B0); 848 #endif 849 } 850 851 /* 852 * If configuration registers were previously saved by 853 * child (before it entered D3), then let the child do the 854 * restore to set up the config regs as it'll first need to 855 * power the device out of D3. 856 */ 857 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 858 "config-regs-saved-by-child") == 1) { 859 DEBUG2(DBG_PWR, ddi_get_parent(child), 860 "INITCHILD: config regs to be restored by child" 861 " for %s@%s\n", ddi_node_name(child), 862 ddi_get_name_addr(child)); 863 864 return (DDI_SUCCESS); 865 } 866 867 DEBUG2(DBG_PWR, ddi_get_parent(child), 868 "INITCHILD: config regs setup for %s@%s\n", 869 ddi_node_name(child), ddi_get_name_addr(child)); 870 871 if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) { 872 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 873 pci_pwr_rm_info(ppb->ppb_pwr_p, child); 874 } 875 876 return (DDI_FAILURE); 877 } 878 879 /* 880 * Determine the configuration header type. 881 */ 882 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 883 884 /* 885 * Support for the "command-preserve" property. 886 */ 887 command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child, 888 DDI_PROP_DONTPASS, "command-preserve", 0); 889 command = pci_config_get16(config_handle, PCI_CONF_COMM); 890 command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB); 891 command |= (ppb_command_default & ~command_preserve); 892 pci_config_put16(config_handle, PCI_CONF_COMM, command); 893 894 /* 895 * If the device has a bus control register then program it 896 * based on the settings in the command register. 897 */ 898 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 899 bcr = pci_config_get8(config_handle, PCI_BCNF_BCNTRL); 900 if (ppb_command_default & PCI_COMM_PARITY_DETECT) 901 bcr |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 902 if (ppb_command_default & PCI_COMM_SERR_ENABLE) 903 bcr |= PCI_BCNF_BCNTRL_SERR_ENABLE; 904 bcr |= PCI_BCNF_BCNTRL_MAST_AB_MODE; 905 pci_config_put8(config_handle, PCI_BCNF_BCNTRL, bcr); 906 } 907 908 /* 909 * Initialize cache-line-size configuration register if needed. 910 */ 911 if (ppb_set_cache_line_size_register && 912 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 913 "cache-line-size", 0) == 0) { 914 pci_config_put8(config_handle, PCI_CONF_CACHE_LINESZ, 915 ppb->ppb_cache_line_size); 916 n = pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ); 917 if (n != 0) { 918 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 919 "cache-line-size", n); 920 } 921 } 922 923 /* 924 * Initialize latency timer configuration registers if needed. 925 */ 926 if (ppb_set_latency_timer_register && 927 ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 928 "latency-timer", 0) == 0) { 929 930 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 931 latency_timer = ppb->ppb_latency_timer; 932 pci_config_put8(config_handle, PCI_BCNF_LATENCY_TIMER, 933 ppb->ppb_latency_timer); 934 } else { 935 min_gnt = pci_config_get8(config_handle, 936 PCI_CONF_MIN_G); 937 latency_timer = min_gnt * 8; 938 } 939 pci_config_put8(config_handle, PCI_CONF_LATENCY_TIMER, 940 latency_timer); 941 n = pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER); 942 if (n != 0) { 943 (void) ndi_prop_update_int(DDI_DEV_T_NONE, child, 944 "latency-timer", n); 945 } 946 } 947 948 /* 949 * SPARC PCIe FMA specific 950 * 951 * Note: parent_data for parent is created only if this is sparc PCI-E 952 * platform, for which, SG take a different route to handle device 953 * errors. 954 */ 955 if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) { 956 if (pcie_init_bus(child) == NULL) { 957 pci_config_teardown(&config_handle); 958 return (DDI_FAILURE); 959 } 960 } 961 962 /* 963 * Check to see if the XMITS/PCI-X workaround applies. 964 */ 965 n = ddi_getprop(DDI_DEV_T_ANY, child, DDI_PROP_NOTPROM, 966 "pcix-update-cmd-reg", -1); 967 968 if (n != -1) { 969 extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value); 970 DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ " 971 "Workaround: value = %x\n", n); 972 pcix_set_cmd_reg(child, n); 973 } 974 pci_config_teardown(&config_handle); 975 return (DDI_SUCCESS); 976 } 977 978 static void 979 ppb_uninitchild(dev_info_t *child) 980 { 981 ppb_devstate_t *ppb; 982 983 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 984 ddi_get_instance(ddi_get_parent(child))); 985 986 /* 987 * SG OPL FMA specific 988 */ 989 if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) 990 pcie_fini_bus(child); 991 992 ppb_removechild(child); 993 } 994 995 static void 996 ppb_removechild(dev_info_t *dip) 997 { 998 ppb_devstate_t *ppb; 999 1000 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1001 ddi_get_instance(ddi_get_parent(dip))); 1002 1003 if (PM_CAPABLE(ppb->ppb_pwr_p)) { 1004 1005 DEBUG2(DBG_PWR, ddi_get_parent(dip), 1006 "UNINITCHILD: removing pwr_info for %s@%s\n", 1007 ddi_node_name(dip), ddi_get_name_addr(dip)); 1008 pci_pwr_rm_info(ppb->ppb_pwr_p, dip); 1009 } 1010 1011 ddi_set_name_addr(dip, NULL); 1012 1013 /* 1014 * Strip the node to properly convert it back to prototype form 1015 */ 1016 ddi_remove_minor_node(dip, NULL); 1017 1018 impl_rem_dev_props(dip); 1019 } 1020 1021 /* 1022 * If bridge is PM capable, set up PM state for nexus. 1023 */ 1024 static void 1025 ppb_pwr_setup(ppb_devstate_t *ppb, dev_info_t *pdip) 1026 { 1027 char *comp_array[5]; 1028 int i; 1029 ddi_acc_handle_t conf_hdl; 1030 uint8_t pmcsr_bse; 1031 uint16_t pmcap; 1032 1033 /* 1034 * Determine if bridge is PM capable. If not, leave ppb_pwr_p NULL 1035 * and return. 1036 */ 1037 if (pci_config_setup(pdip, &ppb->ppb_conf_hdl) != DDI_SUCCESS) { 1038 1039 return; 1040 } 1041 1042 conf_hdl = ppb->ppb_conf_hdl; 1043 1044 /* 1045 * Locate and store the power management cap_ptr for future references. 1046 */ 1047 if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &ppb->ppb_pm_cap_ptr)) 1048 == DDI_FAILURE) { 1049 DEBUG0(DBG_PWR, pdip, "bridge does not support PM. PCI" 1050 " PM data structure not found in config header\n"); 1051 pci_config_teardown(&conf_hdl); 1052 1053 return; 1054 } 1055 1056 /* 1057 * Allocate PM state structure for ppb. 1058 */ 1059 ppb->ppb_pwr_p = (pci_pwr_t *) 1060 kmem_zalloc(sizeof (pci_pwr_t), KM_SLEEP); 1061 ppb->ppb_pwr_p->pwr_fp = 0; 1062 1063 pmcsr_bse = PCI_CAP_GET8(conf_hdl, NULL, ppb->ppb_pm_cap_ptr, 1064 PCI_PMCSR_BSE); 1065 1066 pmcap = PCI_CAP_GET16(conf_hdl, NULL, ppb->ppb_pm_cap_ptr, 1067 PCI_PMCAP); 1068 1069 if (pmcap == PCI_CAP_EINVAL16 || pmcsr_bse == PCI_CAP_EINVAL8) { 1070 pci_config_teardown(&conf_hdl); 1071 return; 1072 } 1073 1074 if (pmcap & PCI_PMCAP_D1) { 1075 DEBUG0(DBG_PWR, pdip, "setup: B1 state supported\n"); 1076 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B1_CAPABLE; 1077 } else { 1078 DEBUG0(DBG_PWR, pdip, "setup: B1 state NOT supported\n"); 1079 } 1080 if (pmcap & PCI_PMCAP_D2) { 1081 DEBUG0(DBG_PWR, pdip, "setup: B2 state supported\n"); 1082 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE; 1083 } else { 1084 DEBUG0(DBG_PWR, pdip, "setup: B2 via D2 NOT supported\n"); 1085 } 1086 1087 if (pmcsr_bse & PCI_PMCSR_BSE_BPCC_EN) { 1088 DEBUG0(DBG_PWR, pdip, 1089 "setup: bridge power/clock control enable\n"); 1090 } else { 1091 DEBUG0(DBG_PWR, pdip, 1092 "setup: bridge power/clock control disabled\n"); 1093 1094 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1095 ppb->ppb_pwr_p = NULL; 1096 pci_config_teardown(&conf_hdl); 1097 1098 return; 1099 } 1100 1101 /* 1102 * PCI states D0 and D3 always are supported for normal PCI 1103 * devices. D1 and D2 are optional which are checked for above. 1104 * Bridge function states D0-D3 correspond to secondary bus states 1105 * B0-B3, EXCEPT if PCI_PMCSR_BSE_B2_B3 is set. In this case, setting 1106 * the bridge function to D3 will set the bridge bus to state B2 instead 1107 * of B3. D2 will not correspond to B2 (and in fact, probably 1108 * won't be D2 capable). Implicitly, this means that if 1109 * PCI_PMCSR_BSE_B2_B3 is set, the bus will not be B3 capable. 1110 */ 1111 if (pmcsr_bse & PCI_PMCSR_BSE_B2_B3) { 1112 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B2_CAPABLE; 1113 DEBUG0(DBG_PWR, pdip, "B2 supported via D3\n"); 1114 } else { 1115 ppb->ppb_pwr_p->pwr_flags |= PCI_PWR_B3_CAPABLE; 1116 DEBUG0(DBG_PWR, pdip, "B3 supported via D3\n"); 1117 } 1118 1119 ppb->ppb_pwr_p->pwr_dip = pdip; 1120 mutex_init(&ppb->ppb_pwr_p->pwr_mutex, NULL, MUTEX_DRIVER, NULL); 1121 1122 i = 0; 1123 comp_array[i++] = "NAME=PCI bridge PM"; 1124 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) { 1125 comp_array[i++] = "0=Clock/Power Off (B3)"; 1126 } 1127 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) { 1128 comp_array[i++] = "1=Clock Off (B2)"; 1129 } 1130 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) { 1131 comp_array[i++] = "2=Bus Inactive (B1)"; 1132 } 1133 comp_array[i++] = "3=Full Power (B0)"; 1134 1135 /* 1136 * Create pm-components property. It does not already exist. 1137 */ 1138 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, pdip, 1139 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) { 1140 cmn_err(CE_WARN, 1141 "%s%d pm-components prop update failed", 1142 ddi_driver_name(pdip), ddi_get_instance(pdip)); 1143 pci_config_teardown(&conf_hdl); 1144 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1145 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1146 ppb->ppb_pwr_p = NULL; 1147 1148 return; 1149 } 1150 1151 if (ddi_prop_create(DDI_DEV_T_NONE, pdip, DDI_PROP_CANSLEEP, 1152 "pm-want-child-notification?", NULL, NULL) != DDI_PROP_SUCCESS) { 1153 cmn_err(CE_WARN, 1154 "%s%d fail to create pm-want-child-notification? prop", 1155 ddi_driver_name(pdip), ddi_get_instance(pdip)); 1156 1157 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, "pm-components"); 1158 pci_config_teardown(&conf_hdl); 1159 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1160 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1161 ppb->ppb_pwr_p = NULL; 1162 1163 return; 1164 } 1165 1166 ppb->ppb_pwr_p->current_lvl = 1167 pci_pwr_current_lvl(ppb->ppb_pwr_p); 1168 } 1169 1170 /* 1171 * Remove PM state for nexus. 1172 */ 1173 static void 1174 ppb_pwr_teardown(ppb_devstate_t *ppb, dev_info_t *dip) 1175 { 1176 int low_lvl; 1177 1178 /* 1179 * Determine the lowest power level supported. 1180 */ 1181 if (ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) { 1182 low_lvl = PM_LEVEL_B3; 1183 } else { 1184 low_lvl = PM_LEVEL_B2; 1185 } 1186 1187 if (pm_lower_power(dip, PCI_PM_COMP_0, low_lvl) != DDI_SUCCESS) { 1188 cmn_err(CE_WARN, "%s%d failed to lower power", 1189 ddi_driver_name(dip), ddi_get_instance(dip)); 1190 } 1191 1192 pci_config_teardown(&ppb->ppb_conf_hdl); 1193 mutex_destroy(&ppb->ppb_pwr_p->pwr_mutex); 1194 kmem_free(ppb->ppb_pwr_p, sizeof (pci_pwr_t)); 1195 1196 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components") != 1197 DDI_PROP_SUCCESS) { 1198 cmn_err(CE_WARN, "%s%d unable to remove prop pm-components", 1199 ddi_driver_name(dip), ddi_get_instance(dip)); 1200 } 1201 1202 if (ddi_prop_remove(DDI_DEV_T_NONE, dip, 1203 "pm-want-child-notification?") != DDI_PROP_SUCCESS) { 1204 cmn_err(CE_WARN, 1205 "%s%d unable to remove prop pm-want_child_notification?", 1206 ddi_driver_name(dip), ddi_get_instance(dip)); 1207 } 1208 } 1209 1210 /* 1211 * Examine the pmcsr register and return the software defined 1212 * state (the difference being whether D3 means B2 or B3). 1213 */ 1214 int 1215 pci_pwr_current_lvl(pci_pwr_t *pwr_p) 1216 { 1217 ppb_devstate_t *ppb; 1218 uint16_t pmcsr; 1219 1220 /* 1221 * Find out current power level 1222 */ 1223 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1224 ddi_get_instance(pwr_p->pwr_dip)); 1225 1226 if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL, 1227 ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16) 1228 return (DDI_FAILURE); 1229 1230 switch (pmcsr & PCI_PMCSR_STATE_MASK) { 1231 case PCI_PMCSR_D0: 1232 1233 return (PM_LEVEL_B0); 1234 case PCI_PMCSR_D1: 1235 1236 return (PM_LEVEL_B1); 1237 case PCI_PMCSR_D2: 1238 1239 return (PM_LEVEL_B2); 1240 case PCI_PMCSR_D3HOT: 1241 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1242 1243 return (PM_LEVEL_B2); 1244 } else { 1245 1246 return (PM_LEVEL_B3); 1247 } 1248 } 1249 /*NOTREACHED*/ 1250 return (PM_LEVEL_B3); 1251 } 1252 1253 /* 1254 * Power entry point. Called by the PM framework to change the 1255 * current power state of the bus. This function must first verify that 1256 * the requested power change is still valid. 1257 */ 1258 /*ARGSUSED*/ 1259 static int 1260 ppb_pwr(dev_info_t *dip, int component, int lvl) 1261 { 1262 ppb_devstate_t *ppb; 1263 uint16_t pmcsr; 1264 char *str; 1265 int lowest_lvl; 1266 int old_lvl; 1267 int new_lvl; 1268 1269 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1270 ddi_get_instance(dip)); 1271 if (ppb == NULL) { 1272 cmn_err(CE_WARN, "%s%d ppb_pwr: can't get soft state", 1273 ddi_driver_name(dip), ddi_get_instance(dip)); 1274 1275 return (DDI_FAILURE); 1276 } 1277 1278 DEBUG1(DBG_PWR, dip, "ppb_pwr(): ENTER level = %d\n", lvl); 1279 1280 mutex_enter(&ppb->ppb_pwr_p->pwr_mutex); 1281 1282 /* 1283 * Find out if the power setting is possible. If it is not, 1284 * set component busy and return failure. If it is possible, 1285 * and it is the lowest pwr setting possible, set component 1286 * busy so that the framework does not try to lower any further. 1287 */ 1288 lowest_lvl = pci_pwr_new_lvl(ppb->ppb_pwr_p); 1289 if (lowest_lvl > lvl) { 1290 pci_pwr_component_busy(ppb->ppb_pwr_p); 1291 DEBUG2(DBG_PWR, dip, "ppb_pwr: failing power request " 1292 "lowest allowed is %d requested is %d\n", 1293 lowest_lvl, lvl); 1294 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1295 1296 return (DDI_FAILURE); 1297 } else if (lowest_lvl == lvl) { 1298 pci_pwr_component_busy(ppb->ppb_pwr_p); 1299 } else { 1300 pci_pwr_component_idle(ppb->ppb_pwr_p); 1301 } 1302 1303 if ((pmcsr = PCI_CAP_GET16(ppb->ppb_conf_hdl, NULL, 1304 ppb->ppb_pm_cap_ptr, PCI_PMCSR)) == PCI_CAP_EINVAL16) 1305 return (DDI_FAILURE); 1306 1307 /* 1308 * Save the current power level. This is the actual function level, 1309 * not the translated bridge level stored in pwr_p->current_lvl 1310 */ 1311 old_lvl = pmcsr & PCI_PMCSR_STATE_MASK; 1312 1313 pmcsr &= ~PCI_PMCSR_STATE_MASK; 1314 switch (lvl) { 1315 case PM_LEVEL_B0: 1316 str = "PM_LEVEL_B0 (full speed)"; 1317 pmcsr |= PCI_PMCSR_D0; 1318 break; 1319 case PM_LEVEL_B1: 1320 str = "PM_LEVEL_B1 (light sleep. No bus traffic allowed)"; 1321 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B1_CAPABLE) == 0) { 1322 cmn_err(CE_WARN, "%s%d PCI PM state B1 not supported", 1323 ddi_driver_name(dip), ddi_get_instance(dip)); 1324 1325 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1326 return (DDI_FAILURE); 1327 } 1328 pmcsr |= PCI_PMCSR_D1; 1329 break; 1330 case PM_LEVEL_B2: 1331 str = "PM_LEVEL_B2 (clock off)"; 1332 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B2_CAPABLE) == 0) { 1333 cmn_err(CE_WARN, "%s%d PM state B2 not supported...", 1334 ddi_driver_name(dip), 1335 ddi_get_instance(dip)); 1336 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1337 1338 return (DDI_FAILURE); 1339 } 1340 1341 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1342 /* 1343 * If B3 isn't supported, use D3 for B2 to avoid the 1344 * possible case that D2 for B2 isn't supported. 1345 * Saves and extra check and state flag.. 1346 */ 1347 pmcsr |= PCI_PMCSR_D3HOT; 1348 } else { 1349 pmcsr |= PCI_PMCSR_D2; 1350 } 1351 break; 1352 case PM_LEVEL_B3: 1353 str = "PM_LEVEL_B30 (clock and power off)"; 1354 if ((ppb->ppb_pwr_p->pwr_flags & PCI_PWR_B3_CAPABLE) == 0) { 1355 cmn_err(CE_WARN, "%s%d PM state B3 not supported...", 1356 ddi_driver_name(dip), 1357 ddi_get_instance(dip)); 1358 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1359 1360 return (DDI_FAILURE); 1361 } 1362 pmcsr |= PCI_PMCSR_D3HOT; 1363 1364 break; 1365 1366 default: 1367 cmn_err(CE_WARN, "%s%d Unknown PM state %d", 1368 ddi_driver_name(dip), ddi_get_instance(dip), lvl); 1369 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1370 1371 return (DDI_FAILURE); 1372 } 1373 1374 new_lvl = pmcsr & PCI_PMCSR_STATE_MASK; 1375 1376 /* 1377 * Save config regs if going into HW state D3 (B2 or B3) 1378 */ 1379 if ((old_lvl != PCI_PMCSR_D3HOT) && (new_lvl == PCI_PMCSR_D3HOT)) { 1380 DEBUG0(DBG_PWR, dip, "ppb_pwr(): SAVING CONFIG REGS\n"); 1381 if (pci_save_config_regs(dip) != DDI_SUCCESS) { 1382 cmn_err(CE_WARN, "%s%d Save config regs failed", 1383 ddi_driver_name(dip), ddi_get_instance(dip)); 1384 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1385 1386 return (DDI_FAILURE); 1387 } 1388 } 1389 1390 PCI_CAP_PUT16(ppb->ppb_conf_hdl, NULL, ppb->ppb_pm_cap_ptr, PCI_PMCSR, 1391 pmcsr); 1392 1393 /* 1394 * No bus transactions should occur without waiting for 1395 * settle time specified in PCI PM spec rev 2.1 sec 5.6.1 1396 * To make things simple, just use the max time specified for 1397 * all state transitions. 1398 */ 1399 delay(drv_usectohz(PCI_CLK_SETTLE_TIME)); 1400 1401 /* 1402 * Restore configuration registers if coming out of HW state D3 1403 */ 1404 if ((old_lvl == PCI_PMCSR_D3HOT) && (new_lvl != PCI_PMCSR_D3HOT)) { 1405 DEBUG0(DBG_PWR, dip, "ppb_pwr(): RESTORING CONFIG REGS\n"); 1406 if (pci_restore_config_regs(dip) != DDI_SUCCESS) { 1407 panic("%s%d restore config regs failed", 1408 ddi_driver_name(dip), ddi_get_instance(dip)); 1409 } 1410 /*NOTREACHED*/ 1411 } 1412 1413 ppb->ppb_pwr_p->current_lvl = lvl; 1414 1415 mutex_exit(&ppb->ppb_pwr_p->pwr_mutex); 1416 1417 DEBUG1(DBG_PWR, dip, "ppb_set_pwr: set PM state to %s\n\n", str); 1418 1419 return (DDI_SUCCESS); 1420 } 1421 1422 /* 1423 * Initialize hotplug framework if we are hotpluggable. 1424 * Sets flag in the soft state if Hot Plug is supported and initialized 1425 * properly. 1426 */ 1427 /*ARGSUSED*/ 1428 static void 1429 ppb_init_hotplug(ppb_devstate_t *ppb) 1430 { 1431 if (ddi_prop_exists(DDI_DEV_T_ANY, ppb->dip, DDI_PROP_DONTPASS, 1432 "hotplug-capable")) { 1433 (void) modload("misc", "pcihp"); 1434 1435 if (pcihp_init(ppb->dip) != DDI_SUCCESS) { 1436 cmn_err(CE_WARN, 1437 "%s #%d: Failed setting hotplug framework", 1438 ddi_driver_name(ppb->dip), 1439 ddi_get_instance(ppb->dip)); 1440 } else 1441 ppb->hotplug_capable = B_TRUE; 1442 } 1443 1444 } 1445 1446 static void 1447 ppb_create_ranges_prop(dev_info_t *dip, 1448 ddi_acc_handle_t config_handle) 1449 { 1450 uint32_t base, limit; 1451 ppb_ranges_t ranges[PPB_RANGE_LEN]; 1452 uint8_t io_base_lo, io_limit_lo; 1453 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit; 1454 int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int); 1455 1456 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW); 1457 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW); 1458 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI); 1459 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI); 1460 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE); 1461 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT); 1462 1463 /* 1464 * Create ranges for IO space 1465 */ 1466 ranges[i].size_low = ranges[i].size_high = 0; 1467 ranges[i].parent_mid = ranges[i].child_mid = 1468 ranges[i].parent_high = 0; 1469 ranges[i].child_high = ranges[i].parent_high |= 1470 (PCI_REG_REL_M | PCI_ADDR_IO); 1471 base = PPB_16bit_IOADDR(io_base_lo); 1472 limit = PPB_16bit_IOADDR(io_limit_lo); 1473 1474 if ((io_base_lo & 0xf) == PPB_32BIT_IO) { 1475 base = PPB_LADDR(base, io_base_hi); 1476 } 1477 if ((io_limit_lo & 0xf) == PPB_32BIT_IO) { 1478 limit = PPB_LADDR(limit, io_limit_hi); 1479 } 1480 1481 if ((io_base_lo & PPB_32BIT_IO) && (io_limit_hi > 0)) { 1482 base = PPB_LADDR(base, io_base_hi); 1483 limit = PPB_LADDR(limit, io_limit_hi); 1484 } 1485 1486 /* 1487 * Create ranges for 32bit memory space 1488 */ 1489 base = PPB_32bit_MEMADDR(mem_base); 1490 limit = PPB_32bit_MEMADDR(mem_limit); 1491 ranges[i].size_low = ranges[i].size_high = 0; 1492 ranges[i].parent_mid = ranges[i].child_mid = 1493 ranges[i].parent_high = 0; 1494 ranges[i].child_high = ranges[i].parent_high |= 1495 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1496 ranges[i].child_low = ranges[i].parent_low = base; 1497 if (limit >= base) { 1498 ranges[i].size_low = limit - base + PPB_MEMGRAIN; 1499 i++; 1500 } 1501 1502 if (i) { 1503 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 1504 (int *)ranges, i * rangelen); 1505 } 1506 } 1507 1508 /* ARGSUSED */ 1509 static int 1510 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 1511 { 1512 ppb_devstate_t *ppb_p; 1513 minor_t minor = getminor(*devp); 1514 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1515 1516 /* 1517 * Make sure the open is for the right file type. 1518 */ 1519 if (otyp != OTYP_CHR) 1520 return (EINVAL); 1521 1522 /* 1523 * Get the soft state structure for the device. 1524 */ 1525 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1526 instance); 1527 1528 if (ppb_p == NULL) 1529 return (ENXIO); 1530 1531 if (ppb_p->hotplug_capable == B_TRUE) 1532 return ((pcihp_get_cb_ops())->cb_open(devp, flags, 1533 otyp, credp)); 1534 1535 /* 1536 * Handle the open by tracking the device state. 1537 */ 1538 mutex_enter(&ppb_p->ppb_mutex); 1539 if (flags & FEXCL) { 1540 if (ppb_p->ppb_soft_state != PPB_SOFT_STATE_CLOSED) { 1541 mutex_exit(&ppb_p->ppb_mutex); 1542 return (EBUSY); 1543 } 1544 ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN_EXCL; 1545 } else { 1546 if (ppb_p->ppb_soft_state == PPB_SOFT_STATE_OPEN_EXCL) { 1547 mutex_exit(&ppb_p->ppb_mutex); 1548 return (EBUSY); 1549 } 1550 ppb_p->ppb_soft_state = PPB_SOFT_STATE_OPEN; 1551 } 1552 mutex_exit(&ppb_p->ppb_mutex); 1553 return (0); 1554 } 1555 1556 1557 /* ARGSUSED */ 1558 static int 1559 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp) 1560 { 1561 ppb_devstate_t *ppb_p; 1562 minor_t minor = getminor(dev); 1563 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1564 1565 if (otyp != OTYP_CHR) 1566 return (EINVAL); 1567 1568 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1569 instance); 1570 1571 if (ppb_p == NULL) 1572 return (ENXIO); 1573 1574 if (ppb_p->hotplug_capable == B_TRUE) 1575 return ((pcihp_get_cb_ops())->cb_close(dev, flags, 1576 otyp, credp)); 1577 1578 mutex_enter(&ppb_p->ppb_mutex); 1579 ppb_p->ppb_soft_state = PPB_SOFT_STATE_CLOSED; 1580 mutex_exit(&ppb_p->ppb_mutex); 1581 return (0); 1582 } 1583 1584 1585 /* 1586 * ppb_ioctl: devctl hotplug controls 1587 */ 1588 /* ARGSUSED */ 1589 static int 1590 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1591 int *rvalp) 1592 { 1593 ppb_devstate_t *ppb_p; 1594 dev_info_t *self; 1595 struct devctl_iocdata *dcp; 1596 uint_t bus_state; 1597 int rv = 0; 1598 minor_t minor = getminor(dev); 1599 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1600 1601 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1602 instance); 1603 1604 if (ppb_p == NULL) 1605 return (ENXIO); 1606 1607 if (ppb_p->hotplug_capable == B_TRUE) 1608 return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, 1609 arg, mode, credp, rvalp)); 1610 1611 self = ppb_p->dip; 1612 1613 /* 1614 * We can use the generic implementation for these ioctls 1615 */ 1616 switch (cmd) { 1617 case DEVCTL_DEVICE_GETSTATE: 1618 case DEVCTL_DEVICE_ONLINE: 1619 case DEVCTL_DEVICE_OFFLINE: 1620 case DEVCTL_BUS_GETSTATE: 1621 return (ndi_devctl_ioctl(self, cmd, arg, mode, 0)); 1622 } 1623 1624 /* 1625 * read devctl ioctl data 1626 */ 1627 if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) 1628 return (EFAULT); 1629 1630 switch (cmd) { 1631 1632 case DEVCTL_DEVICE_RESET: 1633 rv = ENOTSUP; 1634 break; 1635 1636 case DEVCTL_BUS_QUIESCE: 1637 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1638 if (bus_state == BUS_QUIESCED) 1639 break; 1640 (void) ndi_set_bus_state(self, BUS_QUIESCED); 1641 break; 1642 1643 case DEVCTL_BUS_UNQUIESCE: 1644 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1645 if (bus_state == BUS_ACTIVE) 1646 break; 1647 (void) ndi_set_bus_state(self, BUS_ACTIVE); 1648 break; 1649 1650 case DEVCTL_BUS_RESET: 1651 rv = ENOTSUP; 1652 break; 1653 1654 case DEVCTL_BUS_RESETALL: 1655 rv = ENOTSUP; 1656 break; 1657 1658 default: 1659 rv = ENOTTY; 1660 } 1661 1662 ndi_dc_freehdl(dcp); 1663 return (rv); 1664 } 1665 1666 static int ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 1667 int flags, char *name, caddr_t valuep, int *lengthp) 1668 { 1669 ppb_devstate_t *ppb_p; 1670 minor_t minor = getminor(dev); 1671 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1672 1673 ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1674 instance); 1675 1676 if (ppb_p == NULL) 1677 return (ENXIO); 1678 1679 if (ppb_p->hotplug_capable == B_TRUE) 1680 return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, 1681 flags, name, valuep, lengthp)); 1682 1683 return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp)); 1684 } 1685 1686 /* 1687 * Initialize our FMA resources 1688 */ 1689 static void 1690 ppb_fm_init(ppb_devstate_t *ppb_p) 1691 { 1692 dev_info_t *root = ddi_root_node(); 1693 dev_info_t *pdip; 1694 char *bus; 1695 1696 ppb_p->fm_cap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 1697 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 1698 1699 /* 1700 * Request our capability level and get our parents capability 1701 * and ibc. 1702 */ 1703 ddi_fm_init(ppb_p->dip, &ppb_p->fm_cap, &ppb_p->fm_ibc); 1704 ASSERT((ppb_p->fm_cap & DDI_FM_EREPORT_CAPABLE) && 1705 (ppb_p->fm_cap & DDI_FM_ERRCB_CAPABLE)); 1706 1707 pci_ereport_setup(ppb_p->dip); 1708 1709 /* 1710 * Register error callback with our parent. 1711 */ 1712 ddi_fm_handler_register(ppb_p->dip, ppb_err_callback, NULL); 1713 1714 ppb_p->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO; 1715 for (pdip = ddi_get_parent(ppb_p->dip); pdip && (pdip != root) && 1716 (ppb_p->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV); 1717 pdip = ddi_get_parent(pdip)) { 1718 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, 1719 DDI_PROP_DONTPASS, "device_type", &bus) != 1720 DDI_PROP_SUCCESS) 1721 break; 1722 1723 if (strcmp(bus, "pciex") == 0) 1724 ppb_p->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCIE_DEV; 1725 1726 ddi_prop_free(bus); 1727 } 1728 } 1729 1730 /* 1731 * Breakdown our FMA resources 1732 */ 1733 static void 1734 ppb_fm_fini(ppb_devstate_t *ppb_p) 1735 { 1736 /* 1737 * Clean up allocated fm structures 1738 */ 1739 ddi_fm_handler_unregister(ppb_p->dip); 1740 pci_ereport_teardown(ppb_p->dip); 1741 ddi_fm_fini(ppb_p->dip); 1742 } 1743 1744 /* 1745 * Initialize FMA resources for children devices. Called when 1746 * child calls ddi_fm_init(). 1747 */ 1748 /*ARGSUSED*/ 1749 static int 1750 ppb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 1751 ddi_iblock_cookie_t *ibc) 1752 { 1753 ppb_devstate_t *ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1754 ddi_get_instance(dip)); 1755 *ibc = ppb_p->fm_ibc; 1756 return (ppb_p->fm_cap); 1757 } 1758 1759 /* 1760 * FMA registered error callback 1761 */ 1762 static int 1763 ppb_err_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *impl_data) 1764 { 1765 ppb_devstate_t *ppb_p = (ppb_devstate_t *)ddi_get_soft_state(ppb_state, 1766 ddi_get_instance(dip)); 1767 1768 /* 1769 * errors handled by SPARC PCI-E framework for PCIe platforms 1770 */ 1771 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) 1772 return (DDI_FM_OK); 1773 1774 /* 1775 * do the following for SPARC PCI platforms 1776 */ 1777 ASSERT(impl_data == NULL); 1778 pci_ereport_post(dip, derr, NULL); 1779 return (derr->fme_status); 1780 } 1781 1782 static void 1783 ppb_bus_enter(dev_info_t *dip, ddi_acc_handle_t handle) 1784 { 1785 i_ndi_busop_access_enter(dip, handle); 1786 } 1787 1788 /* ARGSUSED */ 1789 static void 1790 ppb_bus_exit(dev_info_t *dip, ddi_acc_handle_t handle) 1791 { 1792 i_ndi_busop_access_exit(dip, handle); 1793 } 1794