1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 * 25 * Assembly code support for the Olympus-C module 26 */ 27 28#pragma ident "%Z%%M% %I% %E% SMI" 29 30#if !defined(lint) 31#include "assym.h" 32#endif /* lint */ 33 34#include <sys/asm_linkage.h> 35#include <sys/mmu.h> 36#include <vm/hat_sfmmu.h> 37#include <sys/machparam.h> 38#include <sys/machcpuvar.h> 39#include <sys/machthread.h> 40#include <sys/machtrap.h> 41#include <sys/privregs.h> 42#include <sys/asm_linkage.h> 43#include <sys/trap.h> 44#include <sys/opl_olympus_regs.h> 45#include <sys/opl_module.h> 46#include <sys/xc_impl.h> 47#include <sys/intreg.h> 48#include <sys/async.h> 49#include <sys/clock.h> 50#include <sys/cmpregs.h> 51 52#ifdef TRAPTRACE 53#include <sys/traptrace.h> 54#endif /* TRAPTRACE */ 55 56/* 57 * Macro that flushes the entire Ecache. 58 * 59 * arg1 = ecache size 60 * arg2 = ecache linesize 61 * arg3 = ecache flush address - Not used for olympus-C 62 */ 63#define ECACHE_FLUSHALL(arg1, arg2, arg3, tmp1) \ 64 mov ASI_L2_CTRL_U2_FLUSH, arg1; \ 65 mov ASI_L2_CTRL_RW_ADDR, arg2; \ 66 stxa arg1, [arg2]ASI_L2_CTRL 67 68/* 69 * SPARC64-VI MMU and Cache operations. 70 */ 71 72#if defined(lint) 73 74/* ARGSUSED */ 75void 76vtag_flushpage(caddr_t vaddr, uint64_t sfmmup) 77{} 78 79#else /* lint */ 80 81 ENTRY_NP(vtag_flushpage) 82 /* 83 * flush page from the tlb 84 * 85 * %o0 = vaddr 86 * %o1 = sfmmup 87 */ 88 rdpr %pstate, %o5 89#ifdef DEBUG 90 PANIC_IF_INTR_DISABLED_PSTR(%o5, opl_di_l3, %g1) 91#endif /* DEBUG */ 92 /* 93 * disable ints 94 */ 95 andn %o5, PSTATE_IE, %o4 96 wrpr %o4, 0, %pstate 97 98 /* 99 * Then, blow out the tlb 100 * Interrupts are disabled to prevent the primary ctx register 101 * from changing underneath us. 102 */ 103 sethi %hi(ksfmmup), %o3 104 ldx [%o3 + %lo(ksfmmup)], %o3 105 cmp %o3, %o1 106 bne,pt %xcc, 1f ! if not kernel as, go to 1 107 sethi %hi(FLUSH_ADDR), %o3 108 /* 109 * For Kernel demaps use primary. type = page implicitly 110 */ 111 stxa %g0, [%o0]ASI_DTLB_DEMAP /* dmmu flush for KCONTEXT */ 112 stxa %g0, [%o0]ASI_ITLB_DEMAP /* immu flush for KCONTEXT */ 113 flush %o3 114 retl 115 wrpr %g0, %o5, %pstate /* enable interrupts */ 1161: 117 /* 118 * User demap. We need to set the primary context properly. 119 * Secondary context cannot be used for SPARC64-VI IMMU. 120 * %o0 = vaddr 121 * %o1 = sfmmup 122 * %o3 = FLUSH_ADDR 123 */ 124 SFMMU_CPU_CNUM(%o1, %g1, %g2) ! %g1 = sfmmu cnum on this CPU 125 126 ldub [%o1 + SFMMU_CEXT], %o4 ! %o4 = sfmmup->sfmmu_cext 127 sll %o4, CTXREG_EXT_SHIFT, %o4 128 or %g1, %o4, %g1 ! %g1 = pgsz | cnum 129 130 wrpr %g0, 1, %tl 131 set MMU_PCONTEXT, %o4 132 or DEMAP_PRIMARY | DEMAP_PAGE_TYPE, %o0, %o0 133 ldxa [%o4]ASI_DMMU, %o2 ! %o2 = save old ctxnum 134 stxa %g1, [%o4]ASI_DMMU ! wr new ctxum 135 136 stxa %g0, [%o0]ASI_DTLB_DEMAP 137 stxa %g0, [%o0]ASI_ITLB_DEMAP 138 stxa %o2, [%o4]ASI_DMMU /* restore old ctxnum */ 139 flush %o3 140 wrpr %g0, 0, %tl 141 142 retl 143 wrpr %g0, %o5, %pstate /* enable interrupts */ 144 SET_SIZE(vtag_flushpage) 145 146#endif /* lint */ 147 148 149#if defined(lint) 150 151void 152vtag_flushall(void) 153{} 154 155#else /* lint */ 156 157 ENTRY_NP2(vtag_flushall, demap_all) 158 /* 159 * flush the tlb 160 */ 161 sethi %hi(FLUSH_ADDR), %o3 162 set DEMAP_ALL_TYPE, %g1 163 stxa %g0, [%g1]ASI_DTLB_DEMAP 164 stxa %g0, [%g1]ASI_ITLB_DEMAP 165 flush %o3 166 retl 167 nop 168 SET_SIZE(demap_all) 169 SET_SIZE(vtag_flushall) 170 171#endif /* lint */ 172 173 174#if defined(lint) 175 176/* ARGSUSED */ 177void 178vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup) 179{} 180 181#else /* lint */ 182 183 ENTRY_NP(vtag_flushpage_tl1) 184 /* 185 * x-trap to flush page from tlb and tsb 186 * 187 * %g1 = vaddr, zero-extended on 32-bit kernel 188 * %g2 = sfmmup 189 * 190 * assumes TSBE_TAG = 0 191 */ 192 srln %g1, MMU_PAGESHIFT, %g1 193 194 sethi %hi(ksfmmup), %g3 195 ldx [%g3 + %lo(ksfmmup)], %g3 196 cmp %g3, %g2 197 bne,pt %xcc, 1f ! if not kernel as, go to 1 198 slln %g1, MMU_PAGESHIFT, %g1 /* g1 = vaddr */ 199 200 /* We need to demap in the kernel context */ 201 or DEMAP_NUCLEUS | DEMAP_PAGE_TYPE, %g1, %g1 202 stxa %g0, [%g1]ASI_DTLB_DEMAP 203 stxa %g0, [%g1]ASI_ITLB_DEMAP 204 retry 2051: 206 /* We need to demap in a user context */ 207 or DEMAP_PRIMARY | DEMAP_PAGE_TYPE, %g1, %g1 208 209 SFMMU_CPU_CNUM(%g2, %g6, %g3) ! %g6 = sfmmu cnum on this CPU 210 211 ldub [%g2 + SFMMU_CEXT], %g4 ! %g4 = sfmmup->cext 212 sll %g4, CTXREG_EXT_SHIFT, %g4 213 or %g6, %g4, %g6 ! %g6 = pgsz | cnum 214 215 set MMU_PCONTEXT, %g4 216 ldxa [%g4]ASI_DMMU, %g5 /* rd old ctxnum */ 217 stxa %g6, [%g4]ASI_DMMU /* wr new ctxum */ 218 stxa %g0, [%g1]ASI_DTLB_DEMAP 219 stxa %g0, [%g1]ASI_ITLB_DEMAP 220 stxa %g5, [%g4]ASI_DMMU /* restore old ctxnum */ 221 retry 222 SET_SIZE(vtag_flushpage_tl1) 223 224#endif /* lint */ 225 226 227#if defined(lint) 228 229/* ARGSUSED */ 230void 231vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt) 232{} 233 234#else /* lint */ 235 236 ENTRY_NP(vtag_flush_pgcnt_tl1) 237 /* 238 * x-trap to flush pgcnt MMU_PAGESIZE pages from tlb 239 * 240 * %g1 = vaddr, zero-extended on 32-bit kernel 241 * %g2 = <sfmmup58|pgcnt6> 242 * 243 * NOTE: this handler relies on the fact that no 244 * interrupts or traps can occur during the loop 245 * issuing the TLB_DEMAP operations. It is assumed 246 * that interrupts are disabled and this code is 247 * fetching from the kernel locked text address. 248 * 249 * assumes TSBE_TAG = 0 250 */ 251 set SFMMU_PGCNT_MASK, %g4 252 and %g4, %g2, %g3 /* g3 = pgcnt - 1 */ 253 add %g3, 1, %g3 /* g3 = pgcnt */ 254 255 andn %g2, SFMMU_PGCNT_MASK, %g2 /* g2 = sfmmup */ 256 srln %g1, MMU_PAGESHIFT, %g1 257 258 sethi %hi(ksfmmup), %g4 259 ldx [%g4 + %lo(ksfmmup)], %g4 260 cmp %g4, %g2 261 bne,pn %xcc, 1f /* if not kernel as, go to 1 */ 262 slln %g1, MMU_PAGESHIFT, %g1 /* g1 = vaddr */ 263 264 /* We need to demap in the kernel context */ 265 or DEMAP_NUCLEUS | DEMAP_PAGE_TYPE, %g1, %g1 266 set MMU_PAGESIZE, %g2 /* g2 = pgsize */ 267 sethi %hi(FLUSH_ADDR), %g5 2684: 269 stxa %g0, [%g1]ASI_DTLB_DEMAP 270 stxa %g0, [%g1]ASI_ITLB_DEMAP 271 flush %g5 ! flush required by immu 272 273 deccc %g3 /* decr pgcnt */ 274 bnz,pt %icc,4b 275 add %g1, %g2, %g1 /* next page */ 276 retry 2771: 278 /* 279 * We need to demap in a user context 280 * 281 * g2 = sfmmup 282 * g3 = pgcnt 283 */ 284 SFMMU_CPU_CNUM(%g2, %g5, %g6) ! %g5 = sfmmu cnum on this CPU 285 286 or DEMAP_PRIMARY | DEMAP_PAGE_TYPE, %g1, %g1 287 288 ldub [%g2 + SFMMU_CEXT], %g4 ! %g4 = sfmmup->cext 289 sll %g4, CTXREG_EXT_SHIFT, %g4 290 or %g5, %g4, %g5 291 292 set MMU_PCONTEXT, %g4 293 ldxa [%g4]ASI_DMMU, %g6 /* rd old ctxnum */ 294 stxa %g5, [%g4]ASI_DMMU /* wr new ctxum */ 295 296 set MMU_PAGESIZE, %g2 /* g2 = pgsize */ 297 sethi %hi(FLUSH_ADDR), %g5 2983: 299 stxa %g0, [%g1]ASI_DTLB_DEMAP 300 stxa %g0, [%g1]ASI_ITLB_DEMAP 301 flush %g5 ! flush required by immu 302 303 deccc %g3 /* decr pgcnt */ 304 bnz,pt %icc,3b 305 add %g1, %g2, %g1 /* next page */ 306 307 stxa %g6, [%g4]ASI_DMMU /* restore old ctxnum */ 308 retry 309 SET_SIZE(vtag_flush_pgcnt_tl1) 310 311#endif /* lint */ 312 313 314#if defined(lint) 315 316/*ARGSUSED*/ 317void 318vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2) 319{} 320 321#else /* lint */ 322 323 ENTRY_NP(vtag_flushall_tl1) 324 /* 325 * x-trap to flush tlb 326 */ 327 set DEMAP_ALL_TYPE, %g4 328 stxa %g0, [%g4]ASI_DTLB_DEMAP 329 stxa %g0, [%g4]ASI_ITLB_DEMAP 330 retry 331 SET_SIZE(vtag_flushall_tl1) 332 333#endif /* lint */ 334 335 336/* 337 * VAC (virtual address conflict) does not apply to OPL. 338 * VAC resolution is managed by the Olympus processor hardware. 339 * As a result, all OPL VAC flushing routines are no-ops. 340 */ 341 342#if defined(lint) 343 344/* ARGSUSED */ 345void 346vac_flushpage(pfn_t pfnum, int vcolor) 347{} 348 349#else /* lint */ 350 351 ENTRY(vac_flushpage) 352 retl 353 nop 354 SET_SIZE(vac_flushpage) 355 356#endif /* lint */ 357 358#if defined(lint) 359 360/* ARGSUSED */ 361void 362vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor) 363{} 364 365#else /* lint */ 366 367 ENTRY_NP(vac_flushpage_tl1) 368 retry 369 SET_SIZE(vac_flushpage_tl1) 370 371#endif /* lint */ 372 373 374#if defined(lint) 375 376/* ARGSUSED */ 377void 378vac_flushcolor(int vcolor, pfn_t pfnum) 379{} 380 381#else /* lint */ 382 383 ENTRY(vac_flushcolor) 384 retl 385 nop 386 SET_SIZE(vac_flushcolor) 387 388#endif /* lint */ 389 390 391 392#if defined(lint) 393 394/* ARGSUSED */ 395void 396vac_flushcolor_tl1(uint64_t vcolor, uint64_t pfnum) 397{} 398 399#else /* lint */ 400 401 ENTRY(vac_flushcolor_tl1) 402 retry 403 SET_SIZE(vac_flushcolor_tl1) 404 405#endif /* lint */ 406 407#if defined(lint) 408 409int 410idsr_busy(void) 411{ 412 return (0); 413} 414 415#else /* lint */ 416 417/* 418 * Determine whether or not the IDSR is busy. 419 * Entry: no arguments 420 * Returns: 1 if busy, 0 otherwise 421 */ 422 ENTRY(idsr_busy) 423 ldxa [%g0]ASI_INTR_DISPATCH_STATUS, %g1 424 clr %o0 425 btst IDSR_BUSY, %g1 426 bz,a,pt %xcc, 1f 427 mov 1, %o0 4281: 429 retl 430 nop 431 SET_SIZE(idsr_busy) 432 433#endif /* lint */ 434 435#if defined(lint) 436 437/* ARGSUSED */ 438void 439init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2) 440{} 441 442/* ARGSUSED */ 443void 444init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2) 445{} 446 447#else /* lint */ 448 449 .global _dispatch_status_busy 450_dispatch_status_busy: 451 .asciz "ASI_INTR_DISPATCH_STATUS error: busy" 452 .align 4 453 454/* 455 * Setup interrupt dispatch data registers 456 * Entry: 457 * %o0 - function or inumber to call 458 * %o1, %o2 - arguments (2 uint64_t's) 459 */ 460 .seg "text" 461 462 ENTRY(init_mondo) 463#ifdef DEBUG 464 ! 465 ! IDSR should not be busy at the moment 466 ! 467 ldxa [%g0]ASI_INTR_DISPATCH_STATUS, %g1 468 btst IDSR_BUSY, %g1 469 bz,pt %xcc, 1f 470 nop 471 sethi %hi(_dispatch_status_busy), %o0 472 call panic 473 or %o0, %lo(_dispatch_status_busy), %o0 474#endif /* DEBUG */ 475 476 ALTENTRY(init_mondo_nocheck) 477 ! 478 ! interrupt vector dispatch data reg 0 479 ! 4801: 481 mov IDDR_0, %g1 482 mov IDDR_1, %g2 483 mov IDDR_2, %g3 484 stxa %o0, [%g1]ASI_INTR_DISPATCH 485 486 ! 487 ! interrupt vector dispatch data reg 1 488 ! 489 stxa %o1, [%g2]ASI_INTR_DISPATCH 490 491 ! 492 ! interrupt vector dispatch data reg 2 493 ! 494 stxa %o2, [%g3]ASI_INTR_DISPATCH 495 496 membar #Sync 497 retl 498 nop 499 SET_SIZE(init_mondo_nocheck) 500 SET_SIZE(init_mondo) 501 502#endif /* lint */ 503 504 505#if defined(lint) 506 507/* ARGSUSED */ 508void 509shipit(int upaid, int bn) 510{ return; } 511 512#else /* lint */ 513 514/* 515 * Ship mondo to aid using busy/nack pair bn 516 */ 517 ENTRY_NP(shipit) 518 sll %o0, IDCR_PID_SHIFT, %g1 ! IDCR<23:14> = agent id 519 sll %o1, IDCR_BN_SHIFT, %g2 ! IDCR<28:24> = b/n pair 520 or %g1, IDCR_OFFSET, %g1 ! IDCR<13:0> = 0x70 521 or %g1, %g2, %g1 522 stxa %g0, [%g1]ASI_INTR_DISPATCH ! interrupt vector dispatch 523 membar #Sync 524 retl 525 nop 526 SET_SIZE(shipit) 527 528#endif /* lint */ 529 530 531#if defined(lint) 532 533/* ARGSUSED */ 534void 535flush_instr_mem(caddr_t vaddr, size_t len) 536{} 537 538#else /* lint */ 539 540/* 541 * flush_instr_mem: 542 * Flush 1 page of the I-$ starting at vaddr 543 * %o0 vaddr 544 * %o1 bytes to be flushed 545 * 546 * SPARC64-VI maintains consistency of the on-chip Instruction Cache with 547 * the stores from all processors so that a FLUSH instruction is only needed 548 * to ensure pipeline is consistent. This means a single flush is sufficient at 549 * the end of a sequence of stores that updates the instruction stream to 550 * ensure correct operation. 551 */ 552 553 ENTRY(flush_instr_mem) 554 flush %o0 ! address irrelevant 555 retl 556 nop 557 SET_SIZE(flush_instr_mem) 558 559#endif /* lint */ 560 561 562/* 563 * flush_ecache: 564 * %o0 - 64 bit physical address 565 * %o1 - ecache size 566 * %o2 - ecache linesize 567 */ 568#if defined(lint) 569 570/*ARGSUSED*/ 571void 572flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize) 573{} 574 575#else /* !lint */ 576 577 ENTRY(flush_ecache) 578 579 /* 580 * Flush the entire Ecache. 581 */ 582 ECACHE_FLUSHALL(%o1, %o2, %o0, %o4) 583 retl 584 nop 585 SET_SIZE(flush_ecache) 586 587#endif /* lint */ 588 589#if defined(lint) 590 591/*ARGSUSED*/ 592void 593kdi_flush_idcache(int dcache_size, int dcache_lsize, int icache_size, 594 int icache_lsize) 595{ 596} 597 598#else /* lint */ 599 600 /* 601 * I/D cache flushing is not needed for OPL processors 602 */ 603 ENTRY(kdi_flush_idcache) 604 retl 605 nop 606 SET_SIZE(kdi_flush_idcache) 607 608#endif /* lint */ 609 610#ifdef TRAPTRACE 611/* 612 * Simplified trap trace macro for OPL. Adapted from us3. 613 */ 614#define OPL_TRAPTRACE(ptr, scr1, scr2, label) \ 615 CPU_INDEX(scr1, ptr); \ 616 sll scr1, TRAPTR_SIZE_SHIFT, scr1; \ 617 set trap_trace_ctl, ptr; \ 618 add ptr, scr1, scr1; \ 619 ld [scr1 + TRAPTR_LIMIT], ptr; \ 620 tst ptr; \ 621 be,pn %icc, label/**/1; \ 622 ldx [scr1 + TRAPTR_PBASE], ptr; \ 623 ld [scr1 + TRAPTR_OFFSET], scr1; \ 624 add ptr, scr1, ptr; \ 625 rd %asi, scr2; \ 626 wr %g0, TRAPTR_ASI, %asi; \ 627 rd STICK, scr1; \ 628 stxa scr1, [ptr + TRAP_ENT_TICK]%asi; \ 629 rdpr %tl, scr1; \ 630 stha scr1, [ptr + TRAP_ENT_TL]%asi; \ 631 rdpr %tt, scr1; \ 632 stha scr1, [ptr + TRAP_ENT_TT]%asi; \ 633 rdpr %tpc, scr1; \ 634 stna scr1, [ptr + TRAP_ENT_TPC]%asi; \ 635 rdpr %tstate, scr1; \ 636 stxa scr1, [ptr + TRAP_ENT_TSTATE]%asi; \ 637 stna %sp, [ptr + TRAP_ENT_SP]%asi; \ 638 stna %g0, [ptr + TRAP_ENT_TR]%asi; \ 639 stna %g0, [ptr + TRAP_ENT_F1]%asi; \ 640 stna %g0, [ptr + TRAP_ENT_F2]%asi; \ 641 stna %g0, [ptr + TRAP_ENT_F3]%asi; \ 642 stna %g0, [ptr + TRAP_ENT_F4]%asi; \ 643 wr %g0, scr2, %asi; \ 644 CPU_INDEX(ptr, scr1); \ 645 sll ptr, TRAPTR_SIZE_SHIFT, ptr; \ 646 set trap_trace_ctl, scr1; \ 647 add scr1, ptr, ptr; \ 648 ld [ptr + TRAPTR_OFFSET], scr1; \ 649 ld [ptr + TRAPTR_LIMIT], scr2; \ 650 st scr1, [ptr + TRAPTR_LAST_OFFSET]; \ 651 add scr1, TRAP_ENT_SIZE, scr1; \ 652 sub scr2, TRAP_ENT_SIZE, scr2; \ 653 cmp scr1, scr2; \ 654 movge %icc, 0, scr1; \ 655 st scr1, [ptr + TRAPTR_OFFSET]; \ 656label/**/1: 657#endif /* TRAPTRACE */ 658 659 660 661/* 662 * Macros facilitating error handling. 663 */ 664 665/* 666 * Save alternative global registers reg1, reg2, reg3 667 * to scratchpad registers 1, 2, 3 respectively. 668 */ 669#define OPL_SAVE_GLOBAL(reg1, reg2, reg3) \ 670 stxa reg1, [%g0]ASI_SCRATCHPAD ;\ 671 mov OPL_SCRATCHPAD_SAVE_AG2, reg1 ;\ 672 stxa reg2, [reg1]ASI_SCRATCHPAD ;\ 673 mov OPL_SCRATCHPAD_SAVE_AG3, reg1 ;\ 674 stxa reg3, [reg1]ASI_SCRATCHPAD 675 676/* 677 * Restore alternative global registers reg1, reg2, reg3 678 * from scratchpad registers 1, 2, 3 respectively. 679 */ 680#define OPL_RESTORE_GLOBAL(reg1, reg2, reg3) \ 681 mov OPL_SCRATCHPAD_SAVE_AG3, reg1 ;\ 682 ldxa [reg1]ASI_SCRATCHPAD, reg3 ;\ 683 mov OPL_SCRATCHPAD_SAVE_AG2, reg1 ;\ 684 ldxa [reg1]ASI_SCRATCHPAD, reg2 ;\ 685 ldxa [%g0]ASI_SCRATCHPAD, reg1 686 687/* 688 * Logs value `val' into the member `offset' of a structure 689 * at physical address `pa' 690 */ 691#define LOG_REG(pa, offset, val) \ 692 add pa, offset, pa ;\ 693 stxa val, [pa]ASI_MEM 694 695#define FLUSH_ALL_TLB(tmp1) \ 696 set DEMAP_ALL_TYPE, tmp1 ;\ 697 stxa %g0, [tmp1]ASI_ITLB_DEMAP ;\ 698 stxa %g0, [tmp1]ASI_DTLB_DEMAP ;\ 699 sethi %hi(FLUSH_ADDR), tmp1 ;\ 700 flush tmp1 701 702/* 703 * Extracts the Physaddr to Logging Buffer field of the OPL_SCRATCHPAD_ERRLOG 704 * scratch register by zeroing all other fields. Result is in pa. 705 */ 706#define LOG_ADDR(pa) \ 707 mov OPL_SCRATCHPAD_ERRLOG, pa ;\ 708 ldxa [pa]ASI_SCRATCHPAD, pa ;\ 709 sllx pa, 64-ERRLOG_REG_EIDR_SHIFT, pa ;\ 710 srlx pa, 64-ERRLOG_REG_EIDR_SHIFT+ERRLOG_REG_ERR_SHIFT, pa ;\ 711 sllx pa, ERRLOG_REG_ERR_SHIFT, pa 712 713/* 714 * Advance the per-cpu error log buffer pointer to the next 715 * ERRLOG_SZ entry, making sure that it will modulo (wraparound) 716 * ERRLOG_BUFSIZ boundary. The args logpa, bufmask, tmp are 717 * unused input registers for this macro. 718 * 719 * Algorithm: 720 * 1. logpa = contents of errorlog scratchpad register 721 * 2. bufmask = ERRLOG_BUFSIZ - 1 722 * 3. tmp = logpa & ~(bufmask) (tmp is now logbase) 723 * 4. logpa += ERRLOG_SZ 724 * 5. logpa = logpa & bufmask (get new offset to logbase) 725 * 4. logpa = tmp | logpa 726 * 7. write logpa back into errorlog scratchpad register 727 * 728 * new logpa = (logpa & ~bufmask) | ((logpa + ERRLOG_SZ) & bufmask) 729 * 730 */ 731#define UPDATE_LOGADD(logpa, bufmask, tmp) \ 732 set OPL_SCRATCHPAD_ERRLOG, tmp ;\ 733 ldxa [tmp]ASI_SCRATCHPAD, logpa ;\ 734 set (ERRLOG_BUFSZ-1), bufmask ;\ 735 andn logpa, bufmask, tmp ;\ 736 add logpa, ERRLOG_SZ, logpa ;\ 737 and logpa, bufmask, logpa ;\ 738 or tmp, logpa, logpa ;\ 739 set OPL_SCRATCHPAD_ERRLOG, tmp ;\ 740 stxa logpa, [tmp]ASI_SCRATCHPAD 741 742/* Log error status registers into the log buffer */ 743#define LOG_SYNC_REG(sfsr, sfar, tmp) \ 744 LOG_ADDR(tmp) ;\ 745 LOG_REG(tmp, LOG_SFSR_OFF, sfsr) ;\ 746 LOG_ADDR(tmp) ;\ 747 mov tmp, sfsr ;\ 748 LOG_REG(tmp, LOG_SFAR_OFF, sfar) ;\ 749 rd STICK, sfar ;\ 750 mov sfsr, tmp ;\ 751 LOG_REG(tmp, LOG_STICK_OFF, sfar) ;\ 752 rdpr %tl, tmp ;\ 753 sllx tmp, 32, sfar ;\ 754 rdpr %tt, tmp ;\ 755 or sfar, tmp, sfar ;\ 756 mov sfsr, tmp ;\ 757 LOG_REG(tmp, LOG_TL_OFF, sfar) ;\ 758 set OPL_SCRATCHPAD_ERRLOG, tmp ;\ 759 ldxa [tmp]ASI_SCRATCHPAD, sfar ;\ 760 mov sfsr, tmp ;\ 761 LOG_REG(tmp, LOG_ASI3_OFF, sfar) ;\ 762 rdpr %tpc, sfar ;\ 763 mov sfsr, tmp ;\ 764 LOG_REG(tmp, LOG_TPC_OFF, sfar) ;\ 765 UPDATE_LOGADD(sfsr, sfar, tmp) 766 767#define LOG_UGER_REG(uger, tmp, tmp2) \ 768 LOG_ADDR(tmp) ;\ 769 mov tmp, tmp2 ;\ 770 LOG_REG(tmp2, LOG_UGER_OFF, uger) ;\ 771 mov tmp, uger ;\ 772 rd STICK, tmp2 ;\ 773 LOG_REG(tmp, LOG_STICK_OFF, tmp2) ;\ 774 rdpr %tl, tmp ;\ 775 sllx tmp, 32, tmp2 ;\ 776 rdpr %tt, tmp ;\ 777 or tmp2, tmp, tmp2 ;\ 778 mov uger, tmp ;\ 779 LOG_REG(tmp, LOG_TL_OFF, tmp2) ;\ 780 set OPL_SCRATCHPAD_ERRLOG, tmp2 ;\ 781 ldxa [tmp2]ASI_SCRATCHPAD, tmp2 ;\ 782 mov uger, tmp ;\ 783 LOG_REG(tmp, LOG_ASI3_OFF, tmp2) ;\ 784 rdpr %tstate, tmp2 ;\ 785 mov uger, tmp ;\ 786 LOG_REG(tmp, LOG_TSTATE_OFF, tmp2) ;\ 787 rdpr %tpc, tmp2 ;\ 788 mov uger, tmp ;\ 789 LOG_REG(tmp, LOG_TPC_OFF, tmp2) ;\ 790 UPDATE_LOGADD(uger, tmp, tmp2) 791 792/* 793 * Scrub the STICK_COMPARE register to clear error by updating 794 * it to a reasonable value for interrupt generation. 795 * Ensure that we observe the CPU_ENABLE flag so that we 796 * don't accidentally enable TICK interrupt in STICK_COMPARE 797 * i.e. no clock interrupt will be generated if CPU_ENABLE flag 798 * is off. 799 */ 800#define UPDATE_STICK_COMPARE(tmp1, tmp2) \ 801 CPU_ADDR(tmp1, tmp2) ;\ 802 lduh [tmp1 + CPU_FLAGS], tmp2 ;\ 803 andcc tmp2, CPU_ENABLE, %g0 ;\ 804 set OPL_UGER_STICK_DIFF, tmp2 ;\ 805 rd STICK, tmp1 ;\ 806 add tmp1, tmp2, tmp1 ;\ 807 mov 1, tmp2 ;\ 808 sllx tmp2, TICKINT_DIS_SHFT, tmp2 ;\ 809 or tmp1, tmp2, tmp2 ;\ 810 movnz %xcc, tmp1, tmp2 ;\ 811 wr tmp2, %g0, STICK_COMPARE 812 813/* 814 * Reset registers that may be corrupted by IAUG_CRE error. 815 * To update interrupt handling related registers force the 816 * clock interrupt. 817 */ 818#define IAG_CRE(tmp1, tmp2) \ 819 set OPL_SCRATCHPAD_ERRLOG, tmp1 ;\ 820 ldxa [tmp1]ASI_SCRATCHPAD, tmp1 ;\ 821 srlx tmp1, ERRLOG_REG_EIDR_SHIFT, tmp1 ;\ 822 set ERRLOG_REG_EIDR_MASK, tmp2 ;\ 823 and tmp1, tmp2, tmp1 ;\ 824 stxa tmp1, [%g0]ASI_EIDR ;\ 825 wr %g0, 0, SOFTINT ;\ 826 sethi %hi(hres_last_tick), tmp1 ;\ 827 ldx [tmp1 + %lo(hres_last_tick)], tmp1 ;\ 828 set OPL_UGER_STICK_DIFF, tmp2 ;\ 829 add tmp1, tmp2, tmp1 ;\ 830 wr tmp1, %g0, STICK ;\ 831 UPDATE_STICK_COMPARE(tmp1, tmp2) 832 833 834#define CLEAR_FPREGS(tmp) \ 835 wr %g0, FPRS_FEF, %fprs ;\ 836 wr %g0, %g0, %gsr ;\ 837 sethi %hi(opl_clr_freg), tmp ;\ 838 or tmp, %lo(opl_clr_freg), tmp ;\ 839 ldx [tmp], %fsr ;\ 840 fzero %d0 ;\ 841 fzero %d2 ;\ 842 fzero %d4 ;\ 843 fzero %d6 ;\ 844 fzero %d8 ;\ 845 fzero %d10 ;\ 846 fzero %d12 ;\ 847 fzero %d14 ;\ 848 fzero %d16 ;\ 849 fzero %d18 ;\ 850 fzero %d20 ;\ 851 fzero %d22 ;\ 852 fzero %d24 ;\ 853 fzero %d26 ;\ 854 fzero %d28 ;\ 855 fzero %d30 ;\ 856 fzero %d32 ;\ 857 fzero %d34 ;\ 858 fzero %d36 ;\ 859 fzero %d38 ;\ 860 fzero %d40 ;\ 861 fzero %d42 ;\ 862 fzero %d44 ;\ 863 fzero %d46 ;\ 864 fzero %d48 ;\ 865 fzero %d50 ;\ 866 fzero %d52 ;\ 867 fzero %d54 ;\ 868 fzero %d56 ;\ 869 fzero %d58 ;\ 870 fzero %d60 ;\ 871 fzero %d62 ;\ 872 wr %g0, %g0, %fprs 873 874#define CLEAR_GLOBALS() \ 875 mov %g0, %g1 ;\ 876 mov %g0, %g2 ;\ 877 mov %g0, %g3 ;\ 878 mov %g0, %g4 ;\ 879 mov %g0, %g5 ;\ 880 mov %g0, %g6 ;\ 881 mov %g0, %g7 882 883/* 884 * We do not clear the alternative globals here because they 885 * are scratch registers, i.e. there is no code that reads from 886 * them without write to them firstly. In other words every 887 * read always follows write that makes extra write to the 888 * alternative globals unnecessary. 889 */ 890#define CLEAR_GEN_REGS(tmp1, label) \ 891 set TSTATE_KERN, tmp1 ;\ 892 wrpr %g0, tmp1, %tstate ;\ 893 mov %g0, %y ;\ 894 mov %g0, %asi ;\ 895 mov %g0, %ccr ;\ 896 mov %g0, %l0 ;\ 897 mov %g0, %l1 ;\ 898 mov %g0, %l2 ;\ 899 mov %g0, %l3 ;\ 900 mov %g0, %l4 ;\ 901 mov %g0, %l5 ;\ 902 mov %g0, %l6 ;\ 903 mov %g0, %l7 ;\ 904 mov %g0, %i0 ;\ 905 mov %g0, %i1 ;\ 906 mov %g0, %i2 ;\ 907 mov %g0, %i3 ;\ 908 mov %g0, %i4 ;\ 909 mov %g0, %i5 ;\ 910 mov %g0, %i6 ;\ 911 mov %g0, %i7 ;\ 912 mov %g0, %o1 ;\ 913 mov %g0, %o2 ;\ 914 mov %g0, %o3 ;\ 915 mov %g0, %o4 ;\ 916 mov %g0, %o5 ;\ 917 mov %g0, %o6 ;\ 918 mov %g0, %o7 ;\ 919 mov %g0, %o0 ;\ 920 mov %g0, %g4 ;\ 921 mov %g0, %g5 ;\ 922 mov %g0, %g6 ;\ 923 mov %g0, %g7 ;\ 924 rdpr %tl, tmp1 ;\ 925 cmp tmp1, 1 ;\ 926 be,pt %xcc, label/**/1 ;\ 927 rdpr %pstate, tmp1 ;\ 928 wrpr tmp1, PSTATE_AG|PSTATE_IG, %pstate ;\ 929 CLEAR_GLOBALS() ;\ 930 rdpr %pstate, tmp1 ;\ 931 wrpr tmp1, PSTATE_IG|PSTATE_MG, %pstate ;\ 932 CLEAR_GLOBALS() ;\ 933 rdpr %pstate, tmp1 ;\ 934 wrpr tmp1, PSTATE_MG|PSTATE_AG, %pstate ;\ 935 ba,pt %xcc, label/**/2 ;\ 936 nop ;\ 937label/**/1: ;\ 938 wrpr tmp1, PSTATE_AG, %pstate ;\ 939 CLEAR_GLOBALS() ;\ 940 rdpr %pstate, tmp1 ;\ 941 wrpr tmp1, PSTATE_AG, %pstate ;\ 942label/**/2: 943 944 945/* 946 * Reset all window related registers 947 */ 948#define RESET_WINREG(tmp) \ 949 sethi %hi(nwin_minus_one), tmp ;\ 950 ld [tmp + %lo(nwin_minus_one)], tmp ;\ 951 wrpr %g0, tmp, %cwp ;\ 952 wrpr %g0, tmp, %cleanwin ;\ 953 sub tmp, 1, tmp ;\ 954 wrpr %g0, tmp, %cansave ;\ 955 wrpr %g0, %g0, %canrestore ;\ 956 wrpr %g0, %g0, %otherwin ;\ 957 wrpr %g0, PIL_MAX, %pil ;\ 958 wrpr %g0, WSTATE_KERN, %wstate 959 960 961#define RESET_PREV_TSTATE(tmp1, tmp2, label) \ 962 rdpr %tl, tmp1 ;\ 963 subcc tmp1, 1, tmp1 ;\ 964 bz,pt %xcc, label/**/1 ;\ 965 nop ;\ 966 wrpr tmp1, %g0, %tl ;\ 967 set TSTATE_KERN, tmp2 ;\ 968 wrpr tmp2, %g0, %tstate ;\ 969 wrpr %g0, %g0, %tpc ;\ 970 wrpr %g0, %g0, %tnpc ;\ 971 add tmp1, 1, tmp1 ;\ 972 wrpr tmp1, %g0, %tl ;\ 973label/**/1: 974 975 976/* 977 * %pstate, %pc, %npc are propagated to %tstate, %tpc, %tnpc, 978 * and we reset these regiseter here. 979 */ 980#define RESET_CUR_TSTATE(tmp) \ 981 set TSTATE_KERN, tmp ;\ 982 wrpr %g0, tmp, %tstate ;\ 983 wrpr %g0, 0, %tpc ;\ 984 wrpr %g0, 0, %tnpc ;\ 985 RESET_WINREG(tmp) 986 987/* 988 * In case of urgent errors some MMU registers may be 989 * corrupted, so we set here some reasonable values for 990 * them. Note that resetting MMU registers also reset the context 991 * info, we will need to reset the window registers to prevent 992 * spill/fill that depends on context info for correct behaviour. 993 * Note that the TLBs must be flushed before programming the context 994 * registers. 995 */ 996 997#if !defined(lint) 998#define RESET_MMU_REGS(tmp1, tmp2, tmp3) \ 999 FLUSH_ALL_TLB(tmp1) ;\ 1000 set MMU_PCONTEXT, tmp1 ;\ 1001 sethi %hi(kcontextreg), tmp2 ;\ 1002 ldx [tmp2 + %lo(kcontextreg)], tmp2 ;\ 1003 stxa tmp2, [tmp1]ASI_DMMU ;\ 1004 set MMU_SCONTEXT, tmp1 ;\ 1005 stxa tmp2, [tmp1]ASI_DMMU ;\ 1006 sethi %hi(ktsb_base), tmp1 ;\ 1007 ldx [tmp1 + %lo(ktsb_base)], tmp2 ;\ 1008 mov MMU_TSB, tmp3 ;\ 1009 stxa tmp2, [tmp3]ASI_IMMU ;\ 1010 stxa tmp2, [tmp3]ASI_DMMU ;\ 1011 membar #Sync ;\ 1012 RESET_WINREG(tmp1) 1013 1014#define RESET_TSB_TAGPTR(tmp) \ 1015 set MMU_TAG_ACCESS, tmp ;\ 1016 stxa %g0, [tmp]ASI_IMMU ;\ 1017 stxa %g0, [tmp]ASI_DMMU ;\ 1018 membar #Sync 1019#endif /* lint */ 1020 1021/* 1022 * RESET_TO_PRIV() 1023 * 1024 * In many cases, we need to force the thread into privilege mode because 1025 * privilege mode is only thing in which the system continue to work 1026 * due to undeterminable user mode information that come from register 1027 * corruption. 1028 * 1029 * - opl_uger_ctxt 1030 * If the error is secondary TSB related register parity, we have no idea 1031 * what value is supposed to be for it. 1032 * 1033 * The below three cases %tstate is not accessible until it is overwritten 1034 * with some value, so we have no clue if the thread was running on user mode 1035 * or not 1036 * - opl_uger_pstate 1037 * If the error is %pstate parity, it propagates to %tstate. 1038 * - opl_uger_tstate 1039 * No need to say the reason 1040 * - opl_uger_r 1041 * If the error is %ccr or %asi parity, it propagates to %tstate 1042 * 1043 * For the above four cases, user mode info may not be available for 1044 * sys_trap() and user_trap() to work consistently. So we have to force 1045 * the thread into privilege mode. 1046 * 1047 * Forcing the thread to privilege mode requires forcing 1048 * regular %g7 to be CPU_THREAD. Because if it was running on user mode, 1049 * %g7 will be set in user_trap(). Also since the %sp may be in 1050 * an inconsistent state, we need to do a stack reset and switch to 1051 * something we know i.e. current thread's kernel stack. 1052 * We also reset the window registers and MMU registers just to 1053 * make sure. 1054 * 1055 * To set regular %g7, we need to clear PSTATE_AG bit and need to 1056 * use one local register. Note that we are panicking and will never 1057 * unwind back so it is ok to clobber a local. 1058 * 1059 * If the thread was running in user mode, the %tpc value itself might be 1060 * within the range of OBP addresses. %tpc must be forced to be zero to prevent 1061 * sys_trap() from going to prom_trap() 1062 * 1063 */ 1064#define RESET_TO_PRIV(tmp, tmp1, tmp2, local) \ 1065 RESET_MMU_REGS(tmp, tmp1, tmp2) ;\ 1066 CPU_ADDR(tmp, tmp1) ;\ 1067 ldx [tmp + CPU_THREAD], local ;\ 1068 ldx [local + T_STACK], tmp ;\ 1069 sub tmp, STACK_BIAS, %sp ;\ 1070 rdpr %pstate, tmp ;\ 1071 wrpr tmp, PSTATE_AG, %pstate ;\ 1072 mov local, %g7 ;\ 1073 rdpr %pstate, local ;\ 1074 wrpr local, PSTATE_AG, %pstate ;\ 1075 wrpr %g0, 1, %tl ;\ 1076 set TSTATE_KERN, tmp ;\ 1077 rdpr %cwp, tmp1 ;\ 1078 or tmp, tmp1, tmp ;\ 1079 wrpr tmp, %g0, %tstate ;\ 1080 wrpr %g0, %tpc 1081 1082 1083#if defined(lint) 1084 1085void 1086ce_err(void) 1087{} 1088 1089#else /* lint */ 1090 1091/* 1092 * We normally don't expect CE traps since we disable the 1093 * 0x63 trap reporting at the start of day. There is a 1094 * small window before we disable them, so let check for 1095 * it. Otherwise, panic. 1096 */ 1097 1098 .align 128 1099 ENTRY_NP(ce_err) 1100 mov AFSR_ECR, %g1 1101 ldxa [%g1]ASI_ECR, %g1 1102 andcc %g1, ASI_ECR_RTE_UE | ASI_ECR_RTE_CEDG, %g0 1103 bz,pn %xcc, 1f 1104 nop 1105 retry 11061: 1107 /* 1108 * We did disabled the 0x63 trap reporting. 1109 * This shouldn't happen - panic. 1110 */ 1111 set trap, %g1 1112 rdpr %tt, %g3 1113 sethi %hi(sys_trap), %g5 1114 jmp %g5 + %lo(sys_trap) 1115 sub %g0, 1, %g4 1116 SET_SIZE(ce_err) 1117 1118#endif /* lint */ 1119 1120 1121#if defined(lint) 1122 1123void 1124ce_err_tl1(void) 1125{} 1126 1127#else /* lint */ 1128 1129/* 1130 * We don't use trap for CE detection. 1131 */ 1132 ENTRY_NP(ce_err_tl1) 1133 set trap, %g1 1134 rdpr %tt, %g3 1135 sethi %hi(sys_trap), %g5 1136 jmp %g5 + %lo(sys_trap) 1137 sub %g0, 1, %g4 1138 SET_SIZE(ce_err_tl1) 1139 1140#endif /* lint */ 1141 1142 1143#if defined(lint) 1144 1145void 1146async_err(void) 1147{} 1148 1149#else /* lint */ 1150 1151/* 1152 * async_err is the default handler for IAE/DAE traps. 1153 * For OPL, we patch in the right handler at start of day. 1154 * But if a IAE/DAE trap get generated before the handler 1155 * is patched, panic. 1156 */ 1157 ENTRY_NP(async_err) 1158 set trap, %g1 1159 rdpr %tt, %g3 1160 sethi %hi(sys_trap), %g5 1161 jmp %g5 + %lo(sys_trap) 1162 sub %g0, 1, %g4 1163 SET_SIZE(async_err) 1164 1165#endif /* lint */ 1166 1167#if defined(lint) 1168void 1169opl_sync_trap(void) 1170{} 1171#else /* lint */ 1172 1173 .seg ".data" 1174 .global opl_clr_freg 1175 .global opl_cpu0_err_log 1176 1177 .align 16 1178opl_clr_freg: 1179 .word 0 1180 .align 16 1181 1182 .align MMU_PAGESIZE 1183opl_cpu0_err_log: 1184 .skip MMU_PAGESIZE 1185 1186/* 1187 * Common synchronous error trap handler (tt=0xA, 0x32) 1188 * All TL=0 and TL>0 0xA and 0x32 traps vector to this handler. 1189 * The error handling can be best summarized as follows: 1190 * 0. Do TRAPTRACE if enabled. 1191 * 1. Save globals %g1, %g2 & %g3 onto the scratchpad regs. 1192 * 2. The SFSR register is read and verified as valid by checking 1193 * SFSR.FV bit being set. If the SFSR.FV is not set, the 1194 * error cases cannot be decoded/determined and the SFPAR 1195 * register that contain the physical faultaddr is also 1196 * not valid. Also the SPFAR is only valid for UE/TO/BERR error 1197 * cases. Assuming the SFSR.FV is valid: 1198 * - BERR(bus error)/TO(timeout)/UE case 1199 * If any of these error cases are detected, read the SFPAR 1200 * to get the faultaddress. Generate ereport. 1201 * - TLB Parity case (only recoverable case) 1202 * For DAE, read SFAR for the faultaddress. For IAE, 1203 * use %tpc for faultaddress (SFAR is not valid in IAE) 1204 * Flush all the tlbs. 1205 * Subtract one from the recoverable error count stored in 1206 * the error log scratch register. If the threshold limit 1207 * is reached (zero) - generate ereport. Else 1208 * restore globals and retry (no ereport is generated). 1209 * - TLB Multiple hits 1210 * For DAE, read SFAR for the faultaddress. For IAE, 1211 * use %tpc for faultaddress (SFAR is not valid in IAE). 1212 * Flush all tlbs and generate ereport. 1213 * 3. TL=0 and TL>0 considerations 1214 * - Since both TL=0 & TL>1 traps are made to vector into 1215 * the same handler, the underlying assumption/design here is 1216 * that any nested error condition (if happens) occurs only 1217 * in the handler and the system is assumed to eventually 1218 * Red-mode. With this philosophy in mind, the recoverable 1219 * TLB Parity error case never check the TL level before it 1220 * retry. Note that this is ok for the TL>1 case (assuming we 1221 * don't have a nested error) since we always save the globals 1222 * %g1, %g2 & %g3 whenever we enter this trap handler. 1223 * - Additional TL=0 vs TL>1 handling includes: 1224 * - For UE error occuring under TL>1, special handling 1225 * is added to prevent the unlikely chance of a cpu-lockup 1226 * when a UE was originally detected in user stack and 1227 * the spill trap handler taken from sys_trap() so happened 1228 * to reference the same UE location. Under the above 1229 * condition (TL>1 and UE error), paranoid code is added 1230 * to reset window regs so that spill traps can't happen 1231 * during the unwind back to TL=0 handling. 1232 * Note that we can do that because we are not returning 1233 * back. 1234 * 4. Ereport generation. 1235 * - Ereport generation is performed when we unwind to the TL=0 1236 * handling code via sys_trap(). on_trap()/lofault protection 1237 * will apply there. 1238 * 1239 */ 1240 ENTRY_NP(opl_sync_trap) 1241#ifdef TRAPTRACE 1242 OPL_TRAPTRACE(%g1, %g2, %g3, opl_sync_trap_lb) 1243 rdpr %tt, %g1 1244#endif /* TRAPTRACE */ 1245 cmp %g1, T_INSTR_ERROR 1246 bne,pt %xcc, 0f 1247 mov MMU_SFSR, %g3 1248 ldxa [%g3]ASI_IMMU, %g1 ! IAE trap case tt = 0xa 1249 andcc %g1, SFSR_FV, %g0 1250 bz,a,pn %xcc, 2f ! Branch if SFSR is invalid and 1251 rdpr %tpc, %g2 ! use %tpc for faultaddr instead 1252 1253 sethi %hi(SFSR_UE|SFSR_BERR|SFSR_TO), %g3 1254 andcc %g1, %g3, %g0 ! Check for UE/BERR/TO errors 1255 bz,a,pt %xcc, 1f ! Branch if not UE/BERR/TO and 1256 rdpr %tpc, %g2 ! use %tpc as faultaddr 1257 set OPL_MMU_SFPAR, %g3 ! In the UE/BERR/TO cases, use 1258 ba,pt %xcc, 2f ! SFPAR as faultaddr 1259 ldxa [%g3]ASI_IMMU, %g2 12600: 1261 ldxa [%g3]ASI_DMMU, %g1 ! DAE trap case tt = 0x32 1262 andcc %g1, SFSR_FV, %g0 1263 bnz,pt %xcc, 7f ! branch if SFSR.FV is valid 1264 mov MMU_SFAR, %g2 ! set %g2 to use SFAR 1265 ba,pt %xcc, 2f ! SFSR.FV is not valid, read SFAR 1266 ldxa [%g2]ASI_DMMU, %g2 ! for faultaddr 12677: 1268 sethi %hi(SFSR_UE|SFSR_BERR|SFSR_TO), %g3 1269 andcc %g1, %g3, %g0 ! Check UE/BERR/TO for valid SFPAR 1270 movnz %xcc, OPL_MMU_SFPAR, %g2 ! Use SFPAR instead of SFAR for 1271 ldxa [%g2]ASI_DMMU, %g2 ! faultaddr 12721: 1273 sethi %hi(SFSR_TLB_PRT), %g3 1274 andcc %g1, %g3, %g0 1275 bz,pt %xcc, 8f ! branch for TLB multi-hit check 1276 nop 1277 /* 1278 * This is the TLB parity error case and it is the 1279 * only retryable error case. 1280 * Only %g1, %g2 and %g3 are allowed 1281 */ 1282 FLUSH_ALL_TLB(%g3) 1283 set OPL_SCRATCHPAD_ERRLOG, %g3 1284 ldxa [%g3]ASI_SCRATCHPAD, %g3 ! Read errlog scratchreg 1285 and %g3, ERRLOG_REG_NUMERR_MASK, %g3! Extract the error count 1286 subcc %g3, 1, %g0 ! Subtract one from the count 1287 bz,pn %xcc, 2f ! too many TLB parity errs in a certain 1288 nop ! period, branch to generate ereport 1289 LOG_SYNC_REG(%g1, %g2, %g3) ! Record into the error log 1290 set OPL_SCRATCHPAD_ERRLOG, %g3 1291 ldxa [%g3]ASI_SCRATCHPAD, %g2 1292 sub %g2, 1, %g2 ! decrement error counter by 1 1293 stxa %g2, [%g3]ASI_SCRATCHPAD ! update the errlog scratchreg 1294 OPL_RESTORE_GLOBAL(%g1, %g2, %g3) 1295 retry 12968: 1297 sethi %hi(SFSR_TLB_MUL), %g3 1298 andcc %g1, %g3, %g0 1299 bz,pt %xcc, 2f ! check for the TLB multi-hit errors 1300 nop 1301 FLUSH_ALL_TLB(%g3) 13022: 1303 /* 1304 * non-retryable error handling 1305 * now we can use other registers since 1306 * we will not be returning back 1307 */ 1308 mov %g1, %g5 ! %g5 = SFSR 1309 mov %g2, %g6 ! %g6 = SFPAR or SFAR/tpc 1310 LOG_SYNC_REG(%g1, %g2, %g3) ! Record into the error log 1311 1312 /* 1313 * Special case for UE on user stack. 1314 * There is a possibility that the same error may come back here 1315 * by touching the same UE in spill trap handler taken from 1316 * sys_trap(). It ends up with an infinite loop causing a cpu lockup. 1317 * Conditions for this handling this case are: 1318 * - SFSR_FV is valid and SFSR_UE is set 1319 * - we are at TL > 1 1320 * If the above conditions are true, we force %cansave to be a 1321 * big number to prevent spill trap in sys_trap(). Note that 1322 * we will not be returning back. 1323 */ 1324 rdpr %tt, %g4 ! %g4 == ttype 1325 rdpr %tl, %g1 ! %g1 == tl 1326 cmp %g1, 1 ! Check if TL == 1 1327 be,pt %xcc, 3f ! branch if we came from TL=0 1328 nop 1329 andcc %g5, SFSR_FV, %g0 ! see if SFSR.FV is valid 1330 bz,pn %xcc, 4f ! branch, checking UE is meaningless 1331 sethi %hi(SFSR_UE), %g2 1332 andcc %g5, %g2, %g0 ! check for UE 1333 bz,pt %xcc, 4f ! branch if not UE 1334 nop 1335 RESET_WINREG(%g1) ! reset windows to prevent spills 13364: 1337 RESET_USER_RTT_REGS(%g2, %g3, 5f) 13385: 1339 mov %g5, %g3 ! pass SFSR to the 3rd arg 1340 mov %g6, %g2 ! pass SFAR to the 2nd arg 1341 set opl_cpu_isync_tl1_error, %g1 1342 set opl_cpu_dsync_tl1_error, %g6 1343 cmp %g4, T_INSTR_ERROR 1344 movne %icc, %g6, %g1 1345 ba,pt %icc, 6f 1346 nop 13473: 1348 mov %g5, %g3 ! pass SFSR to the 3rd arg 1349 mov %g6, %g2 ! pass SFAR to the 2nd arg 1350 set opl_cpu_isync_tl0_error, %g1 1351 set opl_cpu_dsync_tl0_error, %g6 1352 cmp %g4, T_INSTR_ERROR 1353 movne %icc, %g6, %g1 13546: 1355 sethi %hi(sys_trap), %g5 1356 jmp %g5 + %lo(sys_trap) 1357 mov PIL_15, %g4 1358 SET_SIZE(opl_sync_trap) 1359#endif /* lint */ 1360 1361#if defined(lint) 1362void 1363opl_uger_trap(void) 1364{} 1365#else /* lint */ 1366/* 1367 * Common Urgent error trap handler (tt=0x40) 1368 * All TL=0 and TL>0 0x40 traps vector to this handler. 1369 * The error handling can be best summarized as follows: 1370 * 1. Read the Urgent error status register (UGERSR) 1371 * Faultaddress is N/A here and it is not collected. 1372 * 2. Check to see if we have a multiple errors case 1373 * If so, we enable WEAK_ED (weak error detection) bit 1374 * to prevent any potential error storms and branch directly 1375 * to generate ereport. (we don't decode/handle individual 1376 * error cases when we get a multiple error situation) 1377 * 3. Now look for the recoverable error cases which include 1378 * IUG_DTLB, IUG_ITLB or COREERR errors. If any of the 1379 * recoverable errors are detected, do the following: 1380 * - Flush all tlbs. 1381 * - Verify that we came from TL=0, if not, generate 1382 * ereport. Note that the reason we don't recover 1383 * at TL>0 is because the AGs might be corrupted or 1384 * inconsistent. We can't save/restore them into 1385 * the scratchpad regs like we did for opl_sync_trap(). 1386 * - Check the INSTEND[5:4] bits in the UGERSR. If the 1387 * value is 0x3 (11b), this error is not recoverable. 1388 * Generate ereport. 1389 * - Subtract one from the recoverable error count stored in 1390 * the error log scratch register. If the threshold limit 1391 * is reached (zero) - generate ereport. 1392 * - If the count is within the limit, update the count 1393 * in the error log register (subtract one). Log the error 1394 * info in the log buffer. Capture traptrace if enabled. 1395 * Retry (no ereport generated) 1396 * 4. The rest of the error cases are unrecoverable and will 1397 * be handled according (flushing regs, etc as required). 1398 * For details on these error cases (UGER_CRE, UGER_CTXT, etc..) 1399 * consult the OPL cpu/mem philosophy doc. 1400 * Ereport will be generated for these errors. 1401 * 5. Ereport generation. 1402 * - Ereport generation for urgent error trap always 1403 * result in a panic when we unwind to the TL=0 handling 1404 * code via sys_trap(). on_trap()/lofault protection do 1405 * not apply there. 1406 */ 1407 ENTRY_NP(opl_uger_trap) 1408 set ASI_UGERSR, %g2 1409 ldxa [%g2]ASI_AFSR, %g1 ! Read the UGERSR reg 1410 1411 set UGESR_MULTI, %g2 1412 andcc %g1, %g2, %g0 ! Check for Multi-errs 1413 bz,pt %xcc, opl_uger_is_recover ! branch if not Multi-errs 1414 nop 1415 set AFSR_ECR, %g2 1416 ldxa [%g2]ASI_AFSR, %g3 ! Enable Weak error 1417 or %g3, ASI_ECR_WEAK_ED, %g3 ! detect mode to prevent 1418 stxa %g3, [%g2]ASI_AFSR ! potential error storms 1419 ba %xcc, opl_uger_panic1 1420 nop 1421 1422opl_uger_is_recover: 1423 set UGESR_CAN_RECOVER, %g2 ! Check for recoverable 1424 andcc %g1, %g2, %g0 ! errors i.e.IUG_DTLB, 1425 bz,pt %xcc, opl_uger_cre ! IUG_ITLB or COREERR 1426 nop 1427 1428 /* 1429 * Fall thru to handle recoverable case 1430 * Need to do the following additional checks to determine 1431 * if this is indeed recoverable. 1432 * 1. Error trap came from TL=0 and 1433 * 2. INSTEND[5:4] bits in UGERSR is not 0x3 1434 * 3. Recoverable error count limit not reached 1435 * 1436 */ 1437 FLUSH_ALL_TLB(%g3) 1438 rdpr %tl, %g3 ! Read TL 1439 cmp %g3, 1 ! Check if we came from TL=0 1440 bne,pt %xcc, opl_uger_panic ! branch if came from TL>0 1441 nop 1442 srlx %g1, 4, %g2 ! shift INSTEND[5:4] -> [1:0] 1443 and %g2, 3, %g2 ! extract the shifted [1:0] bits 1444 cmp %g2, 3 ! check if INSTEND is recoverable 1445 be,pt %xcc, opl_uger_panic ! panic if ([1:0] = 11b) 1446 nop 1447 set OPL_SCRATCHPAD_ERRLOG, %g3 1448 ldxa [%g3]ASI_SCRATCHPAD, %g2 ! Read errlog scratch reg 1449 and %g2, ERRLOG_REG_NUMERR_MASK, %g3! Extract error count and 1450 subcc %g3, 1, %g3 ! subtract one from it 1451 bz,pt %xcc, opl_uger_panic ! If count reached zero, too many 1452 nop ! errors, branch to generate ereport 1453 sub %g2, 1, %g2 ! Subtract one from the count 1454 set OPL_SCRATCHPAD_ERRLOG, %g3 ! and write back the updated 1455 stxa %g2, [%g3]ASI_SCRATCHPAD ! count into the errlog reg 1456 LOG_UGER_REG(%g1, %g2, %g3) ! Log the error info 1457#ifdef TRAPTRACE 1458 OPL_TRAPTRACE(%g1, %g2, %g3, opl_uger_trap_lb) 1459#endif /* TRAPTRACE */ 1460 retry ! retry - no ereport 1461 1462 /* 1463 * Process the rest of the unrecoverable error cases 1464 * All error cases below ultimately branch to either 1465 * opl_uger_panic or opl_uger_panic1. 1466 * opl_uger_panic1 is the same as opl_uger_panic except 1467 * for the additional execution of the RESET_TO_PRIV() 1468 * macro that does a heavy handed reset. Read the 1469 * comments for RESET_TO_PRIV() macro for more info. 1470 */ 1471opl_uger_cre: 1472 set UGESR_IAUG_CRE, %g2 1473 andcc %g1, %g2, %g0 1474 bz,pt %xcc, opl_uger_ctxt 1475 nop 1476 IAG_CRE(%g2, %g3) 1477 set AFSR_ECR, %g2 1478 ldxa [%g2]ASI_AFSR, %g3 1479 or %g3, ASI_ECR_WEAK_ED, %g3 1480 stxa %g3, [%g2]ASI_AFSR 1481 ba %xcc, opl_uger_panic 1482 nop 1483 1484opl_uger_ctxt: 1485 set UGESR_IAUG_TSBCTXT, %g2 1486 andcc %g1, %g2, %g0 1487 bz,pt %xcc, opl_uger_tsbp 1488 nop 1489 RESET_MMU_REGS(%g2, %g3, %g4) 1490 ba %xcc, opl_uger_panic 1491 nop 1492 1493opl_uger_tsbp: 1494 set UGESR_IUG_TSBP, %g2 1495 andcc %g1, %g2, %g0 1496 bz,pt %xcc, opl_uger_pstate 1497 nop 1498 RESET_TSB_TAGPTR(%g2) 1499 1500 /* 1501 * IUG_TSBP error may corrupt MMU registers 1502 * Reset them here. 1503 */ 1504 RESET_MMU_REGS(%g2, %g3, %g4) 1505 ba %xcc, opl_uger_panic 1506 nop 1507 1508opl_uger_pstate: 1509 set UGESR_IUG_PSTATE, %g2 1510 andcc %g1, %g2, %g0 1511 bz,pt %xcc, opl_uger_tstate 1512 nop 1513 RESET_CUR_TSTATE(%g2) 1514 ba %xcc, opl_uger_panic1 1515 nop 1516 1517opl_uger_tstate: 1518 set UGESR_IUG_TSTATE, %g2 1519 andcc %g1, %g2, %g0 1520 bz,pt %xcc, opl_uger_f 1521 nop 1522 RESET_PREV_TSTATE(%g2, %g3, opl_uger_tstate_1) 1523 ba %xcc, opl_uger_panic1 1524 nop 1525 1526opl_uger_f: 1527 set UGESR_IUG_F, %g2 1528 andcc %g1, %g2, %g0 1529 bz,pt %xcc, opl_uger_r 1530 nop 1531 CLEAR_FPREGS(%g2) 1532 ba %xcc, opl_uger_panic 1533 nop 1534 1535opl_uger_r: 1536 set UGESR_IUG_R, %g2 1537 andcc %g1, %g2, %g0 1538 bz,pt %xcc, opl_uger_panic1 1539 nop 1540 CLEAR_GEN_REGS(%g2, opl_uger_r_1) 1541 ba %xcc, opl_uger_panic1 1542 nop 1543 1544opl_uger_panic: 1545 mov %g1, %g2 ! %g2 = arg #1 1546 LOG_UGER_REG(%g1, %g3, %g4) 1547 ba %xcc, opl_uger_panic_cmn 1548 nop 1549 1550opl_uger_panic1: 1551 mov %g1, %g2 ! %g2 = arg #1 1552 LOG_UGER_REG(%g1, %g3, %g4) 1553 RESET_TO_PRIV(%g1, %g3, %g4, %l0) 1554 1555 /* 1556 * Set up the argument for sys_trap. 1557 * %g2 = arg #1 already set above 1558 */ 1559opl_uger_panic_cmn: 1560 RESET_USER_RTT_REGS(%g4, %g5, 1f) 15611: 1562 rdpr %tl, %g3 ! arg #2 1563 set opl_cpu_urgent_error, %g1 ! pc 1564 sethi %hi(sys_trap), %g5 1565 jmp %g5 + %lo(sys_trap) 1566 mov PIL_15, %g4 1567 SET_SIZE(opl_uger_trap) 1568#endif /* lint */ 1569 1570#if defined(lint) 1571 1572void 1573opl_serr_instr(void) 1574{} 1575 1576#else /* lint */ 1577/* 1578 * The actual trap handler for tt=0x0a, and tt=0x32 1579 */ 1580 ENTRY_NP(opl_serr_instr) 1581 OPL_SAVE_GLOBAL(%g1,%g2,%g3) 1582 sethi %hi(opl_sync_trap), %g3 1583 jmp %g3 + %lo(opl_sync_trap) 1584 rdpr %tt, %g1 1585 .align 32 1586 SET_SIZE(opl_serr_instr) 1587 1588#endif /* lint */ 1589 1590#if defined(lint) 1591 1592void 1593opl_ugerr_instr(void) 1594{} 1595 1596#else /* lint */ 1597/* 1598 * The actual trap handler for tt=0x40 1599 */ 1600 ENTRY_NP(opl_ugerr_instr) 1601 sethi %hi(opl_uger_trap), %g3 1602 jmp %g3 + %lo(opl_uger_trap) 1603 nop 1604 .align 32 1605 SET_SIZE(opl_ugerr_instr) 1606 1607#endif /* lint */ 1608 1609#if defined(lint) 1610/* 1611 * Get timestamp (stick). 1612 */ 1613/* ARGSUSED */ 1614void 1615stick_timestamp(int64_t *ts) 1616{ 1617} 1618 1619#else /* lint */ 1620 1621 ENTRY_NP(stick_timestamp) 1622 rd STICK, %g1 ! read stick reg 1623 sllx %g1, 1, %g1 1624 srlx %g1, 1, %g1 ! clear npt bit 1625 1626 retl 1627 stx %g1, [%o0] ! store the timestamp 1628 SET_SIZE(stick_timestamp) 1629 1630#endif /* lint */ 1631 1632 1633#if defined(lint) 1634/* 1635 * Set STICK adjusted by skew. 1636 */ 1637/* ARGSUSED */ 1638void 1639stick_adj(int64_t skew) 1640{ 1641} 1642 1643#else /* lint */ 1644 1645 ENTRY_NP(stick_adj) 1646 rdpr %pstate, %g1 ! save processor state 1647 andn %g1, PSTATE_IE, %g3 1648 ba 1f ! cache align stick adj 1649 wrpr %g0, %g3, %pstate ! turn off interrupts 1650 1651 .align 16 16521: nop 1653 1654 rd STICK, %g4 ! read stick reg 1655 add %g4, %o0, %o1 ! adjust stick with skew 1656 wr %o1, %g0, STICK ! write stick reg 1657 1658 retl 1659 wrpr %g1, %pstate ! restore processor state 1660 SET_SIZE(stick_adj) 1661 1662#endif /* lint */ 1663 1664#if defined(lint) 1665/* 1666 * Debugger-specific stick retrieval 1667 */ 1668/*ARGSUSED*/ 1669int 1670kdi_get_stick(uint64_t *stickp) 1671{ 1672 return (0); 1673} 1674 1675#else /* lint */ 1676 1677 ENTRY_NP(kdi_get_stick) 1678 rd STICK, %g1 1679 stx %g1, [%o0] 1680 retl 1681 mov %g0, %o0 1682 SET_SIZE(kdi_get_stick) 1683 1684#endif /* lint */ 1685 1686#if defined(lint) 1687 1688/*ARGSUSED*/ 1689int 1690dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain) 1691{ return (0); } 1692 1693#else 1694 1695 ENTRY(dtrace_blksuword32) 1696 save %sp, -SA(MINFRAME + 4), %sp 1697 1698 rdpr %pstate, %l1 1699 andn %l1, PSTATE_IE, %l2 ! disable interrupts to 1700 wrpr %g0, %l2, %pstate ! protect our FPU diddling 1701 1702 rd %fprs, %l0 1703 andcc %l0, FPRS_FEF, %g0 1704 bz,a,pt %xcc, 1f ! if the fpu is disabled 1705 wr %g0, FPRS_FEF, %fprs ! ... enable the fpu 1706 1707 st %f0, [%fp + STACK_BIAS - 4] ! save %f0 to the stack 17081: 1709 set 0f, %l5 1710 /* 1711 * We're about to write a block full or either total garbage 1712 * (not kernel data, don't worry) or user floating-point data 1713 * (so it only _looks_ like garbage). 1714 */ 1715 ld [%i1], %f0 ! modify the block 1716 membar #Sync 1717 stn %l5, [THREAD_REG + T_LOFAULT] ! set up the lofault handler 1718 stda %d0, [%i0]ASI_BLK_COMMIT_S ! store the modified block 1719 membar #Sync 1720 flush %i0 ! flush instruction pipeline 1721 stn %g0, [THREAD_REG + T_LOFAULT] ! remove the lofault handler 1722 1723 bz,a,pt %xcc, 1f 1724 wr %g0, %l0, %fprs ! restore %fprs 1725 1726 ld [%fp + STACK_BIAS - 4], %f0 ! restore %f0 17271: 1728 1729 wrpr %g0, %l1, %pstate ! restore interrupts 1730 1731 ret 1732 restore %g0, %g0, %o0 1733 17340: 1735 membar #Sync 1736 stn %g0, [THREAD_REG + T_LOFAULT] ! remove the lofault handler 1737 1738 bz,a,pt %xcc, 1f 1739 wr %g0, %l0, %fprs ! restore %fprs 1740 1741 ld [%fp + STACK_BIAS - 4], %f0 ! restore %f0 17421: 1743 1744 wrpr %g0, %l1, %pstate ! restore interrupts 1745 1746 /* 1747 * If tryagain is set (%i2) we tail-call dtrace_blksuword32_err() 1748 * which deals with watchpoints. Otherwise, just return -1. 1749 */ 1750 brnz,pt %i2, 1f 1751 nop 1752 ret 1753 restore %g0, -1, %o0 17541: 1755 call dtrace_blksuword32_err 1756 restore 1757 1758 SET_SIZE(dtrace_blksuword32) 1759#endif /* lint */ 1760 1761#if defined(lint) 1762/*ARGSUSED*/ 1763void 1764ras_cntr_reset(void *arg) 1765{ 1766} 1767#else 1768 ENTRY_NP(ras_cntr_reset) 1769 set OPL_SCRATCHPAD_ERRLOG, %o1 1770 ldxa [%o1]ASI_SCRATCHPAD, %o0 1771 or %o0, ERRLOG_REG_NUMERR_MASK, %o0 1772 retl 1773 stxa %o0, [%o1]ASI_SCRATCHPAD 1774 SET_SIZE(ras_cntr_reset) 1775#endif /* lint */ 1776 1777#if defined(lint) 1778/* ARGSUSED */ 1779void 1780opl_error_setup(uint64_t cpu_err_log_pa) 1781{ 1782} 1783 1784#else /* lint */ 1785 ENTRY_NP(opl_error_setup) 1786 /* 1787 * Initialize the error log scratchpad register 1788 */ 1789 ldxa [%g0]ASI_EIDR, %o2 1790 sethi %hi(ERRLOG_REG_EIDR_MASK), %o1 1791 or %o1, %lo(ERRLOG_REG_EIDR_MASK), %o1 1792 and %o2, %o1, %o3 1793 sllx %o3, ERRLOG_REG_EIDR_SHIFT, %o2 1794 or %o2, %o0, %o3 1795 or %o3, ERRLOG_REG_NUMERR_MASK, %o0 1796 set OPL_SCRATCHPAD_ERRLOG, %o1 1797 stxa %o0, [%o1]ASI_SCRATCHPAD 1798 /* 1799 * Disable all restrainable error traps 1800 */ 1801 mov AFSR_ECR, %o1 1802 ldxa [%o1]ASI_AFSR, %o0 1803 andn %o0, ASI_ECR_RTE_UE|ASI_ECR_RTE_CEDG, %o0 1804 retl 1805 stxa %o0, [%o1]ASI_AFSR 1806 SET_SIZE(opl_error_setup) 1807#endif /* lint */ 1808 1809#if defined(lint) 1810/* ARGSUSED */ 1811void 1812opl_mpg_enable(void) 1813{ 1814} 1815#else /* lint */ 1816 ENTRY_NP(opl_mpg_enable) 1817 /* 1818 * Enable MMU translating multiple page sizes for 1819 * sITLB and sDTLB. 1820 */ 1821 mov LSU_MCNTL, %o0 1822 ldxa [%o0] ASI_MCNTL, %o1 1823 or %o1, MCNTL_MPG_SITLB | MCNTL_MPG_SDTLB, %o1 1824 retl 1825 stxa %o1, [%o0] ASI_MCNTL 1826 SET_SIZE(opl_mpg_enable) 1827#endif /* lint */ 1828 1829#if defined(lint) 1830/* 1831 * This function is called for each (enabled) CPU. We use it to 1832 * initialize error handling related registers. 1833 */ 1834/*ARGSUSED*/ 1835void 1836cpu_feature_init(void) 1837{} 1838#else /* lint */ 1839 ENTRY(cpu_feature_init) 1840 ! 1841 ! get the device_id and store the device_id 1842 ! in the appropriate cpunodes structure 1843 ! given the cpus index 1844 ! 1845 CPU_INDEX(%o0, %o1) 1846 mulx %o0, CPU_NODE_SIZE, %o0 1847 set cpunodes + DEVICE_ID, %o1 1848 ldxa [%g0] ASI_DEVICE_SERIAL_ID, %o2 1849 stx %o2, [%o0 + %o1] 1850 ! 1851 ! initialize CPU registers 1852 ! 1853 ba opl_cpu_reg_init 1854 nop 1855 SET_SIZE(cpu_feature_init) 1856#endif /* lint */ 1857 1858#if defined(lint) 1859 1860void 1861cpu_cleartickpnt(void) 1862{} 1863 1864#else /* lint */ 1865 /* 1866 * Clear the NPT (non-privileged trap) bit in the %tick/%stick 1867 * registers. In an effort to make the change in the 1868 * tick/stick counter as consistent as possible, we disable 1869 * all interrupts while we're changing the registers. We also 1870 * ensure that the read and write instructions are in the same 1871 * line in the instruction cache. 1872 */ 1873 ENTRY_NP(cpu_clearticknpt) 1874 rdpr %pstate, %g1 /* save processor state */ 1875 andn %g1, PSTATE_IE, %g3 /* turn off */ 1876 wrpr %g0, %g3, %pstate /* interrupts */ 1877 rdpr %tick, %g2 /* get tick register */ 1878 brgez,pn %g2, 1f /* if NPT bit off, we're done */ 1879 mov 1, %g3 /* create mask */ 1880 sllx %g3, 63, %g3 /* for NPT bit */ 1881 ba,a,pt %xcc, 2f 1882 .align 8 /* Ensure rd/wr in same i$ line */ 18832: 1884 rdpr %tick, %g2 /* get tick register */ 1885 wrpr %g3, %g2, %tick /* write tick register, */ 1886 /* clearing NPT bit */ 18871: 1888 rd STICK, %g2 /* get stick register */ 1889 brgez,pn %g2, 3f /* if NPT bit off, we're done */ 1890 mov 1, %g3 /* create mask */ 1891 sllx %g3, 63, %g3 /* for NPT bit */ 1892 ba,a,pt %xcc, 4f 1893 .align 8 /* Ensure rd/wr in same i$ line */ 18944: 1895 rd STICK, %g2 /* get stick register */ 1896 wr %g3, %g2, STICK /* write stick register, */ 1897 /* clearing NPT bit */ 18983: 1899 jmp %g4 + 4 1900 wrpr %g0, %g1, %pstate /* restore processor state */ 1901 1902 SET_SIZE(cpu_clearticknpt) 1903 1904#endif /* lint */ 1905 1906#if defined(lint) 1907 1908void 1909cpu_halt_cpu(void) 1910{} 1911 1912void 1913cpu_smt_pause(void) 1914{} 1915 1916#else /* lint */ 1917 1918 /* 1919 * Halt the current strand with the suspend instruction. 1920 * The compiler/asm currently does not support this suspend 1921 * instruction mnemonic, use byte code for now. 1922 */ 1923 ENTRY_NP(cpu_halt_cpu) 1924 .word 0x81b01040 1925 retl 1926 nop 1927 SET_SIZE(cpu_halt_cpu) 1928 1929 /* 1930 * Pause the current strand with the sleep instruction. 1931 * The compiler/asm currently does not support this sleep 1932 * instruction mnemonic, use byte code for now. 1933 */ 1934 ENTRY_NP(cpu_smt_pause) 1935 .word 0x81b01060 1936 retl 1937 nop 1938 SET_SIZE(cpu_smt_pause) 1939 1940#endif /* lint */ 1941