1*0e751525SEric Saxe /* 2*0e751525SEric Saxe * CDDL HEADER START 3*0e751525SEric Saxe * 4*0e751525SEric Saxe * The contents of this file are subject to the terms of the 5*0e751525SEric Saxe * Common Development and Distribution License (the "License"). 6*0e751525SEric Saxe * You may not use this file except in compliance with the License. 7*0e751525SEric Saxe * 8*0e751525SEric Saxe * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*0e751525SEric Saxe * or http://www.opensolaris.org/os/licensing. 10*0e751525SEric Saxe * See the License for the specific language governing permissions 11*0e751525SEric Saxe * and limitations under the License. 12*0e751525SEric Saxe * 13*0e751525SEric Saxe * When distributing Covered Code, include this CDDL HEADER in each 14*0e751525SEric Saxe * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*0e751525SEric Saxe * If applicable, add the following below this CDDL HEADER, with the 16*0e751525SEric Saxe * fields enclosed by brackets "[]" replaced with your own identifying 17*0e751525SEric Saxe * information: Portions Copyright [yyyy] [name of copyright owner] 18*0e751525SEric Saxe * 19*0e751525SEric Saxe * CDDL HEADER END 20*0e751525SEric Saxe */ 21*0e751525SEric Saxe /* 22*0e751525SEric Saxe * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23*0e751525SEric Saxe * Use is subject to license terms. 24*0e751525SEric Saxe */ 25*0e751525SEric Saxe 26*0e751525SEric Saxe #include <sys/cpu_pm.h> 27*0e751525SEric Saxe 28*0e751525SEric Saxe /* 29*0e751525SEric Saxe * CPU PM interfaces exposed to the CPU power manager 30*0e751525SEric Saxe */ 31*0e751525SEric Saxe /*ARGSUSED*/ 32*0e751525SEric Saxe id_t 33*0e751525SEric Saxe cpupm_plat_domain_id(struct cpu *cp, cpupm_dtype_t type) 34*0e751525SEric Saxe { 35*0e751525SEric Saxe return (CPUPM_NO_DOMAIN); 36*0e751525SEric Saxe } 37*0e751525SEric Saxe 38*0e751525SEric Saxe /*ARGSUSED*/ 39*0e751525SEric Saxe uint_t 40*0e751525SEric Saxe cpupm_plat_state_enumerate(struct cpu *cp, cpupm_dtype_t type, 41*0e751525SEric Saxe cpupm_state_t *states) 42*0e751525SEric Saxe { 43*0e751525SEric Saxe return (0); 44*0e751525SEric Saxe } 45*0e751525SEric Saxe 46*0e751525SEric Saxe /*ARGSUSED*/ 47*0e751525SEric Saxe int 48*0e751525SEric Saxe cpupm_plat_change_state(struct cpu *cp, cpupm_state_t *state) 49*0e751525SEric Saxe { 50*0e751525SEric Saxe return (-1); 51*0e751525SEric Saxe } 52